DE102021120538B4 - Microelectromechanical microphone with membrane trench reinforcements and method of making - Google Patents

Abstract

A method for manufacturing a microelectromechanical system (MEMS) microphone, comprising:providing a wafer (102);depositing a silicon nitride layer (202) on the wafer (102);depositing a first oxide layer (402) on a front side of the wafer (102 ) over the silicon nitride film (202) and over and adjacent to the wafer (102), wherein depositing adjacent to the wafer (102) comprises filling one or more cavities (302) on the front side of the wafer (102) by oxide deposition;depositing a protective membrane layer (802) over the first oxide layer (402) between a first side of a first cavity (3021) formed in the wafer (102) and a second side of a second cavity (3022) formed in the wafer (102);depositing a second oxide layer (1102) over and adjacent the membrane protection layer (802);depositing a first membrane nitride layer (1402) over the second oxide layer (1102);depositing a membrane polysilicon layer over the first membrane nitride layer (1402);depositing a second membrane nitride layer (1802) over the membrane polysilicon layer;depositing a third oxide layer (2002) over the second membrane nitride layer (1802);depositing a fourth oxide layer (2202) over the third oxide layer (2002);opening a lateral etch stop region by etching the third oxide layer (2002) and the fourth oxide layer (2202);depositing a backplate nitride underlayer (2402) over and adjacent to the fourth oxide layer (2202) and adjacent to the third oxide layer (2002);depositing a first backplate polysilicon layer (2502) over and adjacent the backplate nitride underlayer (2402);depositing a fifth oxide layer (2602) on portions of the first backplate polysilicon layer (2502); depositing a second backplate polysilicon layer (2702) over the fifth oxide layer (2602) and the first backplate polysilicon layer (2502);depositing metal (3102) over the second backplate polysilicon layer (2702) and over the first backplate polysilicon layer (2502 );applying a resist protection (3302) to the front side; defining a cavity (3304) on a back side of the wafer (102) resulting in a defined structure; performing a first step of exposing the defined structure on the front side of the wafer (102), removing at least the resist protection (3302);removing the protective membrane layer (802);performing a second step of exposing the defined structure, removing at least polysilicon; and depositing a self-assembled monolayer coating.

Description

Microelectromechanical systems (MEMS) are a class of structures and/or devices fabricated using semiconductor-like processes. MEMS structures and/or devices exhibit mechanical properties that include the ability to move or deform. Examples of MEMS devices include but are not limited to gyroscopes, accelerometers, magnetometers, pressure sensors, radio frequency components, etc. Silicon wafers that contain MEMS structures are referred to as MEMS wafers.

An exemplary microelectromechanical microphone device is in the reference U.S. 2019/124452 A1 described. The reference discloses a membrane that can be deformed by a pressure wave and includes a backplate that is mechanically connected to the membrane. The backplate includes vent holes that allow the passage of the pressure wave.

There are distinct challenges to providing MEMS devices and/or structures with improved performance and reliability.

At least some of these challenges are solved by the method described below for producing MEMS components and the MEMS component described.

A method for manufacturing a MEMS component (Microelectromechanical System) comprises several steps. The method comprises at least the following steps, which are preferably, but not necessarily, carried out in the order given.

In a first step, a wafer is provided. In one embodiment, the wafer may be aluminum nitride. In another embodiment, the wafer can be made of silicon or similar materials.

In a further step, a silicon nitride thin film is deposited on the wafer. The silicon nitride layer can be applied at least on the front side of the wafer. Furthermore, the silicon nitride layer can be applied to the back of the wafer.

In an embodiment, the silicon nitride layer can be arranged on a first side and a second side of the wafer. The first side and the second side are on opposite sides of the wafer. The first and second sides can be the back side and the front side of the wafer.

The silicon nitride film may be configured as a low stress silicon nitride film (LSN first film). More specifically, a first LSN film may be deposited on a first surface of the wafer and a second LSN film may be deposited on a second surface of the wafer.

In a further step cavities can be formed in the wafer.

In one embodiment, one or more first side cavities may be etched through the first LSN film and into the wafer. A cavity is an opening or depression in a substrate layer. The one or more cavities can be etched with a DRIE (Deep Reactive-Ion Etching) process. In some embodiments, a first mask can be used to etch the one or more cavities. The one or more cavities may be referred to as anterior cavities.

In some cases, the one or more cavities can be a donut ring of about 4 microns (4pm), which can absorb the inaccuracy of the DRIE position. Furthermore, the one or more cavities can define a distance to a membrane stopper and a lateral etch stop, which will be discussed in more detail below.

In a further step, a first oxide layer is deposited on the first side of the wafer, over the silicon nitride thin film and over and next to the wafer. The first oxide layer can consist, for example, of tetraethyl orthosilicate (TEOS), which is also referred to as tetraethoxysilane.

According to one embodiment, depositing the first oxide layer may include filling the one or more cavities by oxide deposition. When a first oxide layer is deposited on the first side of the wafer, the first oxide layer is deposited over the first LSN film.

Furthermore, the first oxide layer may be deposited within the one or more cavities. The first oxide layer deposited within the one or more cavities may be deposited over portions of the wafer exposed by the one or more cavities. Furthermore, the first oxide layer may be deposited on respective sides of the one or more cavities adjacent to the wafer and adjacent to the first LSN film.

In an embodiment, the etching around of the filling oxide can be performed in a next step of the manufacturing process. The etch-around may allow etching of the first oxide layer in one or more portions of the first oxide layer that are not in the areas of the one or more cavities.

The re-etch may include removing the filling oxide by reactive ion etching (RIE) prior to performing a CMP process. During or after the CMP process, one or more portions of the first oxide layer remain in the areas corresponding to the one or more cavities (eg, filled cavities).

According to one embodiment, a base oxide may be deposited over the first LSN film over some or all of the voids filled with the first oxide layer. The base oxide can e.g. B. TEOS include.

In a further step, a protective membrane layer is deposited over the first oxide layer between a first side of a first cavity formed in the wafer and a second side of a second cavity formed in the wafer. The membrane protection layer can be a polysilicon protection layer. In some embodiments, the membrane protective layer is narrower than about 500 nm. In one embodiment, the thickness of the membrane protective layer is about 100 nm.

In one embodiment, the membrane protection layer can be deposited over the base oxide on the first side. In another embodiment, the membrane protection layer can be deposited over the second LSN thin film on the second side.

In addition, the membrane protection layer can provide control over the dimension of a vent hole and protect the performance of the cutoff frequency.

The membrane protection layer (MPL) can protect the silicon nitride layer from various manufacturing process steps, including buffered oxide etch (BOE), and from high frequency or very high frequency (vHF) encountered in various application situations.

In one embodiment, the MPL can be structured during or after the MPL is deposited. Patterning the MPL may include preserving a portion of the MPL located over the first cavity, over the second cavity, and over the region between the first cavity and the second cavity. For example, the portion of the MPL that is retained extends from about a first side of the first cavity filled with the first oxide layer to about a second side of the second cavity filled with the first oxide layer. The other parts of the MPL are removed during structuring of the MPL.

The remaining portion of the MPL is used to protect against over-etching of the membrane's nitride, which may be deposited later in the fabrication process.

In some embodiments, a center-to-center dimension of the two front cavities is at least about 20 microns wide. Etching of the cavities from the back is aligned with the respective centers of the front cavities. Therefore, minor deviations, such as e.g. B. plus or minus half dimension, can be tolerated as a tolerance for the cavity position during etching, which can allow the feasibility of the manufacturing process. This allows for some inaccuracy during the manufacturing process and alignment to the front cavities as provided herein to be accommodated. Otherwise the correct positioning of the cavities could not be achieved.

In one embodiment, a membrane stopper is patterned. Patterning the membrane stopper may include etching the base oxide in the areas not covered by the MPL. Etching can be done at a dimension of about 0.95 microns of the membrane stopper. The etch should be controlled down to the nitride (e.g., the first LSN thin film) in order to obtain a defined amount of material upon entering the exposure process, which is performed towards the end of the fabrication process, as discussed further below.

In a further step, a second oxide layer is deposited over and next to the membrane protection layer.

In some embodiments, the second oxide layer may be referred to as a membrane stopper spacer. For example, a portion of the second oxide layer may be deposited over and adjacent to the MPL. Furthermore, the second oxide layer can be deposited over and next to the base oxide and over the first LSN film. In one embodiment, the second oxide layer may be deposited adjacent to the MPL on a first side of the MPL proximate the first side of the first cavity filled with the first oxide layer and on a second side of the MPL proximate the second side of the second cavity filled with the first oxide layer. In a version In this way, the second oxide layer can be deposited next to the base oxide at the points where the base oxide has been removed.

In one embodiment, another portion of the second oxide layer may be deposited on the second side and over the MPL.

In one embodiment, the second oxide layer may be an interim layer to control the distance between the surface and the membrane stopper. It is noted that the membrane stopper is configured to control the distance to the surface. In some embodiments, the membrane stopper has a target distance of about 250 nm (about plus or minus 50 nm).

The second oxide layer is an oxide layer that defines the spacing during a release etch, which will be discussed in more detail below. The second oxide layer can consist of silicon oxide, which can be a TS oxide that is deposited with a thickness in the range from about 50 nm to about 100 nm, depending on the production method. In some embodiments, the second oxide layer may have a target thickness of about 100 nm.

In one embodiment, a first lateral etch stop (LES 1) is patterned. Patterning the lateral etch stop may include etching the second oxide layer and the base oxide in one or more areas. More specifically, the second oxide layer and the base oxide can be etched up to the first LSN thin layer. This etching can be referred to as overetching. A CMP process can be performed on the exposed first LSN thin film during or after the etching. The first LSN film may have a thickness of about 50 nm in some embodiments.

In one embodiment, the lateral etch stop may be patterned to meet a particular corner radius specification. The defined specification can be, for example, that the corner radius should be more than 100 nm.

Optionally, a second LSN thin film reinforcement can be deposited and etched at this stage of the fabrication process.

In one embodiment, a nitride reinforcement layer is deposited and patterned. For example, the nitride reinforcement layer may be deposited on the first side over and adjacent to the second oxide layer, over and adjacent to the base oxide, and over the first LSN film. In addition, the nitride reinforcement layer can be deposited on the second side over the second oxide layer.

In a further step, a first membrane nitride layer is deposited over the second oxide layer.

In one embodiment, the first membrane nitride layer is deposited over and adjacent to the nitride reinforcement layer. Furthermore, a further first membrane nitride layer can be deposited on the second side.

In one embodiment, the first membrane nitride layer may be an in situ doped polysilicon (ISDP) membrane, which may be deposited and annealed.

In one embodiment, a next step of the fabrication process includes etching the first membrane nitride layer. A trench may be formed in the first membrane nitride layer. For example, the first membrane nitride layer can be etched to a top surface of the nitride reinforcement layer. The trench may have bottom corners. The corners can each have a radius of more than 50 nm. The trench width can be 8 µm or 4 µm reinforcement layer.

According to some implementations, additional processes may be performed, such as defining an active electrode area and a shield. Another process may involve opening ventilation holes in the ISDP (8 pm). Furthermore, the ground contact can be exposed as a donut. Furthermore, the scribe line can be exposed leaving an edge covering on the scribe line. Another process can be the definition of a chip ID.

According to one embodiment, an oxide reinforcement layer may be deposited over and adjacent to the first membrane nitride layer and over the nitride reinforcement layer. This step may also be referred to as depositing a top reinforcement layer. Various parts of the oxide reinforcement layer can be etched. After etching, part of the oxide reinforcement layer remains at the trench.

In a further step, a membrane polysilicon layer is deposited over the first membrane nitride layer.

In a further step, a second membrane nitride layer is deposited over the membrane polysilicon layer. At the second memb ran nitride layer, it can be an LSN thin layer. For example, the second membrane nitride layer may be deposited adjacent to and over the membrane polysilicon layer and/or adjacent to and over the first membrane nitride layer. Furthermore, the second membrane nitride layer may be deposited adjacent to and over a portion of an oxide reinforcement layer over the trench. In addition, the second membrane nitride layer can be deposited over the first LSN film. Furthermore, the second membrane nitride layer may be deposited over the first membrane nitride layer on the second side of the wafer.

In one embodiment, one or more vent holes may be formed by etching through the second membrane nitride layer and the first membrane nitride layer.

In a further step, a third oxide layer is deposited over the second membrane nitride layer.

The third oxide layer can also be referred to as a first air gap oxide. One or more depressions and a second lateral etch stop may be formed (eg, exposed) in the third oxide layer. For example, the one or more pits and the second lateral etch stop may be formed (eg, etched) in the third oxide layer.

In a further step, a fourth oxide layer is deposited over the third oxide layer.

The fourth oxide layer can also be referred to as an air gap oxide deposit. A step of opening the second lateral etch stop region may include etching the third oxide layer and the fourth oxide layer.

In one embodiment, there are two corner radii on the lateral etch stops, shown as a first corner and a second corner. The first corner can have a radius greater than about 100 nm. The second corner can have a radius greater than 25 nm. Furthermore, the pitch (lateral pitch) can be about 4 µm. Note that the radius runs towards the center of the microphone.

The method for producing the two radii can be a two-mask method. For example, the areas on the two outer edges can be structured. Then oxide can be deposited. The areas on the two inner edges can be defined during or after the deposition of the oxide. In this way, first the wide part and then the narrow moat are defined.

In a further step, a nitride backplate underlayer is deposited over and adjacent to the fourth oxide layer and adjacent to the third oxide layer.

The nitride backplate underlayer may be an LSN underlayer. The nitride backplate underlayer may be deposited over and adjacent to the fourth oxide layer and adjacent to corresponding portions of the third oxide layer.

The nitride backplate undercoat can improve the strength of the backplate. For example, the strength of the nitride may be higher than the strength of the polysilicon in the backplate (e.g., the nitride has a much higher ultimate bending strength than polysilicon). Therefore, a nitride underlayer (e.g., the nitride backplate underlayer) can improve the strength of the backplate.

In a further step, a first backplate polysilicon layer is deposited over and adjacent to the nitride backplate underlayer.

The first backplate underlayer may be deposited over and adjacent to the nitride backplate underlayer. Stress annealing can also be performed. On the second side, the first backplate polysilicon layer may be deposited over the second membrane nitride layer. The first backplate polysilicon layer may also be referred to as the top backplate and is part of a rigid plate.

In a further step, a fifth oxide layer is deposited on the corresponding portions of the first backplate polysilicon layer.

In one embodiment, the fifth oxide layer may be a stress spreader, also referred to as an upper backplate stress spreader. The fifth oxide layer may be deposited over the first backplate polysilicon layer and etched, resulting in two portions of the fifth oxide layer. In some embodiments, the voltage spreader may be a nitride, oxide, or other layer of material.

In a further step, a second backplate polysilicon layer is deposited over the fifth oxide layer and the first backplate polysilicon layer.

The first backplate polysilicon layer, the fifth oxide layer, and the second backplate polysilicon layer may form a rigid plate. LSN hole structuring can also be carried out.

In one embodiment, a first contact may be exposed to the wafer via an oxide etch. In addition, second contacts can be exposed to achieve a mass opening from contact to shield contact. In one example, the first oxide can be dry etched and then the nitride layer can be etched in a pattern to contact the membrane.

In a further step, metal is deposited over the second backplate polysilicon layer and over the first backplate polysilicon layer.

In one embodiment, one or more pieces of metal may be deposited within one or more second contacts. Accordingly, the metal may be deposited over and adjacent to the second backplate polysilicon layer, over the first backplate polysilicon layer, and over the nitride reinforcement layer and the first LSN film. The metal can be etched such that only portions of the metal remain at the one or more second contacts. Thus, a first portion of metal can line the bottom and sides of the second contact. Further, a second portion of metal may line the bottom and sides of the second contact.

In one embodiment, front face protection and grinding may be performed in a next stage of the manufacturing process. A front side protection oxide may be deposited over and adjacent to the first backplate polysilicon layer and metal. After depositing the oxide protection on the front side, the wafer can be thinned to the desired thickness. For example, the wafer can be thinned to 350 microns.

In a further step, a cavity is defined on the back of the wafer, which leads to a defined structure.

Defining the cavity may include patterning and etching portions of the wafer and corresponding portions of the backside layers.

The cavity can be defined between the centers of the respective front cavities. According to an optional implementation, a xenon difluoride (XeF2) photoresist may be preserved during a silicon removal process.

In a further step, the defined structure is exposed for the first time.

In an embodiment, the first exposure or initial exposure may comprise a buffered oxide etch (BOE) using buffered oxide, which includes the removal of the resist on the front side. This process can be a wet pre-exposure process. During the BOE pre-exposure, the long line in the 20 micron range is laterally etched. During the BOE pre-exposure, the membrane is protected by the thin polysilicon. The term "exposure" means that all sacrificial material should be removed.

In a further step, the protective membrane layer is removed.

A second exposure of the defined structure is then carried out. In one embodiment, this may include removing the polysilicon. The polysilicon can be removed in a xenon difluoride process. After that, the resist on the front side can be removed.

Furthermore, a SAM coating (Self-Assembled Monolayer, self-organizing monolayer) is applied to the structure.

• Bereitstellen eines Wafers; Abscheiden einer Siliziumnitrid-Dünnschicht auf dem Wafer; Abscheiden einer ersten Oxidschicht auf einer Vorderseite des Wafers über der Siliziumnitrid-Dünnschicht und über und neben dem Wafer;
• Abscheiden einer Membranschutzschicht über der ersten Oxidschicht zwischen einer ersten Seite eines im Wafer ausgebildeten ersten Hohlraums und einer zweiten Seite eines im Wafer ausgebildeten zweiten Hohlraums; Abscheiden einer zweiten Oxidschicht über und neben die Membranschutzschicht;
• Abscheiden einer ersten Membran-Nitridschicht über der zweiten Oxidschicht; Abscheiden einer Membran-Polysiliziumschicht über der ersten Membran-Nitridschicht;
• Abscheiden einer zweiten Membran-Nitridschicht über der Membran-Polysiliziumschicht; Abscheiden einer dritten Oxidschicht über der zweiten Membran-Nitridschicht;
• Abscheiden einer vierten Oxidschicht über der dritten Oxidschicht; Abscheiden einer Rückplatten-Nitrid-Unterschicht über und neben die vierte Oxidschicht und neben die dritte Oxidschicht; Abscheiden einer ersten Rückplatten-Polysiliziumschicht über und neben die Rückplatten-Nitrid-Unterschicht; Abscheiden einer fünften Oxidschicht an jeweiligen Abschnitten der ersten Rückplatten-Polysiliziumschicht; Abscheiden einer zweiten Rückplatten-Polysiliziumschicht über der fünften Oxidschicht und der ersten Rückplatten-Polysiliziumschicht; Abscheiden von Metall über der zweiten Rückseiten-Polysiliziumschicht und über der ersten Rückseiten-Polysiliziumschicht; Definieren eines Hohlraums auf einer Rückseite des Wafers, was zu einer definierten Struktur führt; Durchführen einer ersten Freilegung der definierten Struktur; Entfernen der Membranschutzschicht; Durchführen einer zweiten Freilegung der definierten Struktur; und Abscheiden einer selbstorganisierenden Monoschichtbeschichtung.

In summary, it can be said that the method described for manufacturing a microelectromechanical system (MEMS) includes at least the following steps:

• providing a wafer; depositing a silicon nitride thin film on the wafer; depositing a first oxide layer on a front side of the wafer over the silicon nitride film and over and adjacent to the wafer;
• depositing a membrane protection layer over the first oxide layer between a first side of a first cavity formed in the wafer and a second side of a second cavity formed in the wafer; depositing a second oxide layer over and adjacent to the membrane protection layer;
• depositing a first membrane nitride layer over the second oxide layer; depositing a membrane polysilicon layer over the first membrane nitride layer;
• depositing a second membrane nitride layer over the membrane polysilicon layer; depositing a third oxide layer over the second membrane nitride layer;
• depositing a fourth oxide layer over the third oxide layer; Deposit a backplate nitride underlayer over and next to the fourth oxide layer and adjacent to the third oxide layer; depositing a first backplate polysilicon layer over and adjacent the backplate nitride underlayer; depositing a fifth oxide layer on respective portions of the first backplate polysilicon layer; depositing a second backplate polysilicon layer over the fifth oxide layer and the first backplate polysilicon layer; depositing metal over the second backside polysilicon layer and over the first backside polysilicon layer; defining a cavity on a back side of the wafer resulting in a defined structure; performing a first exposure of the defined structure; removing the membrane protective layer; performing a second exposure of the defined structure; and depositing a self-assembled monolayer coating.

Furthermore, in some embodiments, the method may include the following additional steps.

In one embodiment, the method may include a step of depositing a nitride reinforcement layer over and adjacent to the second oxide layer and defining the nitride reinforcement layer prior to depositing the first membrane nitride layer.

In one embodiment, the method may include a step of depositing an oxide reinforcement layer and defining the oxide reinforcement layer prior to depositing the second membrane nitride layer.

In one embodiment, depositing the membrane polysilicon layer further comprises defining the membrane polysilicon layer and a portion of the membrane polysilicon layer.

In one embodiment, the definition of the membrane polysilicon layer includes the formation of one or more vent holes and an active electrode.

In an embodiment, depositing the second oxide layer further includes opening a first lateral etch stop, wherein a corner radius of the first lateral etch stop is greater than 100 nanometers.

In one embodiment, depositing the fourth oxide layer includes opening a lateral etch stop that includes etching a first corner radius and a second corner radius.

In one embodiment, etching the first corner radius includes etching the first corner radius to a radius greater than 100 nanometers.

In one embodiment, etching the second corner radius includes etching the second corner radius to a radius greater than 25 nanometers.

In one embodiment, the increment between the first corner radius and the second corner radius is less than 4 microns.

The invention further relates to a microelectromechanical microphone device (MEMS microphone). The microelectromechanical microphone device can be manufactured according to the method described above. Embodiments of the microelectromechanical microphone device may include all of the components introduced in connection with the method described above.

The microelectromechanical microphone device includes a flexible sheet that is deformed by a pressure wave, the flexible sheet including a rear bending edge that includes a first lateral etch stop having a first corner radius and a second lateral etch stop having a second corner radius different from the first corner radius. The microelectromechanical microphone device further includes a rigid plate mechanically coupled to the flexible plate, the rigid plate including openings that allow the passage of the pressure wave. And the microelectromechanical microphone device includes a stop member attached to the rigid panel and extending perpendicularly relative to a surface of the rigid panel opposite the surface of the flexible panel, the stop member limiting movement of the flexible panel in response to the pressure wave.

In one embodiment, the first corner radius is greater than 100 nanometers and the second corner radius is greater than 25 nanometers.

In one embodiment, the lateral step width between the first corner radius and the second corner radius is less than about 4 microns.

In one embodiment, the rigid plate includes a stress spreader located between the polysilicon layers.

In one embodiment, the stress spreader includes a nitride layer.

In one embodiment, the microelectromechanical microphone device further comprises a flexible plate that is deformed by a pressure wave.

In one embodiment, the microelectromechanical microphone device further comprises a rigid plate mechanically connected to the flexible plate, the rigid plate including openings that allow the pressure wave to pass through, and the rigid plate including a stress distributor.

In one embodiment, the microelectromechanical microphone device further comprises a stop member attached to the rigid panel and extending perpendicularly relative to a surface of the rigid panel opposite the surface of the flexible panel, the stop member limiting movement of the flexible panel in response to the pressure wave having a threshold amplitude.

In one embodiment, the stress spreader includes a nitride, oxide, or other layer of material.

In one embodiment, the rigid plate includes a rear flex edge that includes a first lateral etch stop having a first corner radius and a second lateral etch stop having a second corner radius that is different than the first corner radius.

In one embodiment, the first corner radius is greater than 100 nanometers and the second corner radius is greater than 25 nanometers.

In one embodiment, a lateral step width between the first corner radius and the second corner radius is less than about 4 microns.

In one embodiment, the MEMS microphone includes one or more front cavities used to control the flexing of a flexible sheet. Furthermore, the flexible plate does not touch the edge of the cavities when moving toward the cavities. For example, the flexible plate moves or is deformed by a pressure wave. Controlling the movement can improve the robustness of the flexible plate when it is deformed by the pressure wave. In some embodiments, the pressure wave may have a threshold amplitude.

In one embodiment, additional membrane stops can help control the flexible panel. Because the microphone can be relatively large, the front diaphragm and diaphragm stops work together to stop or limit downward movement of the flexible plate.

In one embodiment, the MEMS microphone also includes a shield TP contact and a membrane node (raised to TP).

In one embodiment, the MEMS microphone also includes an LSN sub-layer. In one embodiment, the MEMS microphone also includes a cavity.

In one embodiment, a membrane moat separates the active element and the shield in the MEMS microphone.

A buried oxide to reduce stress can also be provided. For example, a parasitic reduction (MEM—Boot) and a bulk/boot node can also be provided. The MEMS microphone may also have oxide reinforcement on top of the membrane trench.

In one embodiment, a reinforcement of the trench is provided. The reinforcement can be made of oxide, nitride or other material.

In one embodiment, the MEMS microphone includes a lower LSN gain.

Reference throughout this specification to “one embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. As such, the phrases "in one embodiment" or "in one aspect" throughout this specification are not necessarily all referring to the same embodiment. Furthermore, any individual feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments.

In addition, the words "example" and "for example" are used herein to serve as an example or illustration. Any embodiment described herein as "example" or "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or configurations.

Rather, the use of the word “example” or “for example” is intended to present concepts in a concrete manner. As used in this application, the term "or" shall rather an inclusive "or" mean than an exclusive "or". That is, unless otherwise indicated or apparent from the context, "X uses A or B" means either of the naturally inclusive implementations. That is, if X uses A, X uses B, or X uses both A and B, then "X uses A or B" is true in each of the above cases. Additionally, as used in this application and the appended claims, the indefinite articles should generally be construed to mean "one or more" unless otherwise specified or the context clearly indicates that they refer to a singular form.

• Verschiedene nicht-einschränkende Ausführungsformen werden unter Bezugnahme auf die beigefügten Zeichnungen näher beschrieben:
  • 1-36 illustrieren beispielhafte, nicht-begrenzende Querschnittsansichten eines MEMS-Mikrofons, das einem Herstellungsprozess gemäß einer oder mehrerer hierin beschriebenen Ausführungsformen unterzogen wird;
  • 37 zeigt eine beispielhafte Darstellung eines MEMS-Mikrofons gemäß einer oder mehrerer der hierin beschriebenen Ausführungsformen;
  • 38 zeigt eine weitere Beispieldarstellung eines MEMS-Mikrofons gemäß einer oder mehrerer hierin beschriebener Ausführungsformen; und
  • 39 zeigt eine weitere Beispieldarstellung eines MEMS-Mikrofons gemäß einer oder mehrerer hierin beschriebener Ausführungsformen.

The embodiments of the invention are explained in more detail below with reference to the attached figures. Similar or seemingly identical elements in the figures are identified with the same reference numbers. The figures and the proportions in the figures are not scalable. The invention is not limited to the following embodiments. The figures show:

• Various non-limiting embodiments are described in more detail with reference to the accompanying drawings:
  • 1-36 12 illustrate exemplary, non-limiting cross-sectional views of a MEMS microphone undergoing a manufacturing process in accordance with one or more embodiments described herein;
  • 37 12 shows an exemplary representation of a MEMS microphone, in accordance with one or more embodiments described herein;
  • 38 12 shows another example representation of a MEMS microphone, in accordance with one or more embodiments described herein; and
  • 39 12 shows another example representation of a MEMS microphone, in accordance with one or more embodiments described herein.

One or more embodiments are described in more detail below with reference to the accompanying drawings, in which exemplary embodiments are illustrated. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments.

The 1-36 12 show exemplary, non-limiting cross-sectional views of a MEMS microphone undergoing a manufacturing process in accordance with one or more embodiments described herein.

1 10 shows a cross-sectional view of a first stage of fabricating a MEMS microphone in accordance with one or more embodiments described herein. In the first stage, a wafer 102 (e.g., a wafer substrate) may be ion implanted. The substrate can e.g. Example, consist of aluminum, copper or silicon. According to an implementation, the ion implantation of the wafer 102 may be a phosphorous ion implantation. In addition, ion implantation can be a process module for bulk doping.

As in 2 As illustrated, a low stress silicon nitride (LSN) thin film may be deposited on the wafer 102 . More specifically, a first LSN film 202 ₁ may be deposited on a first surface (e.g., a first side 204) of the wafer 102 and a second LSN film 202 ₂ may be deposited on a second surface (e.g., a second side 206) of the wafer 102. As illustrated, first side 204 and second side 206 are on opposite sides of wafer 102.

One or more cavities can be etched on the first side 204 through the first LSN film 202 ₁ and into the wafer 102 as shown in FIG 3 shown. For example, three cavities are shown, referred to as a first cavity 302 ₁ , a second cavity 302 ₂ , and a third cavity 302 ₃ . A cavity refers to an opening or depression in a substrate layer (e.g., the wafer 102). In the illustrated example, there are three cavities, but other numbers of cavities (e.g., one or more) may be formed in the wafer 102 according to various implementations. The one or more cavities can be etched with a DRIE (Deep Reactive-Ion Etching) process. In some embodiments, a first mask (M1) may be used to etch the one or more cavities.

In some embodiments, the etch of the first cavity 302 ₁ and the second cavity 302 ₂ may be referred to as a front cavity etch. In these embodiments, the first cavity 302 ₁ may be referred to as the first anterior cavity and the second cavity 302 ₂ may be referred to as the second anterior cavity, or collectively the anterior cavities.

According to some implementations, the one or more cavities may be a donut ring of about 4 microns (4pm) that may absorb the DRIE positional inaccuracy. In addition, the one or more Cavities define a distance to a membrane stopper and a lateral etch stop 1 (LES 1), which will be discussed in more detail below.

4 Figure 12 shows a phase of the manufacturing process that includes the deposition of a first oxide layer. According to one embodiment, the deposition of the first oxide layer may include filling the one or more cavities by oxide deposition. As indicated, a first oxide layer 402 is deposited on the first side 204 of the wafer 102 . The first oxide layer 402 is deposited over the first LSN thin layer 202 ₁ . Further, the first oxide layer 402 may be deposited in one or more cavities (e.g., the first cavity 302 ₁ , the second cavity 302 ₂ , and the third cavity 302 ₃ ). As indicated, the first oxide layer 402 that is deposited in the one or more cavities is deposited over portions of the wafer 102 that are exposed from the one or more cavities. Furthermore, the first oxide layer 402 is deposited on the respective sides of the one or more cavities, adjacent to the wafer 102 and adjacent to the first LSN film 202 ₁ . The first oxide layer 402 can consist of tetraethyl orthosilicate (TEOS), which is also referred to as tetraethoxysilane, for example.

Etching around the filling oxide (e.g. the first oxide layer 402) can be performed in a next phase of the manufacturing process, as shown in FIG 5 shown. The etch-around may allow etching of the first oxide layer 402 at one or more portions of the first oxide layer 402 that are not in the areas connected to the one or more cavities (e.g., the first cavity 302 ₁ , the second cavity 302 ₂ , and the third cavity 302 ₃ ). One or more portions of first oxide layer 402 that may be etched are labeled first portion 502, second portion 504, third portion 506, and fourth portion 508, for example. The first portion 502 represents the portion between the left edge of the device (e.g., the left edge when viewing from 5 ) and the first cavity 302 _1. The second portion 504 represents the portion between the first cavity 302 ₁ and the second cavity 302 _2. The third portion 506 represents the portion between the second cavity 302 ₂ and the third cavity 302 _3. The fourth portion 508 represents the portion between the third cavity 302 ₃ and the right edge of the device (e.g., the right edge when looking at FIG 5 ).

The etch-around may include removing the filling oxide (e.g., the first oxide layer 402) by reactive ion etching (RIE) prior to performing a CMP process, as in FIG 6 shown. During or after the CMP process, one or more portions of the first oxide layer 402 remain in the areas corresponding to the one or more cavities (eg, filled cavities) as indicated by the first cavity filled with the first oxide layer 402 ₁ , the second cavity filled with the first oxide layer 402 ₂ , and the third cavity filled with the first oxide layer 402 ₃ .

The respective centers of the front cavities are identified by a first dashed line 602 for the first cavity 302 ₁ and a second dashed line 604 for the second cavity 302 ₂ .

7 FIG. 7 shows the deposition of the base oxide 702 during a next stage of the fabrication process. The base oxide 702 may be deposited over the first LSN film 202 ₁ , over the first cavity filled with the first oxide layer 402 ₁ , over the second cavity filled with the first oxide layer 402 ₂ , and over the third cavity filled with the first oxide layer 402 ₃ . The base oxide 702 can e.g. B. consist of TEOS.

It should be noted that the front cavities can reduce capacitive coupling between the diaphragm and the backplate through ground. The front cavities can also reduce signal loss. It should be noted that the example shown includes a decoupling capacitor, but other decoupling capacitors can be included in other locations.

8th shows the application of a membrane protection layer (MPL). The MPL 802 ₁ can be deposited over the base oxide 702 on the first side 204 . Furthermore, the MPL 802 ₂ may be deposited over the second LSN film 202 ₂ on the second side 206 .

The MPL 802 ₁ may be a protective polysilicon layer on the backside (e.g., the first side 204). The thickness of the MPL 802 ₁ can be about 100 nm. In some implementations, the MPL 802 ₁ can be less than about 500 nm. In addition, the MPL 802 ₁ can enable control of a vent hole dimension (e.g. mitigate deterioration of the vent hole dimension), thereby protecting the cutoff frequency performance.

The MPL 802 ₁ and/or the MPL 802 ₂ can protect the LSN membrane (eg, the first LSN film 202 ₁ , the second LSN film 202 ₂ ) from various manufacturing processes, including buffered oxide etch (BOE), and from high frequency or very high frequency (vHF) encountered in various application situations. It is noted that the MPL 802 ₁ and/or the MPL 802 ₂ is an interim layer that will be removed later in the manufacturing process.

At or after the deposition of the MPL 802 ₁ , the MPL 802 ₁ is structured as in 9 shown. Patterning the MPL 802 ₁ may include preserving a portion of the MPL 802 ₁ overlying the first cavity 302 ₁ , over the second cavity 302 ₂ , and over the region between the first cavity 302 ₁ and the second cavity 302 ₂ (or over the first cavity filled with the first oxide layer 402 1 and the second cavity filled with the first oxide layer _{402 2 )} . will. The portion of MPL 802 ₁ that is preserved is denoted as portion 902 . For example, the portion of the MPL 802 ₁ that is preserved extends from about a first side 904 of the first cavity filled with the first oxide layer 402 ₁ to about a second side 906 of the second cavity filled with the first oxide layer 402 ₂ . The other sections of MPL _802-1 (labeled section 908 and section 910) are removed during structuring of MPL _802-1 . The remaining part of the MPL 802 ₁ (denoted by section 902) is used to protect against over-etching of the membrane's nitride (which is deposited later in the manufacturing process).

In some embodiments, a center-to-center dimension of the two front cavities (e.g., between first dashed line 602 and second dashed line 604) is at least about 20 microns wide. Etching the cavities from the back is aligned with the respective centers of the front cavities (which is related to 33 will be explained later). Thus, minor deviations, such as e.g. B. plus or minus half dimension as a tolerance for the cavity position during the etch, can be tolerated, which can allow the feasibility of the manufacturing process. This allows for some inaccuracy during the manufacturing process and alignment to the front cavities as provided herein to be accommodated. Otherwise the correct positioning of the cavities could not be achieved.

10 shows the structuring of a membrane stopper according to an embodiment. The patterning of the membrane stopper may include etching the base oxide 702 at the portions not covered by the MPL 802 ₁ or at the portions indicated as portion 908 and portion 910 (see FIG 9 ). For example, in section 908, a first region 1002 and a second region 1004 of base oxide 702 may be removed. Also, in section 910, a scribe line and the ground contact on the right side (as in 10 2) may be exposed, which may include etching or removing the base oxide 702 in a third region 1006 (shown in enlarged view), a fourth region 1008, and a fifth region 1010. FIG. The etch may be on the order of about 0.95 microns for the diaphragm stopper dimension. The etch should be controlled down to the nitride (e.g., the first LSN thin film 202 ₁ ) in order to obtain a defined amount of material upon entering the exposure process, which is performed towards the end of the fabrication process, as discussed further below.

The diaphragm stopper may be hollowed out toward the bulk (e.g., toward the wafer 102). Such removal of the base oxide 702 to create the membrane stopper can reduce stresses in the LES1 or the suspension region.

A second oxide layer can, as in 11 shown to be deposited. In some cases, the second oxide layer can be referred to as a membrane stopper spacer. For example, a portion of the second oxide layer (indicated by second oxide layer 1102 ₁ ) may be deposited over and adjacent to MPL 802 ₁ . Furthermore, the second oxide layer 1102 ₁ may be deposited over and next to the base oxide 702 and over the first LSN film 202 ₁ . The second oxide layer 1102 ₁ may be deposited adjacent to the MPL 802 ₁ on a first side of the MPL 802 ₁ proximate the first side 904 of the first cavity filled with the first oxide layer 402 ₁ and on a second side of the MPL 802 ₁ proximate the second side 906 of the second cavity filled with the first oxide layer 402 ₂ . The second oxide layer 1102 ₁ can be deposited next to the base oxide 702 at the portions where the base oxide 702 has been removed, such as e.g. B. on the portions of the base oxide, the at least one wall (or side) of the first region 1002, the walls of the second region 1004, the walls of the third region 1006 (see the enlarged view of the indicated region in 11 ), the walls of the fourth area 1008 and at least one wall of the fifth area 1010 form.

Furthermore, another portion of the second oxide layer (referred to as the second oxide layer 1102 ₂ ) can be deposited on the second side 106 and over the MPL 802 ₁ .

The second oxide layer 1102 ₁ may be an interim layer to control the distance between the surface and the diaphragm stopper. It is noted that the membrane stopper is configured to control the distance to the surface. According to some embodiments, the membrane stopper has a target distance of about 250 nm (plus or minus about 50 nm). The second oxide layer 1102 ₁ is an oxide layer that defines the spacing during an exposure etch, which will be discussed in more detail below. The second oxide layer 1102 ₁ (and the second oxide layer 1102 ₂ ) can consist of silicon oxide, which can be a TS-oxide, which is deposited in a range of approximately 50 nm to 100 nm depending on the manufacturing method. In some embodiments, the second oxide layer 1102 ₁ (and the second oxide layer 1102 ₂ ) may have a target thickness of about 100 nm.

12 FIG. 12 shows the structuring (eg opening) of a first lateral etch stop (eg lateral etch stop 1). The patterning of the lateral etch stop may include etching the second oxide layer 1102 ₁ and the base oxide 702 in one or more regions. For example, the second oxide layer 1102 ₁ and the base oxide 702 in a first region 1202 (see enlarged part on the left side of FIG 12 ) and in a second area 1204 (see enlarged part on the right side of 12 ) are etched. More specifically, the second oxide layer 1102 ₁ and the base oxide 702 can be etched down to the first LSN thin layer 202 ₁ (or the etching can be stopped at this point), as indicated by the first region 1202 and the second region 1204 . This etch may be referred to as an over etch in some embodiments. A CMP process can be performed on the exposed first LSN thin film 2021 during or after the etching. The first LSN thin film 2021 may have a thickness of about 50 nm in some embodiments.

The lateral etch stop can be patterned to meet a specific corner radius specification. For example, the specification defined may be that the corner radius should be greater than about 100 nm. The corner radius range for the first region 1202 is referred to as the first corner 1206 (e.g., a first corner radius) and the corner radius range for the second region 1204 is referred to as the second corner 1208 (e.g., a second corner radius). The first corner 1206 and the second corner 1208 represent the two inner corner radii. The etch process can be designed to create the required corner radius.

Optionally, a second LSN thin film 202 ₂ can be deposited and etched for reinforcement at this stage of the fabrication process (in 12 not shown).

13 FIG. 12 shows an optional stage of the fabrication process that includes depositing and patterning (eg, etching) a nitride reinforcement layer. For example, the nitride reinforcement layer 1302 ₁ (on the first side 204 ) may be deposited over and adjacent to the second oxide layer 1102 ₁ , over and adjacent to the base oxide 702 , and over the first LSN thin film 202 1 . For example, the nitride reinforcement layer 1302 ₁ may be deposited adjacent to the base oxide 702 on walls defined for the first region 1202 and on walls defined for the second region 1204 . Furthermore, the nitride reinforcement layer 1302 ₁ may be deposited over the first LSN film 202 ₁ at the bottom of the first region 1002 and at the bottom of the fifth region 1010 .

This phase of the manufacturing process can be referred to as LSN1 membrane deposition. Additionally, a nitride reinforcement layer 1302 ₂ may be deposited over the second oxide layer 1102 ₂ on the second side 206 .

Furthermore, as in 14 shown, a first membrane nitride layer are deposited. For example, the first membrane nitride layer 1402 ₁ may be deposited over and adjacent to the nitride reinforcement layer 1302 ₁ . Furthermore, another first membrane nitride layer 1402 ₂ may be deposited on the second side 206 over the nitride reinforcement layer 1302 ₂ . The first membrane nitride layer may be an in situ doped polysilicon (ISDP) membrane, which may be deposited and annealed.

15 14 shows a next stage of the fabrication process, which includes etching the first membrane nitride layer 1402 ₁ .

A trench 1502 is formed (etched) in the first membrane nitride layer 1402 ₁ . For example, the first membrane nitride layer 1402 ₁ may be etched to a top (down) of the nitride reinforcement layer 1302 ₁ . Trench 1502 may have bottom corners, illustrated as first corner 1504 and second corner 1506 . The corners can each have a radius of more than 50 nm. The trench width can be 8 µm or 4 µm reinforcement layer.

According to some implementations, additional processes may be performed, such as defining an active electrode area and a shield. Another process may involve opening ventilation holes in the ISDP (8 pm). Furthermore, the ground contact can be exposed as a donut. Furthermore, the scribe line can be exposed leaving an edge covering on the scribe line. Another process can be the definition of a chip ID.

An oxide reinforcement layer 1602 may be deposited over and adjacent to the first membrane nitride layer 1402 ₁ and over the nitride reinforcement layer 1302 ₁ as shown in FIG 16 shown. This step may also be referred to as top reinforcement layer deposition.

17 16 shows the patterning of the oxide enhancement layer 1602. As shown in the enlargement, various portions of the oxide enhancement layer 1602 may be removed (e.g., etched). After the etch, the part of the oxide reinforcement layer 1602 remains at the trench 1502 (in the enlarged section of FIG 17 labeled 1702).

A next step in the fabrication process involves the deposition of a second membrane nitride layer, as in 18 shown. The second membrane nitride layer may be an LSN film, according to some embodiments. For example, the second membrane nitride layer 1802 ₁ may be deposited adjacent to and over the first membrane nitride layer 1402 ₁ . Furthermore, the second membrane nitride layer 1802 ₁ may be deposited adjacent to and over the portion of the oxide reinforcement layer 1602 over the trench 1502 . In addition, the second membrane nitride layer 1802 ₁ may be deposited over the first LSN film 202 ₁ . Furthermore, the second membrane nitride layer 1802 ₂ may be deposited over the first membrane nitride layer 1402 ₂ on the second side 206 of the wafer.

19 shows the formation of one or more vent holes. The one or more vent holes may be formed by etching through the second membrane nitride layer 1802 ₁ and the first membrane nitride layer 1402 ₁ . As illustrated, one or more vent holes may be formed, as illustrated by first vent hole 1902, second vent hole 1904, and third vent hole 1906. Although three vent holes are illustrated and described, in some embodiments a different number of vent holes may be formed.

Next, a third oxide layer 2002 is deposited as in FIG 20 shown. The third oxide layer 2002 may be deposited over and adjacent to the second membrane nitride layer 1802 ₁ and over the first LSN film 202 ₁ (e.g., in the first region 1002 and the fifth region 1010). The third oxide layer may also be referred to as a first air-gap oxide (e.g., air-gap oxide 1).

The formation of indentations and the definition of the second lateral etch stop (LES2) can be carried out as in 21 shown. As indicated, one or more pits and the second lateral etch stop may be formed (eg, exposed) in the third oxide layer 2002 . For example, the one or more depressions and the second lateral etch stop may be formed (eg, etched) in the third oxide layer 2002 . 22 12 shows a next stage of the manufacturing process, which includes the application of a fourth oxide layer 2202. FIG. The fourth oxide layer 2202 can also be referred to as a deposition of an air-gap oxide 2 .

23 12 shows the opening of the second lateral etch stop region, which may include patterning and etching. Opening the second lateral etch stop region may include etching the third oxide layer 2002 and the fourth oxide layer 2202 .

The lateral etch stops have two corner radii shown as a first corner 2302 and a second corner 2304 . The first corner 2302 can have a radius greater than about 100 nm. The second corner 2304 can have a radius greater than 25 nm. In addition, a step width 2306 (lateral step width) can be about 4 μm. Note that the radius is towards the center of the microphone (shown at magnification 2308).

The process of forming the two radii (e.g., at the first corner 2302 and at the second corner 2304) may be a two-mask process. For example, the areas on the two outer edges can be structured. Then oxide can be deposited. The areas on the two inner edges can be defined during or after the deposition of the oxide. In this way, first the wide section and then the narrow trench are defined.

24 Figure 12 shows the deposition of backplate nitride underlayer 2402, which may be an LSN underlayer. The backplate nitride underlayer 2402 may be over and adjacent to the fourth oxide layer 2202 and adjacent to the corresponding Sections of the third oxide layer 2002 are deposited.

The backplate nitride underlayer 2402 can improve robustness in the LES 2 specification, which can be greater than about 50 nm. The backplate nitride underlayer 2402 can improve the strength of the backplate. For example, the strength of the nitride may be higher than the strength of the polysilicon in the backplate (e.g., the nitride has a much higher ultimate bending strength than polysilicon). Therefore, the nitride underlayer (e.g., backplate nitride underlayer 2402) can improve the strength of the backplate.

25 Figure 12 shows the steps of a fabrication process for depositing a first polysilicon layer on the backplate. The first backplate polysilicon layer 2502 ₁ may be deposited over and adjacent to the backplate nitride underlayer 2402 . Stress relief annealing can also be carried out. On the second side 206, the first backplate polysilicon layer 2502 ₁ may be deposited over the second membrane nitride layer 1802 ₂ . The first backplate polysilicon layer may also be referred to as the top backplate layer and is part of a rigid plate.

26 shows the deposition, patterning and etching of a fifth oxide layer. The fifth oxide layer may be a stress spreader, also referred to as an upper backplate stress spreader. The fifth oxide layer may be deposited over the first backplate polysilicon layer 2502 and etched to form two portions of the fifth oxide layer (referred to as fifth oxide layer 2602 ₁ and 2602 ₂ ). According to some embodiments, the voltage spreader may include a nitride, oxide, or other material layer.

At this stage of the manufacturing process, a (narrow) nitride layer (e.g. the fifth oxide layer 2602 ₁ and 2602 ₂ ) is placed between the two parts of the backplate (e.g. the top backplate, as in 26 described, and a second backplate layer, described below in 27 described) was added to increase the bending stiffness at the backplate hinge. The stress spreader can help make the entire structure stiffer and more robust than it would be without the stress spreader.

A second layer of polysilicon (e.g., a second backplate polysilicon layer 2702) may be deposited to form a second portion of the backplate, as shown in FIG 27 shown. The second polysilicon layer 2702 may be deposited over the first polysilicon layer 2502 and the fifth oxide layer (e.g., fifth oxide layer 2602 ₁ and 2602 ₂ ). The first backplate polysilicon layer 2502, the fifth oxide layer, and the second backplate polysilicon layer may form a rigid plate.

28 12 illustrates the definition (e.g., patterning) of the first backplate polysilicon layer 2502 and the second backplate polysilicon layer 2702. For example, the etch of the first polysilicon layer 2502 and the second polysilicon layer 2702 can be performed as shown at 2802. LSN hole structuring can also be carried out.

The integration of the opening of the contact 1 can be done during a next stage of the manufacturing process, as in FIG 29 shown. The opening of the first contact can be enabled by an oxide etch. For example, a first contact 2902 may be exposed to wafer 102 via the oxide etch. Furthermore, the second contacts 2904 ₁ and 2904 ₂ can be exposed to allow opening of the contact to the shield contact. In one example, the first oxide can be dry etched and then the nitride layer can be etched in a pattern to contact the membrane. 30 shows an LSN etch in which a second contact is integrated.

31 shows the patterning and etching of the metal deposit. One or more pieces of metal 3102 may be deposited within one or more second contacts 2904 ₁ and 2904 ₂ . Accordingly, the metal 3102 may be deposited over and adjacent to the second backplate polysilicon layer 2702, over the first backplate polysilicon layer 2502, and over the nitride reinforcement layer 1302 ₁ and the first LSN thin film 2021 (e.g., in the first contact 2902). The metal 3102 may be etched such that only portions of the metal remain at the one or more second contacts. Thus, a first portion of metal 3102 may line the bottom and sides of second contact 2904 ₁ . Furthermore, a second portion of metal 3102 may line the bottom and sides of second contact 2904 ₂ .

In a next phase of the manufacturing process, the protection of the front and the grinding can be carried out, as in 32 shown. As indicated, the front oxide protection 3202 may be deposited over and adjacent to the first backplate polysilicon layer 2502 and the metal 3102. FIG. After applying the front oxide protection 3202, the wafer can be thinned to a desired thickness. For example, the wafer can be thinned down to 350 micrometers.

Next, the backside cavity definition and etching can be performed as in 33 shown. As indicated, a 3302 resist protector can be applied to the front side. A cavity 3304 may also be defined on the back side (e.g., second side 206) of the wafer. Defining the cavity 3304 may include patterning and etching portions of the wafer 102 and corresponding portions of the backside layers (e.g., the second LSN film 202 ₂ , the MPL 802 ₂ , the second oxide layer 1102 ₂ , the nitride reinforcement layer 1302 ₂ , the first membrane nitride layer 1402 ₂ , and the second membrane nitride layer 1802 ₂ ).

The cavity 3304 can be defined between the respective centers of the front cavities (indicated by the first dashed line 602 for the first cavity 3021 and the second dashed line 604 for the second cavity 3022). According to an optional implementation, a xenon difluoride (XeF2) photoresist may be retained during a silicon removal process.

34 shows a first exposure of the defined structure (e.g. according to 1-33 fabricated structure). The first exposure (or initial exposure) may include a pre-exposure by Buffered Oxide Etch (BOE) using Buffered Oxide, which includes the removal of the resist on the front side, as in FIG 35 shown. This process can be a wet pre-exposure process. During the BOE pre-exposure, the long dimension in the 20 micron range is laterally etched. During the BOE pre-exposure, the membrane is protected by the thin polysilicon. The term "exposure" means that all sacrificial material should be removed. As in 34 shown, the resist is removed, then in the next step the sacrificial layer is removed to protect the membrane. 36 shows the membrane protective layer. A second exposure of the structure can then be made possible. This may include removing the polysilicon. The polysilicon can be removed in a xenon difluoride process. Thereafter, the front resist is removed. Furthermore, the structure can be provided with a SAM layer (Self-Assembled Monolayer).

37 FIG. 37 shows an example of a MEMS microphone 3700 according to one or more embodiments described herein. A front cavity (e.g., first cavity 3021 and second cavity 3022 ) used to control the bending of a flexible panel toward cavity 3304 is shown. Furthermore, the flexible plate does not touch at the edge of the cavity when moving towards the cavity. For example, the flexible plate moves or is deformed by a pressure wave. Controlling the movement can improve the robustness of the flexible plate when it is deformed by the pressure wave. In some embodiments, the pressure wave may have a threshold amplitude.

Additionally, membrane stops (shown as a first membrane stop 3702 and a second membrane stop 3704) can help control the flexible panel. Because the microphone can be relatively large, the front diaphragm and diaphragm stops work together to stop or limit downward movement of the flexible plate. Also shown are a lateral etch stop 3706 and a rear flex edge with lateral etch stop 3708.

The shield TP contact 3710 and a membrane node (raised to TP) 3712 are also shown on the MEMS microphone 3700. An LSN underlayer 3714 and a recess 3716 are also in 37 shown. In the MEMS microphone 3700, a membrane trench separates the active element and the shield 3718. A buried oxide for stress reduction 3720 is also present. The parasitic reduction (MEM - Boot) 3722 and the bulk/boot node 3724 are shown. The 3700 MEMS Microphone also includes an oxide diaphragm on the 3726 top reinforcement.

38 FIG. 3 shows another example of a MEMS microphone 3800 according to one or more embodiments described herein. Repeated description of similar elements used in other embodiments described herein are omitted for the sake of brevity. MEMS microphone 3800 may include one or more of the components and/or functionality of MEMS microphone 3700 and vice versa. The 3800 MEMS microphone is similar to the 3700 MEMS microphone but does not include the oxide reinforcement (e.g. the 3726 oxide reinforcement on the membrane trench). It is noted that the perforated flexible plate can improve the signal. Accordingly, a reinforcement of the ditch was planned here. The reinforcement can be made of oxide, nitride or other material.

39 FIG. 12 shows another example of a MEMS microphone according to one or more embodiments described herein. Repeated description of similar elements used in other embodiments described herein are omitted for the sake of brevity. MEMS microphone 3900 may include one or more of the components and/or functions of MEMS microphone 3700, MEMS microphone 3800, and vice versa returns include. The MEMS microphone 3900 is similar to the MEMS microphone 3800. However, the MEMS microphone 3900 includes a lower LSN gain 3902.

The individual features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or".

Furthermore, the various embodiments may be implemented as a method, apparatus, or product using standard programming and/or techniques to produce software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter. The term "product" as used herein is intended to include a computer program accessible on any computer-readable device, machine-readable device, computer-readable carrier, computer-readable medium, machine-readable medium, computer-readable (or machine-readable) storage/communications medium. Computer-readable media can include, for example, a magnetic storage medium, e.g. ray Disc™ (BD)), a smart card, a flash memory device (e.g., a card, stick, key drive), and/or a virtual device that emulates a storage medium and/or any of the above computer-readable media, include, but are not limited to Of course, those skilled in the art will appreciate that many modifications can be made to this configuration without departing from the scope or spirit of the various embodiments.

Claims (10)

A method of manufacturing a microelectromechanical system (MEMS) microphone, comprising: providing a wafer (102); applying a silicon nitride layer (202) to the wafer (102); depositing a first oxide layer (402) on a front side of the wafer (102) over the silicon nitride film (202) and over and adjacent to the wafer (102), wherein depositing adjacent to the wafer (102) includes filling one or more cavities (302) on the front side of the wafer (102) by oxide deposition; depositing a membrane protection layer (802) over the first oxide layer (402) between a first side of a first cavity (302 ₁ ) formed in the wafer (102) and a second side of a second cavity (302 ₂ ) formed in the wafer (102); depositing a second oxide layer (1102) over and adjacent the membrane protection layer (802); depositing a first membrane nitride layer (1402) over the second oxide layer (1102); depositing a membrane polysilicon layer over the first membrane nitride layer (1402); depositing a second membrane nitride layer (1802) over the membrane polysilicon layer; depositing a third oxide layer (2002) over the second membrane nitride layer (1802); depositing a fourth oxide layer (2202) over the third oxide layer (2002); opening a lateral etch stop region by etching the third oxide layer (2002) and the fourth oxide layer (2202); depositing a backplate nitride underlayer (2402) over and adjacent to the fourth oxide layer (2202) and adjacent to the third oxide layer (2002); depositing a first backplate polysilicon layer (2502) over and adjacent the backplate nitride underlayer (2402); depositing a fifth oxide layer (2602) on portions of the first backplate polysilicon layer (2502); depositing a second backplate polysilicon layer (2702) over the fifth oxide layer (2602) and the first backplate polysilicon layer (2502); depositing metal (3102) over the second backplate polysilicon layer (2702) and over the first backplate polysilicon layer (2502); applying a resist protection (3302) to the front side; defining a cavity (3304) on a back side of the wafer (102) resulting in a defined structure; performing a first step of exposing the defined structure on the front side of the wafer (102), wherein at least the resist protection (3302) is removed; removing the membrane protective layer (802); performing a second step of exposing the defined structure, removing at least polysilicon; and depositing a self-assembled monolayer coating. procedure after claim 1 further comprising: prior to depositing the first membrane nitride layer (1402), depositing a nitride reinforcement layer (1302) over and adjacent the second oxide layer (1102); and patterning the nitride reinforcement layer (1302). procedure after claim 1 , further comprising: depositing an oxide enhancement layer (1602) before depositing the second membrane nitride layer (1802); and patterning the oxide enhancement layer (1602). procedure after claim 1 , wherein depositing the membrane polysilicon layer further comprises patterning the membrane polysilicon layer and a portion of the membrane polysilicon layer. procedure after claim 4 , wherein the defining comprises forming one or more vent holes (1902, 1904, 1906) and an active electrode. procedure after claim 1 , wherein depositing the second oxide layer (1102) further comprises opening a first lateral etch stop (1202, 1204), wherein a corner radius of the first lateral etch stop (1202, 1204) is greater than 100 nanometers. procedure after claim 1 wherein depositing the fourth oxide layer (2202) comprises opening a lateral etch stop which comprises etching a first corner radius (2302) and a second corner radius (2304), wherein a step width (2306) between the first corner radius (2302) and the second corner radius (2304) is less than 4 microns. procedure after claim 7 , wherein etching the first corner radius (2302) comprises etching the first corner radius (2302) to a radius greater than 100 nanometers. procedure after claim 7 , wherein etching the second corner radius (2304) comprises etching the second corner radius (2304) to a radius greater than 25 nanometers. Microelectromechanical microphone device (3700, 3800, 3900) made according to the method of any one of Claims 1 until 9 is made.

Images