DE102021119369A1 - LEVEL SHIFT CIRCUIT AND METHOD - Google Patents

Abstract

A switching circuit includes a bias circuit and a level shifter. The bias circuit has first and second input terminals configured to receive first and second supply voltages and configured to generate a bias voltage that is the greater of a first voltage level of the first supply voltage and a second voltage level of the second has supply voltage. The level shifter includes a first PMOS transistor configured to receive the first supply voltage and a second PMOS transistor configured to receive the second supply voltage, and each of the first and second PMOS transistors has a Volume port configured to receive the bias.

Description

BACKGROUND

Integrated circuits (ICs) sometimes have multiple sections that correspond to independently controlled power supply regions. In some cases, a first power supply range has a first supply voltage level and a second power supply range has a second supply voltage level that is different than the first supply voltage level. Signals are often propagated between these sections using level shifters that shift logic levels between the first and second supply voltage levels.

In order to be able to shift the logic levels, level shifters usually have both n-metal-oxide-semiconductor (NMOS) transistors and p-metal-oxide-semiconductor (PMOS) transistors, which are used in both the first and second power supply area work.

character list

• 1A und 1B sind Schaubilder eines Pegelverschiebungsschaltkreises gemäß einigen Ausführungsformen.
• 2 ist ein Schaubild eines Pegelverschiebers gemäß einigen Ausführungsformen.
• 3A ist eine schematische Darstellung eines Vorspannungsschaltkreises gemäß einigen Ausführungsformen.
• 3B ist ein Schaubild eines IC-Layoutschaubildes und eines Pegelverschiebungsschaltkreises gemäß einigen Ausführungsformen.
• 4A ist eine schematische Darstellung eines Vorspannungsschaltkreises gemäß einigen Ausführungsformen.
• 4B ist ein Schaubild eines IC-Layoutschaubildes und eines Pegelverschiebungsschaltkreises gemäß einigen Ausführungsformen.
• 5 ist ein Schaubild eines Verfahrens zum Betreiben eines Pegelverschiebungsschaltkreises gemäß einigen Ausführungsformen.
• 6 ist ein Schaubild eines Verfahrens zum Generieren eines IC-Layoutschaubildes gemäß einigen Ausführungsformen.
• 7 ist ein Schaubild eines Verfahrens zum Herstellen eines Pegelverschiebungsschaltkreises gemäß einigen Ausführungsformen.
• 8 ist ein Blockschaubild eines IC-Layoutschaubild-Generierungssystems gemäß einigen Ausführungsformen.
• 9 ist ein Blockdiagramm eines IC-Herstellungssystems und eines damit verbundenen IC-Herstellungsflusses gemäß einigen Ausführungsformen.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. Rather, the dimensions of the various structural elements may be increased or decreased as needed for clarity of discussion.

• 1A and 1B 10 are diagrams of a level shift circuit according to some embodiments.
• 2 12 is a diagram of a level shifter according to some embodiments.
• 3A 1 is a schematic diagram of a biasing circuit according to some embodiments.
• 3B 12 is a diagram of an IC layout diagram and a level shift circuit according to some embodiments.
• 4A 1 is a schematic diagram of a biasing circuit according to some embodiments.
• 4B 12 is a diagram of an IC layout diagram and a level shift circuit according to some embodiments.
• 5 10 is a diagram of a method of operating a level shift circuit according to some embodiments.
• 6 12 is a diagram of a method for generating an IC layout diagram, according to some embodiments.
• 7 10 is a diagram of a method for fabricating a level shift circuit according to some embodiments.
• 8th 12 is a block diagram of an IC layout diagram generation system according to some embodiments.
• 9 12 is a block diagram of an IC manufacturing system and an associated IC manufacturing flow, according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. In the following, specific examples of components, values, operations, materials, configurations, or the like are described in order to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. Other components, values, operations, materials, configurations, or the like are also contemplated. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in face-to-face contact, and may also include embodiments in which additional features are formed between the first and the second structural element can be formed in such a way that the first and the second structural element are not necessarily in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and/or devices discussed.

Furthermore, spatially relative terms, such as "below,""below,""lower,""above,""upper," and the like, may be used herein for ease of description to indicate the relationship of an element or feature one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to include other orientations of the Apparatus in use or operation other than in the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees, or other orientations) and the spatially relative descriptors used herein may similarly be interpreted accordingly.

A level shift circuit includes a bias circuit and a level shifter including first and second PMOS transistors. The first and second PMOS transistors are arranged in a common n-well and are configured to operate in first and second power supply ranges, respectively. The bias circuit is configured to bias the common n-well based on the larger of a first voltage level of the first power supply region and a second voltage level of the second power supply region. By integrating the biasing circuitry designed to bias the common n-well, the level shifter circuit is able to avoid latch-up risks while compared to approaches where level shifters have PMOS transistors responsible for it configured to operate in separate power supply regions and positioned in separately biased n-wells has a smaller footprint.

1A and 1B 10 are diagrams of a level shifting circuit 100 according to some embodiments. 1A 12 is a schematic representation of the level shift circuit 100, and 1B 12 is a plan view of the level shift circuit 100 having an X-direction and a Y-direction perpendicular to the X-direction.

Level shifting circuit 100, also referred to as circuit 100 or IC 100 in some embodiments, is an IC configured to operate in first and second power supply ranges (not labeled). The first power supply domain includes a first power distribution structure including a power supply node NVDD1 configured to have a supply voltage VDD1 and a reference node NVSS configured to have a reference voltage VSS. The second power supply domain includes a second power distribution structure including the reference node NVSS and a power supply node NVDD2 configured to have a separate supply voltage VDD2 from the supply voltage VDD1.

Each of the first and second power supply sections can be operated in an on-mode or in an off-mode. In power-on mode, supply voltage VDD1 at power supply node NVDD1 has a first supply voltage level of the first power supply range and supply voltage VDD2 at power supply node NVDD2 has a second supply voltage level of the second power supply range. In power-down mode, both supply voltage VDD1 at power supply node NVDD1 and supply voltage VDD2 at power supply node NVDD2 have a reference voltage level, for example a ground voltage level, of reference voltage VSS at reference node NVSS. A voltage, for example the supply voltage VDD1, is assumed to have a certain voltage level, for example the first supply voltage level, by having a voltage level at or close to the given voltage level.

In various embodiments, the first supply voltage level is less than, equal to, or greater than the second supply voltage level.

As in 1A As shown, the level shifter circuit 100 includes a bias circuit 110 coupled to a level shifter 120 . Biasing circuit 110 has an input terminal 111 coupled to power supply node NVDD1, an input terminal 113 coupled to power supply node NVDD2, an input terminal 115 coupled to reference node NVSS, and an output terminal 112, having an n-well (n-well) NW coupled. In some embodiments, the bias circuit 110 does not have an input terminal 115 coupled to the reference node NVSS.

As in 1B As shown, the level shift circuit 100 is positioned in a substrate region 100S having an n-well NW. A substrate region, for example substrate region 100S, is part or all of a semiconductor wafer, for example a silicon (Si) wafer or an epitaxial Si layer, suitable for forming one or more IC devices. In some embodiments, a substrate region comprises a p-type semiconductor, such as Si, containing one or more acceptor dopants, such as boron (B) or aluminum (Al). An n-well, for example an n-well NW, is a portion of the semiconductor wafer that is positioned within the substrate region and has an n-semiconductor, for example Si, containing one or more donor dopants, for example phosphorus (P) or arsenic (As).

The level shifter 120 has an input terminal 121 coupled to n-well NW, an input terminal 123, an output terminal 122, and is coupled to each of the power supply nodes NVDD1 and NVDD2 and the reference node NVSS.

Two or more circuit elements are said to be coupled when there are one or more direct electrical connections and/or one or more indirect electrical connections involving one or more logic devices, such as an inverter or a logic gate, between the two or more circuit elements. In some embodiments, electrical communication between the two or more coupled circuit elements may be modified, eg, inverted or made dependent, by the one or more logic devices.

The biasing circuit 110 is thus arranged to receive at the input terminal 111 the supply voltage VDD1, at the input terminal 113 the supply voltage VDD2, and at the input terminal 115, if present, the reference voltage VSS.

The bias circuit 110 is an electronic circuit that includes two or more transistors (in the 1A and 1B not shown), for example the PMOS transistors P4 and P5 described below with respect to FIG 3A and 3B be described, or the PMOS transistors P6-P8 and the NMOS transistor N4, which are described below in relation to FIG 4A and 4B and arranged to generate a bias voltage VNW at the output terminal 112 and thereby at the n-well NW based on the greater of the voltage level of the supply voltage VDD1 and the voltage level of the supply voltage VDD2.

In some embodiments, the bias circuit 110 is configured to generate a bias voltage VNW having a bias level equal to the greater of the voltage level of the supply voltage VDD1 and the voltage level of the supply voltage VDD2. In some embodiments, the bias circuit 110 is configured to generate a bias voltage VNW having a bias level equal to a fraction of the greater of the voltage level of the supply voltage VDD1 and the voltage level of the supply voltage VDD2, for example a fraction that is the greater of the voltage level divided by a voltage divider (not shown).

In various embodiments, the biasing circuit 110 includes a biasing circuit 300, described below with reference to FIG 3A and 3B is discussed, or includes a bias circuit 400, which is discussed below with reference to FIG 4A and 4B is discussed.

As described above, the level shifter 120 is arranged to receive the supply voltages VDD1 and VDD2, the reference voltage VSS and the bias voltage VNW at the input terminal 121 and an input signal IN at the input terminal 123 and an output signal OUT at the output terminal 122 in response to the input signal IN to generate.

The input signal IN is an electronic signal arranged to vary between a logic high state corresponding to the voltage level of the supply voltage VDD1 and a logic low state corresponding to the reference voltage level of the reference voltage VSS.

The level shifter 120 is an electronic circuit that includes at least one PMOS transistor (included in the 1A and 1B not shown), for example the PMOS transistor P1 described below with reference to FIG 2 is discussed, which has a source/drain terminal (S/D terminal) arranged to receive the supply voltage VDD1, a gate arranged to receive the input signal IN, and a bulk terminal connected to the n-well NW and thereby adapted to receive the bias voltage VNW.

A bulk lead is a transistor feature that corresponds to the body region or n-well in which the transistor is located. An S/D terminal is one of two structural elements of a given transistor having portions of the body region or n-well whose doping type is opposite to that of the body region or n-well, for example a p-type S/D terminal of a PMOS transistor, which is positioned in an n-well.

The level shifter 120 has two or more additional PMOS transistors (in the 1A and 1B not shown) on, for example those relating to below 2 discussed PMOS transistors P2 and P3, each having an S / D terminal, which is adapted to the receiving supply voltage VDD2 and having a bulk terminal coupled to n-well NW configured to receive bias voltage VNW.

In some embodiments, the level shifter 120 also includes one or more NMOS transistors (in Figs 1A and 1B not shown) on, for example, the NMOS transistors N1-N3 referred to below 2 be discussed.

The level shifter 120, which includes the at least one PMOS transistor, the two or more additional PMOS transistors, and the one or more NMOS transistors (if present), is configured to generate an output signal OUT in response to the input signal IN and vary between the logic high state corresponding to the voltage level of supply voltage VDD2 and the logic low state corresponding to the reference voltage level of reference voltage VSS. In some embodiments, the output terminal 122 has two signal paths, and the level shifter 120 is configured to generate the output signal OUT as a differential signal having complementary components on the signal paths, each component between the logic high state corresponding to the voltage level of the supply voltage corresponds to VDD2 and to vary the logic low state corresponding to the reference voltage level of the reference voltage VSS.

In some embodiments, level shifter 120 includes level shifter 200, described below with respect to FIG 2A and 2 B is discussed.

As in 1B As illustrated, the level shift circuit 100 has a portion positioned inside the n-well NW and a portion positioned outside the n-well NW. The PMOS transistors of the bias circuit 110 and the level shifter 120 are positioned inside the n-well NW, and other elements of the bias circuit 110 and/or the level shifter 120, for example the one or more NMOS transistors, are outside the n-well positioned NW. In some embodiments, level shifting circuit 100 includes one or more circuit elements (not shown) in addition to those found in bias circuit 110 and level shifter 120 positioned inside and/or outside of n-well NW.

By the arrangement discussed above, the PMOS transistors of the level shift circuit 100 have diode junctions based on p-S/D terminals and n-bulk terminals corresponding to the n-well NW. The level shifting circuit 100 includes a bias circuit 110 configured to bias the n-well NW by continuously generating a bias voltage VNW having one or more bias levels large enough to forward bias the diode junctions of the PMOS transistors of the level shifter 120 to avoid.

During operation, when both the first and second power supply regions operate in the on-mode, the bias circuit 110 generates a bias voltage VNW having the bias level based on the larger of the supply voltage VDD1 having the first supply voltage level and the supply voltage VDD2, which has the second supply voltage level. When the first power supply region operates in the on mode and the second power supply region operates in the off mode, the bias circuit 110 generates a bias voltage VNW whose bias level is equal to all or a fraction of the first supply voltage level. When the first power supply region operates in the off mode and the second power supply region operates in the on mode, the bias circuit 110 generates a bias voltage VNW having the bias level whose bias level is equal to all or a fraction of the second supply voltage level.

When both the first and second power supply sections operate in the power saving mode, the bias circuit 110 generates a bias voltage VNW whose bias level is equal to the reference voltage level based on each of the power supply voltages VDD1 and VDD2 that have the reference voltage level. Because the S/D terminals of each of the PMOS transistors of the level shifter 120 are also at the reference voltage level when each of the supply voltages VDD1 and VDD2 are at the reference voltage level, forward biasing of the junction diodes of the PMOS transistors is avoided.

In some embodiments, the n-well NW is an n-well of multiple n-wells NW, the PMOS transistors of the level shift circuit 100 are positioned within the multiple n-wells NW, and the biasing circuit 110 is configured to bias each n-well NW to bias the plurality of n-wells NW, by generating a bias voltage VNW as described above so as to avoid forward biasing of the diode junctions of the PMOS transistors of the level shifter 120.

In various embodiments, each of the single n-well NW and the plurality of n-wells NW configured to be biased by the bias voltage VNW generated by the biasing circuit 110 is referred to as a common n-well of the level shifting circuit 100 .

In other approaches where level shifters have PMOS transistors configured to operate in separate power supply domains and are positioned in separately biased n-wells, the separately biased n-wells are spaced around minimum distances based on the separate power supply domain bias levels spaced apart to reduce latch-up risks. In embodiments where the common n-well comprises the single n-well NW, n-well spacing is avoided. In embodiments where the common n-well has multiple n-wells NW, the n-well spacing may be reduced compared to the n-well spacings in such other approaches because each n-well of the multiple n-wells NW is biased by the same bias voltage VNW.

By providing the above-described arrangement for the purpose of avoiding the forward biasing of PMOS diode transitions of the level shifter 120, the level shifting circuit 100 comprising the biasing circuit 110 is able to avoid latch-up risks while reducing the area required compared to approaches , in which the level shifters comprise PMOS transistors arranged to operate in separate power supply regions and positioned in separately biased n-wells.

2 12 is a schematic representation of level shifter 200 according to some embodiments. Level shifter 200 can be used as level shifter 120 as described above with respect to FIG 1A and 1B described.

Level shifter 200 has power supply nodes NVDD1 and NVDD2, reference node NVSS, input terminals 121 and 123, and output terminal 122 shown as signal paths 122A and 122B, as above with respect to FIG 1A and 1B described. The level shifter 200 is thereby configured to receive the supply voltage VDD1 at the power supply node NVDD1, the supply voltage VDD2 at the power supply node NVDD2, the reference voltage VSS at the reference node NVSS, the bias voltage VNW at the input terminal 121 and the signal IN at the input terminal 123, each as related above on the 1A and 1B described.

Level shifter 200 also includes PMOS transistors P1-P3, NMOS transistors N1-N3, and node ND1. The PMOS transistor P1, the node ND1 and the NMOS transistor N1 are connected in series between the power supply node NVDD1 and the reference node NVSS, and the gates of the PMOS transistor P1 and the NMOS transistor N1 are coupled to each other and to the input terminal 123 . The PMOS transistor P1 and the NMOS transistor N1 are thereby configured as an inverter configured to invert the signal IN received at the input terminal 123 and output the inverted signal IN at the node ND1 during operation.

PMOS transistor P2, signal path 122A and NMOS transistor N2 are connected in series between power supply node NVDD2 and reference node NVSS, a gate of PMOS transistor P2 is coupled to signal path 122B, and a gate of NMOS transistor N2 is coupled to node ND1. PMOS transistor P3, signal path 122B and NMOS transistor N3 are connected in series between power supply node NVDD2 and reference node NVSS, a gate of PMOS transistor P3 is coupled to signal path 122A, and a gate of NMOS transistor N3 is coupled to the input port 123 .

The PMOS transistors P2 and P3 and the NMOS transistors N2 and N3 are thereby arranged to receive, during operation, the input signal IN at input terminal 123 and the inverted input signal IN at node ND1 and the output signal OUT as complementary components OUTA on the signal path 122A and OUTB on the signal path 122B, as above with reference to FIG 1A and 1B described.

A bulk terminal of each of the PMOS transistors P1-P3 is coupled to the input terminal 121 and thereby configured to receive a bias voltage VNW. In various embodiments, the bulk terminals of the PMOS transistors P1-P3 are coupled to a same input terminal 121, which is coupled to a single n-well NW, and are thereby arranged to receive the bias voltage VNW, or they are to multiple input terminals 121 coupled with multiple n-wells NW are coupled and are thereby arranged to receive the bias voltage VNW.

A bulk terminal of each of the NMOS transistors N1-N3 is coupled to the reference node NVSS and is thereby configured to receive the reference voltage VSS.

By the arrangement discussed above, the level shifter 200 has characteristics in accordance with those discussed above in relation to the level shifter 120 such that the circuit 100 comprising the level shifter 200 is capable of the above in relation to the 1A and 1B achieve the benefits discussed.

3A and 4A 10 are schematic representations of respective biasing circuits 300 and 400 according to some embodiments. Any of the bias circuits 300 and 400 can be used as the bias circuit 110 described above with respect to FIG 1A and 1B was described.

3B FIG. 12 is a diagram of an IC layout diagram 100A and a corresponding embodiment of the level shifting circuit 100 described above with respect to FIG 1A and 1B has been discussed, of the level shifter 200 discussed above with respect to 2 was discussed, and includes the biasing circuit 300, according to some embodiments. 4B 10 is a diagram of an IC layout diagram 100B and a corresponding embodiment of level shifting circuit 100 including level shifter 200 and biasing circuit 400, according to some embodiments. 3B and 4B 12 show plan views of the level shift circuit 100 and respective IC layout diagrams 100A and 100B each having n-wells NW positioned in the substrate region 100S and in the X and Y directions, respectively, referenced above with respect to FIG 1B were discussed.

Each of the IC layout diagrams 100A and 100B is a non-limiting example of an IC layout diagram generated by performing part or all of a method 600 described below with respect to FIG 6 is discussed, and each corresponding embodiment of the level shifting circuit 100 is a non-limiting example of an IC structure that is manufactured based on the IC layout diagram 100A or 100B by performing part or all of a method 700, which is described below with reference to FIG 7 is discussed.

The diagrams of 3B and 4B are simplified for the purpose of illustration. 3B and 4B 12 show views of the IC layout diagram 100A or 100B and the level shift circuit 100 with various structural elements added or omitted for the purpose of simplifying the following discussion. In various embodiments, one or more of the IC layout diagrams 100A or 100B or the level shifting circuit 100 in addition to those shown in FIGS 3B and 4B elements shown include one or more elements corresponding to metal interconnects, contacts, vias, gate structures, S/D structures, or other transistor elements, wells, isolation structures, or the like.

The bias circuit 300 comprises the power supply nodes NVDD1 and NVDD2 and the output terminal 112 and is thereby configured to receive the supply voltage VDD1 at the power supply node NVDD1 and the supply voltage VDD2 at the power supply node NVDD2, respectively, which are described above in relation to the 1A and 1B were discussed.

The bias circuit 300 also includes PMOS transistors P4 and P5. PMOS transistor P4 is coupled between power supply node NVDD1 and output terminal 112 , a gate of transistor P4 is coupled to power supply node NVDD2 , and a bulk terminal of transistor P4 is coupled to output terminal 112 . PMOS transistor P5 is coupled between power supply node NVDD2 and output terminal 112 , a gate of transistor P5 is coupled to power supply node NVDD1 , and a bulk terminal of transistor P5 is coupled to output terminal 112 .

The PMOS transistors P4 and P5 are thus designed as cross-coupled PMOS transistors in which both a first S/D connection of the PMOS transistor P4 and the gate of the PMOS transistor P5 are set up to receive a supply voltage VDD1, and both a first S/D terminal of the PMOS transistor P5 and the gate of the PMOS transistor P4 are arranged to receive a supply voltage VDD2.

The second S/D terminals of the PMOS transistors P4 and P5 are coupled to each other and to the output terminal 112 . In some embodiments, the second S/D terminals of PMOS transistors P4 and P5 are a same S/D terminal shared by PMOS transistors P4 and P5. In some embodiments, the output corresponds to an terminal 112 of the n-well NW in which the PMOS transistors P4 and P5 are positioned.

In some embodiments, when both the first and second power supply regions operate in on-mode, the first supply voltage level of supply voltage VDD1 is greater than the second supply voltage level of supply voltage VDD2 by an order of magnitude greater than a threshold voltage of PMOS transistor P4. When the first power supply region operates in the on mode and the second power supply region operates in the off mode, the first supply voltage level of the supply voltage VDD1 is greater than the reference voltage level of the supply voltage VDD2 by an order of magnitude greater than the threshold voltage of the PMOS transistor P4. In such embodiments, when the first power supply region is operating in the on-mode, the bias circuit 300 is configured such that the PMOS transistor P4 is turned on and the PMOS transistor P5 is turned off, regardless of the on or off mode of the second power supply region.

In some embodiments, when both the first and second power supply regions operate in on-mode, the second supply voltage level of supply voltage VDD2 is greater than the first supply voltage level of supply voltage VDD1 by an order of magnitude greater than a threshold voltage of PMOS transistor P5. When the second power supply region operates in the on mode and the first power supply region operates in the off mode, the second supply voltage level of the supply voltage VDD2 is greater than the reference voltage level of the supply voltage VDD1 by an order of magnitude greater than the threshold voltage of the PMOS transistor P5. In such embodiments, when the second power supply region operates in the on-mode, the bias circuit 300 is configured such that the PMOS transistor P5 turns on and the PMOS transistor P4 turns off, regardless of the on or off mode of the first power supply region.

Because an S/D terminal of PMOS transistor P4 is coupled to output terminal 112, the combination of PMOS transistor P4 turning on and PMOS transistor P5 turning off couples output terminal 112 to power supply node NVDD1, thereby biasing voltage VNW is generated at the output terminal 112, which has the first supply voltage level of the supply voltage VDD1. Because an S/D terminal of PMOS transistor P5 is coupled to output terminal 112, the combination of PMOS transistor P5 turning on and PMOS transistor P4 turning off couples output terminal 112 to power supply node NVDD2, thereby biasing voltage VNW is generated at the output terminal 112, which has the second supply voltage level of the supply voltage VDD2.

In each of the embodiments discussed above, the biasing circuit 300 is configured such that when the first power supply domain is operating in the off mode, the biasing circuit 300 generates a bias voltage VNW at the output terminal 112 having the voltage level of the supply voltage VDD2 and when the second power supply domain is in the off mode operates, the biasing circuit 300 generates a bias voltage VNW at the output terminal 112 having the voltage level of the supply voltage VDD1. When both the first and second power supply domains operate in the off mode, the bias circuit 300 is thereby configured to generate a bias voltage VNW at the output terminal 112 that has the reference voltage level of each of the supply voltages VDD1 and VDD2.

in the in 3B In the illustrated embodiment, each of the PMOS transistors P1-P3 of the level shifter 200 and the PMOS transistors P4 and P5 of the bias circuit 300 is positioned in the n-well NW, and each of the NMOS transistors N1-N3 of the level shifter 200 is in the substrate region 100S positioned outside the n-well NW.

An n-well, for example n-well NW, refers both to a region in an IC layout diagram, for example IC layout diagram 100A, and to that portion of the semiconductor wafer positioned within the substrate region shown above in relation to 1B and is defined at least in part by the IC layout region involved in a manufacturing process.

A transistor, for example a PMOS transistor P1-P5 or an NMOS transistor N1-N3, refers both to a plurality of regions in the IC layout diagram and to an IC device defined at least in part by the plurality of IC layout diagrams. Regions are defined that are included in the manufacturing process. in the in 3B illustrated embodiment, a transistor has an active region AR, one or more gate regions GR and one or more conductive regions CR, wherein a representative subset is labeled with respect to the NMOS transistor N1.

An active region, for example an active region AR, refers both to a region in the IC layout diagram and to a resulting structure defined at least in part by the region involved in the manufacturing process. The structure is a contiguous volume of one or more layers of one or more semiconductor materials that are either n- or p-doped. In various embodiments, an active region structure includes one or more of Si, silicon germanium (SiGe), silicon carbide (SiC), B, P, As, Al, gallium (Ga), or other suitable material. In some embodiments, an active region structure comprises a single monolayer or multiple monolayers of a given material.

In various embodiments, an active region structure includes one or more sections comprised in one or more of a planar transistor, a fin field effect transistor (FinFET), or a gate all-around transistor (GAA transistor). and/or has one or more S/D structures (not shown). In some embodiments, an active region structure is electrically isolated from other elements in a semiconductor substrate region by one or more isolation structures (not shown), for example one or more Shallow Trench Isolation (STI) structures.

A gate region, for example a gate region GR, refers both to a region in the IC layout diagram and to a resulting structure defined at least in part by the region involved in the manufacturing process. A gate region structure is a volume overlying the semiconductor substrate and the active region and containing one or more conductive materials substantially surrounded by one or more dielectric layers (not shown) containing one or more dielectric materials that configured to electrically isolate the one or more conductive materials from overlying, underlying, and/or adjacent structures, for example, the active region AR.

Conductive materials include one or more of polysilicon, Al, copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals, and/or one or more other suitable materials. Dielectric materials include one or more of silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), and/or a dielectric material, for example a dielectric material having a high k greater than 3.8 or 7.0 such as aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ) or titanium oxide (TiO ₂ ), or other suitable material.

In some cases, a location where a gate region intersects an active region in the IC layout diagram corresponds to a transistor in the IC structure that some or all of portions of the corresponding gate structure, part or all of the corresponding active region partially surrounded by and/or bordering the respective gate structure, as well as S/D structures in and/or on the respective active region and adjacent to the respective gate structure. In other cases, a gate region intersects an active region at a location that does not correspond to a transistor, and the corresponding gate structure or a portion thereof is referred to as a dummy gate structure in some embodiments.

A conductive region, for example a conductive region CR, refers both to a region in the IC layout diagram and to a resulting structure defined at least in part by the region involved in the manufacturing process. A conductive region structure, also referred to as a conductive segment, line, or via in some embodiments, is one or more portions of one or more corresponding layers that include one or more conductive materials suitable for electrical connection to establish a low resistance between elements of an IC structure, that is, a resistance level below a predetermined threshold corresponding to one or more tolerance levels of a resistance-related effect on circuit performance. In some embodiments, a conductive region refers to multiple conductive regions in the IC layout diagram and corresponding multiple resulting structures, for example, a conductive segment and a via.

In some embodiments, one or more conductive regions correspond to a node, for example one or more of the reference node NVSS and the power supply node NVDD1 or NVDD2 described above with respect to FIG 1A-2 were discussed, and the power supply node NVDDA or NVDDB, which are discussed below in relation to the 4A and 4B be discussed. In some embodiments, one or more conductive regions correspond to one or more portions of a power distribution structure, for example a power distribution structure of a power supply area as above in relation to FIG 1A and 1B was discussed.

in the in 3B In the illustrated embodiment, IC layout diagram 100A includes n-well NW, active regions AR, gate regions GR, and conductive regions CR arranged by at least partially including PMOS transistors P1-P3 and NMOS transistors N1 -N3 configured in accordance with level shifter 200, and define PMOS transistors P4 and P5 configured in accordance with bias circuit 300, which corresponds to the embodiment of level shifter circuit 100 discussed above. In some embodiments, the layout diagram 100A includes n-wells NW, active regions AR, gate regions GR, and conductive regions CR arranged differently, for example by integrating multiple n-wells NW arranged as a common n-well , relating to the above 1B was discussed, such that PMOS transistors P1-P3 and NMOS transistors N1-N3 are arranged according to the level shifter 200, and PMOS transistors P4 and P5 are arranged according to the bias circuit 300, which corresponds to the embodiment of the level shifter circuit 100 discussed above.

By the means discussed above, biasing circuit 300 is capable of generating a bias voltage VNW having the voltage level discussed above with respect to biasing circuit 110 such that circuit 100 comprising biasing circuit 300 is capable of the above in relation to the 1A and 1B achieve the benefits discussed.

Biasing circuit 400 includes reference node NVSS and output terminal 112 and is thereby configured to receive reference voltage VSS at reference node NVSS, each described above with respect to FIGS 1A and 1B were discussed. The bias circuit 400 also has a power supply node NVDDA arranged to have a supply voltage VDDA and a power supply node NVDDB arranged to have a supply voltage VDDB.

In some embodiments, the power supply nodes NVDDA and NVDDB correspond to respective power supply nodes NVDD1 and NVDD2 described above with respect to FIG 1A and 1B were discussed, such that the biasing circuit 400 is thereby configured to receive the supply voltage VDDA, which corresponds to the supply voltage VDD1 at the power supply node NVDDA, and the supply voltage VDDB, which corresponds to the supply voltage VDD2 at the power supply node NVDDB. In some embodiments, the power supply nodes NVDDA and NVDDB correspond to respective power supply nodes NVDD2 and NVDD1, such that the bias circuit 400 is thereby configured to supply the supply voltage VDDA, which corresponds to the supply voltage VDD2 at the power supply node NVDDA, and the supply voltage VDDB, which corresponds to the supply voltage VDD1 at the power supply node NVDDB corresponds to receive.

When both the first and second power supply sections are operated in the on-mode, the supply voltage VDDB has a higher voltage level than the supply voltage VDDA.

Biasing circuit 400 also includes PMOS transistors P6-P8, NMOS transistor N4, and node ND2. The PMOS transistor P6, the node ND2 and the NMOS transistor N4 are connected in series between the power supply node NVDDA and the reference node NVSS, and gates of the PMOS transistor P6 and the NMOS transistor N4 are coupled to each other and to the power supply node NVDDB; the PMOS transistor P6, the node ND2 and the NMOS transistor N4 are thereby formed as an inverter arranged to receive the supply voltage VDDB. A bulk terminal of PMOS transistor P6 is coupled to output terminal 112 and a bulk terminal of NMOS transistor N4 is coupled to reference node NVSS.

PMOS transistor P7 is coupled between power supply node NVDDB and output terminal 112 , a gate of transistor P7 is coupled to node ND2 , and a bulk terminal of transistor P7 is coupled to output terminal 112 . PMOS transistor P8 is coupled between power supply node NVDDA and output terminal 112 , a gate of transistor P8 is coupled to power supply node NVDDB , and a bulk terminal of transistor P8 is coupled to output terminal 112 .

The S/D terminals of the PMOS transistors P7 and P8 are coupled together and to the output terminal 112 . In some embodiments, the S/D terminals of PMOS transistors P7 and P8 are a same S/D terminal shared by PMOS transistors P7 and P8. In some embodiments ent speaks the output terminal 112 of the n-well NW in which the PMOS transistors P7 and P8 are positioned.

When the power supply range corresponding to the power supply voltage VDDB (supply voltage VDDB range) operates in the on mode, the voltage level of the power supply voltage VDDB is greater than the reference voltage level of the reference voltage by an order of magnitude greater than a threshold voltage of the NMOS transistor N4 VSS, causing the NMOS transistor N4 to turn on regardless of the on or off mode of the power supply range corresponding to the supply voltage VDDA (supply voltage VDDA range). Because the supply voltage VDDB has a higher voltage level than the supply voltage VDDA regardless of the on or off mode of the supply voltage VDDA section, the supply voltage VDDB operating in the on mode causes each of the PMOS transistors P6 and P8 to turn on regardless of the on or off mode of the supply voltage -VDDA area is switched off.

Turning on NMOS transistor N4 and turning off PMOS transistor P6 couples node ND2 to reference node NVSS and decouples node ND2 from power supply node NVDDA such that voltage VND2 at node ND2 has the reference voltage level. The voltage level of supply voltage VDDB being greater than the reference voltage level by an order of magnitude greater than a threshold voltage of PMOS transistor P7 causes PMOS transistor P7 to turn on. When the supply voltage VDDB section operates in the on mode, this turns on the PMOS transistor P7 and turns off the PMOS transistor P8, regardless of the on or off mode of the supply voltage VDDA section.

Because an S/D terminal of PMOS transistor P7 is coupled to output terminal 112, the combination of turning on PMOS transistor P7 and turning off PMOS transistor P8 couples output terminal 112 to power supply node NVDDB, and bias circuit 400 is thereby arranged to generate at the output terminal 112 a bias voltage VNW having the voltage level of the supply voltage VDDB regardless of the switch-on or switch-off mode of the supply voltage VDDA range.

When the supply voltage VDDA section operates in the on mode and the supply voltage VDDB section operates in the off mode, the supply voltage VDDB having the reference voltage level causes the NMOS transistor N4 to turn off. When the voltage level of power supply voltage VDDA is greater than the reference voltage level of power supply voltage VDDB by an order of magnitude greater than a threshold voltage of PMOS transistors P6 and P8, this causes each of PMOS transistors P6 and P8 to turn on.

Turning off NMOS transistor N4 and turning on PMOS transistor P6 couple node ND2 to power supply node NVDDA and decouple node ND2 from reference node NVSS such that voltage VND2 at node ND2 has the voltage level of supply voltage VDDA. If the voltage level of the supply voltage VDDA is greater than the reference voltage level of the supply voltage VDDB, this causes the PMOS transistor P7 to turn off. When the supply voltage VDDA section operates in the on mode and the supply voltage VDDB section operates in the off mode, the PMOS transistor P8 is thereby turned on and the PMOS transistor P7 is thereby turned off.

Because an S/D terminal of PMOS transistor P8 is coupled to output terminal 112, the combination of turning on PMOS transistor P8 and turning off PMOS transistor P7 couples output terminal 112 to power supply node NVDDA, and bias circuit 400 is thereby arranged to generate at the output terminal 112 a bias voltage VNW having the voltage level of the supply voltage VDDA when the supply voltage VDDA domain operates in on-mode and the supply voltage VDDB domain operates in off-mode.

When both the supply voltage VDDA domain and the supply voltage VDDB domain are operating in the off mode, the bias circuit 400 is thereby configured to generate a bias voltage VNW at the output terminal 112 having the reference voltage level.

in the in 4B In the illustrated embodiment, each of the PMOS transistors P1-P3 of the level shifter 200 and the PMOS transistors P6-P8 and P5 of the bias circuit 400 is positioned in the n-well NW, and each of the NMOS transistors N1-N3 of the level shifter 200 and the NMOS transistor N4 of the bias circuit 400 are positioned in the substrate region 100S outside the n-well NW.

in the in 4B In the illustrated embodiment, IC layout diagram 100B includes n-well NW, active regions AR, gate regions GR, and conductive regions CR arranged by at least partially including PMOS transistors P1-P3 and NMOS transistors N1 -N3 configured in accordance with level shifter 200, and define PMOS transistors P6-P8 and NMOS transistor N4 configured in accordance with bias circuit 400, which corresponds to the embodiment of level shifter circuit 100 discussed above. In some embodiments, the layout diagram 100B includes n-wells NW, active regions AR, gate regions GR, and conductive regions CR arranged differently, for example by integrating multiple n-wells NW arranged as a common n-well , relating to the above 1B such that PMOS transistors P1-P3 and NMOS transistors N1-N3 are configured according to level shifter 200, and PMOS transistors P6-P8 and NMOS transistor N4 are configured according to bias circuit 400, which is the one discussed above Embodiment of the level shift circuit 100 corresponds.

By the means discussed above, biasing circuit 400 is capable of generating a bias voltage VNW having the voltage level discussed above with respect to biasing circuit 110 such that circuit 100 comprising biasing circuit 400 is capable of the above in relation to the 1A and 1B achieve the benefits discussed.

Compared to the bias circuit 300, the bias circuit 400 has additional structural elements and is thereby further able to generate a bias voltage VNW having the voltage levels discussed above with respect to the bias circuit 110 in embodiments in which the supply voltage VDDB, corresponding to one of the supply voltages VDD1 and VDD2 has a voltage level greater than that of the supply voltage VDDA corresponding to the corresponds to another of the supply voltages VDD1 and VDD2.

5 5 is a flow diagram of a method 500 for operating a level shifting circuit according to one or more embodiments. The method 500 can be used with a level shifting circuit, for example the circuit 100 described above with respect to FIG 1A and 1B was discussed.

The order in which the operations of the method 500 in 5 shown is for illustrative purposes only; the operations of method 500 may also be performed in orders different from those in 5 differentiate. In some embodiments, operations are performed in addition to those in 5 Operations shown before, between, during and/or after the in 5 operations shown performed.

In some embodiments, some or all of the operations of method 500 are a subset of a method of operating a circuit that includes level shifting circuitry, such as input-output circuitry or power supply or sleep mode control circuitry.

At operation 510, first and second supply voltages are received in a bias circuit. Receiving the first supply voltage includes receiving the first supply voltage having a first voltage level equal to a first supply voltage level of a first power supply range or a reference voltage level. In some embodiments, receiving the first supply voltage having the first voltage level equal to the first supply voltage level includes operating the first power supply section in an on-mode, and receiving the first supply voltage having the first voltage level equal to the reference voltage level , includes operating the first power supply section in an off mode.

Receiving the second supply voltage includes receiving the second supply voltage having a second voltage level equal to a second supply voltage level of a second power supply range or the reference voltage level. In some embodiments, receiving the second supply voltage having the second voltage level equal to the second supply voltage level comprises operating the second power supply section in power-on mode, and receiving the second supply voltage having the second voltage level equal to the reference voltage level. includes operating the second power supply domain in the off mode.

Receiving the first and second supply voltages having the first voltage level equal to the first supply voltage level and/or having the second voltage level equal to the second supply voltage level includes the first supply voltage level being different than the second supply voltage level.

In some embodiments, receiving the first and second supply voltages in the biasing circuit includes receiving the supply voltages VDD1 and VDD2 in one of the biasing circuit 110, as described above with respect to FIG 1A and 1B discussed, or the biasing circuit 300 as discussed above with respect to FIG 3A and 3B discussed. In some embodiments, receiving the first and second supply voltages in the biasing circuit includes receiving the supply voltages VDDA and VDDB in the biasing circuit 400, as above with respect to FIG 4A and 4B discussed.

In some embodiments, receiving the first and second supply voltages in the bias circuit includes receiving the first and second supply voltages at S/D terminals of the PMOS transistors of the bias circuit. In some embodiments, receiving the first and second supply voltages in the bias circuit includes receiving the supply voltages VDD1 and VDD2 at S/D terminals of the PMOS transistors P4 and P5 of the bias circuit 300 described above with reference to FIG 3A and 3B or the supply voltages VDDA1 and VDDB at S/D terminals of the PMOS transistors P6-P8 of the bias circuit 400 discussed above with respect to FIG 4A and 4B was discussed.

At operation 520, the bias circuit is used to generate a bias voltage based on the greater of the first voltage level of the first supply voltage and the second voltage level of the second supply voltage. In various embodiments, generating the bias includes generating the bias having a bias level equal to the greater of the first and second voltage levels or having a bias level equal to a fraction of the greater of the first and second voltage levels.

In some embodiments, generating the bias includes operating both the first and second power supply domains in on-mode and generating the bias having the first voltage level based on the first voltage level being greater than the second voltage level, or generating the bias voltage having the second voltage level based on the second voltage level being greater than the first voltage level.

In some embodiments, generating the bias includes operating the first power supply domain in on-mode and operating the second power supply domain in off-mode and generating the bias voltage having the first voltage level based on the first voltage level being greater than the reference voltage level.

In some embodiments, generating the bias voltage includes operating the first power supply region in the off mode and operating the second power supply region in the on mode and generating the bias voltage having the second voltage level based on the second voltage level being greater than the reference voltage level.

In some embodiments, generating the bias includes operating both the first and second power supply domains in the off mode and generating the bias having the reference voltage level based on each of the first and second supply voltages having the reference voltage level.

In some embodiments, generating the bias voltage using the bias circuit includes generating the bias voltage VNW using one of the bias circuit 110 described above with respect to FIG 1A and 1B has been discussed, of the biasing circuit 300 described above with respect to FIG 3A and 3B and the biasing circuit 400 discussed above with respect to FIG 4A and 4B .

In some embodiments, generating the bias using the bias circuit includes using two PMOS transistors of the bias circuit, where the two PMOS transistors are positioned in a common n-well and have S/D terminals that are coupled together. Included in some embodiments using the PMOS transistors positioned in the common n-well and having S/D terminals coupled together, using an S/D terminal shared by the two PMOS transistors. In some embodiments, using the two PMOS transistors positioned in the common n-well includes using the two PMOS transistors positioned in the n-well NW or multiple n-wells NW described above in relation to the 1A-4B were discussed.

In some embodiments, generating the bias voltage using the two PMOS transistors having S/D terminals coupled together includes generating the bias voltage having the first voltage level by turning on one of the two PMOS transistors, and generating the Biasing having the second voltage level by turning on the other of the two PMOS transistors.

In some embodiments, generating the bias using the two PMOS transistors having S/D terminals coupled together includes using the PMOS transistors P4 and P5 of the bias circuit 300 described above with respect to FIG 3A and 3B or the PMOS transistors P7 and P8 of the bias circuit 400 discussed above with respect to FIG 4A and 4B was discussed.

At operation 530, the first supply voltage is received at a first S/D terminal of a first PMOS transistor of a level shifter. Receiving the first supply voltage at the first S/D terminal of the first PMOS transistor of the level shifter includes positioning the first PMOS transistor in the common n-well, for example the n-well NW or the multiple n-wells NW is related to the above 1A-4B were discussed.

In some embodiments, receiving the first supply voltage at the first S/D terminal of the first PMOS transistor of the level shifter includes receiving the supply voltage VDD1 at the level shifter 120 described above with respect to FIGS 1A and 1B was discussed. In some embodiments, receiving the first supply voltage at the first S/D terminal of the first PMOS transistor of the level shifter includes receiving the supply voltage VDD1 at the S/D terminal of the PMOS transistor P1 of the level shifter 200 described above with respect to FIG 2 was discussed.

In some embodiments, receiving the first supply voltage at the first S/D terminal of the first PMOS transistor includes receiving the first supply voltage in an inverter having the first PMOS transistor. In some embodiments, receiving the first supply voltage in the inverter includes receiving the supply voltage VDD1 at the S/D terminal of the PMOS transistor P1, which is connected in series with the NMOS transistor N1, as above with respect to FIG 2 discussed.

At operation 540, the second supply voltage is received at a second S/D terminal of a second PMOS transistor of the level shifter. Receiving the second supply voltage at the second S/D terminal of the second PMOS transistor of the level shifter includes the second PMOS transistor in the common n-well, for example the n-well NW or the multiple n-wells NW, is positioned in relation to the above 1A-4B were discussed.

In some embodiments, receiving the second supply voltage at the second S/D terminal of the first PMOS transistor of the level shifter includes receiving the supply voltage VDD2 at the level shifter 120 described above with respect to FIGS 1A and 1B was discussed. In some embodiments, receiving the second supply voltage at the second S/D terminal of the second PMOS transistor of the level shifter includes receiving the supply voltage VDD2 at the S/D terminal of the PMOS transistor P2 or P2 of the level shifter 200 described above in in reference to 2 was discussed.

In some embodiments, receiving the second supply voltage at the second S/D terminal of the second PMOS transistor includes receiving the second supply voltage at a cross-coupled transistor pair that includes the second PMOS transistor. In some embodiments, receiving the second supply voltage at the cross-coupled transistor pair includes receiving the supply voltage VDD2 at the S/D terminal of one of the cross-coupled PMOS transistors P2 and P3, as above with respect to FIG 2 discussed.

At operation 550, the bias voltage is used to bias the common n-well comprising the first and second PMOS transistors. Included in some embodiments using the bias voltage to bias the common n-well; using the bias voltage VNW to bias the n-well NW as above with respect to FIG 1A-4B discussed.

In some embodiments, using the bias voltage to bias the common n-well includes operating both the first and second power supply regions in on-mode and using the bias voltage having the first voltage level based on the first voltage level being greater than the second voltage level, or using the bias voltage having the second voltage level based on the second voltage level being greater than the first voltage level.

In some embodiments, operating both the first and second power supply sections in power-up mode includes receiving an input signal at an input terminal of the level shifter and, in response to the input signal, generating an output signal at an output terminal of the level shifter. In some embodiments, receiving the input signal includes receiving the input signal IN described above with respect to the 1A-2 was discussed. In some embodiments, generating the output signal includes generating the output signal OUT, described above with respect to the 1A-2 has been discussed, or generating complementary components OUTA and OUTB, discussed above with respect to 2 were discussed.

In some embodiments, using the bias voltage to bias the common n-well includes operating the first power supply region in on-mode and operating the second power supply region in off-mode and using the bias voltage having the first voltage level based on the first voltage level is greater than the reference voltage level.

In some embodiments, using the bias voltage to bias the common n-well includes operating the first power supply region in the off mode and operating the second power supply region in the on mode and using the bias voltage having the second voltage level based on the second voltage level is greater than the reference voltage level.

In some embodiments, using the bias voltage to bias the common n-well includes operating both the first and second power supply regions in the off mode and using the bias voltage having the reference voltage level based on each of the first and second supply voltages has the reference voltage level,

In some embodiments, using the bias voltage to bias the common n-well includes reverse-biasing diode junctions of the first and second PMOS transistors. In some embodiments, the reverse-biased diode junctions of the first and second PMOS transistors comprise the reverse-biased diode junctions of the PMOS transistors P1-P3 of the level shifter 200 described above with respect to FIG 2 was discussed.

By performing some or all of the operations of the method 500, a bias voltage is generated by a bias circuit and used to bias a common n-well in which PMOS transistors of a level shifter operate, thereby realizing advantages as discussed above with respect to the level shifter circuit 100.

6 6 is a flowchart of a method 600 for generating an IC layout diagram, according to some embodiments. In some embodiments, generating the IC layout diagram includes generating an IC layout diagram, for example an IC layout diagram 100A or 100B, that corresponds to a level shifting circuit 100 that was manufactured based on the generated IC layout diagram, as described above in relation to FIG the 1A-4B discussed.

In some embodiments, part or all of method 600 is performed by a processor of a computer. In some embodiments, part or all of the method 600 is performed by a processor 802 of an IC layout diagram generation system 800 described below with respect to FIG 8th is discussed.

Some or all of the operations of method 600 may be performed as part of a design process performed at a design house, for example design house 920 described below with respect to FIG 9 is discussed.

In some embodiments, the operations of the method 600 are described in FIG 6 performed in the order shown. In some embodiments, the operations of the method 600 are performed concurrently and/or at a different time order than the in 6 executed in the order shown. In some embodiments, one or more operations are performed before, between, during, and/or after performing one or more operations of method 600.

At operation 610, in some embodiments, first through fourth PMOS transistors are defined in an n-well region. Defining the first through fourth PMOS transistors includes, at least in part, defining each of the first through fourth PMOS transistors by arranging a plurality of IC layout diagram regions in the IC layout diagram. In some embodiments, arranging the plurality of IC layout diagram regions includes arranging active regions AR in the n-well NW and intersecting active regions AR with gate regions GR, each described above with reference to FIGS 3B and 4B were discussed.

In some embodiments, defining the first through fourth PMOS transistors in the n-well region includes defining the first through fourth PMOS transistors in the n-well region NW, described above with respect to FIG 1A-5 was discussed. In some embodiments, defining the first through fourth PMOS transistors in the n-well region NW includes defining the first through fourth PMOS transistors in a common n-well region that has multiple n-wells NW.

In some embodiments, defining the first and the second of the first through fourth PMOS transistors includes defining the PMOS transistors P4 and P5 described above with respect to the biasing circuit 300 and the 3A and 3B were discussed. In some embodiments, defining the first and the second of the first through fourth PMOS transistors includes defining the PMOS transistors P6-P8 described above with respect to the biasing circuit 400 and the 4A and 4B were discussed.

In some embodiments, defining the third and fourth of the first through fourth PMOS transistors includes defining PMOS transistors P1-P3, as described above with respect to FIG 2-4B were discussed.

In some embodiments, defining the first to fourth PMOS transistors in the n-well region includes defining one or more NMOS transistors outside the n-well region, for example the NMOS transistors N1-N3 of referenced above on the 2-4B have been discussed and/or the NMOS transistor N4 discussed above with respect to FIG 4A and 4B was discussed.

At operation 620, a plurality of conductive regions are arranged whereby a bias circuit is configured to include the first and second PMOS transistors and a level shifter is configured to include the third and fourth PMOS transistors. In some embodiments, setting up the biasing circuit to include the first and second PMOS transistors includes setting up the biasing circuit 110 described above with respect to FIG 1A and 1B was discussed. In some embodiments, configuring the biasing circuit to include the first and second PMOS transistors includes configuring the biasing circuit 300 to include the PMOS transistors P4 and P5 described above with respect to FIG 3A and 3B were discussed. In some embodiments, configuring the biasing circuit to include the first and second PMOS transistors includes configuring the biasing circuit 400 to include the PMOS transistors P6-P8 described above with respect to FIG 4A and 4B were discussed.

In some embodiments, setting up the level shifter to include the third and fourth PMOS transistors includes setting up the level shifter 120 described above with respect to FIG 1A and 1B was discussed. In some embodiments, configuring the level shifter to include the third and fourth PMOS transistors includes configuring the level shifter 200 to include the PMOS transistors P1-P3 described above with respect to FIG 2-4B were discussed.

Arranging the plurality of conductive regions includes at least in part defining conductive structures by arranging the plurality of conductive regions in the IC layout diagram. In some embodiments, arranging the plurality of conductive regions includes arranging conductive regions CR described above with respect to FIG 3B and 4B were discussed.

At operation 630, a plurality of conductive elements are arranged whereby a first power supply region has electrical connections to each of the first and third PMOS transistors and a second power supply region has electrical connections to each of the second and fourth PMOS transistors. Arranging the plurality of conductive elements includes that Arranging conductive regions corresponding to each of the first and second power supply regions, thereby at least partially defining electrical connections to S/D structures of each of the first through fourth PMOS transistors.

In some embodiments, arranging the plurality of conductive elements includes establishing a first power supply domain power distribution structure to include power supply node NVDD1 and a second power supply domain power distribution structure to include power supply node NVDD2, each described above with respect to the 1A-4B were discussed. In some embodiments, arranging the plurality of conductive elements includes establishing power distribution structures of the first and second power supply regions such that power supply nodes NVDDA and NVDDB, described above with respect to FIG 4A and 4B were discussed.

In some embodiments, arranging the plurality of conductive elements includes establishing one or more power distribution structures such that the reference node NVSS, described above with respect to FIG 1A-4B was discussed.

At operation 640, in some embodiments, the IC layout diagram containing the n-well is generated. In some embodiments, generating the IC layout diagram includes generating the IC layout diagram 100A or 100B described above with respect to FIG 3B and 4B were discussed.

At operation 650, in some embodiments, the IC layout diagram is stored on a storage device. Generation of the IC layout diagram is performed by a processor, for example processor 802 of IC layout diagram generation system 800 described below with respect to FIG 8th is discussed.

In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in a non-transitory computer-readable memory or a layout library, such as a database, and/or includes storing the IC layout diagram via a Network. In various embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in the layout library 807 and/or via the network 814 of the IC layout diagram generation system 800 described below with respect to FIG 8th is discussed.

In some embodiments, storing the IC layout diagram includes storing the IC layout diagram 100A or 100B described above with respect to FIG 3B and 4B were discussed.

At operation 660, in some embodiments, at least one of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is fabricated based on the IC layout diagram. Fabrication of one or more semiconductor masks or at least one component in a layer of a semiconductor IC is discussed below with respect to IC fabrication system 900 and 9 discussed.

In some embodiments, fabrication of one or more semiconductor masks or at least one component in the layer of the semiconductor IC is based on the IC layout diagram 100A or 100B provided above with respect to FIG 3B and 4B were discussed.

At operation 670, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout diagram. Performing one or more manufacturing operations, for example one or more lithographic exposures, based on the IC layout diagram is described below with respect to FIG 9 discussed.

In some embodiments, performing one or more manufacturing operations is based on the IC layout diagram 100A or 100B provided above with respect to FIG 3B and 4B were discussed.

Performing some or all of the operations of method 600 generates an IC layout diagram, such as IC layout diagram 100A or 100B, capable of at least partially defining a level shifting circuit that includes a bias circuit and a level shifter configured so are configured as discussed above with respect to level shifting circuit 100, and thereby have the capabilities and advantages discussed above with respect to level shifting circuit 100.

7 7 is a flow diagram of a method 700 for fabricating an IC structure in accordance with some embodiments.

The method 700 is adapted to form an IC structure, for example the level shifting circuit 100 described above with respect to FIG 1A-5 was discussed. In some embodiments, one or more operations of the method 700 are performed based on one or both of the IC layout diagrams 100A and 100B provided above with respect to FIG 3B and 4B were discussed.

In some embodiments, the method 700 may be used by an IC manufacturing system as part of an IC manufacturing flow, for example an IC manufacturing system 900 described below with respect to FIG 9 is discussed.

The order in which the operations of method 700 in 7 shown is for illustrative purposes only; the operations of the method 700 can also be carried out simultaneously and/or in a manner different from that in 7 shown order are executed. In some embodiments, operations are performed in addition to those in 7 Operations shown before, between, during and/or after the in 7 operations shown performed.

In some embodiments, one or more operations of method 700 are performed using various manufacturing tools, for example one or more of a wafer stepper, a photoresist coater, an ion implanter, a process chamber, for example a CVD chamber, or an LPCVD oven , a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes, as discussed below.

At operation 710, in some embodiments, an n-well is formed in a semiconductor substrate. Forming the n-well includes performing one or more suitable fabrication processes, such as photolithography and/or ion implantation processes.

In some embodiments, forming the n-well includes forming a common n-well comprising the n-well NW or multiple n-wells NW described above with respect to FIG 1A-4B were discussed. In some embodiments, forming the n-well includes forming the n-well based on the n-well NW of the IC layout diagram 100A or 100B described above with respect to FIG 3B and 4B were discussed.

In operation 720, first through fourth PMOS transistors are formed in the n-well. Forming the first through fourth PMOS transistors includes performing a number of suitable manufacturing processes, such as photolithography, etching, deposition, and/or ion implantation processes.

In some embodiments, forming the first and second of the first through fourth PMOS transistors includes forming the PMOS transistors P4 and P5 described above with respect to the biasing circuit 300 and the 3A and 3B have been described. In some embodiments, forming the first and second of the first through fourth PMOS transistors includes forming PMOS transistors P6-P8, as described above with respect to bias circuit 400 and FIG 4A and 4B were discussed.

In some embodiments, forming the third and fourth of the first through fourth PMOS transistors includes forming the PMOS transistors P1-P3 described above with respect to FIG 2-4B were discussed.

In some embodiments, forming the first to fourth PMOS transistors in the n-well region includes forming one or more NMOS transistors outside the n-well, for example the NMOS transistors N1-N3 described above with respect to FIG 2-4B have been discussed and/or the NMOS transistor N4 discussed above with respect to FIG 4A and 4B was discussed.

In some embodiments, forming the first through fourth backside via structures includes performing a thinning operation on a semiconductor wafer having the IC structure, for example the substrate 100S, described above with respect to FIG 1A-5 was discussed.

At operation 730, a bias circuit including the first and second PMOS transistors and a level shifter including the third and fourth PMOS transistors is fabricated. Fabricating the bias circuit and level shifter involves establishing a plurality of conductive segments that are supported and electrically separated by one or more layers of insulation. In some embodiments, setting up the plurality of conductive segments includes performing one or more manufacturing processes, for example one or more deposition, patterning, etching, planarization and/or cleaning processes, suitable to generate conductive structures according to circuit setup requirements are arranged.

In some embodiments, forming the one or more insulating layers includes depositing one or more insulating materials, such as dielectric materials, as described above with respect to FIG 1B , 3B and 4B be discussed. In some embodiments, forming the conductive segments includes performing one or more deposition processes for depositing one or more conductive materials described above with respect to FIG 1B , 3B and 4B were discussed.

In some embodiments, forming the conductive segments includes forming the conductive segments based on conductive regions CR described above with respect to FIG 3B and 4B were discussed.

In some embodiments, forming the biasing circuit having the first and second PMOS transistors includes forming the biasing circuit 110 described above with respect to FIG 1A and 1B was discussed. In some embodiments, forming the biasing circuit having the first and second PMOS transistors includes forming the biasing circuit 300 having the PMOS transistors P4 and P5 described above with respect to FIG 3A and 3B were discussed. In some embodiments, forming the biasing circuit having the first and second PMOS transistors includes forming the biasing circuit 400 having the PMOS transistors P6-P8 described above with respect to FIG 4A and 4B were discussed.

In some embodiments, forming the level shifter having the third and fourth PMOS transistors includes forming the level shifter 120 described above with respect to FIG 1A and 1B was discussed. In some embodiments, forming the level shifter having the third and fourth PMOS transistors includes forming the level shifter 200 having the PMOS transistors P1-P3 described above with respect to FIG 2-4B were discussed.

At operation 740, a first current distribution structure is formed having electrical connections to each of the first and third PMOS transistors, and a second current distribution structure is formed having electrical connections to each of the second and fourth PMOS transistors. Forming the first and second power distribution structures includes establishing a plurality of conductive segments supported and electrically separated by one or more insulating layers, as discussed above with respect to operation 730 .

Forming the first and second power distribution structures includes establishing the plurality of conductive segments such that each of the first and second power supply region current distribution structures is electrically coupled to S/D structures of the first through fourth PMOS transistors.

In some embodiments, establishing the plurality of conductive elements includes establishing a first power supply domain power distribution structure to include power supply node NVDD1 and a second power supply domain power distribution structure to include power supply node NVDD2, each of which is described above with respect to the 1A-4B were discussed. In some embodiments, establishing the plurality of conductive segments includes establishing power distribution structures of the first and second power supply domains such that power supply nodes NVDDA and NVDDB, described above with respect to FIG 4A and 4B were discussed.

In some embodiments, establishing the plurality of conductive segments includes establishing one or more power distribution structures such that the reference node NVSS, described above with respect to FIG 1A-4B was discussed.

The operations of method 700 may be used to form an IC structure, for example level shifter circuit 100, having bias circuitry and a level shifter as discussed above with respect to level shifter circuit 100, and thereby having the capabilities and advantages discussed above with respect to level shifting circuit 100.

8th 8 is a block diagram of an IC layout diagram generation system 800 according to some embodiments. For example, the methods described herein for generating IC layout diagrams according to one or more embodiments may be implemented using the IC layout diagram generation system 800 according to some embodiments.

In some embodiments, the IC layout diagram generation system 800 is a general purpose computing device having a hardware processor 802 and a non-transitory computer-readable storage medium 804. The Storage medium 804 is encoded, that is, stores, among other things, computer program code 806, that is, a set of executable instructions. The execution of instructions 806 by the hardware processor 802 constitutes (at least in part) an EDA tool that implements some or all of a method, such as the method 600 for generating an IC layout diagram discussed above with respect to FIG 6 discussed (hereinafter referred to as the processes and/or procedures) implemented.

The processor 802 is electrically coupled to the computer-readable storage medium 804 via a bus 808 . The processor 802 is also electrically coupled to an I/O interface 810 via the bus 808 . A network interface 812 is also electrically connected to processor 802 via bus 808 . The network interface 812 is connected to a network 814 such that the processor 802 and the computer-readable storage medium 804 are able to connect to external elements via the network 814 . The processor 802 is configured to execute the computer program code 806 encoded in the computer-readable storage medium 804 to cause the IC layout diagram generation system 800 to be used for performing some or all of the named processes and/or methods being. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or any suitable processing unit.

In one or more embodiments, computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or apparatus or device). For example, computer readable storage medium 804 includes semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read only memory (ROM), rigid magnetic disk, and/or optical disk. In one or more embodiments employing optical disks, computer-readable storage medium 804 includes compact disk read-only memory (CD-ROM), compact disk read/write (CD-R/W) and/or or a digital video disc (DVD).

In one or more embodiments, the storage medium 804 stores computer program code 806 configured to cause the IC layout diagram generation system 800 (such execution representing (at least in part) the EDA tool) to perform a section or the Entirety of the processes and / or methods mentioned to be usable. In one or more embodiments, the storage medium 804 also stores information that enables performing some or all of the named processes and/or methods. In one or more embodiments, storage medium 804 stores a layout library 807 containing such IC layout diagrams as disclosed herein, such as IC layout diagrams 100A and 100B described above with respect to FIGS 3B and 4B were discussed.

The IC layout diagram generation system 800 has an I/O interface 810 . The I/O interface 810 is coupled to external circuitry. In one or more embodiments, I/O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or arrow keys for communicating information and commands to processor 802.

The IC layout diagram generation system 800 also includes a network interface 812 coupled to the processor 802 . Network interface 812 allows system 800 to communicate with network 814 to which one or more other computer systems are attached. Network interface 812 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA, or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the above processes and/or methods are implemented in two or more IC layout diagram generation systems 800 .

The IC layout diagram generation system 800 is configured to receive information via the I/O interface 810 . The information received via I/O interface 810 includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor 802. The information is transmitted to processor 802 via bus 808. The IC layout diagram generation system 800 is configured to receive information related to a user interface via the I/O interface 810 . The information is stored on the computer-readable medium 804 as a user interface (UI) 842 .

In some embodiments, some or all of the recited processes and/or methods are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the recited processes and/or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the recited processes and/or methods are implemented as a plug-in for a software application. In some embodiments, at least one of said processes and/or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the named processes and/or methods are implemented as a software application used by the IC layout diagram generation system 800 . In some embodiments, a layout diagram containing standard cells is created using a tool such as VIRTUOSO® from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool.

In some embodiments, the processes are implemented as functions of a program stored on a non-transitory computer-readable recording medium. Examples of a non-transitory, computer-readable recording medium include, but are not limited to, external/removable and/or internal/built-in mass or memory devices, for example one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a Semiconductor memories such as a ROM, a RAM, a memory card, and the like.

9 FIG. 9 is a block diagram of an IC manufacturing system 900 and an associated IC manufacturing flow, according to some embodiments. In some embodiments, based on an IC layout diagram, (A) one or more semiconductor masks and/or (B) at least one component in a layer of a semiconductor integrated circuit are manufactured using the manufacturing system 900 .

In 9 For example, the IC manufacturing system 900 includes entities, such as a design house 920, a mask house 930, and an IC fabricator/manufacturer ("Fab") 950, involved in the design, development, and manufacturing cycles and/or services related to the manufacture of an IC component 960 interact with each other. The entities in the system 900 are linked via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of the design house 920, the mask house 930, and the IC fab 950 are owned by a single larger corporation. In some embodiments, two or more of the design house 920, the mask house 930, and the IC fab 950 coexist in a common facility and share common resources.

The design house (or design team) 920 generates an IC design layout diagram 922. The IC design layout diagram 922 includes various geometric structures, for example an IC layout diagram 100A or 100B, described above with respect to FIG 3B and 4B were discussed. The geometric structures correspond to structures of metal, oxide or semiconductor layers from which the various components of the IC device 960 to be manufactured are composed. The different layers combine to form different IC structural elements. For example, a portion of the IC design layout diagram 922 includes various IC structural elements such as an active region, a gate electrode, source and drain, metal lines or vias of an interlayer interconnect, and openings for bonding pads to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 920 implements an appropriate design process to form the IC design layout diagram 922 . The design process includes one or more of a logical design, a physical design, and placement and routing. The IC design layout diagram 922 is presented in one or more files that contain information about the geometric structures. For example, the IC design layout diagram 922 can be expressed in a GDSII file format or a DFII file format.

The mask house 930 includes data prep 932 and mask fabrication 944. The mask house 930 uses the IC design layout diagram 922 to fabricate one or more masks 945 that are used in fabricating the various layers of the IC device 960 according to the IC design layout diagram 922 are to be used. The mask house 930 performs the mask data preparation 932 showing the IC design layout image 922 is translated into a representative data file (RDF). Mask data preparation 932 transmits the RDF to mask maker 944. Mask maker 944 includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) 945 or a semiconductor wafer 953. The design layout diagram 922 is processed by the mask data preparation 932 to match certain characteristics of the mask writer and/or requirements of the IC-Fab 950 is compatible. In 9 mask data preparation 932 and mask fabrication 944 are illustrated as separate elements. In some embodiments, the mask data preparation 932 and the mask fabrication 944 may be collectively referred to as the mask data preparation.

In some embodiments, mask data preparation 932 includes optical proximity correction (OPC) that uses lithography optimization techniques to compensate for artifacts such as those caused by diffraction, interference, other process effects, and the like. OPC adjusts IC design layout diagram 922. In some embodiments, mask data preparation 932 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, the mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout diagram 922 that has undergone processes in OPC with a set of mask generation rules that include certain geometric and/or connectivity constraints to ensure sufficient ensure margins to account for variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 922 to compensate for constraints during mask fabrication 944 that may undo some of the modifications made by OPC to meet mask generation rules.

In some embodiments, mask data preparation 932 includes lithography process checking (LPC) that simulates processing implemented by IC fab 950 to fabricate IC package 960 . The LPC simulates this processing using the IC design layout diagram 922 to produce a simulated manufactured device, such as an IC component 960. The processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle parameters associated with tools used to manufacture the IC and/or other aspects of the manufacturing process. The LPC takes into account various factors such as interframe contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device is formed by the LPC, if the simulated device does not have the shape accurately enough to meet design rules, OPC and/or MRC are repeated to further refine the IC design layout diagram 922 .

It should be understood that the above description of mask data preparation 932 has been simplified for the sake of clarity. In some embodiments, the mask data preparation 932 includes additional features, such as a logic operation (LOP) to modify the IC design layout diagram 922 according to manufacturing rules. Additionally, the processes applied to the IC design layout diagram 922 during the mask data preparation 932 can be performed in a variety of different orders.

After the mask data preparation 932 and during the mask manufacture 944, a mask 945 or a group of masks 945 are manufactured using the modified IC design layout 922. In some embodiments, mask fabrication 944 includes performing one or more lithographic exposures based on the IC design layout diagram 922. In some embodiments, an electron beam (e-beam) or multiple e-beam mechanism is used to form a pattern to form a mask (photomask 945 or reticle) 845 based on the modified IC design layout 922. The mask 945 can be formed in various technologies. In some embodiments, mask 945 is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A ray, such as an ultraviolet (UV) ray or an EUV ray, used to expose the image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque region and is through the transparent regions passed. In one example, a binary mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) that is coated in the opaque regions of the mask. In another example, mask 945 is formed using phase shifting technology. In a phase shift mask (PSM) version of the mask 945, various elements in the structure formed on the phase shift mask are configured to have a correct phase difference to increase resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The one or more masks generated by mask fabrication 944 are used in a variety of different processes. For example, these one or more masks are used in an ion implantation process to form various doped regions in the semiconductor wafer 953, in an etch process to form various etch regions in the semiconductor wafer 953, and/or in other suitable processes.

The IC Fab 950 is an IC manufacturing facility that includes one or more manufacturing facilities for the manufacture of a variety of different IC products. In some embodiments, IC fab 950 is a semiconductor foundry. For example, there may be one manufacturing facility for the front-end manufacturing of multiple IC products (Front-End-of-Line (FEOL) manufacturing), while a second manufacturing facility for the back-end manufacturing of the interconnects and encapsulation of the IC products (back-end-of-line (BEOL) manufacturing) and a third manufacturing facility may provide other services to the foundry company.

The IC fab 950 includes wafer fabrication tools 952 configured to perform various fabrication operations on the semiconductor wafer 953 such that the IC device 960 is fabricated according to the one or more masks, for example mask 945 . In various embodiments, the fabrication tools 952 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber such as a CVD chamber or LPCVD oven, a CMP system, a plasma etch system, a wafer cleaning system or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

The IC fab 950 uses the one or more masks 945 produced by the mask house 930 to fabricate the IC package 960. FIG. Thus, the IC fab 950 at least indirectly uses the IC design layout diagram 922 to fabricate the IC device 960. In some embodiments, a semiconductor wafer 953 is fabricated by the IC fab 950 using the one or more masks 945 to produce the IC package 960 to form. In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram 922 . The semiconductor wafer 953 comprises a silicon substrate or other suitable substrate on which layers of material are formed. The semiconductor wafer 953 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent fabrication steps).

Details regarding an IC manufacturing system (e.g. the system 900 of 9 ) and an associated IC fabrication flow can be found, for example, in U.S. Patent No. 9,256,709 , issued February 9, 2016, in US Pre-grant Publication No. 20150278429, published October 1, 2015, in US Pre-grant Publication No. 20140040838, published February 6, 2014, and in U.S. Patent No. 7,260,442 , issued August 21, 2007, each of which is incorporated herein by reference in its entirety.

In some embodiments, a circuit includes a biasing circuit having a first input terminal configured to receive a first supply voltage and a second input terminal configured to receive a second supply voltage, the biasing circuit configured to generate a bias voltage having the greater of a first voltage level of the first supply voltage and a second voltage level of the second supply voltage, and a level shifter having a first PMOS transistor configured to receive the first supply voltage and a second PMOS transistor configured to receive the second supply voltage, each of the first and second PMOS transistors having a bulk terminal configured to receive the bias voltage. In some embodiments, the bias circuit includes a third PMOS transistor configured to receive the first supply voltage and a fourth PMOS transistor configured to receive the first supply voltage tet to receive the second supply voltage, each of the third and fourth PMOS transistors having a bulk terminal configured to receive the bias voltage. In some embodiments, the third PMOS transistor includes a gate configured to receive the second supply voltage, a first S/D terminal configured to receive the first supply voltage, and a second S/D terminal ; the fourth PMOS transistor includes a gate configured to receive the first supply voltage, a third S/D terminal configured to receive the second supply voltage, and a fourth S/D terminal; and the second and fourth S/D ports are coupled together and configured to generate the bias voltage. In some embodiments, the biasing circuit includes an inverter configured to receive one of the first and second supply voltages, the inverter including a fifth PMOS transistor including a bulk terminal configured to receive the bias voltage; the third PMOS transistor includes a gate configured to receive the one of the first and second supply voltages, a first S/D terminal configured to receive the other of the first and second supply voltages, and a second S/D port; the fourth PMOS transistor includes a gate coupled to a node of the inverter, a third S/D terminal configured to receive the one of the first and second supply voltages, and a fourth S/D terminal ; and the second and fourth S/D ports are coupled together and configured to generate the bias voltage. In some embodiments, the level shifter includes a third PMOS transistor configured to receive the second supply voltage, the third PMOS transistor having a bulk terminal configured to receive the bias voltage. In some embodiments, the level shifter includes a first NMOS transistor connected in series with the first PMOS transistor, a second NMOS transistor connected in series with the second PMOS transistor, and a third NMOS transistor connected in series with the second PMOS transistor is connected in series with the third PMOS transistor, the first NMOS transistor and the first PMOS transistor being arranged as an inverter arranged to receive an input signal, the second NMOS transistor being arranged to generate a through receive the signal output from the inverter, and the third NMOS transistor is configured to receive the input signal. In some embodiments, the bulk terminals of the first and second PMOS transistors are coupled to the same n-well.

In some embodiments, an IC includes an n-well, a first power supply node configured to have a first supply voltage, a second power supply node configured to have a second supply voltage, a bias circuit including a first PMOS transistor, positioned in the n-well and having a first S/D terminal coupled to the first power supply node and a second PMOS transistor positioned in the n-well and a second S/D terminal coupled to the second power supply node, wherein the bias circuit is configured to bias the n-well with a bias voltage having a bias level based on the larger of a first voltage level of the first supply voltage and a second voltage level of the second supply voltage, and a level shifter that a third PMOS transistor positioned in the n-well and having a third S/D terminal coupled to the first power supply node and a fourth PMOS transistor positioned in the n-well and has a fourth S/D port coupled to the second power supply node. In some embodiments, the bias circuit is configured to bias the n-well with the bias voltage having the bias level equal to the greater of the first voltage level and the second voltage level. In some embodiments, the first PMOS transistor has a fifth S/D terminal, the second PMOS transistor has a sixth S/D terminal, and the fifth and sixth S/D terminals are coupled and configured to each other to generate the bias. In some embodiments, the first PMOS transistor has a gate coupled to the second power supply node and the second PMOS transistor has a gate coupled to the first power supply node. In some embodiments, the bias circuit includes a fifth PMOS transistor positioned in the n-well and having: a seventh S/D terminal coupled to the first power supply node, a gate coupled to the second power supply node, and an eighth S/D terminal coupled to an internal node, and an NMOS transistor having: a ninth S/D terminal coupled to the internal node, a gate connected to the second power supply node and a tenth S/D port coupled to a reference node configured to have a reference voltage, the first PMOS transistor having a gate coupled to the second power supply node and the second PMOS transistor having a gate coupled to the internal node. In some embodiments, the bias circuit includes a fifth PMOS transistor positioned in the n-well and having: a gate coupled to the first power supply node, a seventh S/D terminal coupled to the second power supply node, and an eighth S/D terminal coupled to an internal node, and an NMOS transistor having: a ninth S/D terminal coupled to the internal node, a gate coupled to the first power supply node and a tenth S/D terminal coupled to a reference node configured to have a reference voltage, the first PMOS transistor having a gate coupled to the internal node and the second PMOS transistor has a gate coupled to the second power supply node. In some embodiments, the level shifter includes a fifth PMOS transistor positioned in the n-well and having a fifth S/D terminal coupled to the second power supply node, a first NMOS transistor coupled between the third PMOS Transistor and a reference node adapted to have a reference voltage, a second NMOS transistor coupled between the fourth PMOS transistor and the reference node, and a third NMOS transistor coupled between the fifth PMOS transistor and is coupled to the reference node, each of the first through third NMOS transistors having a bulk terminal coupled to the reference node.

In some embodiments, a method of operating a level shifting circuit includes receiving a first and a second supply voltage in a bias circuit, using the bias circuit to generate a bias voltage based on the greater of a first voltage level of the first supply voltage and a second voltage level of the second supply voltage receiving the first supply voltage at a first S/D terminal of a first PMOS transistor of a level shifter, receiving the second supply voltage at a second S/D terminal of a second PMOS transistor of the level shifter, and using the bias voltage to bias an n -well comprising the first and second PMOS transistors. In some embodiments, receiving the first and second supply voltages in the bias circuit includes receiving the first supply voltage at a third S/D terminal of a third PMOS transistor of the bias circuit and receiving the second supply voltage at a fourth S/D terminal of a fourth PMOS transistor of the bias circuit, the n-well comprising the third and fourth PMOS transistors. In some embodiments, using the bias circuit to generate the bias voltage includes generating the bias voltage using a fifth S/D terminal of the third PMOS transistor coupled to a sixth S/D terminal of the fourth PMOS transistor. In some embodiments, using the bias circuit to generate the bias voltage based on the greater of the first voltage level and the second voltage level includes generating the bias voltage having the first voltage level by turning on the third PMOS transistor, and generating the bias voltage having the has the second voltage level by turning on the fourth PMOS transistor. In some embodiments, using the bias circuit to generate the bias voltage based on the greater of the first voltage level and the second voltage level comprises generating the bias voltage having the first voltage level when the second voltage level corresponds to the situation that a power supply range of the second supply voltage is in operates in an off mode, and generating the bias voltage having the second voltage level when the first voltage level corresponds to the situation that a power supply portion of the first supply voltage operates in an off mode. In some embodiments, receiving the first supply voltage at the first S/D terminal of the first PMOS transistor includes receiving the first supply voltage in an inverter having the first PMOS transistor and receiving the second supply voltage at the second S/ D-connecting the second PMOS transistor includes receiving the second supply voltage at a cross-coupled transistor pair comprising the second PMOS transistor.

The above outlines features of various embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and/or advantages as those presented herein achieve embodiments. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and modifications can be made in the present invention without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US9256709 [0183]
• US7260442 [0183]

Claims (20)

Circuit that includes: a bias circuit comprising: a first input terminal configured to receive a first supply voltage; and a second input terminal configured to receive a second supply voltage, wherein the bias circuit is configured to generate a bias voltage having the greater of a first voltage level of the first supply voltage and a second voltage level of the second supply voltage; and a level shifter that includes: a first PMOS transistor configured to receive the first supply voltage; and a second PMOS transistor configured to receive the second supply voltage, wherein each of the first and second PMOS transistors has a bulk terminal configured to receive the bias voltage. circuit after claim 1 , wherein the biasing circuit comprises: a third PMOS transistor configured to receive the first supply voltage; and a fourth PMOS transistor configured to receive the second supply voltage, each of the third and fourth PMOS transistors having a bulk terminal configured to receive the bias voltage. circuit after claim 2 , wherein the third PMOS transistor comprises: a gate configured to receive the second supply voltage, a first source/drain terminal (S/D) configured to receive the first supply voltage, and a second S/D terminal, the fourth PMOS transistor comprising: a gate configured to receive the first supply voltage, a third S/D terminal configured to receive the second supply voltage, and a fourth S /D port, and the second and fourth S/D ports are coupled together and configured to generate the bias voltage. circuit after claim 2 , wherein the biasing circuit further comprises an inverter configured to receive one of the first and second supply voltages, the inverter comprising a fifth PMOS transistor including a bulk terminal configured to receive the bias voltage, the The third PMOS transistor comprises: a gate configured to receive one of the first and second supply voltages, a first source/drain terminal (S/D) configured to receive the other of the first and second to receive supply voltage, and a second S/D terminal, the fourth PMOS transistor comprising: a gate coupled to a node of the inverter, a third S/D terminal arranged to receive one of the first and the second supply voltage, and a fourth S/D port, and the second and fourth S/D ports are coupled to each other and arranged to receive the bias voltage to generate. circuit after claim 1 , wherein the level shifter comprises: a third PMOS transistor configured to receive the second supply voltage, the third PMOS transistor including a bulk terminal configured to receive the bias voltage. circuit after claim 5 , wherein the level shifter comprises: a first NMOS transistor connected in series with the first PMOS transistor; a second NMOS transistor connected in series with the second PMOS transistor; and a third NMOS transistor connected in series with the third PMOS transistor, the first NMOS transistor and the first PMOS transistor being arranged as an inverter configured to receive an input signal, the second NMOS transistor is arranged to receive a signal output by the inverter, and the third NMOS transistor is arranged to receive the input signal. circuit after claim 1 , wherein the bulk terminals of the first and second PMOS transistors are coupled to the same n-well. An integrated circuit (IC) comprising: an n-well; a first power supply node configured to have a first supply voltage; a second power supply node configured to have a second supply voltage; a bias circuit comprising: a first PMOS transistor positioned in the n-well and comprising a first source/drain (S/D) terminal coupled to the first power supply node; and a second PMOS transistor positioned in the n-well and including a second S/D terminal coupled to the second power supply node, wherein the biasing circuit is configured to bias the n-well with a voltage that is one having bias levels based on the larger of a first voltage level of the first supply voltage and a second voltage level of the second supply voltage; and a level shifter comprising: a third PMOS transistor positioned in the n-well and comprising a third S/D terminal coupled to the first power supply node; and a fourth PMOS transistor positioned in the n-well and including a fourth S/D terminal coupled to the second power supply node. IC after claim 8 , wherein the biasing circuit is configured to bias the n-well with the bias voltage having the bias level equal to the greater of the first voltage level and the second voltage level. IC after claim 8 , wherein the first PMOS transistor includes a fifth S/D terminal, the second PMOS transistor includes a sixth S/D terminal, and the fifth and sixth S/D terminals are coupled together and configured to bias the voltage to generate. IC after claim 10 , wherein the first PMOS transistor includes a gate coupled to the second power supply node and the second PMOS transistor includes a gate coupled to the first power supply node. IC after claim 10 , wherein the biasing circuit further comprises: a fifth PMOS transistor positioned in the n-well and comprising: a seventh S/D terminal coupled to the first power supply node, a gate coupled to the second power supply node and an eighth S/D port coupled to an internal node; and an NMOS transistor comprising: a ninth S/D terminal coupled to the internal node, a gate coupled to the second power supply node, and a tenth S/D terminal coupled to a reference node configured to have a reference voltage, the first PMOS transistor including a gate coupled to the second power supply node and the second PMOS transistor including a gate coupled to the internal node. IC after claim 10 , wherein the biasing circuit further comprises: a fifth PMOS transistor positioned in the n-well and comprising: a gate coupled to the first power supply node, a seventh S/D terminal coupled to the second power supply node and an eighth S/D port coupled to an internal node; and an NMOS transistor comprising: a ninth S/D terminal coupled to the internal node, a gate coupled to the first power supply node, and a tenth S/D terminal coupled to a reference node configured to have a reference voltage, the first PMOS transistor including a gate coupled to the internal node and the second PMOS transistor including a gate coupled to the second power supply node. IC after claim 8 , wherein the level shifter comprises: a fifth PMOS transistor positioned in the n-well and comprising a fifth S/D terminal coupled to the second power supply node; a first NMOS transistor coupled between the third PMOS transistor and a reference node configured to have a reference voltage; a second NMOS transistor coupled between the fourth PMOS transistor and the reference node; and a third NMOS transistor coupled between the fifth PMOS transistor and the reference node, each of the first through third NMOS transistors including a bulk terminal coupled to the reference node. A method of operating a level shift circuit, the method comprising: receiving first and second supply voltages in a bias circuit; Using the bias circuit to generating a bias voltage based on the greater of a first voltage level of the first supply voltage and a second voltage level of the second supply voltage; receiving the first supply voltage at a first source/drain (S/D) terminal of a first PMOS transistor of a level shifter; receiving the second supply voltage at a second S/D terminal of a second PMOS transistor of the level shifter; and using the bias voltage to bias an n-well comprising the first and second PMOS transistors. procedure after claim 15 , wherein receiving the first and second supply voltages in the biasing circuit comprises: receiving the first supply voltage at a third S/D terminal of a third PMOS transistor of the biasing circuit; and receiving the second supply voltage at a fourth S/D terminal of a fourth PMOS transistor of the biasing circuit, wherein the n-well comprises the third and fourth PMOS transistors. procedure after Claim 16 , wherein using the bias circuit to generate the bias voltage comprises generating the bias voltage using a fifth S/D terminal of the third PMOS transistor coupled to a sixth S/D terminal of the fourth PMOS transistor. procedure after Claim 17 wherein using the bias circuit to generate the bias voltage based on the greater of the first voltage level and the second voltage level comprises: generating the bias voltage comprising the first voltage level by turning on the third PMOS transistor; and generating the bias voltage comprising the second voltage level by turning on the fourth PMOS transistor. procedure after claim 15 , wherein using the bias circuit to generate the bias voltage based on the larger of the first voltage level and the second voltage level comprises: generating the bias voltage having the first voltage level when the second voltage level corresponds to the situation that a power supply range of the second supply voltage in a shutdown mode works; and generating the bias voltage having the second voltage level when the first voltage level corresponds to the situation that a power supply portion of the first supply voltage is operating in an off mode. procedure after claim 15 , wherein receiving the first supply voltage at the first S/D terminal of the first PMOS transistor comprises receiving the first supply voltage in an inverter comprising the first PMOS transistor and receiving the second supply voltage at the second S/D - connecting the second PMOS transistor comprises receiving the second supply voltage at a cross-coupled transistor pair comprising the second PMOS transistor.

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