DE102021118788A1 - METHODS AND STRUCTURES FOR IMPROVED FERROELECTRIC RANDOM ACCESS MEMORY (FeRAM) - Google Patents

Abstract

Some embodiments relate to a ferroelectric random-access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure has a protrusion reflecting a difference between the first width and the second width. A sidewall dielectric spacer structure is disposed on the projection and covers the outermost sidewalls of the top electrode.

Description

REFERENCE TO RELATED APPLICATIONS

This application is a continuation-in-part of that filed June 26, 2019 U.S. Patent Application 16/452,965 , which is the priority of the preliminary filing on September 28, 2018 U.S. Patent Application 62/738,604 claimed. The content of the aforementioned patent applications is hereby incorporated herein by reference in its entirety.

BACKGROUND

Many modern electronic devices contain non-volatile memory. Non-volatile memory is electronic memory that can store data even when it is not powered. A promising candidate for the next generation of non-volatile memory is ferroelectric random-access memory (FeRAM). The FeRAM has a relatively simple structure and is compatible with CMOS (Complementary Metal-Oxide Semiconductor) logic manufacturing processes.

character list

• 1A veranschaulicht eine Querschnittsansicht einiger Ausführungsformen einer integrierten Schaltung (Integrated Circuit, IC), der eine FeRAM-Zelle umfasst.
• 1B veranschaulicht eine Draufsicht auf einige Ausführungsformen einer integrierten Schaltung (IC), der eine FeRAM-Zelle entsprechend 1A umfasst.
• 1C-1D veranschaulichen Querschnittsansichten anderer Ausführungsformen eines IC, der eine FeRAM-Zelle umfasst.
• 2A-2I veranschaulichen Querschnittsansichten verschiedener Ausführungsformen eines IC, der einen Speicherbereich mit einer oder mehreren FeRAM-Zellen und einen peripheren Bereich, der eine von dem Speicherbereich beabstandeten Logikschaltung aufweist.
• 3-13 veranschaulichen eine Reihe von Querschnittsansichten einiger Ausführungsformen eines Verfahrens zum Bilden eines IC, der eine FeRAM-Zelle umfasst.
• 14 veranschaulicht einige Ausführungsformen eines Verfahrens im Format eines Flussdiagramms zum Bilden eines IC, der eine FeRAM-Zelle umfasst.

Aspects of the present disclosure are best understood by considering the following detailed description when taken in connection with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of explanation.

• 1A FIG. 11 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) that includes a FeRAM cell.
• 1B 12 illustrates a top view of some embodiments of an integrated circuit (IC) corresponding to a FeRAM cell 1A includes.
• 1C-1D 12 illustrate cross-sectional views of other embodiments of an IC that includes a FeRAM cell.
• 2A-2I 12 illustrate cross-sectional views of various embodiments of an IC having a memory area including one or more FeRAM cells and a peripheral area including logic circuitry spaced from the memory area.
• 3-13 12 illustrate a series of cross-sectional views of some embodiments of a method of forming an IC that includes a FeRAM cell.
• 14 FIG. 11 illustrates some embodiments of a method in flowchart format for forming an IC that includes a FeRAM cell.

DETAILED DESCRIPTION

The present disclosure provides many different embodiments or examples for implementing various features of this disclosure. In the following, specific examples of components and arrangements are described in order to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and the second feature may be formed such that the first and second features are not necessarily in direct contact. Furthermore, reference numbers may be repeated in the various examples of the present disclosure. This repetition is for the purpose of simplicity and clarity and does not generally dictate any relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to indicate the relationship of an element or feature one or more other elements or features as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees, or other orientations) and the spatially relative descriptors used herein may similarly be interpreted accordingly.

A one-transistor one-capacitor (1T1C) memory cell is a type of memory that includes a capacitor and a transistor. The capacitor stores varying levels of charge corresponding to a single bit of data stored on the capacitor, and the transistor provides access to the capacitor for read and write operations. The relatively simple structure of the 1T1C memory cher cell allows for high storage density, resulting in high storage capacity and low cost per bit. 1T1C memory cells are typically used with dynamic random-access memory (DRAM). However, DRAM has performance limitations, is volatile, consumes high power, and relies on complex refresh circuitry. Non-volatile memory is electronic memory that is incapable of storing data when not powered. A promising alternative to DRAM is ferroelectric random-access memory (FeRAM). Unlike DRAM, FeRAM has lower power consumption, the potential for better performance, does not depend on complex refresh circuitry, and is non-volatile.

FeRAM memory cells include a transistor and a ferroelectric capacitor structure that includes a ferroelectric structure sandwiched between a top electrode and a bottom electrode. The FeRAM memory cell is configured to store one bit of data depending on how atoms are aligned in the ferroelectric capacitor structure. For example, a first state of the FeRAM memory cell, in which atoms in the ferroelectric structure are polarized in an "up" direction, may represent a binary value of "1", while a second state of the FeRAM memory cell, in which atoms in of the ferroelectric structure are polarized in a "down" direction can represent a binary value of "o", or vice versa.

However, as can be appreciated from some aspects of the present disclosure, an etch process in the manufacture of some FeRAM cells may raise reliability concerns. Specifically, during fabrication, a bottom electrode layer is formed, a ferroelectric layer is formed over the bottom electrode layer, and a top electrode layer is formed over the ferroelectric layer; and a mask is formed over the top electrode layer. Then, with the mask in place, an etch is performed to etch through the top electrode layer, ferroelectric layer, and bottom electrode layer to form the top electrode, ferroelectric structure, and bottom electrode. As the inventors have recognized, this etch can result in atoms removed from these layers during the course of the etch being inadvertently redeposited as conductive residues on the sidewalls of the ferroelectric structure. These conductive residues can eventually short the bottom electrode to the top electrode, resulting in failure and/or rendering the FeRAM device unusable.

Therefore, the present disclosure uses a dielectric sidewall spacer structure disposed along outer sidewalls of the top electrode. This dielectric sidewall spacer structure acts as an electrical barrier to prevent conductive residues generated during device fabrication from shorting the bottom electrode to the top electrode. Thus, this dielectric sidewall spacer and manufacturing process contributes to improving the production yield of FeRAM devices.

In 1A 1, a cross-sectional view 100 of some embodiments of an IC that includes a ferroelectric capacitor structure 102 is shown. In some embodiments, the ferroelectric capacitor structure 102 includes a ferroelectric structure 112 sandwiched between a bottom electrode structure 104 and a top electrode 114 . With this structure, the ferroelectric capacitor structure 102 is configured to store one bit of data. For example, a first state of ferroelectric capacitor structure 102, in which atoms in ferroelectric structure 112 are polarized in an "up" direction, may represent a binary value of "1", while a second state of ferroelectric capacitor structure 102, in which atoms in the ferroelectric capacitor structure 102 polarized in a "down" direction may represent a binary value of "o", or vice versa.

The bottom electrode structure 104 overlies and is electrically coupled to a bottom electrode wire 106be. For example, the bottom electrode wire 106be may be or include aluminum-copper, copper, aluminum, one or more other suitable conductive materials, or any combination of the above. For example, as used herein, a term with the suffix “(s)” may be singular or plural. In some embodiments, bottom electrode structure 104 has a T-shaped profile or other suitable profile. In some embodiments, the bottom electrode structure 104 is homogeneous (e.g., when the entire body of the bottom electrode structure 104 is a single material). In other embodiments, the bottom electrode structure 104 is heterogeneous (e.g., when the body of the bottom electrode structure 104 includes multiple layers and/or materials). The bottom electrode structure 104 may be, for example, titanium nitride, tantalum nitride, titanium, tantalum, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive capable materials or any combination of the above. The bottom electrode structure 104 includes a bottom electrode 108 and a bottom electrode via 110 . For example, the bottom electrode 108 and the bottom electrode via 110 may be individual regions of the bottom electrode structure 104 .

Bottom electrode 108 is electrically coupled to bottom electrode wire 106be by bottom electrode via 110, which extends from bottom electrode 108 to bottom electrode wire 106be. In some embodiments, the ferroelectric structure includes a top ferroelectric portion 112A having the first width, a bottom ferroelectric portion 112B having the second width, and a protrusion 119 corresponding to a height where the top ferroelectric portion 112A meets the bottom ferroelectric section 112B. Thus illustrated 1A an example where the bottom electrode 108 and the ferroelectric structure 112 each have a first width w1 and the top electrode has a second width w2, where w2 is greater than w1. In some embodiments, the first width is about 10 nm and the second width is about 12 nm. In various embodiments, the first width is in a range from about 50% to about 95% of the second width. Furthermore, in some cases, the width of the bottom electrode 108 is uniform or substantially uniform, and/or the width of the bottom electrode via 110 is uniform or substantially uniform. In some embodiments, bottom electrode 108 and bottom electrode via 110 are or include the same material or materials. In other embodiments, bottom electrode 108 and bottom electrode opening 110 are different materials. In some embodiments, bottom electrode 108 and bottom electrode via 110 are integrated and/or continuous with each other. In other embodiments, bottom electrode 108 and bottom electrode via 110 are independent and/or standalone.

Ferroelectric structure 112 overlies bottom electrode structure 104. Ferroelectric structure 112 may be, for example, strontium bismuth tantalite (e.g., SBT), lead zirconate titanate (e.g., PZT), hafnium zirconium oxide (e.g., HZO) , doped hafnium oxide (e.g., Si:HfO2), one or more other suitable ferroelectric materials, or any combination of the above. For example, the doped hafnia may be doped with zirconium, silicon, yttrium, aluminum, gadolinium, lanthanum, strontium, one or more other suitable elements, or any combination of the above. The ferroelectric structure 112 is configured to store one bit of data. For example, in a first state, atoms in ferroelectric structure 112 may be polarized in an "up" direction and represent a binary value of "1", while in a second state, atoms in ferroelectric structure 112 may be polarized in a "down" direction are polarized and can represent a binary value of "0", or vice versa.

A top electrode 114 overlies the ferroelectric structure 112. The top electrode 114 may be, for example, titanium nitride, tantalum nitride, titanium, tantalum, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or any one Be or include a combination of any of the above. The top electrode has a first width w ₁ measured between its outermost sidewalls and the ferroelectric structure has a second width w ₂ measured between its outermost sidewalls. The second width is greater than the first width such that the ferroelectric structure has a protrusion 119 reflecting a difference between the first width and the second width.

In some embodiments, a hard mask 116 overlies top electrode 114. Hard mask 116 may serve as a mask during formation of top electrode 114, ferroelectric structure 112, and bottom electrode 108, for example. Furthermore, the hard mask 116 may be or include, for example, silicon nitride, silicon oxynitride, one or more other suitable dielectrics, or any combination of the above.

A sidewall dielectric spacer structure 118 is located on outer sidewalls of the ferroelectric structure 112 and may partially extend into a top (top) surface of the ferroelectric structure 112 . A bottom of the sidewall dielectric spacer structure rests on the protrusion 119 and is spaced from a top of the bottom electrode 108 . Viewed in cross-section, sidewall dielectric spacer structure 118 includes a pair of spacer segments, and the spacer segments are on opposite outer sides of ferroelectric structure 112, respectively. The spacer segments have curved top sidewalls. In the cross section of 1A it can be seen that the spacer segments have inner sidewalls that are vertical and outer sidewalls that are rounded and/or tapered. The sidewall dielectric spacer structure 118 may have a height hs im ranging from about 50 Angstroms to about 500 Angstroms and may have a bottom on protrusion 119 that may correspond to the bottom of 114 or that may be below the bottom of 114 and within ferroelectric structure 112. Each spacer segment of sidewall dielectric spacer structure 118 may have a width ws in the range from about 50 Angstroms to about 500 Angstroms, and the ratio of width _ws to width _w1 ( _ws : _w1 ) may be in the range of 1 :20 to 2:1, although other values are possible within the scope of this disclosure for this example and other examples in the present application. As in the top view of 1B As can be seen, in some embodiments, when viewed from above, the dielectric sidewall spacer structure 118 may be a continuous spacer that laterally surrounds an outer sidewall of the top electrode 114 . The sidewall dielectric spacer structure 118 may be or include, for example, silicon nitride, silicon oxide, one or more other suitable dielectrics, or any combination of the above. In some embodiments, the dielectric sidewall spacer structure 118 and the hard mask 116 are or comprise the same material or materials.

As in 1A As shown, in some embodiments, a conductive residue 117 may be formed on outer sidewalls of sidewall dielectric spacer structure 118 and be in direct physical and electrical contact with bottom electrode 108 . Conductive residue 117 is spaced and insulated from outer sidewalls of top electrode 114 by sidewall dielectric spacer structure 118 such that sidewall dielectric spacer structure 118 prevents conductive residue 117, if present, from connecting top electrode 114 to the bottom electrode structure 104 short circuits. The conductive residue 117 thus contains chemical species contained in the ferroelectric layer and/or the bottom electrode layer that were redeposited during fabrication along the outermost sidewalls of the sidewall dielectric spacer structure. The conductive residue 117 can be a continuous layer in some cases, but in other cases it can be “fragmented” or discontinuously distributed over the underlying surfaces. For example, in some cases the conductive residue 117 may be a fully formed layer of uniform or non-uniform thickness covering the top of the mask 116, the top and sidewall surfaces of the sidewall dielectric spacer structure 118, the outer sidewalls of the ferroelectric structure 112 and the outer Side walls of the lower electrode 108 covered. In other embodiments, the conductive residue 117 may be fragmented in that the conductive residue 117 covers some, but not all, portions of the top of the mask 116, the top and sidewall surfaces of the dielectric sidewall spacer structure 118, the outer sidewalls of the ferroelectric structure 112 and the outer sidewalls of bottom electrode 108 covered; for example, it covers more than 1% but less than 100% of these underlying areas, although other values are possible within the scope of this disclosure for this example and other examples in the present application.

In some embodiments, a first dielectric liner 128 and/or a second dielectric liner 130 laterally surrounds the dielectric sidewall spacer structure 118, the ferroelectric structure 112, and the bottom electrode 108. The first dielectric liner 128 may, for example, serve as an etch stop during the formation of adjacent Vias serve and/or may be or include, for example, silicon carbide, one or more other suitable dielectrics, or any combination of the above. The second dielectric layer 130 may be or include, for example, TEOS silicon dioxide, one or more other suitable dielectrics, or any combination of the above.

A top electrode wire 106te and a top electrode via 120te overlie top electrode 114. Top electrode via 120te extends from top electrode wire 106te to top electrode 114 to electrically couple top electrode wire 106te to top electrode 114. In some embodiments, the top electrode wire 106te and the top electrode via 120te are the same material. In other embodiments, the top electrode wire 106te and the top electrode via 120te are different materials. In some embodiments, the top electrode wire 106te and the top electrode via 120te are integrated and/or continuous with each other. In other embodiments, the top electrode wire 106te and the top electrode via 120te are independent and/or stand alone from each other.

The bottom and top electrode wires 106be, 106te, the top electrode via 120te, and the ferroelectric capacitor structure 102 are surrounded by a dielectric structure. The dielectric structure includes a lower interconnect dielectric layer 122, a via dielectric layer 124 overlying lower interconnect dielectric layer 122, and an upper interconnect dielectric layer 126 overlying via dielectric layer 124. FIG. The dielectric structure may be or include, for example, tetraethylorthosilicate (TEOS) silicon dioxide, other suitable silicon dioxide, silicon oxynitride, a low-K dielectric, silicon carbide, silicon nitride, one or more other suitable dielectrics, or any combination of the above . As used herein, a low-κ dielectric may be, for example, a dielectric having a dielectric constant κ less than about 3.9, 3, 2, or 1. In some embodiments, the bottom and top interconnect dielectric layers 122, 126 are or include silicon oxide, a low-k dielectric, one or more other suitable dielectrics, or any combination of the above, and/or the via dielectric layer 124 is or includes silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable dielectrics, or any combination of the above.

1C-1D illustrate some additional embodiments of ferroelectric capacitors that fall within the scope of this disclosure. In these embodiments, the reference numbers of some features may be the same as corresponding features in other embodiments, such as in FIGS 1A-1B , such that the materials and/or functionality of these features may be the same in some embodiments, but may also differ. Thus, a feature in 1C and/or 1D having the same reference number as a corresponding feature in 1A and/or 1B has, in some cases, the same functionality and/or materials as in 1A and/or 1B (and vice versa). The same applies to other embodiments in this disclosure.

In 1C sidewall spacers 118 extend continuously from a top of hardmask 116 to a top of dielectric via layer 124. In addition, bottom electrode via 110 may include a barrier layer 109 comprising, for example, tantalum or titanium, and sidewalls and a bottom of the bottom electrodes - Via 110 lined. In some embodiments, the barrier layer 109 may have a top surface that is flush with a top surface of the via dielectric layer 124 . It goes without saying that this barrier layer 109 is also present in 1A could be present, although in 1A is not explicitly illustrated.

In 1D Top electrode 114, ferroelectric structure 112, bottom electrode 104, and barrier layer 109 (if present) may each have a generally U-shaped cross-section and are concentric with one another. Thus, top electrode 114, ferroelectric structure 112, bottom electrode 104, and barrier layer 109 are electrically coupled between bottom electrode wire 106be and top electrode via 120te. In this arrangement, top electrode 114, ferroelectric structure 112, bottom electrode 104, and barrier layer 109 extend through dielectric via layer 124 and a liner layer 119, where liner layer 119 may comprise TEOS, for example.

In 2A A cross-sectional view 200 of some embodiments of an IC is shown. The IC includes a memory region 402 containing one or more ferroelectric capacitor structures and a peripheral region 404 containing one or more logic devices. It is understood that the cross-sectional view of FIG 2A while illustrated as having ferroelectric capacitor structure 102 of FIG 1A contains that but in 2A also the ferroelectric capacitor structures of 1C-1D as well as other ferroelectric capacitor structures could be included.

Within the memory region 402, the ferroelectric capacitor structure 102 of FIG 1A a first storage capacitor structure 102a and a second storage capacitor structure 102b. The first storage capacitor structure 102a overlies an access transistor 304 and is electrically coupled thereto by an interconnect structure 306 . This is thus an example implementation of a ferroelectric random access memory (FeRAM) device. The access transistor 304 overlies a semiconductor substrate 308 and may be, for example, a metal-oxide-semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), a fin field effect transistor (FinFET), any other suitable insulated-gate field effect transistor -Effect Transistor, IGFET) or another suitable transistor. The semiconductor substrate 308 may be or include a bulk monocrystalline silicon substrate, a silicon-on-insulator (SOI) substrate, or any other suitable semiconductor substrate, for example.

Access transistor 304 includes a pair of memory source/drain regions 310, a selectively conductive memory channel 312, a memory gate dielectric layer 314, and a memory gate Electrode 316. The memory source/drain regions 310 and the selectively conductive memory channel 312 are disposed within the semiconductor substrate 308, and the selectively conductive memory channel 312 extends laterally from one of the memory source/drain regions 310 to another of the memories - Source/drain regions 310. The memory gate dielectric layer 314 and the memory gate electrode 316 are stacked over the semiconductor substrate 308 and are sandwiched between the memory source/drain regions 310. FIG. The memory gate dielectric layer 314 may be or include, for example, silicon oxide, a high-k dielectric layer, one or more other suitable dielectrics, or any combination of the above. The memory gate electrode 316 may be or include, for example, doped polysilicon, metal, one or more other suitable conductive materials, or any combination of the above.

In some embodiments, an isolation structure 318 extends into the top surface of semiconductor substrate 308 to provide electrical isolation between access transistor 304 and other semiconductor devices in semiconductor substrate 308 . In some embodiments, isolation structure 318 laterally surrounds an active area of access transistor 304. Isolation structure 318 may be, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, one or more other suitable isolation structures, or any one Be or include a combination of any of the above.

Interconnect structure 306 overlies access transistor 304 and semiconductor substrate 308. Interconnect structure 306 includes a dielectric structure, and further includes a plurality of wires 106 and a plurality of vias 120. Only some of wires 106 and vias 120 are labeled for clarity of illustration , while others are unlabeled. The dielectric structure includes lower interconnect dielectric layer 122 , via dielectric layer 124 overlying lower interconnect dielectric layer 122 , and upper interconnect dielectric layer 126 overlying via dielectric layer 124 . In some embodiments, the dielectric structure further includes a first dielectric liner 128 and/or a second dielectric liner 130. The first and/or second dielectric liner 128, 130 further separate the ferroelectric structure 112 and the dielectric via layer 124 from the top dielectric interconnect layer 126. The first dielectric liner 128 may serve, for example, as an etch stop during the formation of adjacent vias and/or may be or include, for example, silicon carbide, one or more other suitable dielectrics, or any combination of the above. The second dielectric layer 130 may be or include, for example, TEOS silicon dioxide, one or more other suitable dielectrics, or any combination of the above.

The plurality of wires 106 includes the bottom and top electrode wires 106be, 106te, and the plurality of vias 120 includes the top electrode via 120te. Wires 106 and vias 120 are alternately stacked in the dielectric structure to define conductive paths, one of which electrically couples bottom electrode wire 106be to one of memory source/drain regions 310 . Furthermore, the wires 106 and the vias 120 are grouped into wire levels and via levels, respectively. A wire level is a set of wires of a common height above the semiconductor substrate 308, and a via level is a set of vias of a common height above the semiconductor substrate 308. The top electrode wire 106te is in the wire level immediately above the wire level covering the lower Electrode wire 106be accommodates. In some embodiments, as illustrated, bottom electrode wire 106be is in wire plane 4, which may also be referred to as metal4 (M4) in some contexts. However, in other embodiments, the bottom electrode wire 106be may be in any other wire plane/metal layer. For example, the bottom electrode wire 106be may also be in wire plane 1 in other embodiments.

The first storage capacitor structure 102a, the access transistor 304, and the electrical interconnects between the first storage capacitor structure 102a and the access transistor 304 define a first 1T1C FeRAM memory cell. It should be noted that the electrical interconnects between the first storage capacitor structure 102a and the access transistor 304 are defined by the wires 106 and the vias 120 . In some embodiments, the first 1T1C FeRAM memory cell is one of many 1T1C FeRAM memory cells arranged in rows and columns to define a memory array. In some of these embodiments, the plurality of wires 106 includes a source line wire 106sl defining a source line of the memory array, the memory gate electrode 316 defining a word line of the memory array, the top electrode wire 106te defining a bit line of the storage arrays, or any combination of the above. For example, bottom electrode wire 106be and source lead wire 106sl may be electrically coupled to memory source/drain regions 310, respectively.

In the peripheral region 404 of the IC, the metal layers of the interconnect structure are arranged at the same pitches or heights as in the memory region 402. The peripheral region 404 includes a logic transistor 408 having a pair of logic source/drain regions 410, a selectively conductive logic channel 412, a logic gate dielectric layer 414, and a logic gate electrode 416. The logic source/drain regions 410 and the selectively conductive logic channel 412 are disposed within the semiconductor substrate 308, and the selectively conductive logic channel 412 extends laterally from one of the logic source/drain regions 410 to another of the logic source/drain regions 410. The logic gate dielectric layer 414 and the logic gate electrode 416 are stacked over the semiconductor substrate 308 and are sandwiched between the logic source/drain regions 410. FIG. Logic gate dielectric layer 414 may be or include, for example, silicon oxide, a high-k dielectric layer, one or more other suitable dielectrics, or any combination of the above. Logic gate electrode 416 may be or include, for example, doped polysilicon, metal, one or more other suitable conductive materials, or any combination of the above.

2B-2G 12 show various other embodiments of different positions where the ferroelectric capacitors can be placed within the interconnect structure. As can be appreciated from these embodiments, the ferroelectric capacitors 102a, 102b can be placed at any point in or across the interconnect structure. In the 2B-2G Interconnect structure 306 includes a bottom metal layer (e.g., M1) and a top pad layer (e.g., an aluminum bond pad, a copper post, and/or a solder bump). Between the bottom metal layer and the top pad layer are a number of intermediate metal layers and a number of top metal layers. Generally, the intermetal layers, which include intermetal wiring layers and intermetal vias, have smaller feature sizes and are more closely spaced, while the top metal layers, which include top metal wiring layers and top metal vias, have larger feature sizes and are more widely spaced. For example, in some cases, the intermetal layers may include an M1 wiring layer, an M1 via layer, an M2 wiring layer, an M2 via layer, an M3 wiring layer, an M3 via layer, an M4 wiring layer, and an M4 via layer are stacked on top of each other. These wiring layers may each have an intermetal width (e.g., greater than 50 nm) and an intermetal thickness (e.g., 500 Angstroms - 1500 Angstroms, and in some embodiments 900 Angstroms) and may be spaced by a minimum lateral intermetal spacing (e.g., greater than 50 nm) apart. The upper metal layers may include a TM1 upper wiring metal layer, a TM1 upper via metal layer, a TM2 upper wiring metal layer, a TM2 upper via metal layer, and a TM3 upper wiring metal layer. These top metal wiring layers may each have a top metal width (e.g., greater than 0.1 micron) and a top metal thickness (e.g., 1500 Angstroms - 10,000 Angstroms, and in some embodiments 1900 Angstroms) and may be spaced by a top metal lateral spacing (e.g. greater than 0.1 microns). A dielectric passivation material surrounds the top pad layer but leaves a top surface of the top pad layer exposed for electrical bonding.

For example, illustrate the 2B-2C some embodiments where ferroelectric capacitors are placed between the top of the substrate and a bottom of the bottom metal layer (e.g., M1). This approach allows applying a high temperature anneal, for example higher than 400°C, to the ferroelectric capacitors at various points during manufacture for the purpose of optimizing the ferroelectric phase. In 2 B For example, a bottom electrode 104 is disposed over a bottom contact portion, a ferroelectric structure 112 is disposed over bottom electrode 104, a top electrode 114 is disposed over the ferroelectric structure, and a top contact portion couples top electrode 114 to the bottom metal layer. In some cases, the lower contact portion and the upper contact portion may comprise the same metal, such as tungsten, nickel, aluminum, and/or copper, but in other cases, the lower contact portion and the upper contact portion may comprise different metals. For example, in some of these other cases, the lower contact portion may include tungsten, nickel, and/or aluminum, and the upper contact portion may include copper.

2D-2E illustrate some embodiments where the ferroelectric capacitors are disposed within the intermetal layers (ie, between the bottom metal layer and the top intermetal layer). In the examples of 2D-2E For example, the ferroelectric capacitors are arranged between the intermediate metal layer M2 and the intermediate metal layer M3. This embodiment may offer some advantages in that the ferroelectric capacitors compared to the embodiments of FIG 2B-2C are generally subjected to less thermal stress throughout the manufacturing process, so the end devices may be more reliable because they fall within a lower thermal budget.

2F-2G illustrate some embodiments where ferroelectric capacitors are sandwiched between the top intermetal layer and the bottom top metal layer. This embodiment may offer some advantages in that the ferroelectric capacitors compared to the embodiments of FIG 2B-2C are generally subjected to less thermal stress throughout the manufacturing process, so the end devices may be more reliable because they fall within a lower thermal budget. However, placing the ferroelectric capacitors higher in the interconnect structure 306 may also add a small amount of additional resistance compared to embodiments in which the ferroelectric capacitors are placed lower in the interconnect structure, and trade-offs must be made and the different approaches may be better suited to a variety of different situations depending on which design considerations are most important.

2H-2I illustrate some embodiments where ferroelectric capacitors are disposed above the top metal layer and below the pad layer structure. Again, locating the ferroelectric capacitors higher in the interconnect structure 306 can add a small amount of additional resistance compared to embodiments in which the ferroelectric capacitors are located lower in the interconnect structure and can reduce them during bonding subject to additional stresses, which means trade-offs must be made and the different approaches may be better suited to a variety of different situations depending on which design considerations are most important.

Referring to the 3-13 13, a series of cross-sectional views 300-1300 illustrates some embodiments of a method of forming an IC that includes a ferroelectric capacitor structure, where the ferroelectric capacitor structure is part of a 1T1C memory cell. For example, the method can be used to form the IC in one of 1A-1D and/or 2A-2G can be used. Although those in the 3-13 300-1300 shown are described in relation to a method, it will be understood that the cross-sectional views shown in FIGS 3-13 structures shown are not limited to the method and may stand alone without the method.

As indicated by cross-sectional view 300 of FIG 3 As illustrated, the IC includes a memory region 402 corresponding to one or more ferroelectric capacitor structures and a peripheral region 404 corresponding to one or more logic devices. It should be noted that for the sake of clarity of the drawings, a lower section of the IC (for example in 2A shown) in the 3-13 is omitted. Into the top of the bottom dielectric interconnect layer 122 and the respective tops of wires (e.g. 106be in Figs 1A-1B) Planarization is performed along the top of bottom interconnect dielectric layer 122 such that the top of bottom interconnect dielectric layer 122 is flush or substantially flush with the respective tops of the wires along the top of bottom interconnect dielectric layer 122 . The planarization can be performed, for example, by CMP, one or more other suitable planarization processes, or any combination of the above.

As indicated by cross-sectional view 400 of FIG 4 As illustrated, a via dielectric layer 124 is formed covering the lower interconnect dielectric layer 122 . The via dielectric layer 124 may be or include, for example, silicon carbide, silicon nitride, one or more other suitable dielectrics, or any combination of the above. For example, the via dielectric layer 124 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), one or more other suitable deposition techniques, or any combination of the above.

As indicated by cross-sectional view 500 of FIG 5 As illustrated, the via dielectric layer 124 is patterned to create a plurality of memory openings 502 . The storage openings 502 each overlie the lower ones Electrode wires 106be and expose them. In some embodiments, the patterning is performed by an etch process, one or more other suitable patterning processes, or any combination of the above. In some embodiments, the etch process includes forming a mask 506 on the via dielectric layer 124, performing an etch into the via dielectric layer 124 with the mask 506 in place, and removing the mask 506 after the etch. Mask 506 may be or include, for example, photoresist, silicon nitride, one or more other suitable mask materials, or any combination of the above.

As indicated by cross-sectional view 600 of FIG 6 1, a conductive liner 602 is formed covering the via dielectric layer 124 and lining the memory openings 502 (see FIG 5 ). A lower conductive body layer 604 covering the conductive liner layer 602 and filling the storage openings 502 is also formed. Conductive liner layer 602 and lower conductive body layer 604 define in whole or in part lower electrode vias 110 within storage openings 502. In addition, conductive liner layer 602 is configured to prevent material from lower conductive body layer 604 from leaking from the lower conductive body layer 604 away to the surrounding structure. The conductive liner layer 602 may be or include, for example, titanium nitride, titanium, tantalum nitride, tantalum, one or more other suitable conductive barrier materials for the lower conductive body layer 604, or any combination of the above. The bottom conductive body layer 604 may be or include, for example, titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or any combination of the above. The conductive liner layer 602 and lower conductive body layer 604 may be formed, for example, by CVD, PVD, electroless plating, electroplating, sputtering, one or more other suitable deposition processes, or any combination of the above methods.

As indicated by cross-sectional view 700 of FIG 7 1, planarization is incorporated into the respective top surfaces of the conductive liner 602 (see FIG 6 ) and the bottom conductive body layer 604 (see 6 ) until a top of the via dielectric layer 124 is reached. The planarization can be performed, for example, by CMP, one or more other suitable planarization processes, or any combination of the above.

As indicated by cross-sectional view 800 of FIG 8th As illustrated, a top conductive body layer 802, a ferroelectric layer 804, a top electrode layer 806, and a hard mask layer 808 are formed on the dielectric via layer 124 and the bottom conductive body layer 604. FIG. The top conductive body layer 802 may be or include, for example, titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or any combination of the above. Often the upper conductive body layer 802 is the same material as the lower conductive body layer 604, but in alternative embodiments these could be different materials. The ferroelectric layer 804 may be or include, for example, strontium bismuth tantalite, lead zirconate titanate, hafnium zirconium oxide, doped hafnium oxide, one or more other suitable ferroelectric materials, or any combination of the above. The top electrode layer 806 may be or include, for example, titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, copper, nickel, one or more other suitable conductive materials, or any combination of the above. The hard mask layer 808 may be or include, for example, silicon nitride, silicon oxynitride, silicon oxide, one or more other suitable dielectrics, or any combination of the above.

A process for forming the stack may include depositing the top conductive body layer 802, then depositing the ferroelectric layer 804, then depositing the top electrode layer 806, and then depositing the hard mask layer 808, for example. The top conductive body layer 802, the ferroelectric layer 804, the top electrode layer 806, and the hard mask layer 808 may be deposited, for example, by CVD, PVD, ALD, electroless plating, electroplating, one or more other suitable deposition processes, or any combination of the above.

As indicated by cross-sectional view 900 of FIG 9 illustrated, the top electrode layer 806 (see 8th ) and the hard mask layer 808 (see 8th ) patterned to form top electrodes 114 and hard masks 116 . This etch may extend into the top of ferroelectric layer 804 and, in some embodiments, between 5% and about 30% deep into ferroelectric layer 804, for example reach in to form a projection (see, for example, projection 119 in 1A) .

The patterning can be done, for example, by an etching process, one or more other suitable patterning processes, or any combination of the above. The etch process may include, for example, forming a mask 902 on the hard mask layer 116, and performing an etch into the top electrode layer and the hard mask layer with the mask 902 in place, thereby forming the top electrodes 114 and the hard mask 116. Mask 902 can be removed after etching. Mask 902 may be or include, for example, photoresist, a hard mask, and/or one or more other suitable mask materials, or any combination of the above.

As indicated by cross-sectional view 1000 of FIG 10 1, a dielectric spacer layer 1002, such as silicon nitride or silicon oxynitride, is formed over a top surface of ferroelectric structure 112 along sidewalls of top electrodes 114 and along sidewalls and over top surfaces of hard masks 116. FIG. The dielectric spacer layer 1002 is thus a continuous dielectric layer over the structure of FIG 9 and is generally compliant.

As indicated by cross-sectional view 1100 of FIG 11 illustrated, the dielectric spacer layer (see, for example, 1002 in 10 ) is etched back using a first etch, such as a dry etch or a plasma etch with a strong vertical component, typically without forming an additional mask after the dielectric spacer layer has been formed. This etch thus removes lateral portions of the dielectric spacer layer (see, for example, 1002 in 10 ), leaving the dielectric sidewall spacer structure 118 in place after the etch. A second etch is then performed with the dielectric sidewall spacer structure 118 in place to expose exposed portions of the ferroelectric layer (see, for example, 804 in 8th ) and the top conductive body layer (see for example 802 in 8th ) to remove. This etch may result in conductive residue forming on outer sidewalls of the bottom electrode, outer sidewalls of the ferroelectric layer, and/or outer sidewalls of the sidewall dielectric spacer structure 118, as well as on the top of the sidewall dielectric spacer structure 118 and the top of the hardmask 116 117 comprising chemical species etched/removed from the ferroelectric layer 804 and/or the upper conductive body 802. Without the sidewall dielectric spacer structure 118, this conductive residue could short the top and bottom electrodes together, resulting in device inoperability. In some cases, rather than being a continuous layer, the conductive residue 117 may be "spotty" or "fragmented" and may cover some portions of the exposed structure while not covering other portions of the exposed structure. Furthermore, the conductive residue 117 may be thicker towards the top of the dielectric spacer structure 118 and thinner towards the bottom electrode due to the manner in which the etching and redeposition of the conductive residue is removed from the top of the structure to the bottom of the structure, although other structures are within the scope of this disclosure for this example and other examples in the present application.

As indicated by cross-sectional view 1200 of FIG 12 As illustrated, a first dielectric liner 128 and a second dielectric liner 130 are formed covering the via dielectric layer 124 and the memory structures. For example, in some embodiments, the first dielectric liner 128 may be or include silicon carbide and the second dielectric liner 130 may include TEOS silicon dioxide. A top interconnect dielectric layer 126 is then formed to cover first dielectric liner 128 and second dielectric liner 130, and may be, for example, silicon oxide, a low-k dielectric, one or more other suitable dielectrics, or any combination be or include any of the above.

As indicated by cross-sectional view 1300 of FIG 13 As illustrated, planarization is performed into the top surface of top interconnect dielectric layer 126 to flatten the top surface. The planarization can be performed, for example, by CMP, one or more other suitable planarization processes, or any combination of the above. Then, openings are formed in the top dielectric interconnect layer 126, and vias (e.g., 120te and 120te) and metal wires (e.g., 106te, 1304) are formed in the openings. The vias and metal wires can be formed by a damascene process or a dual damascene process, for example. The vias and metal wires can be, for example, copper, aluminum nium, nickel, titanium, tantalum, titanium nitride, tantalum nitride, platinum, iridium, ruthenium, tungsten, silver, one or more other suitable conductive materials, or any combination of the above. In the peripheral region 404 of the IC, the metal layers of the interconnect structure can be spaced at the same pitches or heights as in the memory region 402, which simplifies the integration of the memory region 402 and the peripheral region 404. For example, metal layers 1302, 1304 in peripheral region 404 may have the same vertical spacing as 106be and 106te in memory region 402.

14 14 illustrates a method in flowchart format 1400 according to some embodiments.

At operation 1402, a bottom electrode layer is formed and a ferroelectric layer is formed over the bottom electrode layer. A top electrode layer is formed over the ferroelectric layer. For example, in some embodiments, this action may include all or portions of the 3-8 correspond.

At operation 1404, a mask is formed over the top electrode layer. For example, in some embodiments, this action may include all or portions of 9 correspond.

At operation 1406, with the mask in place, an etch is performed to remove a portion of the top electrode layer and leave a top electrode structure. Etching is stopped at a height corresponding to a surface of the ferroelectric layer. For example, in some embodiments, this action may include all or portions of 9 correspond.

At operation 1408, a conformal dielectric layer is formed over the surface of the ferroelectric layer, along sidewalls of the top electrode structure, and over a top surface of the top electrode structure. For example, in some embodiments, this action may include all or portions of 10 correspond.

At operation 1410, the conformal dielectric layer is etched back to form a sidewall dielectric spacer structure on the surface of the ferroelectric layer and along sidewalls of the top electrode structure and along sidewalls of the mask. For example, in some embodiments, this action may include all or portions of 11 correspond.

At 1412, with the mask and sidewall dielectric spacer structure in place, a portion of the ferroelectric layer and a portion of the bottom electrode layer are removed. For example, in some embodiments, this action may include all or portions of 11 correspond.

At 1414, a first liner is formed along outermost sidewalls of the sidewall dielectric spacer structure and over a top surface of the hardmask. For example, in some embodiments, this action may include all or portions of 12 correspond.

At 1416, a second liner is formed along outermost sidewalls of the first liner and over a top of the first liner. For example, in some embodiments, this action may include all or portions of 12 correspond.

At 1418, a via is formed through the first liner and through the second liner to make electrical contact with the top electrode. For example, in some embodiments, this action may include all or portions of 13 correspond.

Some embodiments thus relate to a memory device. The memory device includes a bottom electrode structure and a top electrode overlying the bottom electrode structure. The top electrode has a first width. A ferroelectric structure separates the bottom electrode structure from the top electrode, and the ferroelectric structure has a second width that is greater than the first width, such that the ferroelectric structure has a protrusion that is a difference between the first width and the second width reflects. A sidewall dielectric spacer structure is disposed on the projection and covers outermost sidewalls of the top electrode.

Other embodiments relate to a method. In this method, a lower electrode layer is formed, a ferroelectric layer is formed over the lower electrode layer, and an upper electrode layer is formed over the ferroelectric layer. A mask is formed over the top electrode layer. With the mask in place, an etch is performed to remove a portion of the top electrode layer and a top elec to leave rodent structure behind. Etching stops at a height corresponding to a surface of the ferroelectric layer. A conformal dielectric layer is formed over the surface of the ferroelectric layer, along sidewalls of the top electrode structure, and over a top surface of the top electrode structure. The conformal dielectric layer is etched back to form a sidewall dielectric spacer structure on the surface of the ferroelectric layer and along sidewalls of the top electrode structure. With the mask and dielectric sidewall spacer structure in place, a portion of the ferroelectric layer and a portion of the bottom electrode layer are removed.

Furthermore, other embodiments relate to a memory device having a bottom electrode structure and a top electrode overlying the bottom electrode structure. The top electrode has a first width measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure includes a top ferroelectric portion having the first width and a bottom ferroelectric portion having a second width greater than the first width such that a protrusion corresponds to a height where the top ferroelectric portion is hits the lower ferroelectric section. A sidewall dielectric spacer structure is disposed on the projection and covers outermost sidewalls of the top electrode.

Features of various embodiments are outlined above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to achieve the same purposes and/or advantages as the embodiments presented herein. It should further be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US16452965 [0001]
• US62738604 [0001]

Claims (20)

Integrated circuit comprising: a semiconductor substrate; an interconnect structure disposed over a top surface of the semiconductor substrate, the interconnect structure comprising: - a bottom metal layer; - an intermediate metal layer arranged over the bottom metal layer and an upper metal layer arranged over the intermediate metal layer; and - a bond pad layer disposed over the top metal layer, the top metal layer having a thickness greater than a thickness of the bottom metal layer; and a ferroelectric capacitor structure disposed within the interconnect structure, the ferroelectric capacitor structure comprising: - a lower electrode arranged over the upper surface of the semiconductor substrate; - a ferroelectric structure over the bottom electrode; and - a top electrode placed above the ferroelectric structure and below the bottom metal layer. Integrated circuit after claim 1 wherein the ferroelectric structure includes a top ferroelectric portion having the first width and a bottom ferroelectric portion having a second width such that a protrusion corresponds to a height where the top ferroelectric portion meets the bottom ferroelectric portion. Integrated circuit after claim 2 wherein the projection is spaced from a top surface of the ferroelectric structure by a distance that is about 5% to about 30% of the overall height of the ferroelectric structure. An integrated circuit according to any one of the preceding claims, further comprising: a dielectric sidewall spacer structure disposed around outer sidewalls of the top electrode; and a conductive residue disposed along outermost sidewalls of the sidewall dielectric spacer structure, along outermost sidewalls of the ferroelectric structure, and along outermost sidewalls of the bottom electrode. Integrated circuit after claim 4 , further comprising: a hard mask over a top surface of the top electrode. Integrated circuit after claim 5 , further comprising: a first dielectric liner along outermost sidewalls of the sidewall dielectric spacer structure and over a top surface of the hardmask. According to integrated circuit claim 6 , wherein the first dielectric liner includes silicon carbide. Integrated circuit after claim 6 or 7 , further comprising: a second dielectric liner along outermost sidewalls of the first dielectric liner and over a top surface of the first dielectric liner. Integrated circuit comprising: a semiconductor substrate; an interconnect structure disposed over a top surface of the semiconductor substrate, the interconnect structure comprising: - a bottom metal layer; - an intermediate metal layer arranged over the bottom metal layer; - an upper metal layer arranged over the intermediate metal layer; and - a bond pad layer disposed over the top metal layer, the top metal layer having a width and a thickness greater than a width and a thickness of the intermediate metal layer; and a ferroelectric capacitor structure disposed within the interconnect structure, the ferroelectric capacitor structure comprising: - a lower electrode arranged over the upper metal layer; - a ferroelectric structure over the bottom electrode; and - a top electrode located above the ferroelectric structure and below the bond pad layer. Integrated circuit after claim 9 , further comprising: a dielectric sidewall spacer structure disposed about outer sidewalls of the top electrode; and a dielectric hard mask disposed over the top electrode and disposed within inner sidewalls of the dielectric sidewall spacer structure. Integrated circuit after claim 10 , further comprising: a first liner along outermost sidewalls of the dielectric sidewall spacer structure and over a top surface of the dielectric hardmask; a second liner along outermost sidewalls of the first liner and over an upper surface of the first liner, the second liner having a second composition different from a first composition of the first liner; and a via extending through the dielectric hardmask, through the first liner, and through the second liner to make electrical contact with the top electrode. Integrated circuit after claim 10 or 11 , further comprising: a conductive residue disposed along outermost sidewalls of the sidewall dielectric spacer structure, along outermost sidewalls of the ferroelectric structure, and along outermost sidewalls of the bottom electrode structure. Integrated circuit after claim 12 , where the conductive residue contains a chemical species and the ferroelectric structure contains the chemical species. Integrated circuit comprising: a semiconductor substrate; an interconnect structure disposed over a top surface of the semiconductor substrate, the interconnect structure comprising: - a bottom metal layer; - several intermediate metal layers arranged at different heights above the bottom metal layer; - a plurality of upper metal layers arranged at different heights above the intermediate metal layers; and - a bond pad layer disposed over the multiple top metal layers, wherein each of the plurality of top metal layers has a width and a thickness greater than a width and a thickness of each of the plurality of intermediate metal layers; and a ferroelectric capacitor structure disposed within the interconnect structure, the ferroelectric capacitor structure comprising: a bottom electrode structure disposed over a top intermetallic layer of the plurality of intermetallic layers; a ferroelectric structure over the bottom electrode structure; and a top electrode structure disposed under a lowermost top metal layer of the plurality of top metal layers. Integrated circuit after Claim 14 , wherein the ferroelectric capacitor structure has a top ferroelectric portion having a first width and a bottom ferroelectric portion having a second width that is greater than the first width such that a protrusion corresponds to a height at which the top ferroelectric portion meets the bottom ferroelectric portion, and wherein the integrated circuit further comprises: a dielectric sidewall spacer structure disposed on the projection and covering outermost sidewalls of the top electrode structure. Integrated circuit after claim 15 , further comprising: a conductive residue disposed along outermost sidewalls of the sidewall dielectric spacer structure, along outermost sidewalls of the ferroelectric structure, and along outermost sidewalls of the bottom electrode structure. Integrated circuit according to one of Claims 14 until 16 , further comprising: a barrier layer along outer sidewalls of a bottom portion of the bottom electrode structure and along a bottom surface of the bottom portion of the bottom electrode structure. Integrated circuit according to one of Claims 14 until 17 , wherein the lower electrode structure, the ferroelectric structure and the upper electrode structure each have a U-shaped cross section and are concentric. Integrated circuit according to one of Claims 14 until 18 , further comprising: a dielectric sidewall spacer structure extending continuously from a top surface of the top electrode structure to a bottom surface of the bottom electrode structure. Integrated circuit according to one of Claims 14 until 19 , wherein the width of each of the plurality of top metal layers is greater than 0.1 micron and the thickness of each of the plurality of top metal layers is 1500 Angstroms to 10000 Angstroms, and wherein the width of each of the plurality of intermediate metal layers is greater than 50 nanometers and the thickness of each of the plurality Intermetallic layers is 500 Angstroms to 1500 Angstroms.

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