DE102021107019A1 - METHOD FOR MANUFACTURING A SEMICONDUCTOR LAYER SEQUENCE AND SEMICONDUCTOR LAYER SEQUENCE - Google Patents

Abstract

A method for producing a semiconductor layer sequence is specified, having the following steps: - applying a first region (2a) of a first semiconductor layer (2), which is based on group III nitrides, to a growth substrate (1), - applying an etching stop layer sequence ( 6) on the first area (2a) of the first semiconductor layer (2), - application of a second area (2b) of the first semiconductor layer (2), on the etch stop layer sequence (6), wherein - the etch stop layer sequence (6) has an etch stop layer (61) which is based on SiN, - the etch stop layer sequence (6) comprises a growth layer (62) which is based on AlGaN, and - the etch stop layer (61) faces the first region (2a) of the first semiconductor layer (2).

Description

A method for producing a semiconductor layer sequence and a semiconductor layer sequence are specified.

One problem to be solved is to specify a method with which a semiconductor layer sequence can be produced particularly economically. A further problem to be solved consists in specifying a correspondingly produced semiconductor layer sequence.

In accordance with at least one embodiment of the method for producing a semiconductor layer sequence, a first region of a first semiconductor layer, which is based on group III nitrides such as GaN, is applied to a growth substrate.

The growth substrate is a sapphire substrate, for example.

The first region of the first semiconductor layer is, for example, the first region of an n-doped semiconductor layer. This means that the first semiconductor layer can be, in particular, an n-conducting semiconductor layer.

The first semiconductor layer is based on group III nitrides, in particular on GaN. Here and below, “based on group III nitrides” or “based on GaN” can mean that the semiconductor layer consists of group III nitrides or GaN, except for dopants. Furthermore, “based on group III nitrides” or “based on GaN” can mean that the semiconductor layer is a ternary or quaternary mixed crystal based on GaN, such as InGaN or AlInGaN, except for dopants.

In accordance with at least one embodiment of the method, in a further method step, an etching stop layer sequence is applied to the first region of the first semiconductor layer.

The etch stop layer sequence comprises at least one etch stop layer based on SiN. This means that the etch stop layer is formed with or consists of a silicon nitride, in particular with Si ₃ N ₄ .

The etch stop layer sequence further includes at least one growth layer based on AlGaN. That is, the growth layer contains or consists of AlGaN. In this case, the growth layer can also contain one or more dopants.

In this case, the etch stop layer sequence can comprise a plurality of etch stop layers and a plurality of growth layers which are arranged alternately one above the other. In this case, the etching stop layer in each case faces the first region of the first semiconductor layer.

In accordance with at least one embodiment, the method for producing a semiconductor layer sequence comprises a further method step in which a second region of the first semiconductor layer, which is based on group III nitrides, for example on GaN, is applied to the etch stop layer sequence. The second region follows, in particular, a growth layer of the etch stop layer sequence. The composition of the second area can be identical to that of the first area. Furthermore, the second region can differ from the first region, for example with regard to the dopant concentration. Like the first region, the second region can be n-doped, for example. For example, the second region may be thinner than the first region.

• - Aufbringen eines ersten Bereichs einer ersten Halbleiterschicht, die auf Gruppe-III-Nitriden, zum Beispiel GaN, basiert, auf ein Aufwachssubstrat,
• - Aufbringen einer Ätzstoppschichtenfolge auf dem ersten Bereich der ersten Halbleiterschicht,
• - Aufbringen eines zweiten Bereichs der ersten Halbleiterschicht auf der Ätzstoppschichtenfolge, wobei
• - die Ätzstoppschichtenfolge eine Ätzstoppschicht umfasst, die auf SiN basiert,
• - die Ätzstoppschichtenfolge eine Aufwachsschicht umfasst, die auf AlGaN basiert, und
• - die Ätzstoppschicht dem ersten Bereich der ersten Halbleiterschicht zugewandt ist.

In accordance with at least one embodiment of the method for producing a semiconductor layer sequence, the method comprises the following steps:

• - Application of a first region of a first semiconductor layer based on group III nitrides, for example GaN, on a growth substrate,
• - Application of an etch stop layer sequence on the first region of the first semiconductor layer,
• - Application of a second region of the first semiconductor layer on the etch stop layer sequence, wherein
• - the etch stop layer sequence comprises an etch stop layer based on SiN,
• - the etch stop layer sequence comprises a growth layer based on AlGaN, and
• - the etch stop layer faces the first region of the first semiconductor layer.

The process steps described here can, for example, take place directly one after the other in a growth chamber, for example a MOVPE reactor. The individual layers, in particular also the etch stop layer sequence, are then applied in situ. In particular, the semiconductor layers are grown epitaxially.

The semiconductor layer sequence produced in this way can be used, for example, in an electronic semiconductor chip, in particular an optoelectronic semiconductor chip. The optoelectronic semiconductor chip can be, for example wise be a light emitting diode chip such as a light emitting diode chip.

The method described here is based, inter alia, on the following considerations. In order to increase the extraction efficiency of a light-emitting diode chip, which is based on InGaN, for example, a roughening step is carried out after the semiconductor layer sequence has been detached from the growth substrate, in which a KOH solution is used, for example. This roughening step, in which the semiconductor material is partially dissolved, forms pyramidal structures. Light generated in the semiconductor chip is refracted at the facets of the pyramids and can consequently leave the semiconductor chip, with the probability of total internal reflection being reduced. This makes the light-emitting diode chip brighter and more efficient.

However, the roughening step is an etching step, which is destructive. The remaining thickness of the semiconductor layer sequence is reduced as the etching time increases. In the extreme case, if the etching is carried out for too long, for example, functional areas of the semiconductor layer sequence, such as an active layer sequence, are also dissolved and thus destroyed. Short circuits can then occur in the component, for example.

The method is now based, inter alia, on the consideration that an etching stop layer can be used to prevent penetration of the active layer sequence in particular during etching. It has been shown that silicon nitride cannot be etched by KOH or only extremely slowly, with an etching speed of less than 0.2 nm/m. An etching stop layer based on SiN can, for example, be deposited in situ in the growth device, in particular a MOVPE reactor, by using the precursors SiH ₄ and NH ₃ . The etch stop layer can be made a few atomic layers thick and acts as an etch stop layer in wet-chemical etching using KOH.

However, the pure in situ deposition of such an etch stop layer induces the 3D growth mode during the deposition of the group III nitride or GaN based semiconductor layer. This can be undesirable as it creates Group III nitrides or GaN islands that must first coalesce before the 2D growth mode resumes. As a result, a relatively thick semiconductor layer has to be deposited.

A finding on which the method described here is based is now that a growth layer that is based on AlGaN and that follows the etch stop layer in the direction of growth leads to the growth mode remaining unaffected during the subsequent deposition of the second region of the first semiconductor layer and thus to a 2D growth occurs. After the etch stop layer, the group III nitride-based or the GaN-based semiconductor layer can be further grown in the same way as before the etch stop layer. An additional three-dimensional layer for the coalescence of islands of semiconductor material is not required. This brings great advantages in terms of the process time, the process costs and possibly also the stress management of the semiconductor layer sequence. The thicker the deposited semiconductor layer sequence is, the greater and more problematic can be stresses that are due, for example, to different thermal expansion coefficients between the growth substrate, which is formed with sapphire, for example, and the semiconductor layer sequence.

At the same time, there is the advantage of an etch stop layer as a targeted safeguard against excessive etching, which would result in the total failure of a component with the semiconductor layer sequence. The use of an etch stop layer can thus increase the roughening time process window before component failure can occur. Since the duration of the roughening is linked directly to the extraction efficiency of, for example, an optoelectronic, radiation-emitting component with the semiconductor layer sequence, the extraction efficiency can be increased by the method described here without a yield loss occurring.

A semiconductor layer sequence is also specified. The semiconductor layer sequence described here can be produced in particular using a method described here. This means that all the features disclosed for the method are also disclosed for the semiconductor layer sequence and vice versa.

In accordance with at least one embodiment of the semiconductor layer sequence, the semiconductor layer sequence comprises a first region of a first semiconductor layer which is based on group III nitrides, for example GaN. Furthermore, the semiconductor layer sequence comprises an etch stop layer sequence on the first region of the first semiconductor layer. The etch stop layer sequence can, for example, directly adjoin the first region of the first semiconductor layer. The semiconductor layer sequence comprises a second region of the first semiconductor layer on that side of the etch stop layer sequence which is remote from the first region. The first semiconductor layer can be an n-doped semiconductor, for example layer of the semiconductor layer sequence. The etch stop layer sequence comprises at least one etch stop layer based on SiN and a growth layer based on AlGaN.

The layers described can in particular follow one another directly in the semiconductor layer sequence. The etch stop layer sequence can comprise an alternating sequence of etch stop layers and growth layers.

The following embodiments relate in particular to the method and the semiconductor layer sequence.

In accordance with at least one embodiment, an active layer sequence is applied to the second region of the first semiconductor layer. The active layer sequence can be a single or multiple quantum well structure, for example. The active layer sequence forms the functional area of the component in the subsequent component. For example, the active layer sequence is provided for generating electromagnetic radiation such as blue light. A second semiconductor layer can then be applied to the active layer sequence. The second semiconductor layer can, for example, likewise be based on group III nitrides, for example on GaN. The second semiconductor layer is then in particular p-doped.

In accordance with at least one embodiment, the growth substrate, the first region of the first semiconductor layer and the etch stop layer sequence are removed after the second semiconductor layer has been applied.

The growth substrate can be removed, for example, by a laser detachment process.

The first region of the first semiconductor layer can be removed by etching, in particular with KOH.

The etch stop layer sequence can be removed, for example, by dry etching, wet etching and/or polishing.

Furthermore, it is possible that the etch stop layer sequence remains in the component and the first region of the first semiconductor layer is only partially removed. In this case, the first region of the first semiconductor layer has a roughened outer surface, with the roughening not leading to damage to the active layer sequence due to the etch stop layer.

In accordance with at least one embodiment, the etch stop layer sequence comprises an alternating sequence of etch stop layers and growth layers. For example, the etch stop layer sequence comprises three or more etch stop layers and three or more growth layers. It has been shown that the formation of pyramids during roughening can result in the selectivity of the etch stop layer decreasing the deeper it is used in the material. This may be due to the fact that the Z amplitude or roughness of the surface increases and the etch stop layer is thus reached at different times in different areas of the wafer. This can be prevented by an alternating arrangement of etch stop layer and growth layers. The selectivity at the etch stop layer can be multiplied by the sequence of a plurality of SiN-based etch stop layers, and as a result a sufficient etch stop effect can be achieved even with a deeper-lying etch stop layer.

The etch stop layer sequence may include etch stop layers and growth layers formed as described herein. In particular, the etching stop layers and the growth layers can each be formed in the same way. This means that all etch stop layers can have the same thickness and/or the same material composition within the scope of the manufacturing tolerance. This also means that all growth layers can have the same thickness and/or the same material composition within the scope of the manufacturing tolerance.

In accordance with at least one embodiment, an etch stop layer is directly adjacent to the first region of the first semiconductor layer and a growth layer is directly adjacent to the second region of the first semiconductor layer.

Furthermore, it is possible for a first growth layer to be arranged between the etching stop layer and the first region.

In accordance with at least one embodiment, a further etching stop layer, which is based on SiN and directly borders the growth layer and the second region of the first semiconductor layer, is arranged between a growth layer and the second region of the first semiconductor layer. A 3D growth in the semiconductor layer sequence can be induced by this further etching stop layer. This further etching stop layer is then not followed by a growth layer in the direction of growth. This can be advantageous if defects in the semiconductor layer sequence are to be further reduced by inducing 3D growth.

In accordance with at least one embodiment, the first region of the first semiconductor layer has a thickness of at least 30 nm and at most 3 µm, for example 300 nm. For example, the first region of the first semiconductor layer has a thickness of 2 μm. The first region of the first semiconductor layer is thus made relatively thin. This is possible because the further layers, that is to say for example the second region of the first semiconductor layer, are protected from damage by the etch stop layer sequence. In this way, after the detachment of the growth substrate, as little epitaxially grown semiconductor material as possible has to be removed during the roughening.

In accordance with at least one embodiment, the second region of the first semiconductor layer has a thickness of less than 1 μm. Such a thin second region is possible since the subsequent active layer sequence is protected by the etch stop layer sequence described here when the first semiconductor layer is detached and etched.

In accordance with at least one embodiment, the etch stop layer has a thickness of at most 5 atomic layers. The etch stop layer can be formed, for example, as a sub-monolayer layer or monolayer layer. In addition, it is possible for the etch stop layer to have a thickness of at most 3 atomic layers.

In accordance with at least one embodiment, the growth layer has a thickness of between at least 15 nm and at most 45 nm, in particular approximately 30 nm.

According to at least one embodiment, the growth layer is formed with Al _x Ga _1-x N with 0.05<x<0.2, in particular x=0.11. Such a growth layer with the composition described and with the thickness described proves to be particularly advantageous for inducing a 2D growth. In addition, such a layer has particularly low absorption for electromagnetic radiation generated in the active layer sequence. Such a growth layer can therefore advantageously remain in the semiconductor layer sequence and thus in the finished component.

The aluminum concentration specified applies in particular to the use of the semiconductor layer sequence in a radiation-emitting component with a peak of the emission wavelength of greater than or equal to 360 nm with InGaN quantum wells in the active layer. When using the semiconductor layer sequence in a radiation-emitting component with a peak emission wavelength of less than 360 nm UV-LEDs, the first semiconductor layers would be formed from AlGaN. Significantly higher aluminum concentrations are then possible for the growth layer.

The values given here for the thickness and the composition of layers in the growth layer sequence relate in each case to all etching stop layers and growth layers in the etching stop layer sequence.

In accordance with at least one embodiment, the first region of the first semiconductor layer is n-doped and roughened, the roughening not penetrating the etch stop layer sequence.

The method described here and the semiconductor layer sequence described here are described in more detail below with reference to exemplary embodiments and the associated figures.

Elements that are the same, of the same type or have the same effect are provided with the same reference symbols in the figures. The figures and the relative sizes of the elements shown in the figures are not to be regarded as being to scale. Rather, individual elements can be shown in an exaggerated size for better representation and/or for better comprehensibility.

Based on the schematic sectional views of 1A until 1D a comparative example for a method described here is explained in more detail in which an etching stop layer sequence described here is not used.

In conjunction with the schematic sectional views of 2A until 2E an exemplary embodiment of a method described here is explained in more detail.

The schematic sectional view of the 3 shows an exemplary embodiment of a semiconductor layer sequence described here.

The schematic sectional views of the 4A until 4C show examples of etch stop layer sequences as are used in exemplary embodiments of the methods and semiconductor layer sequences described here.

Based on the graphical representation of the 5 the procedure described here is explained in more detail.

In conjunction with the schematic sectional views of 1A until 1D a comparative example of a method described here is explained in more detail. In the method, a first semiconductor layer 2 is applied to a growth substrate 1, 1A . The semiconductor layer 2 is based on group III nitrides, for example on GaN, the growth substrate is formed with sapphire, for example de. An active layer sequence 3 is then applied to the first semiconductor layer 2 . The active layer sequence 3 is followed by a second semiconductor layer 4 which, for example, is also based on group III nitrides, for example on GaN. In this case, the first semiconductor layer 2 can in particular be n-doped and the second semiconductor layer 4 is p-doped.

A carrier 5 is then attached to the side of the semiconductor layer sequence which is remote from the substrate 1, 1B . The carrier 5 can be a silicon substrate, for example.

In a subsequent method step, the growth substrate 1 is removed, for example by means of a laser detachment method, 1C .

To increase the light yield, the first semiconductor layer 2 is roughened with KOH at a high temperature of approximately 80°. Deep damage and crystal damage 8 such as tears, which originate from the pre-process of detaching the substrate 1, are etched deeper into the material during the roughening than is the case in the surrounding, less damaged areas. When the target removal or the target roughness is reached, it can then happen that the original crystal damage 8 already extends into the active layer sequence 3 . This may lead to an aging risk and often to short circuits and thus to the immediate failure of the manufactured component, see 1D .

In conjunction with the schematic sectional views of 2A until 2E an exemplary embodiment of a method described here is explained in more detail. In the method, a first region 2a of a first semiconductor layer 2, which is based on group III nitrides, for example on GaN, is applied to a growth substrate 1, which is formed with sapphire, for example.

An etching stop layer sequence 6 is then applied to the first region 2a of the first semiconductor layer 2 .

The etch stop layer sequence 6 can, as in FIG 4A shown, may include, for example, an etch stop layer 61 based on SiN and a growth layer 62 based on AlGaN. It is also possible that the etch stop layer sequence, as shown schematically in FIG 4B shown, alternatingly comprises a plurality of etch stop layers 61 and a plurality of growth layers 62 . Finally, it is possible, as shown schematically in the 4C shown that such an etch stop layer sequence, as in the 4A or 4B is shown, followed by another etch stop layer 7 formed with SiN.

Like in the 2A is shown, after the application of the etch stop layer sequence 6, a second region 2b of the first semiconductor layer 2 is applied.

How further in the 2A is shown, an active layer sequence 3 is applied to the second region 2a of the first semiconductor layer 2, which is provided in the subsequent component, for example for generating radiation. The active layer sequence 3 is followed by a second semiconductor layer 4. The first semiconductor layer 2 is n-doped, for example, and the second semiconductor layer 4 is then p-doped. All layers can be deposited in situ in the growth chamber.

In a subsequent process step, 2 B , a carrier 5 is applied to the side of the second semiconductor layer 4 facing away from the growth substrate 1, which carrier can be a silicon carrier, for example.

In the next step, 2C , the growth substrate 1 is detached, for example by a laser detachment method, and the first region 2a of the first semiconductor layer 2 is subsequently roughened by wet-chemical etching with, for example, KOH. During this etching, the etching process at the etch stop layer sequence 6 is selectively stopped. Depending on how selective the etch stop layer sequence is required, the described sequence of several SiN/AlGaN sequences can be installed. The growth layer, which is based on AlGaN, faces away from the first area 2a of the first semiconductor layer and faces the second area 2b. Because of the etch stop layer sequence 6, the active layer sequence 3 is not damaged.

The result is a component with a semiconductor layer sequence, as is the case, for example, in FIG 3 is shown. In this case, the second region 2a of the first semiconductor layer 2 can be made particularly thin and have a thickness of less than 1 μm, for example.

Alternatively, it is possible for the removal of the first region 2a of the first semiconductor layer 2 to be continued until the first region 2a has been completely removed. 2D .

After the etch stop layer sequence 6 has been uncovered in this way, the etch stop layer sequence can be removed either mechanically by polishing, wet-chemically using controlled etching conditions, for example with buffered hydrofluoric acid, or dry-chemically over the entire area.

In this way, a homogeneous one based on Group III nitrides, for example GaN-based surface exposed, which in turn can be roughened by hot KOH without being affected by the previous laser detachment process. In this case, a semiconductor layer sequence results, as shown in FIG 2E is shown schematically.

In connection with the graphic application of the 5 the procedure described here is explained in more detail.

The ICP-OES method is used to determine the selectivity of the etch stop layer sequence 6 . In this case, a sample is taken from the KOH solution at different etching times, in which the gallium nitride material of the semiconductor layer 2 is etched and the concentration of the dissolved and thus etched gallium is determined therein. This gallium concentration is converted into a mean etching removal, measured in nm, via the area and density of gallium nitride of the entire semiconductor layer sequence. Before etching, the damage caused by the laser ablation process is removed with a mechanical polishing step to achieve good reproducibility of the readings.

In order to examine the functionality of the SiN/AlGaN layer stack as an etch stop layer sequence 6, first semiconductor layer sequences are grown which contain no etch stop layer 61 (sample A) or a simple SiN etch stop layer 61 (sample B). The etching behavior determined from these layer stacks are in the 5 shown.

In the case of sample A, a decrease in the etch rate from 600 nm etch removal z (GaN) can be seen. From this point a constant etch rate is observed up to a total time of 5 min.

In comparison, the introduction of a SiN etch stop layer 61 after 300 nm in sample B resulted in a plateau being reached which prevents significant etch removal between 0.5 min and 1.5 min. After 2 min etch time, the etch rate of sample B increases significantly, which can be attributed to switching to the 3D growth mode. The etch rate of the material after the SiN layer is therefore significantly higher than in the reference material of sample A, which does not contain a SiN etch stop layer 61 .

In comparison, sample C, which after a 300 nm thick GaN layer has a combined etch stop layer sequence 6 consisting of a SiN etch stop layer 61 and a 30 nm thick Al _0.11 Ga _0.89 N growth layer 62, shows the identical plateau formation is observed in sample B.

However, after penetrating the plateau, the identical etching rate that is also shown in sample A sets in. Thus, the introduction of the Al _0.11 Ga _0.89 N layer after the SiN etch stop layer 61 means that although the etch stop layer 61 is functional on the one hand, the material properties relevant for the etching are not changed on the other hand resulted in an identical etch rate as for Sample A.

The invention is not limited to these by the description based on the exemplary embodiments. Rather, the invention encompasses every new feature and every combination of features, which in particular includes every combination of features in the patent claims, even if this feature or this combination itself is not explicitly stated in the patent claims or exemplary embodiments.

Reference List

1

growth substrate

2

first semiconductor layer

2a

first region of the first semiconductor layer

2 B

second region of the first semiconductor layer

3

active layer sequence

4

second semiconductor layer

5

carrier

6

etch stop layer sequence

61

etch stop layer

62

wax layer

7

another etch stop layer

8th

crystal damage

Claims (15)

Method for producing a semiconductor layer sequence with the following steps: - applying a first region (2a) of a first semiconductor layer (2), which is based on group III nitrides, to a growth substrate (1), - Application of an etching stop layer sequence (6) on the first region (2a) of the first semiconductor layer (2), - Application of a second region (2b) of the first semiconductor layer (2) on the etch stop layer sequence (6), wherein - the etch stop layer sequence (6) comprises an etch stop layer (61) based on SiN, - the etch stop layer sequence (6) comprises a growth layer (62) which is based on AlGaN, and - the etch stop layer (61) faces the first region (2a) of the first semiconductor layer (2). Method according to the preceding claim, wherein - an active layer sequence (3) is applied to the second region (2a) of the first semiconductor layer (2), and - a second semiconductor layer (4) is applied to the active layer sequence (3). Method according to one of the preceding claims, wherein - The growth substrate (1), the first region (2a) of the first semiconductor layer (2) and the etch stop layer sequence (6) are removed after the application of the second semiconductor layer (4). Method according to one of the preceding claims, wherein the etch stop layer sequence (6) comprises an alternating sequence of etch stop layers (61) and growth layers (62). Method according to the preceding claim, wherein the etch stop layer sequence (6) comprises three or more etch stop layers (61) and three or more growth layers (62). Method according to one of the preceding claims, wherein an etch stop layer (61) directly borders the first region (2a) of the first semiconductor layer (2) and a growth layer (62) directly borders the second region (2b) of the first semiconductor layer (2). Procedure according to one of Claims 1 until 5 , wherein between a growth layer (62) and the second region (2b) of the first semiconductor layer (2) a further etching stop layer (7) is arranged, which is based on SiN and is directly attached to the growth layer (62) and the second region (2b) the first semiconductor layer (2) borders. Method according to one of the preceding claims, in which the first region (2a) of the first semiconductor layer (2) has a thickness of at least 30 nm and at most 3 µm. Method according to one of the preceding claims, in which the second region (2a) of the first semiconductor layer (2) has a thickness of less than 1 µm. Method according to one of the preceding claims, in which the etch stop layer (61) has a thickness of at most 5 atomic layers. Method according to one of the preceding claims, wherein the growth layer (62) has a thickness of between at least 15 nm and at most 45 nm. A method according to any one of the preceding claims, wherein the growth layer (62) comprises Al _x Ga _(1-x) N with 0.05 < x < 0.2. Method according to one of the preceding claims, wherein the second region (2a) of the first semiconductor layer (2) grows in a 2D growth mode on the etch stop layer sequence (6). Semiconductor layer sequence with - a first region (2a) of a first semiconductor layer (2) based on group III nitrides, - an etching stop layer sequence (6) on the first region (2a) of the first semiconductor layer (2), - A second region (2b) of the first semiconductor layer (2), on the etch stop layer sequence (6), wherein - the etch stop layer sequence (6) comprises an etch stop layer (61) based on SiN, - the etch stop layer sequence (6) comprises a growth layer (62) which is based on AlGaN, and - the etch stop layer (61) faces the first region (2a) of the first semiconductor layer (2). Semiconductor layer sequence according to the preceding claim, in which the first region (2a) of the first semiconductor layer (2) is n-doped and roughened, the roughening not penetrating the etching stop layer sequence (6).

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