DE102021104265A1 - Controller, electronic component and electronic system - Google Patents

Abstract

A controller is provided that has an interface to an interrupt signal generating component, a live signal generator configured to generate a live signal and provide the alive signal to the interface, and an interrupt handler configured to receive an interrupt signal by means of the interface, the interface having a common line both for providing the life signal and for receiving the interrupt signal.

Description

The invention relates to a controller, an electronic component and an electronic system.

In many applications, such as those where reliability is essential, there is often a need to communicate certain information between two or more devices or to share this information with multiple devices.

For example, there may be a control device (also referred to as a controller), such as a microcontroller, and a second device, which may have functions or modules.

A typical monitoring function of modern (micro)controllers 102 is a life signal LS, also referred to as FSP (for "functional safety pin") or "clock monitoring".

A monitoring module LG in the controller 102 constantly monitors the internal status of the controller 102 and collects error indications from various internal units.

If a serious functional problem is detected within the controller 102, the information is forwarded to a device (e.g. the second device 104) external to the controller 102 to take appropriate action, e.g. bring the other devices to a safe state.

In order to also recognize a stuck state as an error state, an alternating signal LS, also referred to as a life signal or heartbeat, is generated by the controller 102, which stops alternating when a malfunction or a serious error state of the controller 102 is recognized. this is in 2A illustrated.

The live signal LS is received and monitored by the second device 104 . If the signal stops alternating, a reset request RR can be triggered, or another reaction, e.g. disabling a power supply or an output driver.

Apart from the life signal LS, the system 400 can generate and transmit other signals (eg Reset RS, Interrupt IS). This is an example in 1A illustrated.

In this case, the reset RS can be provided for more serious error states such as short circuits in supply lines or overheating, and the interrupt IS for less critical states.

The second device 104 may inform the controller of its status, where the second device 104 may be, for example, an actuator control device, a power supply, a communication transceiver, or a sensor device.

This status information can be important, for example, to provide voltage in the correct range and/or to prevent damage due to faulty devices.

There are many different ways to inform the controller about the state of the second device, for example using a communication interface, e.g. UART or SPI, using a serial bit stream.

In this case, a timing of such a communication interface can be controlled by the controller, and the second device can only transmit the information while observing this specified timing.

If there is a condition in the second device, for example a detected alarm condition such as overheating or excessive current, the controller must be informed and react within a certain time window.

However, if the required response time is shorter than an update rate of the communication interface, or the communication interface is unable to send a response due to a problem, an additional information mechanism may need to be used.

1 Figure 1 shows an electronic system 100 having a controller 102 and a second device 104 connected by means of a communication interface 106 1 and a second communication channel 106 2 .

This enables the second device 104 to inform the controller 102 via the second communication channel 106 2 of its status within self-selected timings that satisfy the required response times.

The second communication channel 106 2 can transmit a separate signal IS (also referred to as an interrupt signal, interrupt request or interrupt request) from the second device 104 to the controller 102 . The interrupt signal IS can be generated in the second device 104 as a result of an interrupt event IE by means of an interrupt generator IG.

The controller 102 can respond to a receipt of the interrupt signal IS, e.g others, or something like that.

In addition, the controller 102 informs the second device 104 about a reset state (also referred to as a reset state) of the controller 102. During a reset, the controller 102 transfers at least some of its functions to a defined (initial) state and only provides limited functionality.

Such a condition can occur, for example, when the controller 102 is not fully functional, for example because a power supply is not working properly, or there is an error condition, e.g., within a data memory. This is generally symbolized as a reset event RE, which a reset handler RH processes to generate the reset signal RS.

It may be advantageous to also set the second device 104 (or at least parts thereof) to a defined state (e.g. an initial state) during the reset of the controller 102, so that the function can be resumed after the reset in both devices 102, 104 from one defined state can take place.

The reset signal RS is typically transmitted from the controller 102 to the second device 104 by means of a dedicated signal line 106_1.

For a pure functionality of the data transmission, it is not necessary for a reset signal RS transmitted by the controller 102 to be read back by the controller 102 or for an interrupt signal IS transmitted by the second device 104 to be read back by the second device 104 accordingly.

In cases in which operational reliability plays a role, such a readback can still be necessary in order to check the signal line 106_1, 106_2, for example for short circuits.

As in 1A As shown, the respective signal line 106_1, 106_2 may be connected to open drain outputs 110, 118, respectively, and pull-up devices 108_1, 108_2, respectively.

Such a structure of the signal line is often used when it is necessary or optional to connect more than one event-generating device (e.g. more than a second device 104), which can also trigger the reset or the interrupt, to an input of the information-receiving device (here the controller 102).

Typical waveforms for reset and interrupt signals in a system 100 as in 1A is shown and is often used, for example, in connection with controllers, actuator controls and / or sensors, are in 1B shown. Response times, filter times, etc. are omitted for simplicity.

As shown there, there is a switchover from a high voltage value to a low voltage value on the line 106_1 for the reset signal RS when a reset state is present.

Similarly, when an interrupt state is present, there is a switchover from a high voltage value to a low voltage value on the line 106_2 for the interrupt signal IS.

The system 100 off 1A however, has a disadvantage in that two signals and two interfaces (eg pins and lines 106_1, 106_2) are required per device 102, 104.

This may be of secondary importance for the controller 102, e.g. a microcontroller, since these are typically provided as packages with a large number of pins (e.g. significantly more than 100).

On the other hand, electronic devices 104, such as sensors or actuator controllers, are typically provided in packages with relatively few pins, e.g., 24, 32, 48, or 64 pins, so each is valuable and should be optimally utilized.

The second device 104 can be, for example, a power supply circuit, also referred to as a “power management IC” (PMIC). Such a system 400 is, together with a controller 102, in 4B shown.

Like the (eg micro)controller 102, the second device 104 can have built-in function tests which can trigger suitable predetermined reactions, for example the provision of the reset signal RS, which is distributed within the system (eg to the second device 104). can be and both the controller 102 and the second device 104 in a predetermined state, eg a before certain operationally safe condition.

The generation of the power supply can be closely coupled to the reset generation and transmission, because if the power supply is not within a predetermined range or is switched off, the affected components must be informed, e.g. by means of a reset signal RS. This shows that an additional monitoring function should also trigger a reset if an error affecting the reset signal generation is detected.

The statements made above regarding the reset and interrupt also apply to the life signal, namely that the controller 102 and the second device 104 each require their own line 106_1, 106_2, 106_3 for each function to be transmitted. In addition, it may be necessary to then also provide a check as to whether these lines 106_1, 106_2, 106_3 are connected, in particular with regard to the interrupt signal and the life signal IS, LS.

The task thus arises of how standard functions such as reset and/or interrupt signaling and/or transmission of a life signal can be provided with a reduced number of interfaces. Because that can make it possible to provide additional functionalities within the same package.

In various exemplary embodiments, a signal line is provided between two devices, for example between a controller and an electronic component (component for short), in order to transmit events occurring in one of the devices to the other of the devices. The signal line can be considered as a “split” signal line because the same line is split for signals in one direction and for signals in the other direction.

In various exemplary embodiments, the signals can have an interrupt signal and a life signal.

The signals may include a reset signal (also referred to as a reset signal) and a live signal in various embodiments.

In various exemplary embodiments, the signals can have an interrupt signal, a reset signal and a life signal.

In various exemplary embodiments, the same interface, for example the same line and the same data input/output (pin), can be used in a controller to transmit at least two types of signals, namely an interrupt signal and a life signal, and optionally also a reset signal. between the controller and an electronic component connected to the line. Alternatively, the two types of signals may include the reset and live signals, and the interrupt signal may be optional.

In a complementary case, in various embodiments, the same interface, for example the same line and the same data input/output (pin), can be used in an electronic component to transmit at least two types of signals, namely an interrupt and a life signal, and optionally additionally a reset signal, between the electronic component and a controller connected to the line. Alternatively, the two types of signals may include the reset and live signals, and the interrupt signal may be optional.

In various embodiments, in a system having a controller and an electronic component, each according to various embodiments, a single common line for transmitting a live signal and at least one other signal, e.g. a reset and/or interrupt signal to be provided.

According to various exemplary embodiments, it is possible to reduce a number of interfaces (e.g. lines and pins), which are required for the transmission of two signals (life and reset signal or interrupt and life signal), from two to one without adding any functionality affect.

According to various embodiments, it is possible to reduce a number of interfaces (e.g. lines and pins) required for transmitting three signals (reset and interrupt and life signals) from three to one without impairing functionality.

According to the reduced number of interfaces (e.g. pins), which are required to provide the basic functions, additional functions can be provided that require an output at one of the interfaces that have become free.

In various exemplary embodiments, the data transmission described can be provided as a redundant system. For example, two interfaces (e.g. lines, pins) are provided, which are each used to transmit a life signal and at least one additional signal (reset and/or interrupt signal), the data transmission being mutually redundant.

In various exemplary embodiments, the interface (e.g. lines, pins), which is used to transmit a life signal and at least one additional signal (reset and/or interrupt signals), can be provided as a redundant system for at least one conventional interface, for example as related to 1A described.

Systems with only one controller and one electronic component are described herein. It is understood that a variety of electronic components can be used, each having an interface that can be connected to the controller.

Exemplary embodiments of the invention are shown in the figures and are explained in more detail below.

• 1A eine schematische Darstellung eines elektronischen Systems, und 1B Signale, die im System aus 1A übermittelt werden;
• 2A Signale, die in einem elektronischen System gemäß dem Stand der Technik aus 2B übermittelt werden;
• 3A und 3B jeweils eine schematische Darstellung eines elektronischen Systems gemäß verschiedenen Ausführungsbeispielen, wobei jedes der elektronischen Systeme einen Controller gemäß verschiedenen Ausführungsbeispielen und eine elektronische Komponente gemäß verschiedenen Ausführungsbeispielen aufweist;
• 4A bis 4E jeweils eine Veranschaulichung von Signalen, die in einem System gemäß verschiedenen Ausführungsbeispielen übermittelt werden;
• 5 ein Flussdiagramm eines Verfahrens zum Betreiben eines Controllers gemäß verschiedenen Ausführungsbeispielen;
• 6 ein Flussdiagramm eines Verfahrens zum Betreiben einer elektronischen Komponente gemäß verschiedenen Ausführungsbeispielen; und
• 7 ein Flussdiagramm eines Verfahrens zum Betreiben eines elektronischen Systems gemäß verschiedenen Ausführungsbeispielen.

Show it

• 1A a schematic representation of an electronic system, and 1B signals in the system 1A be transmitted;
• 2A Signals in an electronic system according to the state of the art 2 B be transmitted;
• 3A and 3B each shows a schematic representation of an electronic system according to different embodiments, each of the electronic systems having a controller according to different embodiments and an electronic component according to different embodiments;
• 4A until 4E each an illustration of signals transmitted in a system according to various embodiments;
• 5 a flowchart of a method for operating a controller according to various embodiments;
• 6 a flowchart of a method for operating an electronic component according to various embodiments; and
• 7 a flowchart of a method for operating an electronic system according to various exemplary embodiments.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "front", "rear", etc. is used with reference to the orientation of the figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It is understood that the features of the various exemplary embodiments described herein can be combined with one another unless specifically stated otherwise. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Within the scope of this description, the terms "connected", "connected" and "coupled" are used to describe both a direct and an indirect connection, a direct or indirect connection and a direct or indirect coupling. In the figures, identical or similar elements are provided with identical reference symbols, insofar as this is appropriate.

3A and 3B 12 each show a schematic representation of an electronic system 200 according to various exemplary embodiments, each of the electronic systems 200 having a controller 202 according to various exemplary embodiments and an electronic component 204 according to various exemplary embodiments.

4A until 4E 12 each show an illustration of signals transmitted in an electronic system 200 according to various exemplary embodiments.

The electronic system 200 may include the controller 202, such as a microcontroller, and the electronic component 204 according to various embodiments, such as a power supply circuit (e.g., PMIC), a sensor circuit, a communication transceiver, an actuator controller, or the like.

The controller 202 can have an interface 206, 212, 216 to a component 204 that generates an interrupt signal.

The interrupt signal IS can be received and encoded in the form of one or more signal pulses, which can be formed by a pulse generator (not shown), which can be formed as a separate circuit or as part of the interrupt generator IG.

In various exemplary embodiments, the controller 202 also has a life signal generator LG set up to generate a life signal LS and to provide the life signal at the interface 206, 212, 216, the common line 206 also being set up to provide the life signal LS.

The life signal LS can be formed in the form of a plurality of signal pulses in a defined frequency range and encoded in the signal pulse width T0. As soon as a detector LM in the electronic component 204 detects a frequency outside the defined frequency range, an error can be signaled to other functional units in the component 204 .

The signal pulse width T0 of the life signal LS from the controller 202 to the electronic component 204 can be smaller than a signal pulse width T2 of the interrupt signal IS.

The interface 206, 212, 216 can have a common line 206 for providing both the life signal LS and the interrupt signal IS.

The interrupt signal IS can be received in the form of one or more signal pulses and encoded in the signal pulse width T2.

In various exemplary embodiments, the interrupt handler ID can be set up to decode the interrupt signal IS.

In various exemplary embodiments, the signal pulse width T2 of the interrupt signal IS can be greater than a signal pulse width T0 of the life signal. In addition, the signal pulse width T2 of the interrupt signal IS can be smaller than a signal pulse width T4 of a reset signal RS from the controller 202 to the electronic component 204.

In various exemplary embodiments, the life signal generator LG can be set up to connect the interface 206, 212, 216 to a ground connection in order to generate the life signal LS (so-called open-drain interface). Is in 2 B , 3A and 3B shown. The interface 206, 212, 216 can be permanently connected to a supply voltage 208, which serves as a pull-up device, and the ground connection can serve as a pull-down device, which is only then connected to the interface 206, 212, 216 , if the life signal LS is to be generated and made available at the interface 206, 212, 216.

In the opposite case, the life signal generator LG can be set up to connect the interface 206, 212, 216 to a supply voltage, which is not shown in the figures. In that case, the interface 206, 212, 216 can be permanently connected to a ground connection as a pull-down device, and the supply voltage can serve as a pull-up device, which is connected to the interface 206, 212, 216 only when if the life signal LS is to be generated and made available at the interface 206, 212, 216.

The controller 202 can also have a reset signal generator RH, set up to generate the reset signal RS and to provide the reset signal RS at the interface 206, 212, 216, and an interrupt handler ID, set up to receive an interrupt signal IS by means of the Interface 206, 212, 216. This is in 3A and 3B illustrated.

In various embodiments, the electronic component 204 can (alternatively or additionally) transmit a life signal to the controller 202, for example by means of the interface 206, 212, 216. The life signal from the component 204 to the controller 202 can be in the form of a plurality of signal pulses in one defined frequency range and encoded in the signal pulse width T1. The signal pulse width T1 of this life signal can be wider than the signal pulse width T0 of the life signal from the controller 202 to the component 204, but narrower than the signal pulse width T2 of the interrupt signal IS and/or the signal pulse width T4 of the reset signal RS from the controller 202 to the component 204. The component 204 can receive the life signal, which is generated by the controller 202 with the signal pulse width T0, and lengthen the signal pulse with the aid of an output driver (e.g. also open-drain) in such a way that the signal pulse width T1 is produced.

In various exemplary embodiments, the component 204 can be set up to transmit a reset signal to the controller via the interface 206, 212, 216. The reset signal from the component 204 to the controller 202 can be formed in the form of a plurality of signal pulses and encoded in the signal pulse width T3 be. In this case, the generated by the controller 202 Signal pulse length T0 are extended by the component 204 to the signal pulse width T3.

Illustrations of the priorities of the signal pulse widths T0 to T4 are in 4A until 4E shown and explained in more detail in connection with it.

In various exemplary embodiments, the controller 202 can be set up to measure the signal pulse length at the interface 206, 212, 216 and thus to receive a reset signal RS (e.g. with the signal pulse width T3) and to reset the controller 202. Measuring the signal pulse width (also referred to graphically as the signal pulse length) in the controller 202 makes it possible to distinguish between the different extensions of the signal pulse width by the component 204 . Different operating states can be encoded by different signal pulse lengths. The frequency of the live signal LS may contain information about the operational state of the controller 202, while the resulting signal pulse length may contain information about the operational state of the component 204. Different signal pulse widths can lead to different responses in the controller 202 .

The electronic component 204, which has an interface 206, 212, 216 to the controller 202, can have a reset signal receiver RD, which can be set up to receive a reset signal RS via the interface 206, 212, 216.

The electronic component 204 can also have an interrupt signal generator IG, which can be set up to generate an interrupt signal IS and to provide the interrupt signal IS by means of the interface 206, 212, 216, the interrupt signal IS in Is encoded in the form of one or more signal pulses, and wherein the interface 206, 212, 216 has a common line 206 for providing both the reset signal RS and the interrupt signal IS.

In various embodiments, a reaction of the controller 202 to an event detected in the electronic component 204 and transmitted to the controller 202 can be different than a reaction of the electronic component 204 to an event detected in the controller 202 and transmitted to the electronic component 204 .

The reaction in the controller 202 or in the electronic component 204 can depend, for example, on whether the controller 202 or the electronic component 204 has activated the interface 206, 212, 216 (e.g. internal vs. external activation), and what type of communication it was Signal is (e.g. (missing) life signal LS, interrupt signal IS, reset signal RS).

By using pulsed signals, a priority scheme can be implemented which can make it possible to determine which of two simultaneously transmitted signals is to be given priority, i.e. which of the signals has priority. The priority scheme can assign or determine priorities using a variation of pulse lengths. For example, a higher priority signal can be assigned a longer pulse length than a lower priority signal. Accordingly, a response from the receiving device (i.e., controller 202 or electronic component 204) can be assigned to a signal having a particular pulse length.

This is illustrated below with reference to the in 4A until 4E illustrated embodiments explained.

As explained above, the interface 206, 212, 216 with the common line 206 can be used in various exemplary embodiments to transmit the life signal LS and the interrupt signal IS.

This is an example in 3A and 3B illustrated.

In addition, the controller 202 can be set up to transmit the reset signal RS, either by means of a dedicated line 106_1, which is provided in addition to the shared line 206 (see 3A) , or by means of the split line 206 (see 3B) .

In an idle state (which may mean, for example, that neither a reset signal RS nor an interrupt IS is present on line 206), if the open-drain arrangement (shown) is used, a higher voltage may be present on line 206 (because of the pull-up device 208). The pull-up device 208 can be part of the electronic component 204, or an external part thereof, for example depending on safety requirements and/or a structure of the component 204 or the controller 202.

If the controller 202 detects a reset event RE, depending on the exemplary embodiment, it can activate the separate signal line 106_1 or the divided signal line 206, and the electronic component 204 detects an activation of the signal by means of the controller 202.

In response to this, the controller 202 and the component 204 carry out the operations defined for these cases, e.g. a reset of registers in the controller and in the component 204.

When component 204 detects an interrupt event IE, it activates shared signal line 206, and controller 202 detects an activation of signal line 206 via component 204.

In response, controller 202 and component 204 perform the actions defined for these cases, e.g. an interrupt in controller 202 and no specific response in component 204.

However, this simple coupling does not yet cover an important case that has already been indicated above.

Typically, a reset request with the associated execution of the predefined response (both in the controller 202 and in the component 204) has a higher priority than an interrupt execution.

If an interrupt event IE was detected in the component 204 and would be reported to the controller 202 earlier than a reset request from the controller 202 to the component 204 through the common line 206, the component 204 would see an active signal because of the interrupt signal IS, and would not notice the reset request. Accordingly, component 204 would fail to trigger a reset.

As indicated above, pulsed signals (e.g. in the electronic component 204 but also in the controller 202) can solve this problem by enabling a priority scheme.

The pulsed signal provided by component 204 means that the signal (e.g., interrupt signal IS) on common line 206 is asserted by component 204 for a (e.g., short) time (e.g., T2). , then re-enabled for a period of time so that it can be checked (e.g. by controller 202 and/or component 204) that component 204 is keeping the signal on common line 206 active, then re-enabled, re-enabled, etc. If the component 204 has deactivated its own driver output, but still sees an active signal on the common line 206 for a certain period of time, then this activation can only have occurred from the controller 202. Thus, the component 204 can recognize a signaling by the controller 202 and initiate corresponding reactions.

In various exemplary embodiments, a duration of the activation of the common signal by means of the electronic component 204 can depend on a structure of the common line 206, e.g. time constants due to capacitances and the pull-up device 208.

In various embodiments, the time durations can range from about one microsecond, e.g. a few (e.g. between two and five) microseconds to a few or more tens of microseconds, for example between 10 and 50 microseconds, or for example up to 100 microseconds.

A repetition rate (or duration) of the pulses can be about the same size range (but always greater than the maximum pulse length), or be longer, for example about one and a half or twice as long or even longer.

In various exemplary embodiments, the interface 206, 212, 216 with the common line 206 can be used to transmit a life signal LS and an interrupt signal IS. Optionally, a reset signal RS can also be transmitted using a separate line 106 1 , or the common line 206 can be set up for transmitting both the life signal LS and the interrupt signal IS and the reset signal RS.

In a further embodiment (which is not shown in the figures), the life signal LS and the reset signal RS can be transmitted via the common line 206, and the interrupt signal IS can optionally be transmitted via a separate line 106_2. In this case, the generation, coding, etc. can essentially take place as explained in connection with the other exemplary embodiments.

In various exemplary embodiments, the life signal LS can be used as a reference timer for timing the reset and/or interrupt signals to be output.

In other words, the electronic component 204 can detect the life signal LS of the controller 202, for example by means of a life signal monitor LM, and based on this, for example based on the falling edge, when the signal to be provided by it, for example the interrupt signal IS or the reset signal, is to be provided so that the receiving component (in this case the electronic component 204) knows when to send its signal so that it can be read by the controller 202 is correctly decoded. In addition, component 204 may adjust the length of activation of its output driver to extend the signal pulse length from T0 to T1, T2, or T3 (or other length) to the frequency generated by the live signal. Component 204 may adjust the lengthening of the signal pulse length relative to the received frequency. As an example, T1 can be chosen to be 20% of the life signal frequency. The relative relationship makes it possible to work much more independently of the absolute fluctuations in the time bases.

Signals that can be transmitted between the controller 202 and the electronic component 204 (e.g. with reference to the reference time) can have the meanings, for example: “everything OK”, “warning or error in the electronic component 204”, “reset status in controller 202", "reset state in electronic component 204", "detect serious problem with controller", "detect serious problem with electronic device", and/or "poor connection".

Accordingly, operation of controller 202 may be altered depending on the information it receives from electronic component 204 .

The electronic component 204 can also have a reset signal generator RD, which can be set up to generate a reset signal RS and to provide the reset signal at the interface, the reset signal RS being encoded in the form of one or more signal pulses. In various exemplary embodiments, the reset signal receiver RD can be set up to also generate the reset signal RS or, in a first process, to output a reset request RR, which can be further processed into a reset signal RS.

In various exemplary embodiments, the electronic component 204 can also have a life signal monitor or handler LM, which can be set up to receive a life signal LS via the interface 206, 212, 216, the life signal SL being encoded in the form of a plurality of signal pulses in a defined frequency range is.

In various exemplary embodiments, the life signal handler LM can be set up to generate a reset signal RS by means of the reset signal generator RD if the life signal LS is missing and to make it available at the interface 206, 212, 216, or to reset internal functional units in the component 204 or into a defined operating state.

In various exemplary embodiments, the electronic component 204 can be set up to reset the electronic component 204 or parts of the electronic component 204 when a reset signal RS is received.

In 3A is illustrated for an embodiment how the life signal LS and the interrupt signal IS can be transmitted by means of the common line 206.

The provision of the live signal LS can be based on a monitoring/testing unit, referred to as a live signal generator LG, which is located in the controller 202 .

The live signal generator LG can be set up to check the operating states and values LC of the controller 202 .

If the life signal generator LG does not detect a fatal error, the life signal LS is generated.

In various exemplary embodiments, the life signal LS can be transmitted to the component 204, e.g. a monitoring circuit or a PMIC, by means of the common interface 206, 212, 216.

The component 204 can be set up (e.g. by means of a life-signal monitor LM) to check the course of the life-signal LS over time (e.g. the frequency).

If the component 204 determines that the life signal LS has the value 0 or the value 1 for a longer time than a predetermined maximum time period Tmax, this means that the controller 202 is either not connected correctly (line open or stuck), or that the controller 202 has detected a fatal error and has stopped generating the live signal LS.

In any of these cases, the component 204 may enter an error state due to the state of the controller 202, in which some functions or modules of the second component 204 may be or may be disabled or brought to a safe-to-operate state.

On the other hand, if the component 204 determines the time profile of the life signal LS that the life signal LS behaves as expected (e.g. repetition rate of the 0 pulses within a specified time window Tper), the test result is that the controller 202 like works as expected, and the component 204 can communicate its own state to the controller 202 via the interface 206, 212, 216.

Exemplary signals (e.g. periods of time) which allow priorities to be defined or taken into account are now described with regard to 4A until 4E explained. In this case, the signaling takes place via the common interface 206, 212, 216, which is configured as an open-drain variant.

In one embodiment, only the life signal LS and the interrupt signal IS are combined, as is the case in FIG 3A is shown. The reset signal RS is transmitted there by means of the separate line 106 1 .

If the controller 202 does not detect a fatal error (or reset request, see below), it generates or transmits 0 pulses with a defined time duration T0 and in a defined frequency range ( 4A until 4C ).

If the component 204 is in operation and does not detect an error or warning condition which should be communicated to the controller 202, it extends the 0-pulses of the signal-of-life LS to a predetermined time period T1 (>T0). This time period T1 must be long enough for the Controller 202 can detect them (or their difference to T0) ( 4A) .

When the controller 202 determines that its own 0-pulse of duration T0 has been extended to T1, the controller 202 concludes that the component 204 is connected and operational.

If the controller 202 determines that its own 0 pulses of duration T0 have not been extended, the controller 202 concludes that the component 204 is improperly connected and/or not operational ( 4A , first half). In both cases, the controller 202 can assume an appropriate operating state.

If the controller 202 determines that its own 0 pulses of duration T0 have been extended to T1, the controller 202 concludes that the component 204 has not detected a warning or error condition. In this case, the controller 202 may enter or remain in an appropriate mode of operation ( 4A , second half and 4B , first half).

If the component 204 has detected a warning or error condition of the component 204, it can extend the pulses of length T0 generated by the controller 202 to a time duration T2 (e.g. >T1) ( 4B , second half).

If the controller 202 determines that its 0 pulses of duration T0 have been extended to T2, the controller 202 concludes that the component 204 has determined a warning or error condition. In this case, the controller 202 may enter an appropriate mode of operation ( 4B , second half and 4C , first half).

If the controller 202 determines that a low or high voltage level (corresponding to the signal state 0 or 1) is present at the interface 206, 212, 216 for a longer period than predetermined (related to Tper), the controller 202 comes to the conclusion that the component 204 is inoperable due to a fatal error or the interface 206, 212, 216 is stuck. In this case, the controller 202 can enter an appropriate mode of operation.

In one embodiment, the life signal LS, the reset signal RS and the interrupt signal IS are combined, as is the case in FIG 3B is shown.

If the controller 202 determines a reset state RE, the controller 202 can either stop generating the life signal LS, i.e. generating the 0 pulses, or extend a duration of the pulses to T4, where T4 can be longer than a duration T2, used by component 204 to signal a warning (T4>T2).

If the controller 202 stops generating the 0 pulses, the component 204 cannot distinguish between a serious error in the controller 202, a reset state of the controller 202 and a bad connection of the interface 206, 212, 216, e.g. the signal line 206. Accordingly, stopping the pulse is the less desirable option compared to extending the pulse to T4 ( 4D , second half).

The component 204 can detect that the resulting pulse length is longer than T2 and can distinguish between a reset condition and a fatal controller 202 fault (including a bad connection). In that case, the component 204 may enter an operating mode consistent with a controller 202 reset request or adopt a different operating mode consistent with a controller 202 fatal error.

If the component 204 is a PMIC, which provides the (voltage) supply for the controller 202, this can mean that the reset request of the controller 202 only results in a reset of a few registers in the component 204, and the voltage generation for the Controller 202 continues to be provided. On the other hand, if the component 204 detects a fatal error of the controller 202, it can switch off at least some parts of the power supply of the controller 202.

If the component 204 detects a fault condition that should result in a reset of the controller 202, the component may extend the 0 pulses provided by the controller 202 to a time period T3 (T3>T2). The controller 202 can then capture the longer 0 pulses and enter a reset state that the component requests or expects ( 4C ).

To realize the general concept it is not really relevant whether T3>T4 or T4>T3 or T3=T4. Because the only question here is which device can detect the reset request of the other device 202, 204 in each case. If an action derived from the detected signal is the same in both devices 202, 204, T3 may equal T4.

The time periods Tx (i.e., T0,...,T4) do not represent very precise time periods, but rather a range of time values. There are many reasons for time variations, such as temperature, aging, process differences, trimming accuracy, operating voltage, and other conditions in both the controller 202 and the component 204.

Accordingly, the time period Tx is to be understood in each case as a range which enables generation and detection by the controller 202 or the component 204 without misinterpretations occurring as a result of tolerances when generating or determining one or more of the time periods Tx.

In various embodiments, the repetitive 0-pulses that the controller 202 generates with a relatively stable repetition rate (or time interval TW with a duration of TA or T0 per pulse) allow the component 204 to determine the time intervals between the two or more consecutive to determine falling edges of the (combined) signal provided at the interface 206, 212, 216.

The determined time interval, which is measured in local clock cycles (clock cycles) of the component 204, can serve as a reference for the pulses to be formed by the component 204.

In other words, the component 204 can set a start time for the generation of its own pulses in such a way that they coincide with the start times of the pulses formed by the controller 202, or its own pulses only begin after the edge generated by the controller has been detected. The length of the pulses can be designed by the component 204 in such a way that it enables the statement that is to be transmitted from the component 204 to the controller 202 . For example, a slightly longer signal T1 compared to T0 to provide a life signal LS, a significantly longer signal T2 compared to T0 to transmit an interrupt, and an even longer signal T3 that may just leave room for a reset request with the Length T4 from the controller before the subsequent pulse is provided.

In various exemplary embodiments, the time periods Tx (e.g. T1, T2, T3, T4) can be defined as proportionate time periods in relation to the repetition rate TW of the signal-of-life of the controller 202 instead of as fixed time periods, i.e. for example a time period between successive falling (or successive rising) edges . Alternatively, for example, the duration of the life signal TA or T0 of the controller 202 can serve as a basis for calculating the durations Tx.

Depending on how long the repetition period TW is and how large the error tolerances are, there is also the possibility of making additional gradations, for example distinguishing between different types of interrupt states, or between partial reset and full reset.

Determining the time periods Tx relative to the signal detected by component 204 eliminates the need to precisely time both the controller 202 timer and the component 204 timer. If one of the timers shows a slow drift, the absolute time durations of the generated pulses are slowly adjusted automatically because the relative ratios, e.g. that of the pulse lengths to the repetition frequency, are maintained.

The signal curves in 4A until 4E are also simplified, delays from synchronization, routing, internal processing, or the open-drain connectivity to the pull-up device 208 have been neglected to better illustrate the gist.

Exemplary values for the relevant time-signal-related parameters, eg durations, time intervals, time windows within which an event has to occur, etc., can lie in the following ranges, for example: Tper, a period of time within which a time interval between oc n subsequent pulses of the life signal of the controller 202 can be between about 10 µs and about 50 µs, for example, a time duration T0 (pulse length of the life signal LS of the controller 202) about 1 µs to about 10 µs, depending on an RC value of the circuit (e.g R given by the pull-up device and C by the capacitive load of input and output on the common line).

With a combined signal total capacitance of 200 pF, which would be a very high value, and a 10 kΩ pull-up resistor (allowing for relatively low current), the RC time constant is 2 µs. Assuming two to three time constants, an input threshold should be easily reached, resulting in a rising edge delay of 4 to 6 µs considering these ill-chosen components.

With more carefully chosen components that have more realistic and appropriate characteristics (in capacitance and resistance), shorter delays can be realized.

• 4A: Die Komponente 204 ändert ihren Zustand von „nicht betriebsbereit“ zu „alles in Ordnung“.
• 4B: Die Komponente 204 ändert ihren Zustand von „alles OK“ zu „Warnung oder Fehlerzustand“.
• 4C: Die Komponente 204 ändert ihren Zustand von „Warnung oder Fehlerzustand“ zu „Reset-Forderung“.
• 4D: Der Controller 202 ändert seinen Zustand von „keine Reset-Forderung“ zu „Reset-Forderung“ (hier mit T3 = T4).
• 4E: Der Controller 202 ändert seinen Zustand von „kein schwerer Fehler“ zu „schwerer Fehler“.

The states shown in the exemplary time histories of 4A until 4E are illustrated are the following:

• 4A : The component 204 changes its state from "not ready" to "everything is OK".
• 4B : The component 204 changes its state from "everything OK" to "warning or error state".
• 4C : The component 204 changes its state from "warning or error state" to "reset request".
• 4D : The controller 202 changes its status from "no reset request" to "reset request" (here with T3=T4).
• 4E : The controller 202 changes its state from "no major error" to "major error".

In various exemplary embodiments, in particular when the life signal LS is provided, a combination of results from two monitoring or testing units that are located in two different devices (here in the controller 202 on the one hand and in the electronic component 204 on the other) can be stored on a single Signal line 206 are made possible. A number of required signal inputs/outputs (pins) can thus be reduced.

In various embodiments, it is possible to test connectivity of the individual signal line 206 without providing additional test units. A change in a signal can be detected in the connected units and interpreted as "connection OK". If no change is detected within a time window, the connected units can recognize that the intended functionality cannot be achieved and assume the appropriate operating states.

A reset signal RS can be integrated with the life signal LS and the interrupt signal IS on the single line 206 in various exemplary embodiments.

5 FIG. 5 shows a flow chart 500 of a method for operating a controller according to various exemplary embodiments.

The controller can have an interface to a component that generates an interrupt signal. The controller can have an internal unit for detecting error states and for generating reset signals.

The method may include generating a live signal (at 510), providing the live signal at the interface (at 520), and receiving an interrupt signal via the interface, the interface sharing a common line for both providing the live signal and for comprises receiving the interrupt signal (at 530).

6 FIG. 6 shows a flow chart 600 of a method for operating an electronic component according to various exemplary embodiments.

The electronic component can have an interface to a controller.

The method may include receiving a live signal via the interface, the reset signal being received and encoded in the form of one or more signal pulses (at 610), generating an interrupt signal (at 620), and providing the interrupt signal via the interface , wherein the interface has a common line both for receiving the life signal and for providing the interrupt signal (at 830).

7 a flowchart 700 of a method for operating an electronic system according to various exemplary embodiments.

The electronic system can have a controller and an electronic component sen, wherein the controller and the electronic component are coupled by means of the interface.

The method may be a method of operating a controller according to various embodiments (at 710), for example as related to FIG 5 described, and a method for operating an electronic component according to various embodiments (at 720), for example as in connection with FIG 6 described, have.

Some exemplary embodiments are summarized below.

Embodiment 1 is a controller having an interface to an interrupt signal generating component, a live signal generator set up to generate a live signal and providing the live signal to the interface, and an interrupt handler set up to receive an interrupt signal by means of the interface, the interface having a common line both for providing the life signal and for receiving the interrupt signal.

Embodiment 2 is a controller according to embodiment 1, wherein the interrupt signal is received in the form of one or more signal pulses and encoded in the signal pulse width.

Embodiment 3 is a controller according to embodiment 1 or 2, wherein the interrupt handler is further set up to decode the interrupt signal.

Embodiment 4 is a controller according to embodiment 2 or 3, wherein the signal pulse width of the interrupt signal is larger than a signal pulse width of the alive signal.

Embodiment 5 is a controller according to any one of Embodiments 1 to 4, wherein the vitality signal generator is configured to connect the interface to a ground terminal.

Exemplary embodiment 6 is a controller according to one of exemplary embodiments 1 to 5, the vital signal generator being set up to connect the interface to a supply voltage.

Exemplary embodiment 7 is a controller according to one of exemplary embodiments 1 to 6, set up as a microcontroller.

Exemplary embodiment 8 is a controller according to one of exemplary embodiments 1 to 7, further set up to output a reset signal at the interface and to trigger a resetting of parts of the interrupt signal-generating component.

Embodiment 9 is a controller according to any one of Embodiments 1 to 8, which further includes a reset signal generator configured to generate a reset signal and provide the reset signal to the interface, wherein the common line is further configured to provide the reset signal.

Embodiment 10 is a controller according to embodiment 9, wherein the reset signal is formed in the form of a plurality of signal pulses and encoded in the signal pulse width.

Embodiment 11 is a controller according to any one of Embodiments 4 and 10, wherein the signal pulse width of the reset signal is larger than a signal pulse width of the interrupt signal.

Embodiment 12 is an electronic component that has an interface to a controller, a life signal receiver configured to receive a life signal via the interface, and an interrupt signal generator configured to generate an interrupt signal via the interface, the interface has a common line both for receiving the life signal and for providing the interrupt signal.

Embodiment 13 is an electronic component according to embodiment 12, wherein the interrupt signal and the live signal are encoded in the signal pulse width.

Embodiment 14 is an electronic component according to embodiment 13, wherein the signal pulse width of the interrupt signal is larger than a signal pulse width of the life signal.

Exemplary embodiment 15 is an electronic component according to one of exemplary embodiments 12 to 14, which also has a reset signal handler, set up to receive a reset signal by means of the interface and to reset at least parts of the electronic component.

Exemplary embodiment 16 is an electronic component according to exemplary embodiments 14 and 15, wherein the reset signal handler is set up to reset the electronic component when a reset signal is detected.

Embodiment 17 is an electronic component according to Embodiments 12 and 15, wherein the signal pulse width of the reset signal is larger than a signal pulse width of the interrupt signal.

Exemplary embodiment 18 is an electronic component according to one of exemplary embodiments 14 to 17, which further comprises a reset signal receiver configured to receive a reset signal at the interface and to provide the reset signal for parts of the electronic component.

Embodiment 19 is an electronic component according to any one of Embodiments 14 to 18, wherein the interrupt signal generator is configured to connect the interface to a ground terminal.

Exemplary embodiment 20 is an electronic component according to one of exemplary embodiments 14 to 18, the interrupt signal generator being set up to connect the interface to a supply voltage.

Embodiment 21 is an electronic system including a controller according to any one of Embodiments 23 to 30 and an electronic component according to any one of Embodiments 14 to 20, wherein the controller and the electronic component are coupled via the interface.

Embodiment 22 is a controller that has an interface to a reset signal-generating component, a live signal generator set up to generate a live signal and to provide the live signal at the interface, and a reset signal handler set up to receive a reset signal by means of the interface, wherein the interface has a common line both for receiving the reset signal and for providing the life signal.

Embodiment 23 is a controller according to embodiment 22, wherein the reset signal is encoded in the signal pulse width.

Embodiment 24 is a controller according to embodiment 22 or 23, wherein the reset signal handler is further configured to set parts of the controller to a defined state

Embodiment 25 is a controller according to either embodiment 23 or 24, wherein the signal pulse width of the alive signal is smaller than a signal pulse width of the reset signal.

Embodiment 26 is a controller according to any one of embodiments 22 to 25, wherein the live signal generator is configured to connect the interface to a ground terminal.

Exemplary embodiment 27 is a controller according to one of exemplary embodiments 22 to 25, the vital signal generator being set up to connect the interface to a supply voltage.

Exemplary embodiment 28 is a controller according to one of exemplary embodiments 22 to 27, set up as a microcontroller.

Exemplary embodiment 29 is a controller according to one of exemplary embodiments 22 to 28, which also has an interrupt handler set up to receive an interrupt signal via the interface.

Embodiment 30 is a controller according to embodiment 29, wherein the interrupt signal is formed in the form of a plurality of signal pulses and encoded in the signal pulse width.

Embodiment 31 is a controller according to any one of Embodiments 23 and 30, wherein the signal pulse width of the live signal is smaller than a signal pulse width of the interrupt signal.

Exemplary embodiment 32 is a controller according to one of exemplary embodiments 22 to 31, further set up to reset the controller or parts of the controller when the reset signal is received.

Embodiment 33 is an electronic component that has an interface to a controller, a life signal handler set up to receive a life signal via the interface, and a reset signal generator set up to generate a reset signal via the interface, the interface having a common line to both for providing the reset signal and for receiving the life signal.

Embodiment 34 is an electronic component according to embodiment 33, wherein the live signal and the reset signal are encoded in the signal pulse width.

Embodiment 35 is an electronic component according to embodiment 34, wherein the signal pulse width of the alive signal is smaller than a signal pulse width of the reset signal.

Exemplary embodiment 36 is an electronic component according to one of exemplary embodiments 33 to 35, further comprising a reset signal generator set up to generate a reset signal and to provide the reset signal at the interface, wherein the reset signal is optionally encoded in the form of one or more signal pulses in the signal pulse width .

Exemplary embodiment 37 is an electronic component according to exemplary embodiments 33 and 36, the life signal handler being set up to generate a reset signal by means of the reset signal generator if the life signal is missing and to make it available at the interface.

Exemplary embodiment 38 is an electronic component according to one of exemplary embodiments 33 to 37, set up to reset the electronic component when a reset signal is received by means of the interface.

Exemplary embodiment 39 is an electronic component according to one of exemplary embodiments 33 to 38, which further has an interrupt generator for generating an interrupt signal and for providing the interrupt signal by means of the interface, the interrupt signal being encoded in the form of one or more signal pulses is.

Exemplary embodiment 40 is an electronic component according to exemplary embodiment 39, the interrupt generator being set up to generate the interrupt signal when an interrupt event is detected by means of the interrupt generator and to make it available at the interface.

Embodiment 41 is an electronic component according to Embodiments 34 and 40, wherein the signal pulse width of the life signal is smaller than a signal pulse width of the interrupt signal.

Exemplary embodiment 42 is an electronic component according to one of exemplary embodiments 34 to 41, wherein the vitality signal handler is configured to set parts of the electronic component to a predefined state upon receipt of an erroneous vitality signal.

Embodiment 43 is an electronic system comprising a controller according to any one of Embodiments 22 to 32 and an electronic component according to any one of Embodiments 33 to 42, wherein the controller and the electronic component are coupled via the interface.

Exemplary embodiment 44 is a controller according to one of exemplary embodiments 1 to 11 or 22 to 32, which also has an additional interface to the component for redundantly providing the reset signal, the interrupt signal and/or the life signal.

Exemplary embodiment 45 is an electronic component according to one of exemplary embodiments 13 to 21 or 33 to 42, which also has an additional interface to the component for redundantly providing the reset signal, the interrupt signal and/or the life signal.

Exemplary embodiment 46 is an electronic system according to one of exemplary embodiments 22 or 43, which also has an additional interface to the component for redundantly providing the reset signal, the interrupt signal and/or the life signal.

Exemplary embodiment 47 is a method for operating a controller that has an interface to an interrupt signal-generating component, the method including generating a life signal, providing the life signal at the interface, and receiving an interrupt signal by means of the interface, wherein the interface has a common line both for providing the life signal and for receiving the interrupt signal.

Embodiment 48 is a method according to embodiment 47, wherein the interrupt signal is received in the form of one or more signal pulses and is encoded in the signal pulse width.

Embodiment 49 is a method according to embodiment 47 or 48, further comprising decoding the interrupt signal.

Embodiment 50 is a method according to embodiment 48 or 49, wherein the signal pulse width of the interrupt signal is smaller than a signal pulse width of the alive signal.

Embodiment 51 is a method according to any one of Embodiments 47 to 50, further comprising connecting the interface to a ground terminal to provide the live signal to the interface.

Embodiment 52 is a method according to any one of Embodiments 47 to 50, further comprising connecting the interface to a supply voltage to provide the live signal at the interface.

Embodiment 53 is a method according to any one of Embodiments 47 to 52, further comprising receiving a reset signal nals and a resetting of parts of the interrupt signal-generating component.

Embodiment 54 is a method according to embodiment 53, wherein the reset signal is formed in the form of a plurality of signal pulses and encoded in the signal pulse width.

Embodiment 55 is a method according to any one of Embodiments 48 and 54, wherein the signal pulse width of the reset signal is larger than a signal pulse width of the interrupt signal.

Exemplary embodiment 56 is a method according to one of exemplary embodiments 47 to 55, the controller being set up as a microcontroller.

Embodiment 57 is a method according to any one of Embodiments 47 to 56, further comprising receiving a reset signal at the interface and resetting the controller.

Exemplary embodiment 58 is a method of operating an electronic component that has an interface to a controller, the method including receiving a live signal via the interface, generating an interrupt signal, and providing the interrupt signal via the interface, wherein the Interface has a common line for both receiving the life signal and for providing the interrupt signal.

Embodiment 59 is a method according to embodiment 58, wherein the interrupt signal and the live signal are encoded in the signal pulse width.

Embodiment 60 is a method according to embodiment 59, wherein the signal pulse width of the interrupt signal is larger than a signal pulse width of the alive signal.

Exemplary embodiment 61 is a method according to one of exemplary embodiments 58 to 60, which further comprises generating a reset signal and providing the reset signal at the interface, wherein the reset signal is optionally encoded in the form of one or more signal pulses.

Embodiment 62 is a method according to any one of Embodiments 58 to 61, further comprising connecting the interface to a ground terminal to provide the interrupt signal at the interface.

Exemplary embodiment 63 is a method according to one of exemplary embodiments 58 to 61, further comprising connecting the interface to a supply voltage for providing the interrupt signal at the interface.

Exemplary embodiment 64 is a method according to one of exemplary embodiments 57 to 62, which includes receiving a reset signal by means of the interface, the reset signal being received and encoded in the form of a plurality of signal pulses.

Exemplary embodiment 65 is a method according to exemplary embodiment 64, further comprising, when a reset signal is detected, resetting the electronic component or at least parts of the electronic component.

Embodiment 66 is a method according to Embodiments 59 and 61, wherein the signal pulse width of the reset signal is larger than a signal pulse width of the interrupt signal.

Embodiment 67 is a method of operating an electronic system, which includes a method of operating a controller according to any one of Embodiments 47 to 47 and a method of operating an electronic component according to any one of Embodiments 58 to 66, wherein the controller and the electronic component are are coupled to the interface.

Embodiment 68 is a method for operating a controller that has an interface to a reset signal-generating component, the method comprising generating a live signal, providing the live signal at the interface, and receiving a reset signal by means of the interface, the interface having a has a common line both for providing the life signal and for receiving the reset signal.

Embodiment 69 is a method according to embodiment 68, wherein the reset signal is signal pulse width encoded.

Embodiment 70 is a method according to embodiment 68 or 69, further comprising decoding the reset signal and/or resetting the controller or parts of the controller.

Embodiment 71 is a method according to embodiment 69 or 70, wherein a signal pulse width of the alive signal is smaller than the signal pulse width of the reset signal.

Embodiment 72 is a method according to any one of Embodiments 68 to 71, further comprising connecting the interface to a ground terminal to provide the live signal at the interface.

Embodiment 73 is a method according to any one of Embodiments 68 to 71, further comprising connecting the interface to a supply voltage to provide the live signal at the interface.

Exemplary embodiment 74 is a method according to one of exemplary embodiments 68 to 73, which further comprises receiving an interrupt signal by means of the interface, the interrupt signal being received and encoded in the form of one or more signal pulses.

Embodiment 75 is a method according to embodiment 74, wherein the interrupt signal is formed in the form of a plurality of signal pulses and is encoded in the signal pulse width.

Embodiment 76 is a method according to any one of Embodiments 69 and 75, wherein the signal pulse width of the live signal is smaller than a signal pulse width of the interrupt signal.

Exemplary embodiment 77 is a method according to one of exemplary embodiments 68 to 76, the controller being set up as a microcontroller.

Exemplary embodiment 78 is a method according to one of exemplary embodiments 68 to 77, further set up to reset the controller or at least parts of the controller when the reset signal is received.

Embodiment 79 is a method of operating an electronic component that has an interface to a controller, the method including receiving a live signal via the interface, generating a reset signal, and providing the reset signal via the interface, the interface having a common line both for receiving the life signal and for providing the reset signal.

Embodiment 80 is a method according to embodiment 79, wherein the live signal and the reset signal are signal pulse width encoded.

Embodiment 81 is a method according to embodiment 80, wherein the signal pulse width of the alive signal is smaller than a signal pulse width of the reset signal.

Exemplary embodiment 82 is a method according to one of exemplary embodiments 79 to 81, further comprising generating an interrupt signal and providing the interrupt signal at the interface, the interrupt signal being encoded in the form of one or more signal pulses in the signal pulse width.

Embodiment 83 is a method according to any one of Embodiments 79 to 82, further comprising, in the absence of the live signal, performing the generation of the reset signal.

Exemplary embodiment 84 is a method according to any one of exemplary embodiments 79 to 83, further comprising, upon receiving a reset signal via the interface, resetting the electronic component.

Exemplary embodiment 85 is a method according to exemplary embodiment 82, further comprising generating the interrupt signal when an interrupt event is detected and making it available at the interface.

Embodiment 86 is an electronic component according to Embodiments 80 and 82, wherein the signal pulse width of the life signal is smaller than a signal pulse width of the interrupt signal.

Exemplary embodiment 87 is a method of operating an electronic system, comprising a method of operating a controller according to any one of exemplary embodiments 68 to 78 and a method of operating an electronic component according to any one of exemplary embodiments 79 to 86, wherein the controller and the electronic component are Interface are coupled.

Exemplary embodiment 88 is a method according to one of exemplary embodiments 47 to 88, which also has a redundant provision of the interrupt signal, the life signal and/or the interrupt signal by means of at least one additional interface.

Exemplary embodiment 89 is a method according to exemplary embodiment 88, which includes redundantly providing one of the redundant signals for each additional interface.

Exemplary embodiment 90 is a method according to exemplary embodiment 88, which has the common redundant provision of at least two of the redundant signals by means of the at least one additional interface.

Claims (21)

controller, having • an interface to an interrupt signal generating component; • a live signal generator set up to generate a live signal and to provide the live signal at the interface; • an interrupt handler set up to receive an interrupt signal via the interface; • wherein the interface has a common line both for providing the life signal and for receiving the interrupt signal. controller according to claim 1 , wherein the interrupt signal is received in the form of one or more signal pulses and is encoded in the signal pulse width. controller according to claim 1 or 2 , wherein the interrupt handler is further set up to decode the interrupt signal. Controller according to one of claims 2 or 3 , wherein the signal pulse width of the interrupt signal is greater than a signal pulse width of the life signal. Controller according to one of Claims 1 until 4 , wherein the life signal generator is set up to connect the interface to a ground connection, or is set up to connect the interface to a supply voltage. Controller according to one of Claims 1 until 5 , also set up to output a reset signal at the interface and to reset parts of the interrupt signal-generating component. Electronic component comprising • an interface to a controller; • a vital signal receiver configured to receive a vital signal via the interface; • an interrupt signal generator set up to generate an interrupt signal by means of the interface; • wherein the interface has a common line both for providing the interrupt signal and for receiving the life signal. Electronic component according to claim 7 , where the interrupt signal and the life signal are encoded in the signal pulse width. Electronic component according to claim 8 , wherein the signal pulse width of the interrupt signal is greater than a signal pulse width of the life signal. Electronic component according to one of Claims 7 until 9 , further comprising: a reset signal receiver, configured to receive a reset signal at the interface, and to provide the reset signal for parts of the electronic component. Electronic component according to one of Claims 7 until 10 , wherein the interrupt signal generator is set up to connect the interface to a ground connection, or is set up to connect the interface to a supply voltage. Electronic system, comprising: a controller according to any one of Claims 1 until 6 ; and an electronic component according to any one of Claims 7 until 11 ; wherein the controller and the electronic component are coupled via the interface. controller, having • an interface to a reset signal generating component; • a live signal generator set up to generate a live signal and to provide the live signal at the interface; • a reset signal handler configured to receive a reset signal via the interface; • wherein the interface has a common line both for receiving the reset signal and for providing the life signal. controller according to Claim 13 , where the reset signal is encoded in the signal pulse width. controller according to Claim 13 or 14 , wherein the reset signal handler is further configured to set parts of the controller to a defined state. Controller according to one of Claims 14 or 15 , wherein the signal pulse width of the life signal is smaller than a signal pulse width of the reset signal. Controller according to one of Claims 14 until 16 , wherein the life signal generator is set up to connect the interface to a ground connection, or is set up to connect the interface to a supply voltage. Electronic component, comprising • an interface to a controller; • a live signal handler configured to receive a live signal via the interface; • a reset signal generator set up to generate a reset signal by means of the interface; • wherein the interface has a common line both for providing the reset signal and for receiving the life signal. Electronic component according to Claim 18 , where the live signal and the reset signal are encoded in the signal pulse width. Electronic component according to claim 19 , wherein the signal pulse width of the life signal is smaller than a signal pulse width of the reset signal. Electronic component according to one of claims 18 until 20 , wherein the life signal handler is configured to set parts of the electronic component to a predefined state upon receipt of an erroneous life signal.

Images