DE102020205978A1 - System of galvanically separated, data-coupled microcontrollers - Google Patents

Abstract

The invention relates to a system of microcontrollers, having a first microcontroller (100) and a second microcontroller (200), the first microcontroller (100) and the second microcontroller (200) being galvanically isolated from one another (400), the first microcontroller ( 100) has a first processor unit (110) and a first communication interface (120) which is connected to the first processor unit (110) and which is set up to enable direct memory access to a memory unit (140, 141, 142) of the first processor unit, wherein the second microcontroller (200) has a second processor unit (210) and a second communication interface (220) which is connected to the second processor unit (210) and which is set up to allow direct memory access to a memory unit (240, 241, 242) of the second processor unit to enable, and wherein the first communication interface (120) and the second communication Interface (220) are coupled to one another (300).

Description

The present invention relates to a system of galvanically separated microcontrollers.

State of the art

Modern microcontrollers, which are used, for example, in (motor) vehicles, in addition to a processor unit or a microprocessor and memory units (flash, EEPROM, RAM memory, etc.) usually include additional peripherals, e.g. network interfaces, ADC, DAC, timers, CAN, I / O, etc., which are connected to one another via an internal communication system, such as an internal bus, and are in communication with one another.

Such processor units or microprocessors are mostly designed as multicore processors with several (at least two) processor cores. A processor core or core comprises an arithmetic-logic unit (ALU), which represents the actual electronic arithmetic unit for executing tasks, programs, arithmetic commands, etc., as well as one or more local memories. Such a local memory can be designed, for example, as a cache memory or register set from one or more registers or as a RAM memory.

In technical fields of application such as the (motor) vehicle sector, a large number of different microcontrollers are often used, which can often also be provided in different voltage domains. For example, different on-board networks with different supply or on-board network voltages can be provided in vehicles, for example low-voltage on-board networks with a low on-board network voltage of e.g. 12V or 24V and high-voltage on-board networks with high supply voltages of e.g. 48V up to 800V. For safety reasons, for example to prevent feedback in the event of a fault and to avoid crosstalk and voltage peaks, such on-board networks with different voltage levels are usually galvanically isolated and there is no common reference potential. Thus, the microcontrollers provided in these on-board networks are also galvanically isolated from one another. It can often turn out to be complex and costly to exchange data or signals between such electrically isolated microcontrollers. Exemplary implementations that couple the various microcontrollers via vehicle bus systems (e.g. CAN) are therefore limited in terms of data rate and latency.

Disclosure of the invention

According to the invention, a system of galvanically separated microcontrollers with the features of claim 1 is proposed. Advantageous refinements are the subject matter of the subclaims and the description below.

The system has a first microcontroller and a second microcontroller which are electrically isolated from one another. There is therefore no common reference potential between these two microcontrollers. In particular, the first microcontroller is set up to be connected to a first supply voltage source, and the second microcontroller is set up in particular to be connected to a second supply voltage, the first supply voltage source and the second supply voltage source being galvanically separated. Furthermore, supply voltages of different levels are expediently provided in each case by the first and the second supply voltage source. The first and second microcontrollers are each provided in particular in different voltage domains and there is no common reference potential for these two voltage domains. It goes without saying that, in addition to the respective microcontroller, further components can be provided in these voltage domains. It is also understood that the system can also have further microcontrollers and further elements.

The present invention now provides a possibility of coupling these galvanically isolated microcontrollers or their processor units to one another in a data-transferring manner, so that the microcontrollers or their processor units can communicate directly with one another.

The first microcontroller has a first processor unit and a first communication interface connected to the first processor unit, which is set up to enable direct memory access (DMA) to a memory unit, in particular working memory such as RAM or registers, of the first processor unit . Correspondingly, the second microcontroller has a second processor unit and a second communication interface connected to the second processor unit, which is set up to enable direct memory access to a memory unit, in particular working memory such as RAM or registers, of the second processor unit. The first communication interface and the second communication interface are connected to transmit data by means of an isolation coupler, e.g. by means of opto, magnetic or capacitive couplers.

The first and the second processor unit can each be designed, for example, as single-core processors with one processor core or expediently also as multicore processors with several processor cores. In particular, the first processor unit and the first communication interface are connected to a first microcontroller-internal communication or connection system, for example to an internal bus of the first microcontroller or to an internal crossbar connection. Correspondingly, the second processor unit and the second communication interface are also connected to a corresponding second microcontroller-internal communication or connection system of the second microcontroller. Furthermore, in the first or second microcontroller, further components can expediently be connected to the respective processor unit and the respective communication interface via the respective communication or connection system, in particular storage units, e.g. flash, EEPROM, RAM etc., as well as additional peripherals, e.g. network interfaces, ADC, DAC, timer, CAN, I / O, etc.

By means of the coupling between the first and the second communication interface, it is particularly expedient to establish a virtual connection between the communication or connection systems of the first and second microcontrollers. In particular, a virtual, cross-microcontroller communication or connection system can be generated in this way, via which the first and the second processor unit can communicate directly with one another.

Furthermore, the processor units can particularly expediently access components of the respective other microcontroller directly via the coupled communication interfaces, in particular in each case to components which are connected to the microcontroller-internal communication or connection system of the respective other microcontroller. For example, the processor unit of one of the two microcontrollers can directly access memories or peripheral devices of the other microcontroller via the coupling.
The present invention provides a tightly coupled multicore processor system in which the individual processor units are provided on different, electrically isolated voltage domains. By coupling the two microcontrollers via the communication interfaces, in particular a number of signals which have to cross the voltage domains of the microcontrollers can be significantly reduced. For example, fast signal or control loops can be processed locally.

When the overall system is implemented with microcontrollers from the same processor family, for example, program code components can be assigned in the way that makes the most sense from the point of view of resource distribution, runtime behavior and access to interfaces of the corresponding voltage domain. In particular, such an assignment of program code parts can be established once in the course of the original programming.

Due to the high performance of the communication interfaces, in particular due to the high data rate and low latency, code portions can expediently be bundled on one microcontroller and only certain portions can be implemented in the other microcontroller. In this way, flexible allocation of similar software code components can be achieved.

Furthermore, for example, a larger selection of resources or peripheral devices can be made possible by the processor unit of one microcontroller being able to access peripheral devices of the other microcontroller via the coupled communication interfaces.

The communication interfaces serve in particular to couple the microcontroller-internal communication systems and thus the processor units. The processor units are particularly advantageously in a bidirectional or full duplex communication link via the communication interfaces. In particular, data can be transmitted between the two processor units in both directions at the same time. Each of the processor units can thus particularly expediently send data to and receive data from the other processor unit at the same time.

The first communication interface and the second communication interface are preferably optically coupled. Signals are transmitted optically between the communication interfaces. In particular, electrical signals and optical signals are converted for this purpose. To transmit data, electrical signals are expediently converted into optical signals at the respective transmitting communication interface, which signals are transmitted to the other receiving communication interface via the coupling. There the optical signals are expediently converted back into electrical signals. In order to transmit data or signals between the microcontrollers, there is therefore particularly expediently no need for an electrical connection between the microcontrollers.

The first communication interface and the second are particularly preferred Communication interface coupled via at least one optocoupler. In particular, different transmitting / receiving units (transceivers) of the two communication interfaces are each coupled to one another via an optocoupler. An optocoupler is in particular a coupling mechanism or an element of optoelectronics for the optical transmission of signals between galvanically separated units. For this purpose, the optocoupler has in particular an optical transmitter, for example a light-emitting diode (LED) or a laser diode (LD), and an optical receiver, for example a photodiode, phototransistor, triac, etc., the transmitter and the receiver being optically coupled and for example are connected via a light guide.

The first communication interface and the second communication interface are preferably each designed as a full duplex interface, in particular as a full duplex high-speed interface, and preferably set up for simultaneous bidirectional transmission. In this way, in particular, a simultaneous data transmission between the first and second processor unit can be made possible. The two processor units can expediently send and receive data at the same time.

The first communication interface and the second communication interface are each advantageously designed as an LVDS interface (Low Voltage Differential Signaling, LVDS). LVDS is an interface standard for high-speed data transmission, standardized according to ANSI / TIA / EIA-644-1995. Such LVDS interfaces have, in particular, low voltage levels (“low voltage”) and also differential voltage levels (“differential signaling”). Furthermore, signals are generated in particular with a constant current source. For example, such LVDS interfaces can be used as so-called LFAST / SIPI interfaces ("LVDS Fast Asynchronous Serial Transmission Interface", LFAST, or "Serial Inter-Processor Interface", SIPI) or, for example, also as so-called HSCT / HSSL interfaces ("High Speed Serial Link ", HSSL).

According to a preferred embodiment, at least five signal connections of the first communication interface and at least five signal connections of the second communication interface are coupled to one another. These signal connections are particularly useful optically, in particular coupled via one or more optocouplers. In particular, these signal connections are used to couple signals in and out.

Particularly preferably, the at least five signal connections of the first communication interface and the at least five signal connections of the second communication interface each include at least one signal connection for transmitting a time or clock signal, at least two signal connections for outputting a data signal and at least two signal connections for receiving a data signal. Two of the signal connections of a communication interface thus expediently function as output connections in order to transmit a data signal to the other communication interface. Correspondingly, two of the signal connections function as input connections for receiving a data signal from the other communication interface. The clock signal functions in particular to synchronize the microcontrollers or to generate their internal clocks. In particular, one of the microcontrollers is provided as a master, which specifies a time base for the other microcontroller provided as a slave.

The signal connections of the two communication interfaces for the clock signal are particularly expediently coupled via a first optocoupler. The at least two input connections of the first communication interface are coupled to the at least two output connections of the second communication interface, in particular via a second optocoupler. Accordingly, in particular the at least two output connections of the first communication interface are coupled to the at least two input connections of the second communication interface via a third optocoupler.

The first processor unit is preferably set up to access a memory unit connected to the second processor unit via the coupled communication interfaces in the course of direct memory access (DMA). Accordingly, the second processor unit is preferably set up to access a memory unit connected to the first processor unit via the coupled communication interfaces in the course of direct memory access (DMA). In particular, these memory units are connected to the respective processor unit via the respective microcontroller-internal communication system. These storage units can, for example, each be a flash, EEPROM or RAM memory. The processor units can thus communicate particularly expediently with reciprocal DMA access via the coupled communication interfaces. Such direct memory access (DMA) expediently enables the processor units to access the respective other processor unit directly to access the connected memory unit without communicating with the other processor unit.

According to a particularly advantageous embodiment, the system comprising the microcontrollers is used in a (motor) vehicle. In particular, the microcontrollers can be used in control units of a vehicle that are electrically isolated from one another.

The first microcontroller is particularly advantageously provided in a first vehicle electrical system in which a first supply voltage source provides a first vehicle electrical system voltage. The second microcontroller is advantageously provided in a second vehicle electrical system in which a second supply voltage source provides a second vehicle electrical system voltage. The two vehicle electrical systems are expediently galvanically separated from one another and do not have a common reference potential. The two vehicle electrical system voltages are expediently different. One of the two vehicle electrical systems is intended in particular as a low-voltage vehicle electrical system with a low vehicle electrical system voltage of e.g. 12V. The other vehicle electrical system is expediently provided as a high-voltage vehicle electrical system with a high vehicle electrical system voltage, for example between 48V and 800V. In particular, communication between these electrically isolated vehicle electrical systems or their control units is made possible without the signals having a common reference potential for this purpose.

Further advantages and embodiments of the invention emerge from the description and the accompanying drawing.

The invention is shown schematically in the drawing using exemplary embodiments and is described below with reference to the drawing.

Figure list

• 1 shows schematically a preferred embodiment of a system according to the invention composed of microcontrollers.
• 2 schematically shows a section of a preferred embodiment of a system according to the invention composed of microcontrollers.

Embodiment (s) of the invention

1 shows schematically a preferred embodiment of a system according to the invention comprising a first microcontroller 100 and a second microcontroller 200 .

The microcontroller 100 , 200 are, for example, each provided in a control unit of a vehicle and furthermore each in different on-board networks 410 , 420 of the vehicle.

For example, the first is a microcontroller 100 in a first electrical system 410 provided in which a first supply voltage source 411 provides a first vehicle electrical system voltage, and the second microcontroller 200 is in a second on-board network 420 is provided in which a second supply voltage source 421 provides a second vehicle electrical system voltage. For example, the first electrical system is 410 a low-voltage electrical system with an electrical system voltage of 12V and the electrical system 420 a high-voltage electrical system with 48V electrical system voltage. For safety reasons, for example to prevent feedback in the event of a fault and to avoid crosstalk and voltage peaks, the vehicle electrical systems are 410 , 420 and thus the microcontroller 100 , 200 galvanically isolated and have no common reference potential. Each of the electrical systems 410 , 420 has its own, independent reference potential 412 respectively. 422 . The galvanic separation between the microcontrollers 100 , 200 is in 1 furthermore schematically by the dashed line 400 indicated.

The first microcontroller 100 has a first processor unit 110 with two processor cores 111 , 112 on. For example, the individual processor cores 111 and 112 each have an arithmetic-logic unit and an internal RAM memory as well as interfaces to the processor cores 111 , 112 to a microcontroller internal communication system 101 of the first microcontroller 100 to connect. This microcontroller internal communication system 101 can for example be designed as a crossbar connection.

This communication system 101 is provided in particular as a processor core communication system to other components of the microcontroller 100 directly to the processor cores 111 , 112 to connect. In particular, different storage units are connected to the crossbar connection 101 connected, for example a flash memory 140 , an EEPROM memory 141 as well as a RAM memory 142 .

It is also in the microcontroller 100 a second microcontroller internal communication system 102 provided, for example another crossbar connection 102 . This further crossbar connection 102 can be provided in particular for peripheral units. For example, a variety of different interfaces 150 , 151 , 152 , 153 , 154 , 155 be provided to the microcontroller 100 to connect with components of the vehicle such as sensors, actuators, field buses, etc. For example, there is also a message buffer or buffer 160 to the further crossbar link 102 connected, which has two connections 161 , 162 can be connected to a fieldbus (e.g. CAN or similar) of the vehicle for receiving or sending messages. There is also an analog-to-digital converter 170 to the crossbar connection 102 .

The two crossbar connections 101 , 102 of the first microcontroller 100 are also about a unit 103 connected to each other for direct memory access (DMA). In this way, the individual peripheral units can usefully directly access the storage units 140 , 141 , 142 access without using the processor cores 111 , 112 to communicate.

The first microcontroller 100 also has a first communication interface 120 on that over the crossbar connection 102 to the processor unit 110 or to the processor cores 111 , 112 is connected. Furthermore, the first microcontroller 100 further communication interfaces 130 , 131 have which, for example, correspond to the communication interface 120 can be formed.

The communication interface 120 is intended to be the first microcontroller 100 or its processor unit with the second microcontroller 200 to pair.

The second microcontroller 200 is, for example, identical in construction to the first microcontroller 100 designed. Elements of the second microcontroller 200 that are identical or structurally identical to elements of the first microcontroller 100 are, are with one about the value 100 marked with a raised reference number.

The first communication interface 120 and the second communication interface 220 are coupled to each other for data transmission via an isolation coupler, particularly expediently optically via a coupling mechanism 300 for the optical transmission of signals between galvanically isolated units.

About this coupling 300 the communication interfaces 120 , 220 stand the first processor unit 110 or the processor cores 111 , 112 and the second processor unit 210 or their processor cores 211 , 212 with each other in a direct communication link.

By means of the coupling 300 between the communication interfaces 120 , 220 A virtual connection between the processor core communication systems or crossbar connections can be particularly useful 101 and 201 of the first and second microcontrollers 100 , 200 getting produced. In this way, a virtual, cross-microcontroller communication system for the processor cores is particularly useful 111 , 112 , 211 , 212 of the two microcontrollers 100 , 200 generated, via which the first and the second processor unit 110 , 210 can communicate directly with each other.

Furthermore, this virtual, cross-microcontroller communication system enables direct memory access from the processor unit of one microcontroller to the memory units of the respective other microcontroller. For example, the first processor unit 110 or their cores 111 , 112 via the coupled communication interfaces 120 , 220 in the course of direct memory access directly to the memory units 240 , 241 , 242 of the second microcontroller 200 access. The second processor unit can 210 or their cores 211 , 212 via the coupled communication interfaces 120 , 220 in the course of direct memory access directly to the memory units 140 , 141 , 142 of the first microcontroller 100 to access.

The communication interfaces 130 , 230 are designed, for example, as full duplex interfaces for simultaneous bidirectional data transmission, so that the two processor units of the microcontroller 110 , 120 can exchange data with each other at the same time. Furthermore, the communication interfaces 130 , 230 each designed, for example, as an LVDS interface (“Low Voltage Differential Signaling”, LVDS), with low, differential voltage levels.

In particular, communication takes place via the communication interfaces 130 , 230 according to the HSSL protocol (High Speed Serial Link). However, the invention is not limited thereto and can find application in connection with any other type of suitable interface.

2 schematically shows a section of a preferred embodiment of a system according to the invention composed of microcontrollers. In 2 are the communication interfaces 120 , 220 the microcontroller 110 , 210 as well as the coupling mechanism 300 shown schematically. Identical reference symbols in the 1 and 2 denote identical or structurally identical elements.

The first communication interface 120 has a first signal terminal 121 to send a time signal. The second communication interface 220 a signal connector 221 to receive a time signal. For example, the first microcontroller 100 act as a master and the second microcontroller 200 as a slave, being the master microcontroller 100 a corresponding time signal to the slave microcontroller to create a common time base 200 sends.

The second communication interface also includes 220 two signal connections 222 , 223 for outputting a data signal, in particular a positive connection 222 and a negative terminal 223 . The first communication interface also comprises accordingly 120 a positive signal terminal 124 and a negative signal terminal 125 for outputting a data signal.

The first communication interface 120 furthermore has a positive and a negative signal connection 122 respectively. 123 for receiving a data signal and the second communication interface 220 accordingly has a positive signal connection for receiving a data signal 224 and a negative signal terminal 225 .

The signal connections 121 , 122 , 123 , 124 , 125 the first communication interface 120 come with appropriate transceivers 126 , 127 , 128 connected, and the signal connections are accordingly 221 , 222 , 223 , 224 , 225 the second communication interface 220 with respective transceivers 226 , 227 , 228 tied together.

With the help of these different connections for sending and receiving data signals, bidirectional full-duplex data transmission can be made possible, i.e. simultaneous sending and receiving of data.

The coupling mechanism has three optocouplers, via which the signal connections 121 until 125 and 221 until 225 the communication interfaces 120 , 220 are optically coupled to one another.

For example, is a first optocoupler 310 with an optical transmitter 311 and an optical receiver 312 provided to the signal connections 121 and 221 to couple for the time signal.

A second optocoupler 320 with optical transmitter 321 and optical receiver 322 is provided to the signal connections 222 and 223 the second communication interface 220 for sending a data signal with the signal terminals 122 and 123 the first communication interface 120 to be optically coupled to receive a data signal.

There is also a third optocoupler 330 with optical transmitter 331 and optical receiver 332 provided via which the signal connections 124 and 125 the first communication interface 120 for sending a data signal with the signal terminals 224 and 225 the second communication interface 220 are optically coupled to receive a data signal.

For example, the individual optical transmitters 311 , 321 , 331 the optocoupler 310 , 320 , 330 each be designed as a light emitting diode (LED) or laser diode (LD). The optical receivers 312 , 322 , 332 can each be designed as a photodiode, phototransistor, triac, etc., for example.

Claims (9)

System of microcontrollers, comprising a first microcontroller (100) and a second microcontroller (200), wherein the first microcontroller (100) and the second microcontroller (200) are galvanically isolated from one another (400), wherein the first microcontroller (100) has a first processor unit (110) and a first communication interface (120) which is connected to the first processor unit (110) and which is set up to allow direct memory access to a memory unit (140, 141, 142) of the first To enable processor unit, wherein the second microcontroller (200) has a second processor unit (210) and a second communication interface (220) connected to the second processor unit (210), which is set up to allow direct memory access to a memory unit (240, 241, 242) of the second To enable processor unit, and wherein the first communication interface (120) and the second communication interface (220) are coupled to transmit data by means of an isolation coupler (300, 310, 320, 330). System according to Claim 1 , wherein the first communication interface (120) and the second communication interface (220) are each designed as a full duplex interface and are set up for simultaneous bidirectional transmission. System according to Claim 1 or 2 , wherein the first communication interface (120) and the second communication interface (220) are each designed as an LVDS interface. System according to one of the preceding claims, wherein the first communication interface (120) and the second communication interface (220) are optically coupled (300). System according to one of the preceding claims, wherein at least five signal connections (121, 122, 123, 124, 125) of the first communication interface (120) and at least five signal connections (221, 222, 223, 224, 225) of the second Communication interface (220) are coupled to one another. System according to Claim 5 , wherein the at least five signal connections (121, 122, 123, 124, 125) of the first communication interface (120) and the at least five signal connections (221, 222, 223, 224, 225) of the second communication interface (220) each have at least one signal connection ( 121, 221) for transmitting a clock signal, at least two signal connections (124, 125, 222, 223) for outputting a data signal and at least two signal connections (122, 123, 224, 225) for receiving a data signal. System according to one of the preceding claims, wherein the first processor unit (110) is set up to use the coupled communication interfaces (110, 220, 300) in the course of a direct memory access to a memory unit (240, 241, 242 connected to the second processor unit (210) ), and wherein the second processor unit (210) is set up to access a memory unit (140, 141, 142) connected to the first processor unit (110) via the coupled communication interfaces (110, 220, 300) in the course of direct memory access. A system according to any preceding claim used in a vehicle. System according to Claim 8 , wherein the first microcontroller (100) is provided in a first vehicle electrical system (410) in which a first supply voltage source (411) provides a first vehicle electrical system voltage, and wherein the second microcontroller (200) is provided in a second vehicle electrical system (420), in which a second supply voltage source (421) provides a second vehicle electrical system voltage.

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