DE102020133802B4 - ACCESSING AN ASSOCIATIVE MEMORY - Google Patents

Abstract

Method for accessing a memory, the memory being an associative memory and having a multiplicity of data words, each of which has n memory cells,- in which a code word of a k-out-of-n code is searched for in the memory, with at least one of the Data words based on the code word a hit criterion is determined - in which the hit criterion is determined for each of the plurality of data words in relation to at least one other data word.

Description

The invention relates to efficient access to an associative memory.

Out of US 9,805,771 B2 the evaluation of states that are read from memory cells is known. A transformation into the time domain takes place, so that states that arrive correspondingly earlier in time can be used for efficiently reading out memory cells.

Associative memory or content-addressable memory (CAM) is a form of memory that works with the association of content in order to access individual memory contents. A further description of content-addressable memory is that access to memory content takes place via the input of a memory value and not via a memory address.

With regard to the architecture and functionality of associative memories, reference is made to [K. Pagiamtzis, A. Sheikholeslami: Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey, IEEE Journal of Solid-State Circuits, Vol.41, No.3, March 2016, pages 712 to 727].

One task is to improve existing solutions and in particular to create an efficient approach to using a memory, in particular an associative memory.

This object is solved according to the features of the independent claims. Preferred embodiments can be found in particular in the dependent claims.

• - bei dem ein Codewort eines k-aus-n-Codes in dem Speicher gesucht wird, wobei für mindestens eines der Datenwörter anhand des Codeworts ein Trefferkriterium bestimmt wird,
• - bei dem das Trefferkriterium für jedes der mehreren Datenwörter in Bezug auf mindestens ein anderes Datenwort bestimmt wird.

To solve the problem, a method for accessing a memory is proposed, the memory being an associative memory and having a large number of data words, each of which has n memory cells,

• - in which a code word of a k-out-of-n code is searched for in the memory, with a hit criterion being determined for at least one of the data words on the basis of the code word,
• - in which the hit criterion for each of the plurality of data words is determined in relation to at least one other data word.

The associative memory can be embodied at least in part as an RRAM.

It is advantageous here that the use of the code words enables a significant saving in memory cells compared to the use of complementary memory cells, in which two memory cells are required per information bit.

In a further development, the data words of the memory are code words of the k-out-of-n code when there are no errors.

The memory has preferably previously been written to with a quantity of data words. A search pattern, which is also a code word, is now searched for in memory. In particular: n>2 and k>0.

A development is that each bit of the data word is represented by a memory cell.

A further development is that a binary search word is transformed into the code word before the code word is searched for in the memory.

• - ein perfekter Treffer,
• - ein bester Treffer,
• - kein Treffer,
• - ein schlechtester Treffer,
• - ein i-bester Treffer,
• - ein j-schlechtester Treffer,
• - ein Treffer, der mittels einer k-Bitfehlerkorrektur korrigierbar ist.

It is a further development that the hit criterion is at least one of the following:

• - a perfect hit,
• - a best hit,
• - No hit,
• - a worst hit,
• - an i-best hit,
• - a j-worst hit,
• - a hit correctable by k-bit error correction.

In this case, i,j are natural numbers >1 and k is a natural number greater than 0. In particular, it is an option that multiple hit criteria can be determined: for example, the best hit or the second-best hit can be determined independently of whether a perfect hit is present.

It is a development that the k-out-of-n code is an n/2-out-of-n code.

In a further development, the hit criterion is determined in relation to at least one threshold value.

In one development, the at least one threshold value was/is determined beforehand or during the search for the code word in the data words.

For example, the hit criterion can be determined relative to one of the other data words. Thus, relative to the set of items searched, the best match may identify a item that is not a perfect match but is the next best match.

In one development, at least one hit criterion is determined for a number of data words in relation to at least one threshold value.

In one development, the code word is searched for in the memory by using the code word to determine the hit criterion for each data word for a set of several data words.

The data words can thus be compared with one another and/or with at least one threshold value with regard to the hit criterion.

In a further development, the hit criterion is a measure of a match between the data word and the code word.

In one development, the hit criterion is determined in the time domain by integrating a current through the memory cells of the respectively stored data word for a predetermined period of time.

A device is also proposed for accessing a memory, the memory being an associative memory and having a multiplicity of data words, each of which has n memory cells, the device being set up to carry out the method described herein.

In a further development, the data words of the memory are code words of the k-out-of-n code when there are no errors.

In one development, the memory includes resistive memory cells.

In one development, the memory is part of the device or is designed separately from it.

The properties, features and advantages described above and the manner in which these are achieved are explained further in connection with the following schematic description of exemplary embodiments which are explained in more detail in connection with the drawings. For the sake of clarity, elements that are the same or have the same effect can be provided with the same reference symbols.

• 1 eine beispielhafte Anordnung mit vier Bits, deren jedes zwei zueinander komplementäre Speicherzellen aufweist;
• 2 eine beispielhafte Anordnung vergleichbar mit der aus 1 mit einer unterschiedlichen Kodierung der komplementären Speicherzellen;
• 3 ein Diagramm, das eine Menge möglicher 4-Bit-Wörter zeigt, die in komplementären Speicherzellen eines Assoziativspeichers gespeichert sein können;
• 4 ein Diagramm, das die möglichen Kombinationen der Widerstandswerte LRS und HRS für vier Bits in Abhängigkeit von Messleitungsstrom Messzeit zeigt;
• 5 eine beispielhafte Anordnung mit acht Speicherzellen, deren Inhalt mit einer Bitfolge eines Codeworts eines k-aus-n-Codes, verglichen wird;
• 6 ein symbolisches Diagramm mit beispielhaft vier in einem Assoziativspeicher gespeicherten 4-Bit-Wörter, die mit einem Suchwort verglichen werden;
• 7 ein symbolisches Diagramm mit beispielhaft vier in einem Assoziativspeicher gespeicherten 4-Bit-Wörter, die mit dem Suchwort verglichen werden;
• 8 ein Diagramm zur Veranschaulichung mehrerer Beispiele für Vergleiche von Suchwörtern und gespeicherten Wörtern, wobei jeder dieser Vergleiche einen Messleitungsstrom bestimmt und diesen über eine Laufzeit t_r integriert;
• 9 ein Diagramm zur Veranschaulichung weiterer Beispiele für Vergleiche von Suchwörtern und gespeicherten Wörtern, wobei jeder dieser Vergleiche einen Messleitungsstrom bestimmt und diesen über eine Laufzeit t_r integriert.

Show it:

• 1 an exemplary arrangement with four bits, each of which has two mutually complementary memory cells;
• 2 an exemplary arrangement comparable to that of 1 with a different coding of the complementary memory cells;
• 3 a diagram showing a set of possible 4-bit words that can be stored in complementary memory cells of an associative memory;
• 4 a diagram showing the possible combinations of the resistance values LRS and HRS for four bits depending on the measuring line current measuring time;
• 5 an exemplary arrangement with eight memory cells, the content of which is compared with a bit sequence of a code word of a k-out-of-n code;
• 6 a symbolic diagram with an example of four 4-bit words stored in an associative memory, which are compared with a search word;
• 7 a symbolic diagram with an example of four 4-bit words stored in an associative memory, which are compared with the search word;
• 8th a diagram to illustrate several examples of comparisons of search words and stored words, each of these comparisons determines a measuring line current and integrates it over a delay time t _r ;
• 9 a diagram to illustrate further examples for comparisons of search words and stored words, each of these comparisons determines a measuring line current and integrates it over a delay time t _r .

For example, a search word (a predetermined number of n bits that represent a search pattern) serves as the input variable. The search word can be stored in a search register and applied to a table of stored words (dates or addresses) via search lines. Each stored word in the table runs via a match line to an evaluation unit (also referred to as an encoder). The evaluation unit can be used to identify whether the respective stored word is identical to the search word.

A single bit can be stored using two complementary bits. For example, resistive non-volatile memory cells can be used in an associative memory for this purpose.

1 FIG. 12 shows an exemplary arrangement with four bits, each of which has two mutually complementary memory cells.

1 1 shows an example of four complementary memory cells 110 to 113. Each of the complementary memory cells 110 to 113 includes two memory cells 101, 102 and has the following structure: The memory cell 101 contains a series connection of a MOSFET T1 and a low-impedance resistor LRS (“Low Resistive State”). , which is connected to ground on one side and to a node 120 on the other side. The memory cell 102 contains a series circuit made up of a mosfet T2 and a high-impedance resistor HRS (“High Resistive State”), which is connected to ground on the one hand and to node 120 on the other hand.

A data line of the complementary memory cell is connected on the one hand directly to the gate connection of the mosfet T1 and on the other hand via an inverter 103 to the gate connection of the mosfet T2.

If the value 1 is present on the data line of the complementary memory cell, a current I _LRS is fed into node 120, which current flows through the low-impedance resistor LRS, since the gate connection of transistor T1 is on and the gate connection of transistor T2 is off .

If the value 0 is present on the data line of the complementary memory cell, then a current I _HRS is fed into node 120, which current flows through the high-impedance resistor HRS, since the gate connection of transistor T2 is on and the gate connection of transistor T1 is off .

Due to the different resistance values LRS and HRS it follows immediately: $$I_{LRS}>I_{HRS}.$$

A current I _ML (measuring line current), which is composed of the contributions of the currents of the individual complementary memory cells 110 to 113, thus flows from the node 120 .

The data line for the respective memory cell 110 to 113 is in 1 denoted by D0 to D3. The values of the bits present on the data lines D0 to D3 thus determine the current I _ML .

Since only one of the two memory cells 101 or 102 is active per complementary memory cell 110 to 113, either the current I _LRS or the current I _HRS is fed into the node 120 for each complementary memory cell 110 to 113.

bereit.Due to the in 1 The following applies to the choice of resistance values LRS and HRS shown: A value of 1 supplies the current contribution I _LRS and a value of 0 supplies the current contribution I _HRS . If the binary word 1111 is present on the data lines D0 to D3, then the node 120 has the maximum possible current $$I_{ML}=4\cdot I_{LRS}$$

ready.

2 shows an exemplary arrangement comparable to that of FIG 1 . In contrast to 1 if the binary word 1100 is encoded in the complementary memory cells 110, 111, 212 and 213, ie only if the binary word 1100 is present on the data lines D0 to D1 does the node 120 supply the maximum current 4 I _LRS .

This is achieved by providing a complementary memory cell 212 in which, in contrast to the complementary memory cell 112, the resistance values HRS and LRS are swapped. This applies analogously to a complementary memory cell 213 which is constructed in the same way as memory cell 212 .

The complementary memory cell 212 thus supplies the higher current I _LRS when the value 0 is present on the associated data line D2, and the complementary memory cell 213 then supplies the higher current I _LRS when the value 0 is present on the associated data line D3.

3 Figure 12 shows a diagram showing a set 301 of possible 4-bit words that can be stored in the complementary memory cells of an associative memory.

For example, the memory includes the words $$\begin{array}{cccc}0& 0& 0& \mathrm{0,}\\ 0& 0& 1& \mathrm{1,}\\ 1& 1& 0& \mathrm{0,}\\ 1& 1& 1& 1.\end{array}$$

1. (i) Gespeichertes Wort 0000: Es stimmen 2 Bits mit dem Suchwort 302 überein, 2 Bits sind von dem Suchwort 302 verschieden. An dem Knoten 120 (siehe 1 oder 2) kann somit der Strom I_ML = 2I_LRS + 2I_HRS abgegriffen werden.
2. (ii) Das gespeicherte Wort 0011 ist vollständig verschieden von dem Suchwort 302. An dem Knoten 120 kann somit der Strom I_ML = 4I_HRS abgegriffen werden.
3. (iii) Das gespeicherte Wort 1100 ist identisch mit dem Suchwort 302. An dem Knoten 120 kann der maximale Strom I_ML = 4I_IRS abgegriffen werden.
4. (iv) Gespeichertes Wort 1111: Es stimmen 2 Bits mit dem Suchwort 302 überein, 2 Bits sind von dem Suchwort 302 verschieden. An dem Knoten 120 kann somit der Strom I_ML = 2I_LRS + 2I_HRS abgegriffen werden.

The word 1100 is used as the search word 302. A comparison of the search word 302 with the individual stored words results in the current contribution I _LRS in the node 120 for each matching bit and the current contribution I _HRS in the node 120 for each mismatched bit saved words follows:

1. (i) Stored word 0000: 2 bits match search word 302, 2 bits differ from search word 302. At node 120 (see 1 or 2 ) the current I _ML = 2I _LRS + 2I _HRS can be tapped.
2. (ii) The stored word 0011 is completely different from the search word 302. The current I _ML =4I _HRS can thus be tapped off at the node 120.
3. (iii) The stored word 1100 is identical to the search word 302. The maximum current I _ML =4I _IRS can be tapped off at the node 120.
4. (iv) Stored word 1111: 2 bits match search word 302, 2 bits differ from search word 302. The current I _ML =2I _LRS +2I _HRS can thus be tapped off at node 120 .

4 FIG. 12 shows a diagram showing the possible combinations of the resistance values LRS and HRS for four bits depending on the measuring line current I _ML and a measuring time.

As discussed above, the resistance values LRS and HSR contribute to different currents in node 120 . The maximum current is 4I _IRS if the search word is identical to the stored word and the minimum current is 4I _HRS if no bit of the search word is identical to the stored word. Correspondingly, in the case of partial matches of individual bits, streams between the maximum and the minimum stream result.

If the current is integrated over time, for example a capacitor is charged until a predetermined voltage is reached, this happens faster with the lower resistance value than with the high resistance value. Correspondingly, the measurement time or duration of the measurement is maximum for a total resistance value of 4 HRS and minimum for a total resistance value of 4 LRS.

The following shows how advantageously the individual memory cells can be used more efficiently. One disadvantage of complementary memory cells is that two memory cells are required for each logical bit. So in the previous example, eight memory cells are needed to store the four bits.

5 FIG. 12 shows an exemplary arrangement with eight memory cells 511 to 518 corresponding to memory cells 101 and 102. FIG 1 are constructed. Each of the memory cells 511 to 518 contains a resistive element with a resistance value of LRS or HRS. As explained above, the low-impedance resistance value LRS causes a higher current contribution I _LRS to a measuring line current I _ML (ie in a node 510 of the measuring line) and the high-impedance resistance value HRS a lower current contribution I _HRS to the measuring line current I _ML . Each of the memory cells has an input connected to the gate of the mosfet of the memory cell. The inputs are labeled B0 to B7 in accordance with the sequence of memory cells 511 to 518.

In 5 1 shows by way of example that the memory cells 511, 513, 516 and 518 have a low-impedance resistance value LRS and the memory cells 512, 514, 515 and 517 have a high-impedance resistance value HRS. Because of the sequence of resistance values in the memory cells 511 to 518, this results in the bit sequence stored therein $$\begin{array}{cccccccc}1& 0& 1& 0& 0& 1& 0& 1.\end{array}$$

In other words: If exactly this bit sequence is present at the inputs B0 to B7, the memory cells 511, 513, 516 and 518 each supply the current contribution I _LRS and the remaining memory cells do not supply any current contribution in the node 510.

An advantageous embodiment is that a search word, e.g. a 6-bit search word 110100 is encoded in a code word 01101100 of a k-out-of-n code, in particular in a code word of an n/2-out-of-n code (see step 521).

This allows a 6-bit search word to be encoded into a code word of a 4-out-of-8 code, i.e. eight memory cells are required to map six bits. This is an advantage over complementary memory cells, which require twice as many memory cells as data bits; in the present case, the 6-bit search word would therefore require six complementary memory cells with twelve individual memory cells. In the present case, the saving is four storage cells, i.e. 33% in relation to the twelve storage cells mentioned.

The code word 01101100 is used according to 5 to the inputs B0 to B7. According to the example shown here, this code word results in the following test lead current: $$I_{ML}=0+I_{HRS}+I_{LRS}+0+I_{HRS}+I_{LRS}+0+0=2\cdot I_{LRS}+2\cdot I_{HRS}.$$

This measuring line current I _ML lies between the maximum measuring line current 4I _LRS and the minimum measuring line current 4I _HRS .

The measurement line current I _ML is preferably evaluated or detected in the time domain.

A k-out-of-n code can be used for coding. In an exemplary 3-of-6 code, each code word has 6 bits (e.g. physical states of the memory cells), of which 3 bits always have either the value 0 or the value 1 and the remaining 3 bits then have the value complementary thereto.

Codewörter gibt, die jeweils k erste Werte und (n-k) zweite Werte aufweisen. Es gilt $$\left(\begin{array}{c}n\\ k\end{array}\right)=\frac{n!}{k!\cdot \left(n-k\right)!}$$

und somit für den 3-aus-6-Code $$\left(\begin{array}{c}6\\ 3\end{array}\right)=\frac{6!}{3!\cdot \left(6-3\right)!}=\frac{6!}{3!\cdot 3!}=\frac{120}{6}=20.$$

It is generally true for a k-out-of-n code that there $\left(\begin{array}{c}n\\ k\end{array}\right)$

There are code words each having k first values and (nk) second values. It applies $$\left(\begin{array}{c}n\\ k\end{array}\right)=\frac{n!}{k!\cdot \left(n-k\right)!}$$

and thus for the 3-of-6 code $$\left(\begin{array}{c}6\\ 3\end{array}\right)=\frac{6!}{3!\cdot \left(6-3\right)!}=\frac{6!}{3!\cdot 3!}=\frac{120}{6}=20$$

Thus, in the 3-of-6 code, there are a total of 20 code words in which three bits have a first value and the other three bits have a second value.

This in 5 example shown encodes the 6-bit search word into an 8-bit codeword of a 4-of-8 code. The 4 out of 8 code has $$\left(\begin{array}{c}\mathrm{8th}\\ 4\end{array}\right)=\frac{\mathrm{8th}!}{4!\cdot \left(\mathrm{8th}-4\right)!}=\frac{\mathrm{8th}!}{4!\cdot 4!}=\frac{1680}{24}=70$$

codewords, while there are 2 ⁶ = 64 possible combinations for the 6-bit search word. Correspondingly, the coding in step 521 is preferably chosen such that there is a clear mapping of each of the 64 possible search words to one code word each, with the remaining code words not being used, for example.

6 shows a symbolic diagram with four 4-bit words (from top to bottom) 0000, 0011, 1101 and 1111 stored in an associative memory by way of example. A search word 1100 is created by way of example. There is no perfect match for this search term 1100 in the associative memory since none of the stored 4-bit words are identical to this search term.

1. (i) Bei dem gespeicherten Wort 0000 stimmen 2 Bits mit dem Suchwort 1100 überein, 2 Bits sind verschieden. Der abgreifbare Messleitungsstrom ergibt sich zu: I_ML = 2I_LRS + 2I_HRS.
2. (ii) Das gespeicherte Wort 0011 ist vollständig verschieden von dem Suchwort 1100. Der abgreifbare Messleitungsstrom ergibt sich zu: $$I_{ML}=4I_{HRS}.$$
   
3. (iii) Bei dem gespeicherten Wort 1101 stimmen drei Bits mit dem Suchwort 1100 überein, das letzte Bit ist von dem Suchwort verschieden. Der abgreifbare Messleitungsstrom ergibt sich zu: $$I_{ML}=3I_{LRS}+I_{HRS}.$$
   
4. (iv) Bei dem gespeicherten Wort 1111 stimmen 2 Bits mit dem Suchwort 1100 überein, 2 Bits sind verschieden. Der abgreifbare Messleitungsstrom ergibt sich zu: I_ML = 2I_LRS + 2I_HRS.

Using the system described above, the following test lead currents result for the individually stored words in relation to the search word 1100:

1. (i) With the stored word 0000, 2 bits match the search word 1100, 2 bits are different. The measuring line current that can be tapped is: I _ML = 2I _LRS + 2I _HRS .
2. (ii) The stored word 0011 is completely different from the search word 1100. The test lead current that can be tapped is: $$I_{ML}=4I_{HRS}.$$
   
3. (iii) In the stored word 1101, three bits match the search word 1100, the last bit is different from the search word. The measuring line current that can be measured results in: $$I_{ML}=3I_{LRS}+I_{HRS}.$$
   
4. (iv) In the stored word 1111, 2 bits match the search word 1100, 2 bits are different. The measuring line current that can be tapped is: I _ML = 2I _LRS + 2I _HRS .

In this example, there is no perfect match. However, the stored word 1101 provides the relatively best match, i.e. among the words 0000, 0011, 1101 and 1111 stored in the associative memory, the word 1101 provides the next best match for the search word 1100. The next best match also provides the largest lead current among the stored words .

7 shows a symbolic diagram with four 4-bit words (from top to bottom) 1100, 0011, 1100 and 1111 stored in an associative memory by way of example. A search word 1100 is created by way of example. There are two perfect hits for this search word 1100 in the associative memory.

1. (i) Bei dem gespeicherten Wort 1100 stimmen alle 4 Bits mit dem Suchwort überein, der abgreifbare Messleitungsstrom ergibt sich zu: $$I_{ML}=4I_{LRS}.$$
   
2. (ii) Das gespeicherte Wort 0011 ist vollständig verschieden von dem Suchwort 1100. Der abgreifbare Messleitungsstrom ergibt sich zu: $$I_{ML}=4I_{HRS}.$$
   
3. (iii) Auch bei diesem gespeicherten Wort 1100 stimmen alle 4 Bits mit dem Suchwort überein, der abgreifbare Messleitungsstrom ergibt sich zu: $$I_{ML}=4I_{LRS}.$$
   
4. (iv) Bei dem gespeicherten Wort 1111 stimmen 2 Bits mit dem Suchwort 1100 überein, 2 Bits sind verschieden. Der abgreifbare Messleitungsstrom ergibt sich zu: I_ML = 2I_LRS + 2I_HRS.

Using the system described above, the following test lead currents result for the individually stored words in relation to the search word 1100:

1. (i) With the stored word 1100, all 4 bits match the search word, the measuring line current that can be tapped is: $$I_{ML}=4I_{LRS}.$$
   
2. (ii) The stored word 0011 is completely different from the search word 1100. The test lead current that can be tapped is: $$I_{ML}=4I_{HRS}.$$
   
3. (iii) With this stored word 1100, too, all 4 bits match the search word, the measurement line current that can be tapped is: $$I_{ML}=4I_{LRS}.$$
   
4. (iv) In the stored word 1111, 2 bits match the search word 1100, 2 bits are different. The measuring line current that can be tapped is: I _ML = 2I _LRS + 2I _HRS .

The first entry and the third entry of the associative memory each provide a perfect match for the search term 1100.

The two 6 and 7 illustrate that there can be different modes for determining hits. These can also be combined with one another if necessary. In this way, relatively best matches that are not perfect matches can be searched for. You can also (only) search for perfect matches. In both cases, several relatively best and/or perfect hits can be possible or permitted.

This approach is advantageous if you not only want to search for at least one perfect match, but also for (at least) one next-best match. Accordingly, depending on the application, a second or third best hit can also be important.

It is explained below how the evaluation or the detection of the measuring line current takes place in the time domain and thus at least one relatively best hit and/or at least one perfect hit can be determined.

8th 8 shows several examples 801 to 805 for comparisons of search words and stored words, each of these comparisons determining a measuring line current and integrating it over a transit time t _r .

The test lead current is integrated across a capacitance (e.g. at least one capacitor). The time results as the integration time of the current at the capacitance, with the capacitor preferably being (substantially) discharged at a time “start” and the capacitor being charged up to a predetermined threshold value at a time “target”.

Since the low-resistance memory cells deliver the greater current contribution, they also ensure that the capacitor is charged more quickly.

The time period until n/2 of the n memory cells have supplied their current contribution I _LRS (eg up to a predetermined threshold value) can preferably be used as a threshold value for the time that corresponds to the target. If an n/2-out-of-n code is used, then all "fast" memory cells (of a code word) have already made their current contribution to the integration: the remaining memory cells can be classified as slow and the code word and thus a perfect hit is recognized .

Based on this, a reference value for a perfect hit can also be determined in advance or at runtime. Preferably, a reduced value can be determined as a reference value, from which a perfect hit is considered to be recognized. The reference value preferably has a certain distance from the next worst integrated voltage value, which does not correspond to a perfect hit.

If there is no perfect match, a predetermined reference value can be used. Based on the integrated voltages of each comparison, an order (or prioritization) of the next best hits can be determined. This can be an advantage if, for example, there is no perfect match.

A measure of quality (or quality) for the individual hits can be determined on the basis of the sequence or a distance from the reference value. This can be particularly beneficial when the hit isn't perfect. It should be noted here that the result of the comparison is referred to as “hit”; in this respect, the term "hit" also denotes the degree of agreement, which in absolute terms can also be low. In contrast, the term "perfect match" denotes a complete match (in all bits) between the search word and the stored word.

A comparison 801 of the search word with a first entry in the associative memory results in an integrated voltage U1 after the time t _L (transit time) due to the current I _ML1 supplied. As explained, the current over the period of time (here the transit time t _L ) is integrated at a capacitor. The integrated voltage is known to be proportional to the integral of the current flowing in the capacitor over time.

A comparison 802 of the search word with a second entry in the associative memory results in an integrated voltage U2 after the time t _L due to the current I _ML2 supplied.

A comparison 803 of the search word with a third entry in the associative memory results in an integrated voltage U3 after the time t _L due to the current I _ML3 supplied.

A comparison 804 of the search word with a fourth entry in the associative memory results in an integrated voltage U4 after the time t _L due to the current I _ML4 supplied.

A comparison 805 of the search word with a fifth entry in the associative memory results in an integrated voltage U5 after the time t _L due to the current I _ML5 supplied.

The voltages U1 to U5 thus illustrate a "level" of the capacitor when the running time t _r is reached. The more current was delivered during this time per comparison, the higher the integrated voltage or the further the in 8th symbolically shown runners. Clearly, the path covered by the runner shown during the running time t _r corresponds to the integrated voltage.

bis zum Erreichen eines vorgegebenen Schwellwerts benötigt, wobei n die Zahl der Speicherzellen ist.For example, the time t _r may have been determined in advance based on the integration time to be expected, which the stream of $$\frac{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE102020133802B4\_0022.png,DE102020133802B4\_0023.png"\; state="\{\{state\}\}">n</figure-callout>}}{2}\cdot I_{LRS}$$

required to reach a predetermined threshold, where n is the number of memory cells.

integriert werden und die zugehörige Zeitdauer angeben, wann ein nächstbester Treffer vorliegt.It is also possible for the time t _r to be defined differently from this. For example, a stream could $$\frac{n-1}{2}\cdot I_{LRS}$$

are integrated and specify the associated time period when a next-best hit is available.

1. (i) Der Vergleich 801 liefert die Spannung U1, die anzeigt, dass das Ziel nicht erreicht wurde. Der Vergleich 801 liefert also keinen relativ besten und auch keinen perfekten Treffer.
2. (ii) Der Vergleich 802 liefert die größte Spannung U2 aller Vergleiche 801 bis 805. Das Ziel wurde überschritten. Es liegt also ein perfekter Treffer vor. Zusätzlich handelt es sich um den besten Treffer aller Vergleiche.
3. (iii) Der Vergleich 803 liefert die Spannung U3, die anzeigt, dass das Ziel nicht erreicht wurde. Der Vergleich 803 liefert also keinen relativ besten und auch keinen perfekten Treffer.
4. (iv) Der Vergleich 804 liefert die Spannung U4, die anzeigt, dass das Ziel erreicht wurde. Der Vergleich 804 liefert also einen perfekten aber keinen besten Treffer.
5. (v) Der Vergleich 805 liefert die Spannung U5, die anzeigt, dass das Ziel gerade nicht erreicht (d.h. überschritten) wurde. Der Vergleich 805 liefert daher keinen relativ besten und auch keinen perfekten Treffer.

After the expiry of the term t _r shows 8th example the following result:

1. (i) The comparison 801 supplies the voltage U1, which indicates that the goal has not been reached. The comparison 801 therefore does not provide a relatively best hit, nor does it provide a perfect hit.
2. (ii) The comparison 802 supplies the greatest voltage U2 of all the comparisons 801 to 805. The target has been exceeded. So there is a perfect match. In addition, it is the best hit of all comparisons.
3. (iii) The comparison 803 supplies the voltage U3, which indicates that the goal has not been reached. The comparison 803 therefore does not provide a relatively best hit, nor does it provide a perfect hit.
4. (iv) The comparison 804 supplies the voltage U4, which indicates that the goal has been reached. The comparison 804 thus provides a perfect but not the best match.
5. (v) The comparison 805 supplies the voltage U5, which indicates that the target has just not been reached (ie exceeded). The comparison 805 therefore does not deliver a relatively best and also no perfect hit.

If all comparisons 801 to 805 are present, it can be decided which comparison has led to no hit, a perfect hit or the best hit.

In principle, the transit time t _r and thus the target or the associated threshold value for the integrated voltage can be flexibly defined.

9 9 shows several examples 901 to 905 for comparisons of search words and stored words, each of these comparisons determining a measuring line current and integrating it over the transit time t _r .

vorgegeben sein. Auch kann die Referenzspannung U_ref einen Toleranzbereich bzw. Abstand von einem solchen Wert aufweisen, damit sichergestellt ist, dass jede Integration des Referenzstroms $\frac{n}{2}{I}_{LRS}$

als perfekter Treffer erkannt wird. Beispielsweise kann die Referenzspannung U_ref bestimmt sein durch Integration eines Referenzstroms $$\left(n-1\right)\cdot I_{LRS}+\frac{I_{LRS}+I_{HRS}}{2}.$$

By way of example, the comparison 905 here is a comparison with a reference value that determines the destination and thus also the transit time t _r . For example, comparison 905 may be a comparison to a codeword that corresponds to a perfect match. The reference value can be determined differently. For example, a reference voltage U _ref by integrating a reference current $\frac{n}{2}{I}_{LRS}$

be predetermined. The reference voltage U _ref can also have a tolerance range or distance from such a value to ensure that each integration of the reference current $\frac{n}{2}{I}_{LRS}$

recognized as a perfect match. For example, the reference voltage U _ref can be determined by integrating a reference current $$\left(n-1\right)\cdot I_{LRS}+\frac{I_{LRS}+I_{\mathrm{<figure-callout\; id="2"\; label="H\; R\; S"\; filenames="DE102020133802B4\_0022.png,DE102020133802B4\_0023.png"\; state="\{\{state\}\}">H</figure-callout>}RS}}{2}.$$

In contrast to 8th there is otherwise no perfect hit in the present case. There are four further comparisons whose current is integrated over the transit time t _r .

At the end of the running time, one of the voltages U1 to U4 and Uref was determined for each comparison, which indicates a measure for reaching and/or exceeding the target (ie a predetermined voltage threshold value). It can thus be determined here, for example, whether the comparison between the search word and the respective stored word results in a perfect hit, a best hit or no hit.

1. (i) Der Vergleich 901 liefert die Spannung U1, die anzeigt, dass das Ziel nicht erreicht wurde. Der Vergleich 901 liefert also keinen relativ besten und auch keinen perfekten Treffer.
2. (ii) Der Vergleich 902 liefert die größte Spannung U2 aller Vergleiche 901 bis 904. Das Ziel wurde aber nicht überschritten. Es liegt also kein perfekter Treffer vor, aber der Vergleich ist der beste Treffer aller Vergleiche 901 bis 904 (der Vergleich 905 wird hier nicht berücksichtigt, weil er zur Bestimmung des Referenzwerts dient).
3. (iii) Der Vergleich 903 liefert die Spannung U3, die anzeigt, dass das Ziel nicht erreicht wurde. Der Vergleich 903 liefert also keinen relativ besten und auch keinen perfekten Treffer.
4. (iv) Der Vergleich 904 liefert die Spannung U4, die anzeigt, dass das Ziel nicht erreicht wurde. Der Vergleich 904 liefert also keinen relativ besten und auch keinen perfekten Treffer.
5. (v) Der Vergleich 905 liefert den eingangs erwähnten Referenzwert zur Festlegung des Ziels.

After expiry of the running time t _r returns 9 example the following result:

1. (i) The comparison 901 supplies the voltage U1, which indicates that the goal has not been reached. The comparison 901 therefore does not deliver a relatively best and also no perfect hit.
2. (ii) The comparison 902 delivers the greatest voltage U2 of all the comparisons 901 to 904. However, the target was not exceeded. There is therefore no perfect match, but the comparison is the best match of all comparisons 901 to 904 (comparison 905 is not considered here because it is used to determine the reference value).
3. (iii) The comparison 903 supplies the voltage U3, which indicates that the goal has not been reached. The comparison 903 therefore does not deliver a relatively best and also no perfect hit.
4. (iv) The comparison 904 supplies the voltage U4, which indicates that the goal has not been reached. The comparison 904 therefore does not deliver a relatively best and also no perfect hit.
5. (v) The comparison 905 provides the reference value mentioned at the outset for determining the goal.

If all comparisons 901 to 905 are present, it can be decided which comparison has led to no hit, a perfect hit or the best hit.

It is an option that at least one reference value is determined. In particular, several reference values can be determined and the integrated voltage can be compared with these several measured values.

For example, reference values can be determined in order to identify the perfect hit and/or to identify a hit that is not perfect but can be corrected, for example by means of an error correction. For example, hits can be specifically recognized that have a one-bit error, a two-bit error, etc.—preferably depending on the stage of expansion and the performance of the error correction used.

Further configurations and advantages:

A sense amplifier can advantageously be provided, which transforms a current on a measuring line into the time domain. This can be achieved, for example, by integrating the current across at least one capacitor. The duration of the integration (measuring time) determines a voltage. If the duration is constant, the different currents result in different voltages that can be compared with one another.

If the quality of a comparison is proportional to the level of the voltage integrated during the runtime (integration period), comparison results (hits) can be set in relation to one another. For example, hits can be sorted according to their quality. By comparing the hit with a threshold value, it is possible to identify a hit criterion, e.g. a perfect hit. Several threshold values can also be used to determine different hit criteria, e.g. quality levels of hits. A quality level is, for example, a hit that is not perfect but can be corrected (using an error-correcting code).

Efficient use of the memory cells is possible through the use of an n/2-out-of-n code. In addition, the n/2-of-n code has the advantage of being able to terminate the comparison from a number of n/2 fastest cells. In this way, the runtime can be limited to the n/2 fastest cells being detected. Based on this, a reference runtime can be determined for the further (substantially) simultaneously started comparisons.

A k-of-n code can be used, where k is a positive integer greater than or equal to 1 and n is a positive integer greater than 2. If n is an odd number, k can be the largest integer less than n/2 or k can be the smallest integer greater than n/2.

• - kein Treffer,
• - perfekter Treffer,
• - bester Treffer,
• - schlechtester Treffer,
• - i-bester Treffer,
• - j-schlechtester Treffer,
• - Treffer, der mittels einer k-Bitfehlerkorrektur korrigierbar ist.

It is also an option that a previously determined reference runtime is used for a run through of further comparisons. A run through a number of comparisons includes, for example, a search word that is compared with a number of entries in a memory. The comparisons can be made one after the other or at least partially with a time overlap (eg simultaneously). The comparisons are then related to each other so that it can be determined which of the comparisons meets or does not meet a specified hit criterion, e.g.:

• - No hit,
• - perfect hit,
• - best hit,
• - worst hit,
• - i-best hit,
• - j-worst hit,
• - Hit correctable by k-bit error correction.

Here, i, j and k can be integers.

With regard to the determination of states in the time domain, reference is also made to US 9,805,771 B2 referred. By transforming the variables to be detected into the time domain, the individual states occur one after the other. In US 9,805,771 B2 also describes how, starting from a hold signal determined by logic, a large number of latches (eg a latch can be implemented as a D flip-flop) are stopped or the state of these latches is frozen. This mechanism of freezing the latches can also be used for the examples described herein.

Claims (15)

Method for accessing a memory, the memory being an associative memory and having a multiplicity of data words, each of which has n memory cells, - in which a code word of a k-out-of-n code is searched for in the memory, with a hit criterion being determined for at least one of the data words on the basis of the code word, - in which the hit criterion for each of the plurality of data words is determined in relation to at least one other data word. procedure after claim 1 , in which the data words of the memory are code words of the k-out-of-n code in the error-free case. procedure after claim 1 , in which each bit of the data word is represented by a memory cell. A method according to any one of the preceding claims, in which a binary search word is transformed into the code word before the code word is searched for in the memory. Method according to one of the preceding claims, in which the hit criterion is at least one of the following: - a perfect hit, - a best hit, - No hit, - a worst hit, - an i-best hit, - a j-worst hit, - a hit correctable by k-bit error correction. Method according to one of the preceding claims, in which the k-out-of-n code is an n/2-out-of-n code. Method according to one of the preceding claims, in which the hit criterion is determined in relation to at least one threshold value. procedure after claim 7 , in which the at least one threshold value was/is determined in advance or during the search for the code word in the data words. Method according to one of the preceding claims, in which at least one hit criterion is determined for a plurality of data words in relation to at least one threshold value. Method according to one of the preceding claims, in which the code word is searched for in the memory by the hit criterion per data word being determined in each case for a quantity of a plurality of data words on the basis of the code word. Method according to one of the preceding claims, in which the hit criterion is a measure of a match between the data word and the code word. Method according to one of the preceding claims, in which the hit criterion is determined in the time domain by integrating a current through the memory cells of the respectively stored data word for a predetermined period of time. Device for accessing a memory, the memory being an associative memory and having a multiplicity of data words, each of which has n memory cells, the device being set up to carry out the method according to one of the preceding claims. device after Claim 13 , in which the memory comprises resistive memory cells. Device according to one of Claims 13 or 14 , in which the memory is part of the device or executed separately from this.

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