DE102020133739A1 - Extremely high coding rates for next-generation WLAN systems - Google Patents

Abstract

A method of extremely high coding rates for local radio network, WLAN, systems of a next generation comprises coding input data at a first coding rate using codes which are designed for coding up to a second coding rate which is lower than the first coding rate to provide encoded data (1310). The method also includes wirelessly transmitting the encoded data (1320).

Description

Cross-reference to a related patent application

The present disclosure is part of a non-provisional patent application that has priority over the provisional U.S. Patent Application No. 62 / 951,189 , filed on December 20, 2019, the contents of which are included in their entirety.

Technical area

The present disclosure relates generally to radio communications and, more particularly, to extremely high coding rates for next generation radio local area network (WLAN) systems.

background

Unless otherwise indicated here, approaches that are described in this section are not prior art to the claims listed below and are not recognized as prior art by including them in this section.

For extreme high throughput (EHT) systems, such as WLAN systems in accordance with the future Institute of Electrical and Electronics Engineers (IEEE) 802.11be standard, 4096 quadrature amplitude modulation (4096-QAM) is selected as one of the technologies to achieve the goal of extremely high throughput. In current WLAN systems based on one or more of the IEEE 802.11 standards, the highest coding rate is 5/6. Considering up to eight or even sixteen transmission antennas which might be available in an EHT WLAN based on the IEEE 802.11be standard, it may be reasonable to assume that with transmission beamforming to achieve beamforming gain, a higher coding rate ( n) can be carried out. Therefore, there is a need for a solution to provide higher coding rates in order to achieve extremely high throughput in next generation WLAN systems.

Summary

The following summary is illustrative only and is not intended to be limiting in any way. That is, the summary below is provided to introduce concepts, highlights, uses, and advantages of the new and non-obvious techniques described herein. Selected implementations are described further below in the detailed description. Thus, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.

One object of the present disclosure is to provide schemes, concepts, designs, techniques, methods and devices that relate to extremely high coding rates for next-generation WLAN systems. In particular, in various proposed schemes according to the present disclosure, new coding rates higher than 5/6, such as 7/8 and 11/12, can be implemented. With such new higher coding rates, overall system throughput can be improved (e.g. by about 5% and 10% respectively compared to existing coding rates). Further, in order to reduce complexity in an implementation, coding processes of the new coding rates according to various proposed schemes of the present disclosure on existing Low Density Parity Check (LDPC) codes as defined in IEEE 802.11n / ac / ax standards , using several new parameters introduced here. Advantageously, LDPC encoder and decoder designs that are used in a WLAN based on IEEE 802.11n / ac / ax standards can be reused for these new coding rates.

A method according to the invention is defined in independent claim 1. The subclaims define preferred embodiments thereof. In one aspect, a method may include encoding input data at a first encoding rate using codes designed to be encoded up to a second encoding rate that is lower than the first encoding rate to provide encoded data. The method can also include wireless transmission of the encoded data.

It is noteworthy that, although the description presented herein may be in the context of certain radio access technologies, networks, and network topologies such as Wi-Fi, the proposed concepts, schemes, and any variation (s) / derivatives thereof in, for and by other types of radio access technologies, networks and network topologies, such as, without limitation, Bluetooth, ZigBee, ^5th generation (5G) / New radio (NR), Long-term evolution (LTE), LTE-Advanced, LTE Advanced Pro, Internet of Things (loT), Industrial loT (Ilot) and Narrowband loT (NBloT) can be implemented. Thus, the scope of the present disclosure is not limited to the examples described herein.

Figure list

• 1 ist ein Diagramm einer Beispielnetzwerkumgebung, in welcher verschiedene Lösungen und Schemen gemäß der vorliegenden Offenbarung implementiert sein können.
• 2 ist ein Diagramm einer Beispielauslegung gemäß der vorliegenden Offenbarung.
• 3 ist ein Diagramm einer Beispielauslegung gemäß der vorliegenden Offenbarung.
• 4 ist ein Diagramm einer Beispielauslegung gemäß der vorliegenden Offenbarung.
• 5 ist ein Diagramm eines Beispielszenariums gemäß der vorliegenden Offenbarung.
• 6 ist ein Diagramm einer Beispielauslegung gemäß der vorliegenden Offenbarung.
• 7 ist ein Diagramm einer Beispielauslegung gemäß der vorliegenden Offenbarung.
• 8 ist ein Diagramm einer Beispielauslegung gemäß der vorliegenden Offenbarung.
• 9 ist ein Diagramm einer Beispielauslegung gemäß der vorliegenden Offenbarung.
• 10 ist ein Diagramm eines Beispielszenariums gemäß der vorliegenden Offenbarung.
• 11 ist ein Diagramm eines Beispielszenariums gemäß der vorliegenden Offenbarung.
• 12 ist ein Blockdiagramm eines Beispielkommunikationssystems gemäß einer Implementierung der vorliegenden Offenbarung.
• 13 ist ein Ablaufdiagramm eines Beispielprozesses gemäß einer Implementierung der vorliegenden Offenbarung.

The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated into and constitute a part of the present disclosure. The drawings illustrate implementations of the disclosure and, together with the description, serve to explain the principles of the disclosure. It should be noted that the drawings are not necessarily to scale as some components may not be shown proportional to size in an actual implementation in order to clearly illustrate the concept of the present disclosure

• 1 Figure 13 is a diagram of an example network environment in which various solutions and schemes in accordance with the present disclosure may be implemented.
• 2 Figure 13 is a diagram of an example layout in accordance with the present disclosure.
• 3 Figure 13 is a diagram of an example layout in accordance with the present disclosure.
• 4th Figure 13 is a diagram of an example layout in accordance with the present disclosure.
• 5 Figure 3 is a diagram of an example scenario in accordance with the present disclosure.
• 6th Figure 13 is a diagram of an example layout in accordance with the present disclosure.
• 7th Figure 13 is a diagram of an example layout in accordance with the present disclosure.
• 8th Figure 13 is a diagram of an example layout in accordance with the present disclosure.
• 9 Figure 13 is a diagram of an example layout in accordance with the present disclosure.
• 10 Figure 3 is a diagram of an example scenario in accordance with the present disclosure.
• 11 Figure 3 is a diagram of an example scenario in accordance with the present disclosure.
• 12th FIG. 3 is a block diagram of an example communication system in accordance with an implementation of the present disclosure.
• 13th Figure 3 is a flow diagram of an example process according to an implementation of the present disclosure.

Detailed description of preferred embodiments

Detailed embodiments and implementations of the claimed subject matter are disclosed herein. It should be understood, however, that the disclosed embodiments and implementations are only illustrative of the claimed subject matter, which can be embodied in various forms. However, the present disclosure may be embodied in many different forms and should not be viewed as limited to the exemplary embodiments and implementations set forth herein. Rather, these exemplary embodiments and implementations are provided so that a description of the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In the following description, details of known features and techniques may be omitted in order to avoid unnecessarily obscuring the presented embodiments and implementations.

overview

Implementations in accordance with the present disclosure relate to various techniques, methods, schemes and / or solutions relating to extremely high coding rates for next-generation WLAN systems. In accordance with the present disclosure, a number of possible solutions can be implemented separately or together. That is, although these possible solutions may be described separately below, two or more of these possible solutions can be implemented in one or another combination.

1 provides a sample network environment 100 Figure 12 in which various solutions and schemes may be implemented in accordance with the present disclosure. 2 ~ 11 provide examples of implementations of various proposed schemes in the network environment 100 in accordance with the present disclosure. The following description of various proposed schemes is made with reference to FIG 1 ~ 11 provided.

In terms of 1 can the network environment 100 include that at least one STA 110 wireless with an access point (AP) 120 communicates. In some cases, the STA 110 and the AP 120 with a basic service rate (BSS) 130 according to one or more IEEE 802.11 Standards (e.g. IEEE 802.11be and standards developed in the future) must be linked. Each of the STA 110 and the AP 120 may be arranged to communicate with one another using extremely high coding rates according to various proposed schemes described below.

2 provides an example design 200 according to the present disclosure. Regarding 2 leads the interpretation 200 new LDPC Parameters associated with a new coding rate R of 7/8. For example, for R = 7/8, a length of an LDPC information block (which is the length of a bit stream of data at the input of an LDPC encoder) can be 539 bits, 1078 bits or 1617 bits, and the corresponding length of an LDPC code word block (which is the length of the encoded stream of data at the output of the LDPC encoder) can be 616 bits, 1232 bits, or 1848 bits, respectively. It can be further in the interpretation 200 give several ranges of numbers of available bits (N _avbits ) each of which corresponds to respective LDPC parameters including a number of LDPC codewords (N _CW ) and a length of an LDPC codeword (L _LDPC ).

In part (A) of 2 various example sets of an input length and an output length are shown, which correspond to a coding rate R = 7/8. In part (B) of 2 various example LDPC parameters N _CW and L _{LDPC are} shown, which correspond to a coding rate R = 7/8. In particular, depending on the length of the input data (for example with regard to the number of available bits N _avbits ), a corresponding set of N _CW and L _{LDPC can be used} when coding the data. For example, for the range of N _avbits ≤ 616, N _CW 1 and L _LDPC can be either 1232 (if N _avbits ≥ the number of bits in the Physical Layer Convergence Protocol (PLCP) Service Data Unit (PSDU) and a SERVICE field (N _pld ) + 864 x (1 - R)) or 616 (otherwise). For the range of 616 <N _avbits ≤ 1232, N _CW can be 1 and L _LDPC can be either 1848 (if N _avbits ≥ N _pld + 1392 x (1 - R)) or 1232 (otherwise). For the range of 1232 <N _avbits ≤ 1848, N _CW can be 1 and L _LDPC can be 1848. For the range of 1848 <N _avbits ≤ 2464, N _CW 2 and L _LDPC can either be 1848 (if N _avbits ≥ N _pld + 2776 x (1 - R)) or 1232 (otherwise). For the range of 2464 <N _avbits , N can be _CW [N _pld / (1848 × R)] and L _LDPC can be 1848.

3 provides an example design 300 according to the present disclosure. Regarding 3 leads the interpretation 300 new LDPC parameters associated with a new coding rate R of 11/12. For example, for R = 11/12, an LDPC information block length 539 Bits, 1078 bits or 1617 bits, and the corresponding LDPC codeword block length can be 588 bits, 1176 bits or 1764 bits, respectively. It can be further in the interpretation 300 give multiple ranges of N _avbits each of which corresponds to a respective N _CW and L _LDPC.

In part (A) of 3 various example sets of an input length and an output length are shown, which correspond to a coding rate R = 11/12. In part (B) of 3 various example LDPC parameters N _CW and L _{LDPC are} shown, which correspond to a coding rate R = 11/12. In particular, depending on the length of the input data (for example with regard to the number of available bits N _avbits ), a corresponding set of N _CW and L _{LDPC can be used} when coding the data. For example, for the range of N _avbits 588, N _{CW can be} 1 and L _LDPC can be either 1176 (if N _avbits N _pld + 828 × (1-R)) or 588 (otherwise). For the range of 588 <N _avbits ≤ 1176, N _CW can be 1 and L _LDPC can be either 1764 (if N _avbits ≥ N _pld + 1320 × (1 - R)) or 1176 (otherwise). For the range of 1176 <N _avbits ≤ 1764, N _CW can be 1 and L _LDPC can be 1764. For the range of 1764 <N _avbits ≤ 2352, N _CW 2 and L _LDPC can be either 1764 (if N _avbits ≥ N _pld + 2652 × (1 - R)) or 1176 (otherwise). For the range of 2352 <N _avbits , N can be _CW [N _pld / (1764 × R)] and L _LDPC can be 1764.

4th provides an example design 400 according to the present disclosure. Regarding 4th leads the interpretation 400 introduce new coding parameters associated with the higher coding rates of the present disclosure, including a number of total shortening bits (N _shrt ), a predetermined number of total shortening bits (N _{shrt_default} ), a number of total punctured bits (N _punc ), and a predetermined number total punctured bits (N _{punc_default} ). In the interpretation 400 there can be several combinations of parameters associated with the new coding rates 7/8 and 11/12. For example, for R = 7/8 the length of an information block ( K0 ) 539 bits, the length of a code word block (L) can be 616 bits, the length of parity bits (P) can be 77 bits, N _{shrt_default} can be 1, N _{punc_default} can be 31 and the parameters that are used when selecting used by LDPC parity check matrices, Z = 27, R = 5/6 and n = 648. Alternatively, K0 can be 1078 bits for R = 7/8, L can be 1232 bits, P can be 154 bits, N _{shrt_default} can be 2, N _{punc_default} can be 62 and the parameters that are used when selecting LDPC parity check matrices can be used, Z = 54, R = 5/6 and n = 1296. As an alternative, R = 7/8 K0 can be 1617 bits, L can be 1848 bits, P can be 231 bits, N _{shrt_default} can be 3, N _{punc_default} can be 93 and parameters that are used when selecting LDPC parity check matrices can be used, Z = 81, R = 5/6 and n = 1944. For R = 11/12, K0 can be 539 bits, L can be 588 bits, P can be 49 bits, N _{shrt_default} can be 1, N _{punc_default} can be 59 and parameters that are used when selecting LDPC parity check matrices , Z = 27, R = 5/6 and n = 648. Alternatively, for R = 11/12 K0 can be 1078 bits, L can be 1176 bits, P can be 98 bits, N _{shrt_default} can be 2, N _{punc_default} can be 118 and parameters used when selecting LDPC parity check matrices can be Z = 54, R = 5/6 and n = 1296. Alternatively, R = 11/12 K0 can be 1617 bits, L can be 1764 bits, P can be 147 bits, N _{shrt_default} can be 3, N _{punc_default} can be 117 and parameters that are used when selecting LDPC parity check matrices can be used, Z = 81, R = 5/6 and n = 1944.

5 provides an example scenario 500 according to a proposed scheme of the present disclosure. The scenario 500 Figure 12 shows an example of an overall LDPC coding process for new coding rates (e.g., R = 7/8 and 11/12) in a proposed scheme of the present disclosure. It is noteworthy that, in addition to the use of a fixed R = 5/6 in the function block of an LDPC parity check bit generation, new coding rates (eg R = 7/8 and 11/12) in other function blocks in the scenario 500 be valid.

In terms of 5 When coding data bits of input data, a shortening procedure can be carried out on the input data in order to provide a bit sequence. The bit sequence can have a plurality of data bits of the input data, one or more predetermined shortened bits (eg zero to three “0” bits) and a plurality of shortening bits that are calculated by the shortening process. In addition, a plurality of parity bits can be generated based on the bit sequence. The parity bits can also be appended to the bit sequence in order to provide a concatenated bit sequence. Furthermore, the one or more predetermined shortened bits and the plurality of shortened bits from the concatenated bit sequence can be discarded in order to provide a shortened bit sequence. Either a puncturing procedure or a repetition procedure can then be carried out on the shortened bit sequence.

1. (a) für R = 7/8, K0 = 539, L = 616 und P = 77 N_{shrt_default} = 1 ist; (b) für R = 7/8, K0 = 1078, L = 1232 und P = 154 N_{shrt_default} = 2 ist; (c) für R = 7/8, K0 = 1617, L = 1848 und P = 231 N_{shrt_detault} = 3 ist; (d) für R = 11/12, K0 = 539, L = 588 und P = 49 N_{shrt_default} = 1 ist; (e) für R = 11/12, K0 = 1078, L = 1176 und P = 98 N_{shrt_default} = 2 ist; und (f) für R = 11/12, KO = 1617, L = 1764 und P = 147 N_{shrt_default} = 3 ist.

In the proposed scheme, a number of total shortening bits (N _shrt ) of the plurality of shortening bits can be calculated as follows: N _shrt = max (0, N _CW XL _LDPC × R) - N _pld ). Furthermore, a value of the number of predetermined shortened bits (N shrt_default) for the first coding rate (R), a respective information _{block length (} K0 ), a respective code word block length (L), a respective length of the parity bits (P), so that:

1. (a) for R = 7/8, K0 = 539, L = 616 and P = 77 N _{shrt_default} = 1; (b) for R = 7/8, K0 = 1078, L = 1232 and P = 154, N _{shrt_default} = 2; (c) for R = 7/8, K0 = 1617, L = 1848 and P = 231, N _{shrt_detault} = 3; (d) for R = 11/12, K0 = 539, L = 588 and P = 49, N _{shrt_default} = 1; (e) for R = 11/12, K0 = 1078, L = 1176 and P = 98, N _{shrt_default} = 2; and (f) for R = 11/12, KO = 1617, L = 1764 and P = 147 N _{shrt_default} = 3.

With the proposed scheme, certain operations can be performed when the puncturing procedure is carried out. For example, a number of total punctured bits can be calculated. Further, in response to the determination that the number of total punctured bits is greater than zero, a first number of bits of the parity bits may be punctured. Alternatively, in response to determining that the number of total punctured bits is equal to zero and a number of repeated bits per code word is greater than a number of predetermined punctured bits, a second number of bits of the parity bits can be punctured. In such cases, the first number can be equal to the number of predetermined punctured bits plus a number of punctured bits per code word. In addition, the second number can be equal to the number of predetermined punctured bits minus the number of repeated bits per code word.

In the proposed scheme, a value of the number of predetermined punctured bits (N punc_default) can be added to the first coding rate (R), a respective information _{block length (} K0 ), a respective code word block length (L), a respective length of the parity bits (P), so that: (a) for R = 7/8, K0 = 539, L = 616 and P = 77 N _{punc_default} = 31; (b) for R = 7/8, K0 = 1078, L = 1232 and P = 154, N _{punc_default} = 62; (c) for R = 7/8, K0 = 1617, L = 1848 and P = 231, N _{punc_default} = 93; (d) for R = 11/12, K0 = 539, L = 588 and P = 49, N _{punc_default} = 59; (e) for R = 11/12, K0 = 1078, L = 1176 and P = 98, N _{punc_default} = 118; and (f) for R = 11/12, K0 = 1617, L = 1764 and P = 147, N _{punc_default} = 177.

With the proposed scheme, additional operations can be performed when performing the puncturing procedure. For example, the number of punctured bits per code word (N _ppcw ) can be determined based on the number of total punctured bits. In such cases, in calculating the number of total punctured bits, the number of total punctured bits (N _punc ) can be calculated as follows: N _punc = max (0, (N _CW × L _LDPC ) - N _avbits - N _shrt ).

With the proposed scheme, certain operations can be carried out when the retry procedure is carried out. For example, a number of total repeated bits can be calculated. In addition, in response to a number of total punctured bits being equal to zero and a number of predetermined punctured bits being less than a number of repeated bits per code word to which parity bits are appended, the total repeated bits may be added.

In the proposed scheme, when calculating the number of total repeated bits, the number of total repeated bits (N _rep ) can be as can be calculated as follows: N _rep = max (0, N _avbits - N _CW XL _LDPC × (1 - R) - N _pld ).

In the proposed scheme, when executing the puncturing procedure in response to the fact that a number of total punctured bits (N _punc ) is greater than or equal to zero, continuous puncturing on the shortened bit sequence by discarding the last N _{punc_default} + N _ppcw bits of the parity -Bits are executed.

In the proposed scheme, when the puncturing procedure is carried out in response to the fact that a number of total punctured bits (N _punc ) is greater than zero, an interleaved puncturing on the shortened bit sequence by first discarding N _{punc_default} bits of the parity bits on one interleaved and then discarding the last N _ppcw bits of remaining bits of the parity bits.

In the proposed scheme, when the N _{punc_default} bits of the parity bits are discarded in the interleaved manner, one bit for every three bits of the parity bits can be discarded in response to the first coding rate being 7/8. Alternatively, one bit for every two bits of the parity bits can be discarded in response to the first coding rate being 11/12.

6th provides an example design 600 according to the present disclosure. Regarding 6th leads the interpretation 600 insert new coding parameters for other high coding rates, such as, without limitation, 6/7, 8/9, 9/10 and 10/11. For example, for R = 6/7, K0 can be 540 bits, L can be 630 bits, P can be 90 bits, N _{shrt_default} can be 0, N _{punc_default} can be 18 and parameters that can be used when selecting LDPC parity Check matrices can be used, Z = 27, R = 5/6 and n = 648. Alternatively for R = 6/7, K0 can be 1080 bits, L can be 1260 bits, P can be 180 bits, N _{shrt_default} can be 0, N _{punc_default} can be 36 and can be parameters that are used when selecting LDPC parity check matrices can be used, Z = 54, R = 5/6 and n = 1296. As an alternative for R = 6/7, K0 can be 1620 bits, L can be 1890 bits, P can be 270 bits, N _{shrt_default} can be 0, N _{punc_default} can be 54 and parameters that can be used when LDPC parity is selected. Check matrices can be used, Z = 81, R = 5/6 and n = 1944. For R = 8/9, K0 can be 536 bits, L can be 603 bits, P can be 67 bits, N _{shrt_default} can be 4, N _{punc_default} can be 41 and can be parameters used when selecting LDPC parity check matrices will be, Z = 27, R = 5/6 and n = 648. Alternatively for R = 8/9, K0 can be 1080 bits, L can be 1215 bits, P can be 135 bits, N _{shrt_default} can be 0, N _{punc_default} can be 81 and can be parameters that are used when selecting LDPC parity check matrices can be used, Z = 54, R = 5/6 and n = 1296. As an alternative for R = 8/9, K0 can be 1616 bits, L can be 1818 bits, P can be 202 bits, N _{shrt_default} can be 4, N _{punc_default} can be 122 and parameters that can be used when selecting LDPC parity Check matrices can be used, Z = 81, R = 5/6 and n = 1944. For R = 9/10, K0 can be 540 bits, L can be 600 bits, P can be 60 bits, N _{shrt_default} can be 0, N _{punc_default} can be 48 and can be parameters used in selecting LDPC parity check matrices will be, Z = 27, R = 5/6 and n = 648. Alternatively for R = 9/10, K0 can be 1080 bits, L can be 1200 bits, P can be 120 bits, N _{shrt_default} can be 0, N _{punc_default} can be 96 and can be parameters that should be used when selecting LDPC parity check matrices can be used, Z = 54, R = 5/6 and n = 1296. As an alternative for R = 9/10, K0 can be 1620 bits, L can be 1800 bits, P can be 180 bits, N _{shrt_default} can be 0, N _{punc_default} can be 144 and parameters that can be used when selecting LDPC parity Check matrices can be used, Z = 81, R = 5/6 and n = 1944. For R = 10/11, K0 can be 540 bits, L can be 594 bits, P can be 54 bits, N _{shrt_default} can be 0, N _{punc_default} can be 54 and can be parameters used when selecting LDPC parity check matrices will be, Z = 27, R = 5/6 and n = 648. Alternatively for R = 10/11, K0 can be 1080 bits, L can be 1188 bits, P can be 108 bits, N _{shrt_default} can be 0, N _{punc_default} can be 108 and can be parameters that are used when selecting LDPC parity check matrices can be used, Z = 54, R = 5/6 and n = 1296. As an alternative for R = 10/11, K0 can be 1620 bits, L can be 1782 bits, P can be 162 bits, N _{shrt_default} can be 0, N _{punc_default} can be 162 and parameters that can be used when LDPC parity is selected. Check matrices can be used, Z = 81, R = 5/6 and n = 1944.

In a proposed scheme of puncturing parity bits in accordance with the present disclosure, either a continuous puncturing option or another interleaved puncturing option may be used. With continuous puncturing, the last N _{punc_default} plus a number of punctured bits per code word (N _ppcw ), referred to here as N _{punc_default} + N _ppcw , parity bits can be discarded as: Pn-k- N _ppcw - N _{punc_default-1,.} .. P _nk-1 . In the proposed scheme, the option of continuous puncturing can be used both for the case in which a number of total punctured bits N _punc > 0 and for the case in which N _punc = 0.

With interleaved puncturing, the first N _{punc_default} parity bits can be punctured in an interleaved manner, as described below. For R = 7/8 the N _{punc_default} bits can be discarded as: P _{0: 3: 3} * N _{punc_default-1} . That is, in a case that R = 7/8, a parity Bits of every three parity bits are discarded. For the remaining parity bits, the last N _ppcw bits can be discarded. For R = 11/12 the N _{punc_default} bits can be discarded as: P _{0: 2: 2} * ( _n -kN _{punc_default} ) P _{2 *} ( _n -k- N _{punc_default} ) _{+1: nk-1} . That is, in a case that R = 11/12, one parity bit can be discarded out of every two parity bits. For the remaining parity bits, the last N _ppcw bits can be discarded. In the proposed scheme, the option of nested puncturing can be used for the case of N _punc > 0.

7th provides an example design 700 according to the present disclosure. Regarding 7th leads the interpretation 700 insert new modulation and coding scheme (MCS) indices for the proposed new coding with 4096-QAM. For example, the in 7th new MCSs shown can be appended to existing high-efficiency (HE) MCSs in the IEEE 802.11ax standard for different resource units (RUs) and RU combinations. Correspondingly, the signaling MCSs, as defined in the IEEE 802.11 standards, with new MCS indices can be reused for signaling the new coding rates proposed here.

8th provides an example design 800 according to the present disclosure. Regarding 8th leads the interpretation 800 new MCS indexes for the proposed new encoding with 4096-QAM. For example, the in 8th The new MCSs shown here can be appended to existing HE-MCSs and EHT-MCSs in the IEEE 802.11ax / be standards for different RUs and RU combinations. Correspondingly, the signaling MCSs, as defined in the IEEE 802.11 standards, with new MCS indices can be reused for signaling the new coding rates proposed here. In a proposed scheme in accordance with the present disclosure, a reserved bit may be used in conjunction with existing MCS bits to indicate the newly defined MCSs, as in FIG 8th shown.

9 provides an example design 900 in accordance with the present disclosure. In one proposed scheme, support for 4096 QAM in an EHT WLAN may be optional. In the proposed scheme, an indication of support for 4096-QAM and different coding rates may be included in the scope field (s) and may be exchanged between STAs (comprising APs and non-AP-STAs). For example, two bits can be used as the indication of new coding rates with 4096-QAM or new MCSs, as in FIG 9 shown.

10 provides an example scenario 1000 in accordance with the present disclosure. For illustrative purposes and without limiting the scope of the present disclosure, the scenario shows 1000 Sensitivity signal-to-interference signal (SNR) requirements for higher coding rates proposed here (e.g. R = 7/8 and 11/12). 11 provides an example scenario 1100 in accordance with the present disclosure. For illustrative purposes and without limiting the scope of the present disclosure, the scenario shows 1100 Sensitivity SNR requirements for higher coding rates proposed here (e.g. R = 7/8 and 11/12).

Illustrative implementations

12th provides an example system 1200 , the at least one example device 1210 and an example device 1220 according to an implementation of the present disclosure. Any of the devices 1210 and the device 1220 May perform various functions to implement schemes, techniques, processes, and methods described herein that involve extremely high coding rates for next generation WLAN systems, including the various schemes described above with respect to both the various proposed designs, concepts described above , Schemes, systems and procedures as well as the processes described below are described. For example, the device 1210 in a STA 110 be implemented and the device 1220 can in an AP 120 implemented, or vice versa.

Each of the device 1210 and the device 1220 may be part of an electronic device, which may be an STA or an AP, such as a transportable or mobile device, a portable device, a radio communication device, or a computing device. When implemented in an STA, any of the devices can 1210 and the device 1220 be implemented in a smartphone, a smart watch, a personal digital assistant, a digital camera or a computer equipment such as a tablet computer, a laptop computer or a notebook computer. Each of the device 1210 and the device 1220 may also be part of a machine-like device, which may be a loT device, such as a stationary or stationary device, a home device, a wire communication device, or a computing device. For example, each of the devices 1210 and the device 1220 be implemented in a smart thermostat, smart refrigerator, smart door lock, wireless speaker, or home control center. When implemented in or as a network device is, the device can 1210 and / or the device 1220 be implemented in a network node such as an AP in a WLAN.

In some implementations, any of the devices 1210 and the device 1220 be implemented in the form of one or more integrated circuit (IC) chips, such as, for example, and without limitation, one or more single core processors, one or more multi-core processors, one or more Reduced Instruction Set Computing (RISC) processors, or one or more Complex Instruction Set Computing (CISC) processors. In the various schemes described above, each of the devices 1210 and the device 1220 be implemented in or as an STA or in or as an AP. Each of the device 1210 and the device 1220 may have at least some of those components that are in 12th are shown, such as one processor at a time 1212 and a processor 1222 . Each of the device 1210 and the device 1220 may further comprise one or more other components that are not relevant to the proposed scheme of the present disclosure (e.g. an internal power supply, a display device and / or a user interface device), and thus such a component (s) of the device 1210 and the device 1220 in the interests of simplicity and brevity neither in 12th shown and described below.

In one aspect, anyone can use the processor 1212 and the processor 1222 be implemented in the form of one or more single core processors, one or more multi-core processors, one or more RISC processors, or one or more CISC processors. That is, even if a singular term "a processor" is used here to refer to the processor 1212 and the processor 1222 can refer to any of the processor 1212 and the processor 1222 in accordance with the present disclosure, have multiple processors in some implementations and a single processor in other implementations. In another aspect, anyone can use the processor 1212 and the processor 1222 be implemented in the form of hardware (and optionally firmware) with electronic components, which for example and without limitation include one or more transistors, one or more diodes, one or more capacitors, one or more resistors, one or more inductors, one or more memristors and / or have one or more varactors configured and arranged to achieve certain purposes in accordance with the present disclosure. In other words, in at least some implementations, each is the processor 1212 and the processor 1222 describe a special purpose machine specifically designed, engineered, and configured to perform specific tasks including those involving extremely high coding rates for next generation WLAN systems in accordance with various implementations of the present disclosure.

In some implementations, the device can 1210 also a transceiver 1216 having that with the processor 1212 connected is. The transceiver 1216 may have a transmitter that is suitable for wirelessly transmitting data and a receiver that is suitable for wirelessly receiving data. In some implementations, the device can 1220 also a transceiver 1226 having that with the processor 1222 connected is. The transceiver 1226 may have a transmitter that is suitable for wirelessly transmitting data and a receiver that is suitable for wirelessly receiving data. It is noteworthy that although the transceiver 1216 and the transceiver 1226 are shown as each external to and separate from the processor 1212 and the processor 1222 In some implementations, the transceiver is an integral part of the processor 1212 as a system on a chip (SoC) and / or the transceiver 1226 an integral part of the processor 1222 than a SoC can be.

In some implementations, the device can 1210 further a memory 1214 having that with the processor 1212 connected and suitable is that the processor 1212 accesses it and to store data in it. In some implementations, the device can 1220 further a memory 1224 having that with the processor 1222 connected and suitable is that the processor 1222 accesses it and to store data in it. Everyone of the store 1214 and memory 1224 may include some type of random access memory (RAM) such as dynamic RAM (DRAM), static RAM (SRAM), thyristor RAM (T-RAM), and / or zero capacitor RAM (Z-RAM). Alternatively or in addition, each of the memory 1214 and memory 1224 comprise some type of read-only memory (ROM) such as mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM) and / or electrically erasable programmable ROM (EEPROM). Alternatively or in addition, each of the memory 1214 and memory 1224 some type of non-volatile random access memory (NVRAM), such as flash memory, solid-state memory, ferroelectric RAM (FeRAM), magnetoresistive RAM (MRAM) and / or phase change memory.

Each of the device 1210 and the device 1220 may be a communication unit capable of using various to communicate with one another according to the proposed schemes according to the present disclosure. For illustrative purposes and without limitation, the following is a description of the possibilities of the device 1210 as an STA 110 and the device 1220 as an AP 120 provided. It is worth noting that, although the following is a detailed description of the possibilities, functionalities and / or technical features of the device 1210 is provided, the same on the device 1220 may be applied, although a detailed description thereof is not provided for the sake of brevity. It is also noteworthy that although the example implementations described below are provided in the context of a WLAN, the same can be implemented in other types of networks.

In a proposed scheme involving extremely high coding rates for next generation WLAN systems, according to the present disclosure, with the apparatus 1210 who are in or as the STA 110 is implemented, and the device 1220 that in or as the AP 120 is implemented in a network environment 100 can the processor 1212 the device 1210 Encode input data at a first encoding rate using codes designed to be encoded up to a second encoding rate that is lower than the first encoding rate to provide encoded data. In addition, the processor 1212 the encoded data via the transceiver 1216 send wirelessly (e.g. to the device 1220 than the AP 120 ).

In some implementations, when encoding the input data at the first encoding rate using codes designed to encode up to a second encoding rate, the processor may 1212 encode the input data at a rate higher than 5/6 using LDPC codes defined in one of the IEEE 802.11n / ac / ax standards using 4096-QAM. The processor can also transmit the coded data wirelessly 1212 send the encoded data wirelessly with a transmit beam shaping.

In some implementations, the second coding rate can be 5/6 and the first coding rate can be a rate higher than 5/6. For example, the first coding rate can be 6/7, 7/8, 8/9, 9/10, 10/11 or 11/12.

In some implementations, when the input data is encoded, the processor 1212 perform certain operations. For example, the processor can 1212 perform a truncation procedure on the input data to generate a bit sequence comprising a plurality of data bits of the input data, one or more predetermined truncated bits, and a plurality of truncation bits calculated by the truncation process. In addition, the processor 1212 generate a plurality of parity bits based on the bit sequence. The processor can continue 1212 append the parity bits to the bit sequence in order to provide a concatenated bit sequence. The processor can continue 1212 discard the one or more predetermined shortened bits and the plurality of shortened bits from the concatenated bit sequence to provide a shortened bit sequence. Then the processor can 1212 either: (a) perform a puncturing procedure on the truncated bit string; or (b) execute a retry procedure on the shortened bit sequence.

In some implementations, when performing the truncation procedure, the processor 1212 calculate a number of total shortening bits (N _shrt ) of the plurality of shortening bits as follows: N _shrt = max (0, N _CW XL _LDPC × R) - N _pld ). Here Ncw can indicate a number of LDPC code words, L _LDPC can indicate a length of an LDPC code word, R can indicate the first coding rate, which is 7/8 or 11/12, and N _pld can indicate a number of bits in a PSDU and a SERVICE field.

In some implementations, a value of the number of predetermined shortened bits (N shrt_default) can be added to the first coding rate (R), a respective information _{block length (} K0 ), a respective code word block length (L), a respective length of the parity bits (P), so that: (a) for R = 7/8, K0 = 539, L = 616 and P = 77 N _{shrt_default} = 1; (b) for R = 7/8, K0 = 1078, L = 1232 and P = 154, N _{shrt_default} = 2; (c) for R = 7/8, K0 = 1617, L = 1848 and P = 231, N _{shrt_default} = 3; (d) for R = 11/12, K0 = 539, L = 588 and P = 49, N _{shrt_default} = 1; (e) for R = 11/12, K0 = 1078, L = 1176 and P = 98, N _{shrt_default} = 2; and (f) for R = 11/12, K0 = 1617, L = 1764 and P = 147 N _{shrt_default} = 3.

In some implementations, when performing the puncturing procedure, the processor 1212 perform certain operations. For example, the processor can 1212 calculate a number of total punctured bits. The processor can continue 1212 either: (a) in response to the determination that the number of total punctured bits is greater than zero, puncturing a first number of bits of the parity bits; or (b) in response to determining that the number of total punctured bits is zero and a number of repeated bits per codeword is greater than a number of predetermined punctured bits, puncturing a second number of bits of the parity bits. In such cases, the first number of the number of predetermined punctured bits plus a number of punctured bits per Same code word. In addition, the second number can be the same as the number of predetermined punctured bits minus the number of repeated bits per code word.

In some implementations, a value of the number of predetermined punctured bits (N punc_default) can be added to the first coding rate (R), a respective information _{block length (} K0 ), a respective code word block length (L), a respective length of the parity bits (P), so that: (a) for R = 7/8, K0 = 539, L = 616 and P = 77 N _{punc_default} = 31; (b) for R = 7/8, K0 = 1078, L = 1232 and P = 154, N _{punc_default} = 62; (c) for R = 7/8, K0 = 1617, L = 1848 and P = 231, N _{punc_default} = 93; (d) for R = 11/12, K0 = 539, L = 588 and P = 49, N _{punc_default} = 59; (e) for R = 11/12, K0 = 1078, L = 1176 and P = 98, N _{punc_default} = 118; and (f) for R = 11/12, K0 = 1617, L = 1764 and P = 147, N _{punc_default} = 177.

In some implementations, when performing the puncturing procedure, the processor 1212 perform additional operations. For example, the processor can 1212 determine the number of punctured bits per code word (N _ppcw ) based on the number of total punctured bits. In such cases, in calculating the number of total punctured bits, the processor 1212 calculate the number of total punctured bits (N _punc ) as follows: N _punc = max (0, (N _CW × L _LDPC ) - N _avbits - N _shrt ). Here, N _CW can indicate a number of LDPC code words, L _LDPC can indicate a length of an LDPC code word, N _avbits can indicate a number of available bits, and N _shrt can indicate a number of total shortening bits.

In some implementations, when the retry procedure is performed, the processor 1212 perform certain operations. For example, the processor can 1212 calculate a number of total repeated bits. In addition, the processor 1212 in response to a number of total punctured bits being equal to zero and a number of predetermined punctured bits being less than a number of repeated bits per code word, appending the total repeated bits to the parity bits.

In some implementations, when calculating the number of total repeated bits, the processor 1212 calculate the number of total repeated bits (N _rep ) as follows: N _rep = max (0, N _avbits - N _CW XL _LDPC × (1 - R) - N _pld ). Here N _avbits can indicate a number of available bits, N _CW can indicate a number of LDPC code words, L _LDPC can indicate a length of an LDPC code word, R can indicate the first coding rate, which is 7/8 or 11/12, and N _pld can identify a number of bits in a PSDU and a SERVICE field.

In some implementations, in response to a number of total punctured bits (N _punc ) being greater than or equal to zero, the processor may perform the puncturing procedure 1212 carry out continuous puncturing on the shortened bit sequence by discarding the last N _{punc_default} + N _ppcw bits of the parity bits. Here N _{punc_default} can identify a number of predetermined punctured bits and N _ppcw can identify a number of punctured bits per code word.

In some implementations, in response to a total punctured bit number (N _punc ) being greater than zero, the processor may perform the puncturing procedure 1212 _perform an interleaved puncturing on the shortened bit sequence by first discarding N punc_default bits of the parity bits in an interleaved manner and then discarding the last N _ppcw bits of the remaining bits of the parity bits. Here N _{punc_default} can identify a number of predetermined punctured bits and N _ppcw can identify a number of punctured bits per code word.

In some implementations, if the N _{punc_default} bits of the parity bits are discarded in the interleaved manner, the processor 1212 discard one bit for every three bits of the parity bits in response to the first coding rate being 7/8. Alternatively, the processor 1212 discard one bit for every two bits of the parity bits in response to the first coding rate being 11/12.

In some implementations, when the input data is encoded at the first encoding rate, the processor 1212 encode the input data at a coding rate of 7/8 with an MCS index of 14 and using 4096 QAM.

In some implementations, when the input data is encoded at the first encoding rate, the processor 1212 encode the input data at a coding rate of 11/12 with an MCS index of 14 or 15 and using 4096 QAM.

In some implementations, when the input data is encoded at the first encoding rate, the processor 1212 the input data at a coding rate of 7/8 with an MCS index of 16 and using 4096 QAM encode. Corresponding EHT-MCS bits can also be used 0000 exhibit.

In some implementations, when the input data is encoded at the first encoding rate, the processor 1212 encode the input data at a coding rate of 11/12 with an MCS index of 17 and using 4096 QAM. Corresponding EHT-MCS bits can also be used 0001 exhibit.

In some implementations, the processor can 1212 also via the transceiver 1216 to a station (e.g. the device 1220 than the AP 120 ) in a WLAN to indicate support of the first coding rate with 4096-QAM by displaying "11" in a scope of services field.

Explanatory processes

13th provides an example process 1300 according to an implementation of the present disclosure. The process 1300 may represent an aspect of implementing various proposed designs, concepts, schemes, systems, and methods described above. In particular, the process 1300 represent an aspect of the proposed concepts and schemes that relate to extremely high coding rates for next generation WLAN systems in accordance with the present disclosure. The process 1300 may include one or more operations, actions, or functions, such as by one or more of the blocks 1310 and 1320 shown. Although they are shown as individual blocks, the process can be different blocks 1300 Depending on the desired implementation, subdivided into additional blocks, combined into fewer blocks or eliminated. The blocks / sub-blocks of the process 1300 in the in 13th sequence shown or, alternatively, can be carried out in a different sequence. Next, one or more of the blocks / sub-blocks of the process 1300 executed repeatedly or iteratively. The process 1300 can be done both by or in the device 1210 and by or in the device 1220 as well as variations thereof can be implemented. The process is for illustrative purposes only and without limiting the scope of protection 1300 below in the context of the device 1210 who are in or as the STA 110 is implemented, and the device 1220 that in or as the AP 120 is implemented, a radio network, such as a WLAN in a network environment 100 according to one or more of the IEEE 820.11 Standards. The process 1300 can at the block 1310 start.

At 1310 can the process 1300 involve that the processor 1212 the device 1210 Input data at a first encoding rate using codes designed to be encoded up to a second encoding rate that is less than the first encoding rate, encoded to provide encoded data. The process 1300 can continue from 1310 to 1320.

At 1320 can the process 1300 involve that the processor 1212 the encoded data via the transceiver 1216 sends wirelessly (e.g. to the device 1220 than the AP 120 ).

In some implementations, when encoding the input data at the first encoding rate using codes that are designed to encode up to a second encoding rate, the process may 1300 involve that the processor 1212 the input data is encoded at a rate higher than 5/6 using LDPC codes defined in one of the IEEE 802.11n / ac / ax standards using 4096-QAM. In the case of a wireless transmission of the encoded data, the process 1300 involve that the processor 1212 sends the coded data wirelessly with a transmit beam shaping.

In some implementations, the second coding rate can be 5/6 and the first coding rate can be a rate higher than 5/6. For example, the first coding rate can be 6/7, 7/8, 8/9, 9/10, 10/11 or 11/12.

In some implementations, when the input data is encoded, the process 1300 involve that the processor 1212 performs certain operations. For example, the process can 1300 involve that the processor 1212 executes a truncation procedure on the input data to provide a bit sequence that provides a plurality of data bits of the input data, one or more predetermined truncated bits, and a plurality of truncation bits calculated by the truncation process. Additionally, the process can 1300 involve that the processor 1212 a plurality of parity bits is generated based on the bit sequence. The process can continue 1300 involve that the processor 1212 appends the parity bits to the bit sequence in order to provide a concatenated bit sequence. The process can continue 1300 involve that the processor 1212 which discards the one or more predetermined shortened bits and the plurality of shortened bits from the concatenated bit sequence to provide a shortened bit sequence. Then the process can 1300 involve that the processor 1212 either: (a) perform a puncturing procedure on the truncated bit string; or (b) carries out a retry procedure on the shortened bit sequence.

In some implementations, when performing the truncation procedure, the process 1300 involve that the processor 1212 calculates a number of total shortening bits (N _shrt ) of the plurality of shortening bits as follows: N _shrt = max (0, N _CW XL _LDPC × R) - N _pld ). Here, N _CW can identify a number of LDPC code words, L _LDPC can identify a length of an LDPC code word, R can identify the first coding rate which is 7/8 or 11/12, and N _pld can indicate a number of bits in a PSDU and a SERVICE field.

In some implementations, a value of the number of predetermined shortened bits (N shrt_default) can be added to the first coding rate (R), a respective information _{block length (} K0 ), a respective code word block length (L), a respective length of the parity bits (P), so that: (a) for R = 7/8, K0 = 539, L = 616 and P = 77 N _{shrt_default} = 1; (b) for R = 7/8, K0 = 1078, L = 1232 and P = 154, N _{shrt_default} = 2; (c) for R = 7/8, K0 = 1617, L = 1848 and P = 231, N _{shrt_default} = 3; (d) for R = 11/12, K0 = 539, L = 588 and P = 49, N _{shrt_default} = 1; (e) for R = 11/12, K0 = 1078, L = 1176 and P = 98, N _{shrt_default} = 2; and (f) for R = 11/12, K0 = 1617, L = 1764 and P = 147 N _{shrt_default} = 3.

In some implementations, when performing the puncturing procedure, the process 1300 involve that the processor 1212 performs certain operations. For example, the process can 1300 involve that the processor 1212 calculates a number of total punctured bits. The process can continue 1300 involve that the processor 1212 either: (a) in response to determining that the number of total punctured bits is greater than zero, punctures a first number of bits of the parity bits; or (b) in response to determining that the number of total punctured bits is zero and a number of repeated bits per codeword is greater than a number of predetermined punctured bits, punctures a second number of bits of the parity bits. In such cases, the first number can equal the number of predetermined punctured bits plus a number of punctured bits per code word. In addition, the second number can be the same as the number of predetermined punctured bits minus the number of repeated bits per code word.

In some implementations, a value of the number of predetermined punctured bits (N punc_default) can be added to the first coding rate (R), a respective information _{block length (} K0 ), a respective code word block length (L), a respective length of the parity bits (P), so that: (a) for R = 7/8, K0 = 539, L = 616 and P = 77 N _{punc_default} = 31; (b) for R = 7/8, KO = 1078, L = 1232 and P = 154, N _{punc_default} = 62; (c) for R = 7/8, K0 = 1617, L = 1848 and P = 231, N _{punc_default} = 93; (d) for R = 11/12, K0 = 539, L = 588 and P = 49, N _{punc_default} = 59; (e) for R = 11/12, K0 = 1078, L = 1176 and P = 98, N _{punc_default} = 118; and (f) for R = 11/12, K0 = 1617, L = 1764 and P = 147, N _{punc_default} = 177.

In some implementations, when performing the puncturing procedure, the process 1300 involve that the processor 1212 perform additional operations. For example, the process can 1300 involve that the processor 1212 determines the number of punctured bits per code word (N _ppcw ) based on the number of total punctured bits. In such cases, in calculating the number of total punctured bits, the process 1300 involve that the processor 1212 the number of total punctured bits (N _punc ) is calculated as follows: N _punc = max (0, (N _CW × L _LDPC ) - N _avbits - N _shrt ). Here, N _CW can indicate a number of LDPC code words, L _LDPC can indicate a length of an LDPC code word, N _avbits can indicate a number of available bits, and N _shrt can indicate a number of total shortening bits.

In some implementations, when the retry procedure is performed, the process 1300 involve that the processor 1212 performs certain operations. For example, the process can 1300 involve that the processor 1212 calculates a number of total repeated bits. Additionally, the process can 1300 involve that the processor 1212 in response to a number of total punctured bits being equal to zero and a number of predetermined punctured bits being less than a number of repeated bits per code word, appending the total of repeated bits to the parity bits.

In some implementations, when calculating the number of total repeated bits, the process 1300 involve that the processor 1212 the number of total repeated bits (N _rep ) is calculated as follows: N _rep = max (0, N _avbits - N _CW XL _LDPC × (1 - R) - N _pld ). Here N _avbits can indicate a number of available bits, N _CW can indicate a number of LDPC code words, L _LDPC can indicate a length of an LDPC code word, R can indicate the first coding rate, which is 7/8 or 11/12, and N _pld can identify a number of bits in a PSDU and a SERVICE field.

In some implementations, when performing the puncturing procedure in response to a number of total punctured bits (N _punc ) being greater than or equal to zero, the process may 1300 involve that the processor 1212 carries out continuous puncturing by discarding the last N _{punc_default} + N _ppcw bits of the parity bits on the shortened bit sequence. Here N _{punc_default} can identify a number of predetermined punctured bits and N _ppcw can identify a number of punctured bits per code word.

In some implementations, when performing the puncturing procedure in response to a total punctured bit number (N _punc ) being greater than zero, the process may 1300 involve that the processor 1212 nested puncturing by first discarding N _{punc_default} Bits of the parity bits in an interleaved manner and then discarding last N _ppcw bits of remaining bits of the parity bits on the truncated bit sequence. Here N _{punc_default} can identify a number of predetermined punctured bits and N _ppcw can identify a number of punctured bits per code word.

In some implementations, if the N _{punc_default} bits of the parity bits are discarded in the interleaved manner, the process 1300 involve that the processor 1212 discards one bit for every three bits of the parity bits in response to the first coding rate being 7/8. Alternatively, the process can 1300 involve that the processor 1212 discards one bit for every two bits of the parity bits in response to the first coding rate being 11/12.

In some implementations, when encoding the input data at the first encoding rate, the process 1300 involve that the processor 1212 the input data is encoded at a coding rate of 7/8 with an MCS index of 14 and using 4096 QAM.

In some implementations, when encoding the input data at the first encoding rate, the process 1300 involve that the processor 1212 the input data is encoded at a coding rate of 11/12 with an MCS index of 14 or 15 and using 4096 QAM.

In some implementations, when encoding the input data at the first encoding rate, the process 1300 involve that the processor 1212 the input data is encoded at a coding rate of 7/8 with an MCS index of 16 and using 4096 QAM. Corresponding EHT-MCS bits can also be used 0000 exhibit.

In some implementations, when encoding the input data at the first encoding rate, the process 1300 involve that the processor 1212 the input data is encoded at a coding rate of 11/12 with an MCS index of 17 and using 4096 QAM. Corresponding EHT-MCS bits can also be used 0001 exhibit.

In some implementations, the process 1300 further involve that the processor 1212 via the transceiver 1216 to a station (e.g. the device 1220 than the AP 120 ) in a WLAN to indicate support of the first coding rate with 4096-QAM by displaying "11" in a scope of services field.

additional comments

The subject matter described herein sometimes presents different components included in or connected to various other components. It should be understood that such illustrated architectures are only examples, and in fact many other architectures can be implemented that achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "connected" so that the desired functionality is achieved. Therefore, two components that are combined here to achieve a particular functionality can be viewed as “linked together” so that the desired functionality is achieved, regardless of architectures or intermediate components. Similarly, two components linked in this way can also be viewed as "operably linked" or "operably coupled" to each other in order to achieve the desired functionality, and two components that are capable of being linked in this way can also be viewed as "operably coupled" so that they achieve the desired functionality. Specific examples of operably connectable include, but are not limited to, physically connectable and / or physically interacting components and / or wirelessly operable and / or wirelessly interacting components and / or logically interacting and / or logically operable components.

Further, those skilled in the art of using substantially any plural and / or singular terms may translate herein from plural to singular and / or singular to plural as is appropriate for the context and / or application . The various singular / plural permutations can be expressly set forth here for the sake of clarity.

Furthermore, it is understood by those with knowledge in the field that in general terms that are used here and specifically in the appended claims, e.g. the features of the appended claims, are generally intended as "open" terms, e.g. the term "including" should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least”, the term “comprising” should be interpreted as “including but not limited to,” etc. It is further defined by those having a knowledge of the field understood that when a certain number of an introduced claim recitation is intended, such intention is explicitly recited in the claim, and in the absence of such a recitation there is no such intention. For example, as an aid to understanding, the following appended claims may have use of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such language should not be taken as implicit in the sense that the introduction of a claim recitation by the indefinite article “a” restricts a particular claim that has such introduced claim recitation to implementations that have only one such recitation, even if the same Claim has the introductory wording “one or more” or “at least one” and indefinite articles such as “a”, eg “a” should be interpreted to mean “at least one” or “one or more”; the same is true of the use of certain articles used to introduce claim recitations. In addition, even if a certain number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such a recitation should be interpreted as meaning at least the number being recited, e.g., the mere recitation of "two recitations" means without other attributes, at least two recitations or two or more recitations. Furthermore, in those cases in which a statement is used analogously to "at least one of A, B and C, etc.", such a construct is generally intended in the sense that someone with knowledge of the field would understand the statement, e.g. “A system has at least one of A, B and C” would include but not be limited to systems that only A, only B, only C, A and B together, A and C together, B and C together and / or A, B and C together, etc. In those cases in which a statement is used analogously to "at least one of A, B or C, etc.", such a construct is generally intended in the sense of someone with knowledge in the field would understand the statement, e.g., “a system that has at least one of A, B, or C” would include, but is not limited to, systems that have only A, only B, only C, A and B together, A and C together, B and C together, and / or A, B and C together, etc. It is further described by those with K As is understood in the art, nearly any separating word and / or phrase that presents two or more alternative terms, whether in the description, claims or drawings, should be understood to include the possibility of including one does not consider one of the terms, or both terms. For example, the phrase “A or B” is understood to encompass the options “A” or “B” or “A and B”.

From the foregoing, it will be appreciated that various implementations of the present disclosure have been described herein for purposes of illustration, and that various modifications can be made without departing from the scope of the present disclosure. Accordingly, the various implementations disclosed herein are not intended to be limiting, with the true scope of protection indicated by the following claims.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 62951189 [0001]

Claims (15)

Method comprising: Encoding input data at a first encoding rate using codes designed to be encoded up to a second encoding rate that is lower than the first encoding rate to provide encoded data (1310); and wireless transmission of the encoded data (1320). Procedure according to Claim 1 wherein the coding of the input data at the first coding rate using codes which are designed for coding up to a second coding rate, coding of the input data at a rate higher than 5/6 using low-density parity check , hereinafter also referred to as LDPC, includes codes that are defined in one of Institute-of-Electrical-and-Electronics-Engineers, hereinafter also referred to as IEEE, 802.11n / ac / ax standards, using 4096 quadrature -Amplitude modulation, hereinafter also referred to as 4096-QAM, and wherein the wireless transmission of the coded data comprises a wireless transmission of the coded data with a transmission beam shaping. Procedure according to Claim 1 or 2 wherein the second coding rate is 5/6, and wherein the first coding rate comprises a rate higher than 5/6; and / or wherein the first coding rate is 6/7, 7/8, 8/9, 9/10, 10/11 or 11/12. Method according to one of the Claims 1 to 3 wherein encoding the input data comprises: performing a truncation procedure on the input data to provide a bit sequence comprising a plurality of data bits of the input data, one or more predetermined truncated bits, and a plurality of truncation bits calculated by the truncation process; Generating a plurality of parity bits based on the bit sequence; Appending the parity bits to the bit string to provide a concatenated bit string; Discarding the one or more predetermined shortened bits and the plurality of shortened bits from the concatenated bit sequence to provide a shortened bit sequence; and either: performing a puncturing procedure on the truncated bit sequence; or performing a repetition procedure on the shortened bit sequence. Procedure according to Claim 4 , wherein the execution of the shortening procedure comprises calculating a number of total shortening bits, hereinafter also referred to as N _shrt , of the plurality of shortening bits as follows: $$N_{sHrt}=\text{Max}\left(\mathrm{0,}\left(N_{\mathrm{C.}\mathrm{W.}}\times {\mathrm{L.}}_{\mathrm{L.}\mathrm{D.}\mathrm{P.}\mathrm{C.}}\times \mathrm{R.}\right)-N_{pld}\right),$$

where: N _CW denotes a number of LDPC code words, L _LDPC denotes a length of an LDPC code word, R denotes the first coding rate, which is 7/8 or 11/12, and N _pld a number of bits in a physical layer -Convergence Protocol, hereinafter also referred to as PLCP, service data unit, hereinafter also referred to as PSDU, and a SERVICE field. Procedure according to Claim 5 , where a value of the number of predetermined shortened bits, hereinafter also referred to as N _{shrt_default, to R, a respective information block length} , hereinafter also referred to as K0, a respective code word block length, hereinafter also referred to as L, a respective length of the parity bits , hereinafter also referred to as P, corresponds, so that: for R = 7/8, K0 = 539, L = 616 and P = 77 N _{shrt_default} = 1; for R = 7/8, K0 = 1078, L = 1232 and P = 154 N _{shrt_default} = 2; for R = 7/8, K0 = 1617, L = 1848 and P = 231 N _{shrt_default} = 3; for R = 11/12, K0 = 539, L = 588 and P = 49 N _{shrt_default} = 1; for R = 11/12, K0 = 1078, L = 1176 and P = 98 N _{shrt_default} = 2; and for R = 11/12, K0 = 1617, L = 1764 and P = 147 N _{shrt_default} = 3. Method according to one of the Claims 4 to 6th wherein performing the puncturing procedure comprises: computing a number of total punctured bits; and either: puncturing a first number of bits of the parity bits in response to determining that the number of total punctured bits is greater than zero; or puncturing a second number of bits of the parity bits in response to determining that the number of total punctured bits is equal to zero and a number of repeated bits per code word is greater than a number of predetermined punctured bits, the first number of the number of predetermined punctured bits plus a number of punctured bits per code word equals, and wherein the second number equals the number of predetermined punctured bits minus the number of repeated bits per code word. Procedure according to Claim 7 , where a value of the number of predetermined punctured bits, im Also referred to below as N _{punc_default} , corresponds to R, K0, L, P, so that: for R = 7/8, K0 = 539, L = 616 and P = 77, N _{punc_default} = 31; for R = 7/8, K0 = 1078, L = 1232 and P = 154, N _{punc_default} = 62; for R = 7/8, K0 = 1617, L = 1848 and P = 231 N _{punc_default} = 93; for R = 11/12, K0 = 539, L = 588 and P = 49, N _{punc_default} = 59; for R = 11/12, K0 = 1078, L = 1176 and P = 98, N _{punc_default} = 118; and for R = 11/12, K0 = 1617, L = 1764 and P = 147, N _{punc_default} = 177. Procedure according to Claim 7 or 8th , wherein executing the puncturing procedure further comprises: determining the number of punctured bits per code word, hereinafter also referred to as N _ppcw , based on the number of total punctured bits, wherein calculating the number of total punctured bits comprises calculating the number of total punctured bits, im Also referred to below as N _punc , includes as follows: $$N_{punc}=\text{Max}\left(\mathrm{0,}\left(N_{\mathrm{C.}\mathrm{W.}}\times {\mathrm{L.}}_{\mathrm{L.}\mathrm{D.}\mathrm{P.}\mathrm{C.}}\right)-N_{avbits}-N_{sHrt}\right),$$

where: N _CW indicates a number of LDPC code words, L _LDPC indicates a length of an LDPC code word, N _{avbits indicates} a number of available bits, and N _{shrt indicates} a number of total shortening bits. Method according to one of the Claims 4 to 9 wherein performing the iteration procedure comprises: computing a number of total repeated bits; and appending the total repeated bits to the parity bits in response to a number of total punctured bits being equal to zero and a number of predetermined punctured bits being less than a number of repeated bits per code word. Procedure according to Claim 10 , wherein calculating the number of total repeated bits comprises calculating the number of total repeated bits, hereinafter also referred to as N _rep , as follows: $$N_{rep}=\text{Max}\left(\mathrm{0,}{N}_{avbits}-N_{\mathrm{C.}\mathrm{W.}}\times {\mathrm{L.}}_{\mathrm{L.}\mathrm{D.}\mathrm{P.}\mathrm{C.}}\times \left(1-\mathrm{R.}\right)-N_{pid}\right),$$

where: N _{avbits denotes} a number of available bits, N _CW denotes a number of LDPC code words, L _LDPC denotes a length of an LDPC code word, R denotes the first coding rate, which is 7/8 or 11/12, and N _pld one Identifies the number of bits in a PLCP-PSDU and a SERVICE field. Method according to one of the Claims 4 to 11 _{wherein performing the puncturing procedure comprises} performing continuous puncturing on the truncated bit sequence by discarding last N punc_default + N _ppcw bits of the parity bits in response to N _{punc being} greater than or equal to zero. Method according to one of the Claims 4 to 11 , wherein the execution of the puncturing procedure includes performing an interleaved puncturing on the shortened bit sequence by first discarding N _{punc_default} bits of the parity bits in an interleaved manner and then discarding the last N _ppcw bits of remaining bits of the parity bits in response thereto that N _{punc is} greater than zero; preferably discarding the N _{punc_default} bits of the parity bits in an interleaved manner comprising: discarding one bit for every three bits of the parity bits in response to the coding rate being 7/8; or discarding one bit for every two bits of the parity bits in response to the first coding rate being 11/12. Method according to one of the Claims 1 to 13th wherein the coding of the input data at the first coding rate comprises coding the input data at a coding rate of 7/8 with a modulation and coding scheme, hereinafter also referred to as MCS, index of 14 and using 4096-QAM; or wherein encoding the input data at the first encoding rate comprises encoding the input data at an encoding rate of 11/12 with an MCS index of 14 or 15 and using 4096-QAM; or wherein the coding of the input data at the first coding rate comprises coding the input data at a coding rate of 7/8 with an MCS index of 16 and using 4096-QAM, and corresponding extremely high throughput, hereinafter also designated as EHT, have MCS bits 0000; or wherein coding the input data at the first coding rate comprises coding the input data at a coding rate of 11/12 with an MCS index of 17 and using 4096-QAM, and wherein corresponding EHT-MCS bits have 0001. Method according to one of the Claims 1 to 14th , further comprising: signaling to a station in a local radio network, also referred to below as WLAN, in order to indicate support for the first coding rate with 4096-QAM by displaying “11” in a scope of services field.

Images