DE102020133339A1 - CMOS STACK STRUCTURE - Google Patents

Abstract

A semiconductor structure includes: an operating voltage line; a first source/drain element disposed over the power supply line; a via connecting the power supply line to the first source/drain element; an isolation element disposed over the first source/drain element; and a second source/drain element disposed over the isolation element, the first and second source/drain elements having opposite conductivity types.

Description

priority claim

The present application claims priority to US provisional patent application filed on May 20, 2020 with the docket number 63/027.811 , which is incorporated by reference into the present application.

background

Conventionally, CMOS (CMOS: Complementary Metal Oxide Semiconductor) devices in integrated circuits (ICs) are formed by a pair of an NMOS transistor and a PMOS transistor arranged side by side. As the integration density of devices continues to increase, miniaturization of such structures has become more difficult in some cases. While existing approaches to semiconductor fabrication have by and large been adequate for their intended purposes, they have not been entirely satisfactory in every respect.

character list

• Die 1A, 1C, 1E, 1H und 1J zeigen schematische Darstellungen einiger beispielhafter Schaltkreise, die von verschiedenen Aspekten der vorliegenden Erfindung profitieren.
• Die 1B, 1D, 1F, 1G, 1I und 1K zeigen Schaltkreise und Vorrichtungen, die gemäß verschiedenen Aspekten der vorliegenden Erfindung konfiguriert sind.
• Die 2A, 2B, 2C und 2D zeigen ein Ablaufdiagramm eines Verfahrens zum Herstellen einer Halbleitervorrichtung gemäß verschiedenen Aspekten der vorliegenden Erfindung.
• Die 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12 und 22A zeigen Draufsichten eines Teils einer Halbleitervorrichtung gemäß einigen Ausführungsformen.
• Die 3, 4B, 5B, 5C, 6B, 6C, 6D, 7B, 7C, 7D, 8B, 8C, 8D, 9B, 9C, 9D, 10B, 10C, 100, 11B, 11C, 11D, 13A-1, 13A-2, 13A-3, 14A-1, 14A-2, 14A-3, 15A-1, 15A-2, 15A-3, 16A-1, 16A-2, 16A-3, 17A-1, 17A-2, 17A-3, 18A-1, 18A-2, 18A-3, 19A-1, 19A-2, 19A-3, 20A-1, 20A-2, 20A-3, 21A-1, 21A-2, 21A-3, 22B, 22C, 23, 24, 25, 26, 27, 28, 29, 30 und 31 zeigen Teil-Schnittansichten einer Halbleitervorrichtung gemäß einigen Ausführungsformen.

The present invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale and are for explanation only. In fact, the dimensions of the various features may be arbitrarily exaggerated or minimized for the sake of clarity of explanation.

• the 1A , 1C , 1E , 1H and 1y 12 show schematic representations of some example circuits that benefit from various aspects of the present invention.
• the 1B , 1D , 1F , 1G , 1I and 1K 10 show circuits and devices configured in accordance with various aspects of the present invention.
• the 2A , 2 B , 2C and 2D 12 shows a flow diagram of a method for manufacturing a semiconductor device according to various aspects of the present invention.
• the 4A , 5A , 6A , 7A , 8A , 9A , 10A , 11A , 12 and 22A 12 show plan views of a portion of a semiconductor device according to some embodiments.
• the 3 , 4B , 5B , 5C , 6B , 6C , 6D , 7B , 7C , 7D , 8B , 8C , 8D , 9B , 9C , 9D , 10B , 10C , 100, 11B , 11C , 11D , 13A-1 , 13A-2 , 13A-3 , 14A-1 , 14A-2 , 14A-3 , 15A-1 , 15A-2 , 15A-3 , 16A-1 , 16A-2 , 16A-3 , 17A-1 , 17A-2 , 17A-3 , 18A-1 , 18A-2 , 18A-3 , 19A-1 , 19A-2 , 19A-3 , 20A-1 , 20A-2 , 20A-3 , 21A-1 , 21A-2 , 21A-3 , 22B , 22C , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 and 31 12 show partial cross-sectional views of a semiconductor device according to some embodiments.

Detailed description

The description below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, fabrication of a first element over or on a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements are formed between the first and can be made with the second element so that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numbers and/or letters may be repeated in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like may be used herein for ease of reference describing the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be oriented differently (rotated 90 degrees or in a different orientation) and the spatially relative descriptors used herein can correspond be interpreted accordingly. Additionally, when a number or range of numbers is described by the terms "about,""approximately," and the like, the term is intended to include numbers that are within certain deviations (such as within ±10% or other values) of number specified are within the knowledge of one skilled in the art of the particular technology disclosed herein, unless otherwise noted. For example, the term "about 5 nm" can encompass the dimensional range of 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, and so on.

The present application relates generally to semiconductor structures and methods of fabrication thereof, and more particularly to semiconductor devices having stacked CMOS transistors. It is an object of the present invention to provide vertically stacked CMOS transistors (or structures) wherein transistors on the bottom of the stack are fed from backside power supply lines and transistors on the top of the stack are fed from front side power supply lines. By using vertically stacked CMOS devices, the area of CMOS circuits is aggressively reduced. For example, the vertically stacked CMOS devices can be used in SRAM, NAND flash, NOR flash, or other circuits. Using front and back power supply lines increases the number of metal lines available in the device for direct connection to sources/drains and gates. This also increases gate density for higher device integration than existing structures. The details of the structures and manufacturing methods of the present invention are described below in conjunction with the accompanying drawings, which show a method of manufacturing a GAA (GAA: Gate-All-Around) device according to some embodiments. A GAA device is a device with vertically stacked, horizontally oriented multi-channel transistors, such as nanowire transistors and nanosheet transistors. GAA devices are strong candidates to take CMOS to the next stage of the roadmap because of their better gate controllability, lower leakage current, and full layout compatibility with FinFET devices. Those skilled in the art should appreciate that they can readily use the present invention as a basis for designing or modifying other methods and structures (such as FinFET devices) to achieve the same goals and/or achieve the same benefits as the embodiments presented herein .

1A Figure 12 shows a latch circuit 30 having two inverters 20 cross-coupled together to form a storage node. Each inverter 20 includes a PMOS transistor (PU1 or PU2) and an NMOS transistor (PD1 or PD2) sharing a common gate and drain. For example, an inverter 20 has a PU1 and a PD1 sharing a common gate and drain, with a source of PU1 connected to a positive power source V _DD and a source of PD1 connected to a negative power source V _SS (or ground) is connected. 1B 12 shows an implementation of the inverter 20 with a CMOS stack structure according to the present invention. In 1B For example, the PMOS transistor PU1 comprises two P-type epitaxially grown semiconductor layers ("P-EPIs") connected via a channel 62, and the NMOS transistor PD1 comprises two N-type epitaxially grown semiconductor layers ("N-EPIs") , which are connected via two channels 62. Channels 62 comprise intrinsic silicon in one embodiment. The N-EPIs are arranged vertically above the P-EPIs. A gate 54 encloses the channels 62 for transistor PU1 and transistor PD1. The P-EPIs and N-EPIs on the left are separated by an insulating material that will be discussed later. The P-EPIs and the N-EPIs on the right are physically and electrically connected together and function as the common drain for transistors PU1 and PD1. The P-EPIs on the left are connected to the positive power source V _DD implemented on a back side of a wafer. The N-EPIs on the left are connected to the negative power source (or ground) V _SS implemented on a front side of the wafer. Basically, the inverter 20 (comprising the transistors PU1 and PD1 stacked vertically) occupies the area of only one transistor, greatly increasing the integration density of the device. In the illustrated embodiment, transistor PD1 is stacked over transistor PU1 (ie, the N-EPIs are stacked over the P-EPIs), and the V _SS and VDD are implemented on the front side and the back side of a wafer, respectively. In another embodiment, transistor PU1 is placed above transistor PD1 (ie, the P-EPIs are placed above the N-EPIs), and the V _SS and VDD are implemented on the backside and the frontside of a wafer, respectively.

1C FIG. 1 shows a high density SRAM cell 40 incorporating a latch circuit 30, which is described with reference to FIG 1A as described, and further comprises two NMOS transistors PG1 and PG2 implemented as pass gate transistors. Gates of PG1 and PG2 are connected to a word line WL, while sources (or drains) of PG1 and PG2 are connected to bit lines BL and /BL (or BLB). 1D 12 shows a layout diagram of certain structural elements of SRAM cell 40. The layout includes: active areas 52 (channels and sources/drains of transistors) oriented longitudinally along the x-direction; gates 54 and source/drain (S/D) contacts 56 oriented longitudinally along the y-direction; and jumper connectors 58 connecting some of the gates 54 to some of the S/D contacts 56. FIG. The dashed box in 1D Figure 12 shows the layout of the latch circuit 30 comprising the transistors PU1, PU2, PD1 and PD2 (which form the two inverters 20). As referring to 1B As set forth above, in one embodiment of the present invention, transistor PD1 is placed above transistor PU1 and transistor PD2 is placed above transistor PU2. A length of SRAM cell 40 along the y-direction is only three widths of active area 52. In approaches where transistors PU1, PU2, PD1 and PD2 are implemented on the same wafer level (ie, not on top of each other), the length would be of the SRAM cell 40 along the y-direction are four widths of the active area 52. Thus, by stacking the transistors in accordance with the present invention (e.g., placing PD1 over PU1 and PD2 over PU2), the SRAM cell 40 achieves a 25% reduction in its footprint. In other words, the integration density of the SRAM cell 40 increases by 25% over other approaches.

1E FIG. 1 shows a high current SRAM cell 50 similar to the SRAM cell 40 described with reference to FIG 1C has been described. However, NMOS transistors PD1' and PD2' of SRAM cell 50 may carry a higher current than transistors PD1 and PD2 of SRAM cell 40. In some embodiments, each of the transistors PD1' and PD2' of the SRAM cell 50 is implemented as multiple NMOS transistors connected in parallel. The latch circuit of the SRAM cell 50 is denoted by 30'. 1F shows a layout diagram of certain structural elements of the SRAM cell 50. The dashed box in 1F Figure 12 shows the layout of latch circuit 30', which includes transistors PU1, PU2, PD1' and PD2'. A box 20' corresponds to the layout of one of the inverters, for example the inverter comprising transistors PU1 and PD1'. 1G Figure 12 shows a perspective view of the inverter 20' implemented on a wafer. As in 1G As shown, the inverter 20' is implemented with three transistors, with a first NMOS field effect transistor (or N-FET) on the back side, a second N-FET on the front side, and a PMOS transistor (or P-FET) on the front side. The second N-FET is placed over the P-FET as referred to in FIG 1B has been set out. The two N-FETs are connected in parallel via S/D contacts 56 and share a common gate 54. The N-FETs have N-EPI S/D devices connected by channels 62 and the P-FET has P-EPI-S/D elements connected by channel 62. By using the CMOS stack structure of the present invention, the layout of the SRAM cell 50 ( 1F) uses only four widths of active regions 52, yielding a 20% reduction in their footprint over approaches where all transistors are implemented on the same wafer level (no stacking). In other words, the integration density of the SRAM cell 50 increases by 20% over other approaches.

1H 12 shows a schematic representation of a NAND circuit 60. The NAND circuit 60 has two P-FETs P1 and P2 connected in parallel and two N-FETs N1 and N2 connected in series. Drain terminals of the transistors N1, P1 and P2 are connected to each other. Sources of transistors P1 and P2 are connected to VDD. The source of transistor N2 is connected to V _SS . 1I 12 shows an implementation of the NAND circuit 60 with CMOS stack structures according to the present invention. In 1I each of the transistors P1 and P2 has two P-EPIs connected via a channel 62. FIG. P-EPI drain elements of transistors P1 and P2 are connected via a backside signal line (ie, a metal line implemented on the backside of a wafer). Transistors P1 and P2 share a common P-EPI source element connected to the VDD implemented on the backside of the wafer. Each of the transistors N1 and N2 has two N-EPIs that are connected via two channels 62. FIG. An N-EPI drain of transistor N1 is directly connected to the P-EPI drain of transistor P1. The other N-EPI elements are insulated from the P-EPI elements by an insulating material. An N-EPI source element of transistor N2 is connected to V _SS implemented on the front side of the wafer. Gates 54 enclose channels 62. By stacking transistors N1 and N2 on top of transistors P1 and P2, the wafer footprint of NAND circuit 60 of the present invention is advantageously reduced. At the in 1I In the illustrated embodiment, the NMOS transistors N1 and N2 are arranged above the PMOS transistors P1 and P2. In an alternate embodiment, NAND circuit 60 may be implemented by stacking PMOS transistors P1 and P2 on top of NMOS transistors N1 and N2, implementing V _SS on the back side of a wafer, and implementing V _DD on the front side of the wafer.

1y shows a schematic representation of a NOR circuit 70. The NOR circuit 70 has two P-FETs P1 and P2 connected in series and two N-FETs N1 and N2 connected in parallel. Drain terminals of the transistors P2, N1 and N2 are connected together. The source of transistor P1 is connected to VDD. The sources of transistors N1 and N2 are connected to V _SS . 1K 12 shows an implementation of the NOR circuit 70 with CMOS stack structures according to the present invention. In 1K each of the transistors P1 and P2 has two P-EPIs connected via a channel 62. FIG. The P-EPI source element of transistor P1 is connected to VDD, which is implemented on the back side of the wafer. Transistors P1 and P2 share a common P-EPI source/drain device. Each of the transistors N1 and N2 has two N-EPIs that are connected via two channels 62. FIG. The N-EPI drain of transistor N2 is directly connected to the P-EPI drain of transistor P2. The other N-EPI elements are insulated from the P-EPI elements by an insulating material. The N-EPI drain elements of transistors N1 and N2 are connected together by a signal line implemented on the front side of the wafer. The N-EPI sources of transistors N1 and N2 are shared and connected to the V _SS implemented on the front side of the wafer. Gates 54 enclose channels 62. By stacking transistors N1 and N2 on top of transistors P1 and P2, the wafer footprint of NOR circuit 70 of the present invention is advantageously reduced. At the in 1K In the illustrated embodiment, the NMOS transistors N1 and N2 are arranged above the PMOS transistors P1 and P2. In an alternate embodiment, NOR circuit 70 may be implemented by stacking PMOS transistors P1 and P2 on top of NMOS transistors N1 and N2, implementing V _SS on the back side of a wafer, and implementing V _DD on the front side of the wafer.

the 1A , 1C , 1E , 1H and 1y are non-limiting example circuits that may benefit from the CMOS stack structure of the present invention. In particular, the disclosed inverters, latches, SRAM cells, NAND and NOR circuits are among the building blocks of a CMOS integrated circuit. Those skilled in the art should appreciate that they can readily use the present invention as a basis for designing or modifying other circuits to achieve the same goals and/or obtain the same benefits as the embodiments presented herein, without departing from the scope of the present invention .

the 2A , 2 B , 2C and 2D 12 shows a flow diagram of a method 100 for manufacturing a semiconductor device having a CMOS stacked structure according to various aspects of the present invention. In the present invention, further processing is contemplated. Additional steps may be provided before, during, and after the method 100, and some of the described steps may be moved, substituted, or omitted in other embodiments of the method 100.

The method 100 is described below in connection with the 3 until 31 1, which show various top and cross-sectional views of a semiconductor device (or a semiconductor structure) 200 at various stages of fabrication according to the method 100, according to some embodiments. In some embodiments, device 200 is part or part of an IC chip or system-on-chip (SoC) that includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, P-FETs, N -FETs, FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal oxide semiconductor field effect transistors (MOSFETs), CMOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS transistors), high voltage transistors , high frequency transistors, memory devices, other suitable components, or combinations thereof. the 3 until 31 have been simplified for clarity in order to better understand the inventive concepts of the present invention. Other structural elements may be added to device 200, and some of the structural elements described later may be substituted, modified, or omitted in other embodiments of device 200.

In a step 102, in the method 100 ( 2A) a structure is provided comprising a substrate 201 in or on which various components are fabricated, including semiconductor fins 218, an isolation structure 230, dielectric fins (isolation fins) 229, sacrificial gate stacks (or dummy gate stacks) 240, gate spacers 247, and miscellaneous other components, such as those in the 3 until 5C are shown. These components and the methods of their manufacture are described later with reference to FIG 3 until 5C discussed in more detail.

In 3 For example, a stack 205 of semiconductor layers 210 and 215 is fabricated over a semiconductor layer 204 over a substrate 201. FIG. In one embodiment, substrate 201 is a bulk silicon substrate (ie, comprises bulk single crystal silicon). With different versions In other forms, the substrate 201 may include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AllnAs, AlGaAs, GalnAs, GaInP, or GalnAsP, or combinations thereof. In an alternative embodiment, the substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium- on insulator substrate (GO1 substrate). In some embodiments, the semiconductor layer 204 may be silicon, silicon germanium, germanium, or another suitable semiconductor.

The semiconductor layer stack 205 comprises semiconductor layers 210 and semiconductor layers 215 stacked on top of each other vertically (eg, along the z-direction) in an interleaved or alternating configuration. In some embodiments, semiconductor layers 210 and semiconductor layers 215 are epitaxially grown in the illustrated interleaved and alternating configuration. The epitaxial growth of the semiconductor layers 210 and the semiconductor layers 215 can be performed by Molecular Beam Epitaxy (MBE), Chemical Vapor Deposition (CVD), Metal Organic Chemical Vapor Deposition (MOCVD), any other suitable epitaxial growth method, or combinations thereof. A composition of the semiconductor layers 210 is different from a composition of the semiconductor layers 215 to achieve etch selectivity and/or different oxidation rates during later processing. For example, the semiconductor layers 210 and the semiconductor layers 215 may have different materials, constituent atomic fractions, constituent mass fractions, thicknesses, and/or properties to achieve a desired etch selectivity and/or different oxidation rates. For example, in one embodiment, semiconductor layers 210 may include silicon germanium and semiconductor layers 215 may include silicon. In some embodiments, the semiconductor layers 210 and the semiconductor layers 215 may comprise the same material but with different constituent atomic fractions to achieve etch selectivity and/or different oxidation rates. For example, both the semiconductor layers 210 and the semiconductor layers 215 may comprise silicon germanium, with the semiconductor layers 210 having a first silicon atomic fraction and/or a first germanium atomic fraction and the semiconductor layers 215 having a second, different silicon atomic fraction and/or a second, have a different proportion of germanium atoms. In the present invention, it is contemplated that the semiconductor layers 210 and the semiconductor layers 215 comprise a combination of semiconductor materials that can provide the desired etch selectivity, desired oxidation rate differences, and/or desired performance properties (e.g., materials that optimize current flow). including some of the semiconductor materials disclosed herein.

As will be explained in more detail later, the semiconductor layers 215 or parts thereof form channel regions of the device 200. In the illustrated embodiment, the semiconductor layer stack 205 has three semiconductor layers 210 and three semiconductor layers 215. After the layers have undergone further processing, this configuration results in the device 200 having three channels. However, the present invention contemplates embodiments where, for example, depending on a number of channels desired for the device 200, the semiconductor layer stack 205 has more or fewer semiconductor layers. For example, the semiconductor layer stack 205 may include two to ten semiconductor layers 210 and two to ten semiconductor layers 215 . As will be explained later, in the method 100 layers on both sides of the substrate 201 are processed. In the present invention, the side of the substrate 201 on which the stack 205 is located is referred to as the front side, and the side opposite the front side is referred to as the back side.

4A 12 shows a top view of device 200 with fins 218 oriented along the x-direction, and 4B FIG. 12 shows a partial sectional view of the device 200 along a line BB of FIG 4A . As in 4B As shown, fins 218 include patterned stack 205 (comprising layers 210 and 215), patterned regions 204, and one or more patterned hard mask layers 206. FIG. The fins 218 can be patterned using any suitable method. For example, the fins 218 may be patterned with one or more photolithographic processes, such as double patterning or multiple patterning processes. In general, double-patterning or multi-patterning processes combine photolithographic and self-aligned processes that can create structures that have, for example, grid spacings that are smaller than those that can otherwise be achieved with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is fabricated over the stack 205, which is then patterned with a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers, or mandrels, can then be used as a Masking element for structuring the fins 218 are used. For example, the masking element can be used to etch recesses in the stack 205 and the substrate 201 such that the fins 218 remain on the substrate 201 . The etching process may include a dry etch, a wet etch, a reactive ion etch (RIE), and/or other suitable processes. For a dry etching process, for example, an oxygen-containing gas, a fluorine-containing gas (e.g. CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and/or C ₂ F ₆ ), a chlorine-containing gas (e.g. Cl ₂ , CHCI ₃ , CCI ₄ and/or BCI ₃ ), a bromine-containing gas (e.g. HBr and/or CHBr ₃ ), an iodine-containing gas, other suitable gases and/or plasmas and/or combinations thereof can be used. A wet etch process may include, for example, a dilute hydrofluoric acid (DHF) etch; potassium hydroxide (KOH) solution; Ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO ₃ ) and/or acetic acid (CH ₃ COOH); or in another suitable wet etchant. Numerous other embodiments of methods of manufacturing the fins 218 may be suitable.

5A shows a top view of the device 200, and the 5B and 5C show partial sectional views of the device 200 along a line B - B and a line C - C of FIG 5A . In the 5A , 5B and 5C Various components are fabricated around and/or over the fins 218, including the following: an isolation structure (or isolation element) 230 that isolates a lower portion of the fins 218; a cladding layer 231 over the isolation structure 230 and on sidewalls of the fins 218; dielectric fins (or dummy fins) 229 over isolation structure 230 and on sidewalls of cladding layer 231; sacrificial gate stack 240 over fins 218; and gate spacers 247 on sidewalls of sacrificial gate stacks 240.

In 5C the one or more isolation elements 230 are fabricated over the substrate 201 to isolate various areas of the device 200 . For example, the isolation elements 230 enclose a lower portion of the fins 218 to separate and isolate the fins 218 from each other. The isolation elements 230 include silicon oxide, silicon nitride, silicon oxynitride, other suitable insulating materials (e.g., silicon, oxygen, nitrogen, carbon, or other suitable insulating components), or combinations thereof. The isolation elements 230 may have different structures, such as STI structures (STI: shallow trench isolation) and/or DTI structures (DTI: deep trench isolation). In one embodiment, the isolation elements 230 may be manufactured by: filling trenches between fins 218 with insulating material (e.g., with a CVD process or a spin-on-glass process); performing a CMP (Chemical Mechanical Polishing) process to remove excess insulating material and/or to planarize a top surface of the insulating material layer; and etching back the insulating material layer to form the insulating elements 230. In some embodiments, the isolation elements 230 have a multi-layer structure, such as a silicon nitride layer disposed over a thermal oxide scale layer.

The cladding layer 231 is deposited over the sidewall surfaces of the fins 218 and over the isolation elements 230 . In one embodiment, cladding layer 231 comprises SiGe. The cladding layer 231 may be formed by CVD, physical deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDP-CVD), metal organic chemical vapor deposition (MOCVD), remote plasma CVD (RPCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), or other suitable methods or combinations thereof.

In the present embodiment, the dielectric fin 229 includes a dielectric liner 232 , a dielectric fill layer 233 , and a dielectric cap 234 . Dielectric fin 229 may be configured differently in alternative embodiments. Dielectric liner 232 is deposited over the sidewalls of cladding layer 231 and on tops of insulating members 230, and dielectric fill layer 233 is deposited over dielectric liner 232 and fills gaps between fins 218. In one embodiment, dielectric liner 232 has a dielectric low -k material containing Si, O, N and C, for example. Exemplary low-k dielectric materials are fluorosilicate glass (FSG), carbon-doped silica, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (benzocyclobutene), polyimide, or combinations thereof. Low-k dielectric materials are generally dielectric materials that have a low dielectric constant (k), which is less than about 7, for example. The dielectric film 232 may be deposited by CVD, PVD, ALD, HDP-CVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In one embodiment, the dielectric fill layer 233 comprises silicon oxide, silicon nitride, silicon oxynitride, TEOS oxide (TEOS: tetraethyl orthosilicate), phosphorus silicate glass (PSG), borophosphorus silicate glass (BPSG), a dielectric cal low-k material, another suitable dielectric material, or combinations thereof. The dielectric fill layer 233 may be deposited with an FCVD process (FCVD: flowable CVD), which may involve, for example, depositing a flowable material (such as a liquid compound) over the device 200 and converting the flowable material into a solid material with a suitable methods such as thermal annealing and / or UV irradiation. The dielectric fill layer 233 can also be deposited using other methods.

Dielectric cap 234 is deposited over dielectric layers 232 and 233 and between cladding layers 231 on opposite sidewalls of fins 218 . In one embodiment, the dielectric cap 234 comprises a high-k dielectric material, such as HfO ₂ , HfSiO, HfSiO ₄ , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO _x , ZrO, ZrO ₂ , ZrSiO ₂ , AIO, AlSiO, Al ₂ O ₃ , TiO, TiO ₂ , LaO, LaSiO, Ta ₂ O ₃ , Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ , BaZrO, BaTiO _s (BTO), (Ba,Sr)TiO ₃ ( BST), Si ₃ N ₄ , hafnia-alumina alloy (HfO ₂ -Al ₂ O ₃ alloy), another suitable high-k dielectric material, or combinations thereof. High-k dielectric materials are generally dielectric materials that have a high dielectric constant, e.g., k > 7. The dielectric cap 234 is fabricated using any of the processes mentioned herein, such as ALD, CVD, PVD, an oxidation-based deposition process, other suitable methods or combinations thereof. In one embodiment, dielectric layers 232 and 233 may be recessed with a selective etch process that etches dielectric layers 232 and 233 but leaves hard mask 206 ( 4B) and the cladding layer 231 are not etched or only minimally etched. Then, one or more dielectric materials are deposited into the recesses and a CMP process is performed on the one or more dielectric materials to form the dielectric cap 234 . Next, the hard mask layers 206 are removed and the sacrificial gate stacks 240 are fabricated over the fins 218 .

In 5B sacrificial gate stacks 240 include a dummy gate dielectric layer 235, a dummy gate electrode layer 245, and one or more hard mask layers 246. FIG. In the present embodiment, the sacrificial gate stacks 240 are replaced with functional gate stacks 240' in a later manufacturing step. In some embodiments, dummy gate dielectric layer 235 comprises a dielectric material, such as silicon oxide, a high-k dielectric material, other suitable dielectric materials, or combinations thereof; dummy gate electrode layer 245 comprises polysilicon or other suitable material; and the one or more hard mask layers 246 comprise silicon oxide, silicon nitride, or other suitable materials. The sacrificial gate stacks 240 are fabricated using deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. For example, layers 235, 245, and 246 may be deposited by CVD, PVD, ALD, or other suitable methods. Then a lithographic patterning and etching process is performed to pattern the layers 235, 245 and 246 into the sacrificial gate stacks 240 as shown in FIG 5B is shown. The lithographic patterning processes include resist coating (e.g., spin coating), pre-bake, mask alignment, exposure, post-exposure bake, development of the resist, washing, drying (e.g., post-bake), other suitable lithographic processes, or combinations thereof. The etch processes include dry etch, wet etch, other etch processes, or combinations thereof.

let's stay put 5B . Gate spacers 247 are fabricated on sidewalls of sacrificial gate stacks 240 . The gate spacers 247 are formed using any suitable method and comprise a dielectric material. The dielectric material can be silicon, oxygen, carbon, nitrogen, another suitable material or a combination thereof, e.g. B. silicon oxide, silicon nitride, silicon oxide nitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxide carbide (SiOC) or silicon oxide carbonitride (SiOCN). For example, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, may be deposited over sacrificial gate stacks 240 and then etched (eg, anisotropically) to form gate spacers 247 . In some embodiments, the gate spacers 247 have a multi-layer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some embodiments, more than one set of spacers, such as gasket spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, are fabricated adjacent to the sacrificial gate stacks 240 .

In a step 104, in the method 100 ( 2A) Source/drain trenches 250 created by etching fins 218 adjacent to gate spacers 247 . The resulting structure is in the 6A until 6D shown according to one embodiment. 6A shows a top view of the device 200, and the 6B , 6C and 6D show partial sectional views of the device 200 along a line B - B, a line C - C and a line D - D of 6A . In particular, the line C - C bisects one of the source/drain regions of the transistors and is parallel to the gate stacks 240, and the line D - D bisects other source/drain regions of the transistors and is parallel to the gate stacks 240. The lines C - C and the lines D - D in the 7A until 11A are configured similarly.

In the illustrated embodiment, the semiconductor layer stack 205 in the source/drain regions of the fins 218 is completely removed with an etching process, thereby exposing the semiconductor layer 204 of the fins 218 in the source/drain regions. The source/drain trenches 250 thus have sidewalls formed by remaining parts of the semiconductor layer stack 205 deposited in channel regions under the gate stacks 240 and bottoms defined by the semiconductor layer 204 and the isolation structure 230 . In some embodiments, the etch process partially but not completely removes the semiconductor layer stack 205 such that the source/drain trenches 250 have bottoms defined by the semiconductor layer 210 or the semiconductor layer 215 in the source/drain regions. In some embodiments, the etch process also partially but not completely removes the semiconductor layer 204 of the fins 218 such that the source/drain trenches 250 extend below a top surface of the isolation structure 230 . The etch process may be a dry etch process, a wet etch process, another suitable etch process, or a combination thereof. In some embodiments, the etch process is a multi-step etch process. For example, alternating etchants may be used for the etching process to separately and alternately remove the semiconductor layers 210 and the semiconductor layers 215 . In some embodiments, parameters of the etch process are designed such that the semiconductor layer stack 205 is selectively etched, but the gate stacks 240 and/or the isolation features 230 are minimally (or not at all) etched. In some embodiments, a lithography process, such as any of the foregoing, is performed to fabricate a patterned mask layer covering the gate stacks 240 and/or the isolation elements 230, the patterned mask layer being used as an etch mask in the etch process.

In a step 106, in the method 100 ( 2A) 255 inner spacers manufactured. The resulting structure is in the 7A until 7D shown. 7A shows a top view of the device 200, and the 7B , 7C and 7D FIG. 12 shows partial sectional views of the device 200 along a line B-B, a line C-C and a line D-D of FIG 7A . In one embodiment, a first etch process is performed in which the semiconductor layers 210 exposed by the source/drain trenches 250 are selectively etched while the semiconductor layers 215 are minimally (to not at all) etched, leaving gaps between the semiconductor layers 215 and between the semiconductor layers 215 and 204 under the gate spacers 247. Parts (edges) of the semiconductor layers 215 are thus suspended in the channel regions under the gate spacers 247 . The first etch process is a dry etch process, a wet etch process, another suitable etch process, or a combination thereof. A spacer layer that partially (and in some embodiments completely) fills the source/drain trenches 250 is then formed with a deposition process. The deposition process is configured to ensure that the spacer layer fills the gaps between semiconductor layers 215 and between semiconductor layers 215 and 204 under gate spacers 247 . Then, a second etch process is performed in which the spacer layer is selectively etched to produce internal spacers 255, as in FIG 7B is shown with minimal (to no) etching of semiconductor layers 215, dummy gate stacks 240, and gate spacers 247. The inner spacers 255 comprise a material different from a material of the semiconductor layers 215 and a material of the gate spacers 247 to achieve a desired etch selectivity during the second etch process. The inner spacer layer 255 may comprise a dielectric material that is silicon, oxygen, carbon, nitrogen, another suitable material, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride). In some embodiments, the inner spacer layer 255 comprises a low-k dielectric material, such as one of the low-k dielectric materials mentioned herein.

In a step 108, in the method 100 ( 2A) an etch mask 241 is fabricated covering some of the source/drain trenches 250 and leaving other of the source/drain trenches 250 uncovered through openings 238 in the etch mask 241. FIG. 8A shows a top view of the device 200, and the 8B , 8C and 8D FIG. 12 shows partial sectional views of the device 200 along a line B-B, a line C-C and a line D-D of FIG 8A . In the present embodiment, the source/drain trenches 250 exposed by the openings 238 are those in which source/drain devices fabricated therein are connected to backside power lines or backside signal lines. This S/D Ele Elements may be source only, drain only, or a combination of source and drain elements in various embodiments. For ease of discussion, the S/D trenches 250 exposed through etch mask 241 will be referred to as S/D trenches 250'. In the present embodiment, the etching mask 241 has a structured hard mask 236 - 1 and a structured resist 237 . The etch mask 241 may also include a BARC layer (BARC: lower anti-reflective coating) between the patterned hard mask 236 - 1 and the patterned resist 237 in some embodiments. The patterned resist 237 may be formed by resist coating (e.g., spin coating), pre-bake, mask alignment, exposure, post-exposure bake, development of the resist, washing, drying (e.g., post-bake), other suitable lithographic processes, or combinations thereof. The patterned hard mask 236-1 is made by depositing a hard mask layer (before the resist 237 is spin-coated) and etching the hard mask layer using the resist pattern 237 as an etch mask.

In a step 110, in the method 100 ( 2A) the S/D trenches 250' are etched to deepen them. The resulting structure is in the 9A until 9D shown. 9A shows a top view of the device 200, and the 9B , 9C and 9D FIG. 12 shows partial sectional views of the device 200 along a line B-B, a line C-C and a line D-D of FIG 9A . The etch process may be a dry etch, a wet etch, a reactive ion etch, or any other suitable etch. The etch process is substantially anisotropic (ie, substantially vertical) in this embodiment. In addition, the etch process is adjusted so that it is selective to the material of the semiconductor layer 204 and the etch mask 241, the gate spacers 247, the dummy dielectric fins 229, the gate hard mask layers 246, the inner spacers 255 and the isolation structure 230 are not ( or only minimally) etches. The S/D trenches 250' are etched until only a thin semiconductor layer 204 remains therein, whereby the S/D trenches 250' reach into the substrate 201. After the end of the etching process, the structured resist 237 is removed in step 110, for example using a stripping process.

In a step 112, in the method 100 ( 2A) a semiconductor layer 239 is formed in the S/D trenches 250'. The resulting structure is in the 10A until 10D shown. 10A shows a top view of the device 200, and the 10B , 10C and 10D FIG. 12 shows partial sectional views of the device 200 along a line B-B, a line C-C and a line D-D of FIG 10A . The semiconductor layer 239 can be deposited with an epitaxial growth process or with other suitable processes. In some embodiments, the epitaxial growth of the semiconductor layer 239 is performed with an MBE process (MBE: Molecular Beam Epitaxy), a CVD process, a MOCVD process, another suitable epitaxial growth process, or combinations thereof. Semiconductor layer 239 comprises a different semiconductor material than that in semiconductor layer 204 to achieve etch selectivity during later processing. For example, the semiconductor layers 239 and 204 may have different materials, different constituent atomic fractions, different constituent mass fractions, thicknesses, and/or other properties to achieve a desired etch selectivity during an etch process. In one embodiment, semiconductor layer 204 comprises silicon and semiconductor layer 239 comprises silicon germanium. In an alternative embodiment, the semiconductor layers 239 and 204 may both comprise silicon germanium but with different constituent atomic fractions. In the present invention, it is contemplated that semiconductor layers 239 and 204 comprise a combination of semiconductor materials capable of providing the desired etch selectivity, including any of the semiconductor materials disclosed herein. Since other S/D trenches 250 ( 10D ) are covered by the patterned hard mask layer 236-1, the semiconductor layer 239 is only deposited in the S/D trenches 250' ( 10B and 10C ). Semiconductor layer 239 is deposited to a thickness such that it is near the bottom of stack 205 ( 10B) and approximately level with the top of the isolation members 230 ( 10C ) is. Step 112 may include an etch process that etches the semiconductor layer 239 to that shown in FIGS 10B and 10C level shown is recessed when the semiconductor layer 239 is first grown higher than this.

In a step 114, in the method 100 ( 2A) the patterned hard mask layer 236-1 is removed with one or more etching processes. The resulting structure is in the 11A until 11D shown according to one embodiment. 11A shows a top view of the device 200, and the 11B , 11C and 11D FIG. 12 shows partial sectional views of the device 200 along a line B-B, a line C-C and a line D-D of FIG 11A . In one embodiment, step 114 performs one or more etch processes selective to the materials of hard masks 236-1, including gate spacers 247, gate hard mask 246, inner spacers 255, semiconductor layers 215, 239, and 204 and various other structure elements that have been exposed by the removal of the hard masks 236-1 are not (or only minimally) etched. The etching processes can be dry etching processes, wet etching processes, reactive ion etching processes or other suitable etching processes.

Steps 116 through 132 of the method 100 in FIGS 2 B and 2C are performed on various areas of the device 200. In 12 three exemplary regions 200-1, 200-2 and 200-3 are shown. In various embodiments, these regions 200-1, 200-2, and 200-3 in device 200 may be contiguous or spaced apart. All areas 200-1, 200-2 and 200-3 have gone through steps 102 to 114. Region 200-1 is fabricated to include a second type of S/D devices (such as n-doped S/D devices). Region 200-2 is fabricated to include S/D devices of a first type (such as p-doped S/D devices) and region 200-3 is fabricated to include S/D devices of the second type arranged over the S/D elements of the first type. The first type is a conductivity type opposite to the second type. In one embodiment, the first type is p-type and the second type is n-type. In an alternative embodiment, the first type is n-type and the second type is p-type. The present invention shows that by using the three regions 200-1, 200-2 and 200-3, embodiments of the method 100 can be used to fabricate PMOS transistors, NMOS transistors and stacked CMOS transistors simultaneously on the same wafer. In the following discussion, the 13A-1 , 14A-1 , 15A-1 , 16A-1 , 17A-1 , 18A-1 , 19A-1 , 20A-1 and 21A-1 Sectional views of the device 200 in the area 200-1 along a line A-1 - A-1 of FIG 12 during various manufacturing steps of the method 100; the 13A-2 , 14A-2 , 15A-2 , 16A-2 , 17A-2 , 18A-2 , 19A-2 , 20A-2 and 21A-2 FIG. 12 shows sectional views of device 200 in area 200-2 along line A-2-A-2 of FIG 12 during various manufacturing steps of the method 100; and the 13A-3 , 14A-3 , 15A-3 , 16A-3 , 17A-3 , 18A-3 , 19A-3 , 20A-3 and 21A-3 FIG. 12 shows sectional views of device 200 in area 200-3 along line A-3-A-3 of FIG 12 during various manufacturing steps of the process 100.

In step 116, in the method 100 ( 2 B) a hard mask 236-2 is fabricated to cover the first area 200-1 and leave the second area 200-2 and the third area 200-3 uncovered. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 13A-1 , 13A-2 or. 13A-3 shown according to one embodiment. Hard mask 236-2 may be fabricated in the same manner as hard mask 236-1 (see, for example, the discussion of step 108 and 8B and 10B) , such as through deposition, photolithography, and etching processes. For simplicity, the resist pattern used to etch and fabricate the hard mask 236-2 is shown in FIGS 13A-1 , 13A-2 and 13A-3 not shown (or has been omitted).

In step 118, in the method 100 ( 2 B) Semiconductor SID elements 260-1 are grown in the S/D trenches 250 in the second area 200-2 and the third area 200-3 while the hard mask 236-2 covers the first area 200-1. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 14A-1 , 14A-2 or. 14A-3 shown according to one embodiment. As in the 14A-2 and 14A-3 As shown, epitaxial S/D elements 260-1 are grown from semiconductor layers 204, 239 and 215 in S/D trenches 250. FIG. For the epitaxial growth process, CVD deposition methods, for example vapor phase epitaxy (VPE) and/or ultra high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes or combinations thereof can be used. Gaseous and/or liquid precursors that interact with the compositions of the semiconductor layers 204, 239 and 215 can be used for the epitaxial process. The epitaxial S/D elements 260-1 are doped with n-type dopants for n-type transistors or with p-type dopants for p-type transistors. For n-type transistors, in some embodiments, the epitaxial S/D devices 260-1 comprise silicon, which may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (such that epitaxial Si:CS/D- elements, epitaxial Si:PS/D elements or epitaxial Si:C:PS/D elements arise). For p-type transistors, in some embodiments, the epitaxial S/D devices 260-1 comprise silicon germanium or germanium, which may be doped with boron, other p-type dopants, or combinations thereof (so that, for example, epitaxial Si:Ge:BS/D- elements arise). In some embodiments, the epitaxial S/D devices 260-1 include more than one epitaxial semiconductor layer, where the epitaxial semiconductor layers may have the same or different materials and/or doping concentrations. Also, in one embodiment, S/D element 260-1 (or at least a portion thereof adjacent semiconductor layer 239) has a different material composition than semiconductor layer 239 to provide etch selectivity during fabrication to achieve development of rear vias. For example, in one embodiment, semiconductor layer 239 comprises SiGe and S/D element 260-1 comprises Si (for an n-type transistor). In another embodiment, for example, the semiconductor layer 239 comprises SiGe with a first Ge atomic fraction and the S/D element 260-1 comprises SiGe (for a p-type transistor) with a second Ge atomic fraction, the first and the second Ge atomic proportion are different from each other. In some embodiments, the epitaxial S/D devices 260-1 include materials and/or dopants to achieve a desired tensile and/or compressive stress in respective channel regions. In some embodiments, the epitaxial S/D devices 260-1 are doped (ie, in situ) during deposition by adding dopants to a starting material for the epitaxial process. In some embodiments, the epitaxial S/D elements 260-1 are doped with an ion implantation process after a deposition process. In some embodiments, annealing processes, e.g. B. rapid thermal annealing (RTA) and/or laser annealing, performed to activate the dopants in the epitaxial S/D devices 260-1.

In step 120, in the method 100 ( 2 B) a hard mask 236-3 is fabricated to cover the second area 200-2 and leave the first area 200-1 and the third area 200-3 uncovered. The first area 200-1 is still covered by the hard mask 236-2. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 15A-1 , 15A-2 or. 15A-3 shown according to one embodiment. Hard mask 236-3 may be fabricated in the same manner as hard mask 236-1 (see, for example, the discussion of step 108 and 8B and 10B) , such as through deposition, photolithography, and etching processes. In addition, hard mask 236-3 comprises a different material than hard mask 236-2 to achieve etch selectivity. For simplicity, the resist pattern used to etch and fabricate the hard mask 236-3 is shown in FIGS 15A-1 , 15A-2 and 15A-3 not shown (or has been omitted).

In step 122, in the method 100 ( 2 B) the S/D elements 260-1 are partially recessed in the third area 200-3, while the hard masks 236-2 and 236-3 cover the area 200-1 and 200-2, respectively. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 16A-1 , 16A-2 or. 16A-3 shown according to one embodiment. The S/D elements 260-1 may be recessed using a dry etch, wet etch, reactive ion etch, or other suitable etch process. The etch process is adjusted to be selective for the material of semiconductor layer 260-1, leaving etch masks 236-2 and 236-3, inner spacers 255, gate spacers 247, and other features such as the dummy dielectric fins 229, the gate hard mask layers 246 and the isolation structure 230, are not (or only minimally) etched. The S/D elements 260-1 in the third region 200-3 are recessed such that a portion of the S/D trenches 250 is restored such that one or more channel layers 215 in the S/D trenches 250 are exposed. In addition, the S/D elements 260-1 are only partially recessed in the third region 200-3 such that one or more channel layers 215 (including the bottom channel layer 215) are still connected between the S/D elements 260-1 . A depth of the recess of the S/D elements 260-1 can be controlled with a timer or other means in various embodiments.

In step 124, in the method 100 ( 2 B) a hard mask 236-4 is fabricated such that it leaves a subset of the S/D elements 260-1 in the third area 200-3 uncovered and covers other S/D elements 260-1 in the third area 200-3. The first and second regions 200-1 and 200-2 are still covered by the hard mask 236-2 and 236-3, respectively. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 17A-1 , 17A-2 or. 17A-3 shown according to one embodiment. Hard mask 236-4 may be fabricated in the same manner as hard mask 236-1 (see, for example, the discussion of step 108 and 8B and 10B) , such as through deposition, photolithography, and etching processes. In the present embodiment, hard mask 236-4 has the same or a similar material as hard mask 236-2 so that both can be removed with the same etch process. Also, hard mask 236-4 comprises a different material than hard mask 236-3 to achieve etch selectivity. For simplicity, the resist pattern used to etch and fabricate the hard mask 236-4 is shown in FIGS 17A-1 , 17A-2 and 17A-3 not shown (or has been omitted). In the present embodiment, the hard mask 236-4 leaves uncovered some or all of the S/D devices 260-1 that are located directly above the semiconductor layer 239 (ie, the S/D devices 260-1 that are connected to backside vias ). The hardmask 236-4 may also, in some embodiments, leave uncovered some of the S/D devices 260-1 that are not disposed directly over the semiconductor layer 239 (ie, the S/D devices 260-1 that are not provided with backside vias get connected).

In step 126, in the method 100 ( 2C ) an isolation layer 244 is formed over the subset of the S/D elements 260-1 in the third region 200-3 that are exposed through the hard mask 236-4. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 18A-1 , 18A-2 or. 18A-3 shown according to one embodiment. In one embodiment, insulating layer 244 is first deposited over hard masks 236-2, 236-3, and 236-4 and is then removed from hard masks 236-2, 236-3, and 236-4 with one or more etch processes. In the present embodiment, the isolation layer 244 is deposited to such a level that some of the channel layers 215 in the S/D trenches 250 and over the isolation layer 244 are still exposed. In some embodiments, isolation layer 244 may block (or cover) some, but not all, channel layers 215 in S/D trenches 250 . In one embodiment, the insulating layer 244 comprises a dielectric material that is silicon, oxygen, carbon, nitrogen, another suitable material, or a combination thereof, for example, silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON ), silicon carbonitride (SiCN) or silicon oxide carbonitride (SiOCN). The insulating layer 244 can be deposited by CVD, PVD, ALD, or other suitable methods.

In step 128, in the method 100 ( 2C ) removes hard masks 236-2 and 236-4 while leaving hard mask 236-3 over second region 200-2. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 19A-1 , 19A-2 or. 19A-3 shown according to one embodiment. In one embodiment, step 128 performs one or more etch processes selective to the materials in hard masks 236-2 and 236-4, wherein hard mask 236-3, gate spacers 247, gate hard mask 246, the inner spacers 255, the isolation layer 244, the S/D elements 260-1 and various other features exposed by the removal of the hard masks 236-2 and 236-4 are not (or only minimally) etched. The etching processes can be dry etching processes, wet etching processes, reactive ion etching processes or other suitable etching processes. In step 128, the S/D trenches 250 in the first area 200-1 and the third area 200-3 are restored.

In step 130, in the method 100 ( 2C ) Semiconductor S/D elements 260-2 are grown in the S/D trenches 250 in the first area 200-1 and the third area 200-3, while the hard mask 236-3 covers the second area 200-2. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 20A-1 , 20A-2 or. 20A-3 shown according to one embodiment. As in 20A-1 As shown, epitaxial S/D elements 260-2 are grown from semiconductor layers 204, 239 and 215 in S/D trenches 250. FIG. As in 20A-3 1, epitaxial S/D devices 260-2 are grown from semiconductor layers 260-1 and 215 in S/D trenches 250. FIG. CVD deposition methods (e.g. VPE and/or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes or combinations thereof can be used for the epitaxial growth process. Gaseous and/or liquid precursors that interact with the compositions of the semiconductor layers 204, 239, 215 and 260-1 can be used for the epitaxial process. The epitaxial S/D elements 260-2 are doped with n-type dopants for n-type transistors or with p-type dopants for p-type transistors. For n-type transistors, in some embodiments, the epitaxial S/D devices 260-2 comprise silicon, which may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (such that epitaxial Si:CS/D- elements, epitaxial Si:PS/D elements or epitaxial Si:C:PS/D elements arise). For p-type transistors, in some embodiments, the epitaxial S/D devices 260-2 comprise silicon germanium or germanium, which may be doped with boron, other p-type dopants, or combinations thereof (so that, for example, epitaxial Si:Ge:BS/D- elements arise). In some embodiments, the epitaxial S/D devices 260-2 include more than one epitaxial semiconductor layer, where the epitaxial semiconductor layers may have the same or different materials and/or doping concentrations. Also, in one embodiment, S/D element 260-2 (or at least a portion thereof adjacent semiconductor layer 239) has a different material composition than semiconductor layer 239 to achieve etch selectivity during backside via formation. For example, in one embodiment, semiconductor layer 239 comprises SiGe and S/D element 260-2 comprises Si (for an n-type transistor). For example, in another embodiment, the semiconductor layer 239 comprises SiGe with a first Ge atomic fraction and the S/D element 260-2 comprises SiGe (for a p-type transistor) with a second Ge atomic fraction, the first and the second Ge atomic proportion are different from each other. In some embodiments, the epitaxial S/D devices 260-2 include materials and/or dopants to achieve a desired tensile and/or compressive stress in respective channel regions. In some embodiments, the epitaxial S/D elements 260-2 are doped (ie, in situ) during deposition by a Starting material for the epitaxy process is mixed with dopants. In some embodiments, the epitaxial S/D elements 260-2 are doped with an ion implantation process after a deposition process. In some embodiments, annealing processes, e.g. B. rapid thermal annealing (RTA) and/or laser annealing, performed to activate the dopants in the epitaxial S/D devices 260-2. In the present embodiment, S/D devices 260-2 have a different conductivity than S/D devices 260-1, resulting in CMOS stack structures in region 200-3. In one embodiment, S/D elements 260-1 are p-type and S/D elements 260-2 are n-type. In another embodiment, S/D elements 260-1 are n-type and S/D elements 260-2 are p-type. In 20A-3 some of the S/D elements 260-2 are connected directly to the S/D elements 260-1. These can function as a common drain element or as a common source element. Some of the S/D elements 260-2 are isolated by the isolation layer 244 from the S/D elements 260-1. These S/D elements 260-2 and 260-1 function as individual (not common) source elements or as individual drain elements.

In step 132, in the method 100 ( 2C ) removes the hard mask 236-3 from the second region 200-2. The resulting structures of the three areas 200-1, 200-2 and 200-3 are in 21A-1 , 21A-2 or. 21A-3 shown according to one embodiment. In one embodiment, step 132 performs one or more etch processes selective to the materials in hard mask 236-3, including gate spacers 247, gate hard mask 246, S/D devices 260-1, and 260-2 and various other structure elements that have been exposed by removing the hard mask 236-3 are not (or only minimally) etched. The etching processes can be dry etching processes, wet etching processes, reactive ion etching processes or other suitable etching processes. As in the 21A-1 , 21A-2 and 21A-3 1, S/D elements 260-1 of a first type are manufactured in the second region 200-2, S/D elements 260-2 of a second type are manufactured in the first region 200-1, and the S/D - Elements 260-1 and 260-2 of the first and second type are stacked on top of each other in the third area 200-3.

In steps 134 and 136, the method 100 ( 2C ) the dummy gates 240 are replaced by functional gates, and MEOL and BEOL processes are performed on the front side of the substrate 201 (MEOL: Middle End of Line; BEOL: Back End of Line). In steps 138 through 150, the method 100 ( 2D ) Manufacturing processes performed on the back of the substrate 201. Steps 134 through 150 are performed in regions 200-1, 200-2 and 200-3 in the same manner, given that different transistors having gates with different work functions can be fabricated. For the sake of simplicity, the range 200-3 in FIGS 22A until 30 1 is shown to describe the various steps 134 through 150, with the premise that the same or similar structures are fabricated in regions 200-1 and 200-2.

In step 134, in the method 100 ( 2C ) a contact etch stop layer (CESL) 269 and an interlayer dielectric (ILD) layer 270 are fabricated in the device 200 and over all three regions 200-1, 200-2 and 200-3, and then the dummy gate stacks 240 replaced with functional gate stacks 240' (such as high-k metal gates). The resulting structure is in the 22A until 22C shown according to one embodiment. 22A 12 shows a top view of device 200 (area 200-3), and FIG 22B and 22C show partial sectional views of the device 200 along a line B - B and a line C - C of FIG 22A .

As in 22B As shown, CESL 269 is deposited over S/D devices 260-2 and ILD layer 270 is deposited over CESL 269 and fills a gap between opposing gate spacers 247. CESL 269 comprises a material which is different from those of the ILD layer 270 and the dielectric layer 234 . The CESL 269 can La ₂ O ₃ , Al ₂ O ₃ , SiOCN, SiOC, SiCN, SiO ₂ , SiC, ZnO, ZrN, Zr ₂ Al ₃ O ₉ , TiO ₂ , TaO ₂ , ZrO ₂ , HfO ₂ , Si ₃ N ₄ , Y ₂ O ₃ , AION, TaCN, ZrSi or other suitable materials and can be prepared by CVD, PVD, ALD or other suitable methods. The ILD layer 270 may be TEOS oxide, undoped silicate glass or doped silicon oxide such as borophosphorus silicate glass (BPSG), fluorosilicate glass (FSG), phosphorus silicate glass (PSG) or borosilicate glass (BSG), a low-k dielectric material, other suitable dielectric materials or combinations thereof. The ILD layer 270 can be formed by PECVD, FCVD, or other suitable methods. After the deposition of the CESL 269 and the ILD layer 270, a CMP process and/or other planarization process may be performed until a top portion (or top) of the dummy gate stacks 240 is reached (exposed). In some embodiments, the planarization process removes the hard mask layers 246 of the dummy gate stacks 240 to expose the underlying dummy gate electrodes 245, such as polysilicon gate electrode layers.

Subsequently, in step 134, the dummy gate stacks 240 (the dummy gate electrodes 245 and the dummy gate dielectric layer 235; see 5B) removed with one or more etching processes. This creates gate trenches. The etch processes may be dry etch processes, wet etch processes, other suitable etch processes, or combinations thereof. In some embodiments, the etch process is a multi-step etch process. For example, alternating etchants may be used for the etch process to separately remove different layers of the dummy gate stacks 240 . In some embodiments, the etch process is configured such that the dummy gate stacks 240 are selectively etched but other structural elements of the device 200, such as the ILD layer 270, the gate spacers 247, the isolation elements 230, the cladding layer 231, the semiconductor layers 215 and the semiconductor layers 210, are etched only minimally (or not at all).

Subsequently, in step 134, the cladding layer 231 (see 5C ) exposed in the gate trenches. In the etch process, the cladding layer 231 may be selectively etched, but the semiconductor layers 215, gate spacers 247, and inner spacers 255 are minimally (or not at all) etched. Then, in step 134, the semiconductor layers 210 exposed in the gate trenches are removed so that the semiconductor layers 215 are floated over the semiconductor layer 204 and connected to the S/D elements 260-1 and 260-2. This process is also referred to as a channel exposure process, and the semiconductor layers 215 are also referred to as channel layers. With the etch process, the semiconductor layers 210 are selectively etched, but the semiconductor layers 215 are minimally (to no) etched, and in some embodiments the gate spacers 247 and/or the inner spacers 255 are minimally (to no) etched.

Then, in step 134, a gate dielectric layer 349 is formed to enclose each of the semiconductor layers 215, and a gate electrode 350 is formed over the gate dielectric layer 349. FIG. Functional gate stacks 240 ′ include gate dielectric layer 349 and gate electrode 350 . The gate dielectric layer 349 may comprise a high-k dielectric material such as HfO ₂ , HfSiO, HfSiO ₄ , HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO _x , ZrO, ZrO ₂ , ZrSiO _z , AlO, AlSiO, Al ₂ O ₃ , TiO, TiO ₂ , LaO, LaSiO, Ta ₂ O ₃ , Ta ₂ O ₅ , Y ₂ O ₃ ,SrTiO ₃ , BaZrO, BaTiO ₃ (BTO), (Ba,Sr)TiO ₃ (BST), Si ₃ N ₄ , hafnia-alumina alloy (HfO ₂ -Al ₂ O ₃ alloy), other suitable high-k dielectric material, or combinations thereof. Gate dielectric layer 349 may be formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable methods. In some embodiments, the gate stack 240 ′ further includes an interface layer between the gate dielectric layer 349 and the channel layers 215 . The interface layer may include silicon dioxide, silicon oxynitride, or other suitable materials. In some embodiments, the gate electrode layer 350 (depending on the type of transistors) comprises an n or a p work function layer and a metal fill layer. For example, the n-work function layer may comprise a metal with a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or combinations thereof. For example, the p-work function layer may comprise a metal with a sufficiently high effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The metal fill layer may include, for example, aluminum, tungsten, cobalt, copper, and/or other suitable materials. Gate electrode layer 350 may be formed by CVD, PVD, plating, and/or other suitable methods. Because the gate stack 240' includes a high-k dielectric layer and one or more metal layers, it is also referred to as a high-k metal gate.

In step 136, in the method 100 ( 2C ) MEOL and BEOL processes are performed on the front side of the substrate 201. The resulting structure is in 23 shown according to one embodiment. the 23 until 30 FIG. 12 shows sectional views of the device 200 along a line BB of FIG 22A according to some embodiments. In one embodiment, in step 136, S/D vias are etched to protect some of the S/D elements 260-2 in regions 200-1 and 200-2 and some of the S/D elements 260-1 in the region 200-2 to expose. The S/D elements 260-2 and 260-1 may only be partially etched in some embodiments. The etching processes can be dry etching processes, wet etching processes, reactive ion etching processes or other etching processes. Then, in step 136, silicide elements 273 are formed over the S/D elements 260-2 and 260-1, and over the silicide elements 273 S/D contacts (or vias) 275 are formed. Because the silicide elements 273 and the S/D contacts 275 are fabricated on the front side of the device 200, they are also referred to as front-side silicide elements 273 and front-side S/D contacts 275, respectively.

The silicide elements 273 can be titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germa nium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi) or other suitable compounds. In one embodiment, the S/D contacts 275 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer can be titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru) or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAIN), tungsten nitride (WN), tantalum nitride (TaN) or combinations thereof and can be produced by CVD, PVD, ALD and/or other suitable methods. The metal fill layer may comprise tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable methods. In some embodiments, the conductive barrier layer in the S/D contacts 275 is omitted.

Step 136 may also include: forming gate vias that connect to the gate stacks 240'; forming S/D vias that connect to S/D contacts 275; and forming one or more interconnect layers with wires and vias embedded in dielectric layers. The one or more interconnect layers connecting gate, source, and drain electrodes of various transistors, as well as other circuitry in device 200, form part or all of an integrated circuit. Also at step 136, one or more passivation layers may be formed over the interconnect layers. in the in 23 In the example shown, a reference numeral 277 is used to designate various dielectric and metal layers, including interconnect layers and passivation layers, that are fabricated on the front side of device 200 over S/D contacts 275 .

In step 138, in the method 100 ( 2D ) the device 200 is turned upside down and the front of the device 200 is attached to a support 370, as in FIG 24 is shown. As a result, the device 200 is accessible for further processing from its rear side. Any suitable attachment method, such as direct bonding, hybrid bonding, using an adhesive, or other bonding method, may be used for step 138 . Step 138 may further include alignment, annealing, and/or other processes. The carrier 370 may be a silicon wafer in one embodiment. In the 24 until 30 shows the z-direction from the back of the device 200 to its front, while the -z-direction shows from the front of the device 200 to its back.

In step 140, in the method 100 ( 2D ) the device 200 is thinned from its rear side until the semiconductor layer 204, the semiconductor layer 239 and the insulating elements 230 (see 22C ) have been removed from the back of the device 200. The resulting structure is in 25 shown according to one embodiment. The thinning process may include a mechanical grinding process and/or a chemical thinning process. First, a significant amount of substrate material may be removed from substrate 201 during a mechanical grinding process. An etching chemical can then be applied to the back side of the substrate 201 in a chemical thinning process in order to further thin the substrate 201 .

In step 142, in the method 100 ( 2D ) the semiconductor layer 204 is selectively etched to form trenches 272 over the backside of the gate stacks 240' and over the S/D devices 260-1 in the regions 200-2 and 200-3 and the S/D devices 260-2 in the generate area 200-1. The resulting structure is in 26 shown according to one embodiment. In the present embodiment, step 142 uses an etch process that is adapted to be selective to the materials of semiconductor layer 204 but semiconductor layer 239, S/D devices 260-1 and 260-2, the gate stacks 240' and the isolation elements 230 are not (or only minimally) etched. The etch process may be a dry etch process, a wet etch process, a reactive ion etch process, or any other suitable etch process.

In step 144, in the method 100 ( 2D ) one or more dielectric layers are formed to fill the trenches 272 . The one or more dielectric layers may include a dielectric liner 274 and one or more dielectric layers 276, for example. The resulting structure is in 27 shown according to one embodiment. In some embodiments, the dielectric coating 274 _{comprises La 2} O ₃ , Al ₂ O ₃ , SiOCN, SiOC, SiCN, SiO ₂ , SiC, ZnO, ZrN, Zr ₂ Al ₃ O ₉ , TiO ₂ , TaO ₂ , ZrO ₂ , HfO ₂ , Si ₃ N ₄ , Y ₂ O ₃ , AION, TaCN, ZrSi or other suitable materials and it can be prepared by CVD, PVD, ALD or other suitable methods. In some embodiments, the one or more dielectric layers 276 may be TEOS oxide, undoped silicate glass, or doped silicon oxide, such as borophosphorus silicate glass (BPSG), fluorosilicate glass (FSG), phosphorus silicate glass (PSG), or borosilicate glass (BSG), and/or other suitable dielectric have materials. the Dielectric layers 276 may be formed by PECVD, FCVD, or other suitable methods.

In step 146, in the method 100 ( 2D ) removes the semiconductor layer 239 from the back side of the device 200. The resulting structure is in 28 shown according to one embodiment. In the present embodiment, step 146 uses an etch process that is adjusted to be selective to the materials of the semiconductor layer 239 (such as SiGe in one embodiment), the dielectric liner 274, the dielectric layers 276, and the isolation elements 230 does not (or only minimally) etch. In some embodiments, the S/D elements 260-1 and 260-2 may not be etched, and in alternative embodiments they may be partially etched. The etch process creates trenches 278 that expose some of the S/D elements 260-1 in regions 200-2 and 200-3 and some of the S/D elements 260-2 in region 200-1 from the backside of the device uncover 200. The etch process may be a dry etch process, a wet etch process, a reactive ion etch process, or any other suitable etch process. In particular, in the present embodiment, the etch of the semiconductor layer 239 is self-aligned. In other words, an etch mask (e.g., an etch mask made with photolithography processes) for etching the semiconductor layer 239 need not be made in step 146 . Rather, step 146 is based on the etch selectivity of the materials in the semiconductor layer 239 and the layers surrounding it. This advantageously creates the trenches 278 that are to be aligned with the underlying S/D devices 260-1 and 260-2 without offsets, such as those caused by photolithography registration shift. Using this method creates backside contacts (or vias) that are ideally aligned with S/D elements 260-1 and 260-2, as discussed later.

In step 148, in the method 100 ( 2D ) backside silicide source elements 280 and backside contacts (or vias or metal studs) 282 are fabricated in the trenches (or via openings) 278 . The resulting structure is in 29 shown according to one embodiment. In one embodiment, step 148 includes: depositing one or more metals into via openings 278; performing an annealing process on device 200 to cause a reaction between the one or more metals and S/D elements 260-1 (such as in regions 200-2 and 200-3) and S/D elements 260 trigger -2 (such as in region 200-1) to produce silicide elements 280; and removing unreacted portions of the one or more metals, leaving the silicide elements 280 in the via opening. The one or more metals can be titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co ) or a combination thereof (e.g. an alloy of two or more metals) and they can be deposited by CVD, PVD, ALD or other suitable methods. The silicide element 280 may be titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), Ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi) or other suitable compounds.

Then in step 148 the via 282 is deposited in the via opening 278 so that it contacts the silicide element 280 . In one embodiment, via 282 may include a conductive barrier layer and a metal fill layer over the conductive barrier layer. The conductive barrier layer can be titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru) or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAIN), tungsten nitride (WN), tantalum nitride (TaN) or combinations thereof and can be produced by CVD, PVD, ALD and/or other suitable methods. The metal fill layer may comprise tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals and may be formed by CVD, PVD, ALD, plating, or other suitable methods.

In step 150, in the method 100 ( 2D ) further manufacturing processes are carried out on the device 200 . For example, in step 150, backside power lines 284 and backside interconnect structure 286 are fabricated. The resulting structure is in 30 shown according to one embodiment. As in 30 As shown, backside via 282 is electrically connected to backside power lines 284 . In one embodiment, the backside power rails 284 may be fabricated using a single damascene process, a dual damascene process, a metal patterning process, or other suitable processes. The backside power lines 284 may and may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals deposited by CVD, PVD, ALD, plating or other suitable methods. Although it's in 30 it is not shown who the backside power lines 284 are embedded in one or more dielectric layers, and the backside interconnect structure 286 includes wires and vias embedded in one or more dielectric layers. In some embodiments, the backside power lines 284 are considered part of the backside interconnect structure 286 . Advantageously, utilizing the backside power supply lines 284 increases the number of metal traces available in the device 200 for direct connection to source/drain contacts and vias. In addition, the gate density increases for higher device integration than other structures without the backside power supply lines 284. The backside power supply lines 284 can be wider than the first level metal lines (M0 metal lines) on the front side of the device 200, making a resistance of the backside power supply lines 284 advantageous is reduced. In step 150, further manufacturing processes may be performed on the device 200, such as forming passivation layers on the back side of the device 200; removing carrier 370; and performing further BEOL processes. 31 shows the device 200 in a partial sectional view after the removal of the carrier 370.

Embodiments of the present invention, which are not intended to be limiting, provide one or more of the following benefits. For example, embodiments of the present invention provide stacked CMOS structures having a first transistor stacked on top of a second transistor, the first and second transistors having different conductivities. This greatly reduces the footprint of the CMOS structure compared to approaches where the first and second transistors are implemented side-by-side. Thus, the integrated circuits can be further miniaturized. Embodiments of the present invention can be easily integrated into existing semiconductor manufacturing processes.

In an exemplary aspect, the present invention is directed to a semiconductor structure, comprising: an operating voltage line; a first source/drain element disposed over the power supply line; a via connecting the power supply line to the first source/drain element; an isolation element disposed over the first source/drain element; and a second source/drain element disposed over the isolation element, the first and second source/drain elements having different conductivity types.

In some embodiments of the semiconductor structure, the first source/drain element is p-type and the second source/drain element is n-type. In some embodiments, the semiconductor structure further includes: a third source/drain element disposed over the power supply line; a fourth source/drain element arranged over the third source/drain element; a first channel layer connecting the first and third source/drain elements; a second channel layer disposed over the first channel layer connecting the second and fourth source/drain elements; and a gate structure enclosing the first and second channel layers. In a further embodiment, the semiconductor structure further comprises a second isolation element arranged between the third source/drain element and the fourth source/drain element. In some embodiments, the third source/drain element directly contacts the fourth source/drain element. In another embodiment, the semiconductor structure further includes a second power supply line disposed over the fourth source/drain element; and a first via connecting the second power supply line to the fourth source/drain element. In one embodiment, the semiconductor structure further includes a second via disposed over and connected to the second source/drain element.

In another exemplary aspect, the present invention is directed to a method that includes providing a structure, the structure comprising: a substrate; a fin having a stack of first and second semiconductor layers alternately stacked over the substrate; a sacrificial gate structure over the fin; and gate spacers on sidewalls of the sacrificial gate structure. The method further includes: etching the fin adjacent to the gate spacers to create first and second source/drain trenches; laterally recessing the second semiconductor layers exposed in the first and second source/drain trenches to create gaps; Making interior spacers in the columns; epitaxially growing first and second source/drain elements in the first and second source/drain trenches, respectively; partially removing the first and second source/drain elements; after the partial removal, forming a hard mask so that it covers the second source/drain element and does not cover the first source/drain element; depositing an insulating material over the first source/drain element when the hard mask is in place; removing the hard mask; and epitaxially growing a third source/drain element over the insulating material and a fourth source/drain element over the second source/drain element, wherein the first and second source/drain elements have a first conductivity type and the third and fourth source/drain elements have a second conductivity type Have conductivity type opposite to the first conductivity type.

In one embodiment, prior to epitaxially growing the first and second source/drain devices, the method further comprises: performing an additional etch on the first source/drain trench; and after performing the additional etch, depositing a dummy material into the first source/drain trench, wherein the first source/drain element is grown over the dummy material. In another embodiment, the method further comprises: removing the dummy material from a backside of the structure to create a backside via opening; and forming a via in the backside via opening.

In some embodiments, the method further includes replacing the sacrificial gate structure with a high-k metal gate. In another embodiment, the replacement includes: removing the sacrificial gate structure to create a gate trench; removing the second semiconductor layers exposed in the gate trench; depositing a high-k gate dielectric layer over each of the first semiconductor layers exposed in the gate trench; and depositing a metal gate electrode over the high-k gate dielectric layer.

In yet another exemplary aspect, the present invention is directed to a method that includes providing a structure having a substrate and first, second, and third regions over the substrate, the third region being a stack of first and second Semiconductor layers alternately stacked over the substrate. The method further comprises: etching source/drain trenches in each of the first, second and third regions, wherein the source/drain trenches in the third region are etched into the stack of the first and second semiconductor layers ; fabricating a first hard mask to cover the first area and not to cover the second and third areas; and epitaxially growing source/drain elements of a first type in the source/drain trenches in the second and third regions when the first hard mask is in place. The method further includes: fabricating a second hard mask to cover the second area and not to cover the third area; partially recessing the source/drain elements in the third region when the first and second hard masks are in place; after the partial recess, fabricating a third hard mask so that it does not cover a first one of the source/drain elements in the third area and covers a second one of the source/drain elements in the third area; and depositing an insulating material over the first of the source/drain elements in the third region when the first, second, and third hard masks are in place.

In one embodiment, the method further comprises: removing the first and third hard masks; and forming source/drain devices of a second type in the source/drain trenches in the first region, over the insulating material and over the second of the source/drain devices in the third region when the second hard mask is at the correct location, the first and second types being opposite conductivity types. In another embodiment, the first type is p-type and the second type is n-type. In another embodiment, after forming the second type source/drain devices, the method further comprises removing the second hard mask.

Also in one embodiment, the first and second regions each comprise a stack of the first and second semiconductor layers, and the source/drain trenches in the first and second regions are also included in the stack of the first and second semiconductor layers etched. In another embodiment, after etching the source/drain trenches and before forming the first hard mask, the method further comprises: performing an additional etch on one of the source/drain trenches in the third region; and depositing a sacrificial semiconductor layer in the one of the source/drain trenches, wherein the first of the source/drain elements is grown on the sacrificial semiconductor layer in the third region. In another embodiment, the method further comprises: thinning the substrate from a back side of the structure to expose the sacrificial semiconductor layer; removing the sacrificial semiconductor layer to create a via opening; and forming a via in the via opening. In one embodiment, at least one of the first semiconductor layers connects the first and second of the source/drain elements in the third region.

The foregoing has described features of various embodiments so that those skilled in the art may better understand aspects of the present invention. Experts should be clear be that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same ends and/or obtain the same benefits as the embodiments presented herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention and that they can make various changes, substitutions and modifications therein without departing from the spirit and scope of the present invention.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US63/027811 [0001]

Claims (20)

semiconductor structure with: an operating voltage line; a first source/drain element disposed over the power supply line; a via connecting the power supply line to the first source/drain element; an isolation element arranged over the first source/drain element; and a second source/drain element disposed over the isolation element, the first and second source/drain elements having different conductivity types. semiconductor structure claim 1 , wherein the first source/drain element is p-type and the second source/drain element is n-type. semiconductor structure claim 1 or 2 , further comprising: a third source/drain element disposed over the power supply line; a fourth source/drain element arranged over the third source/drain element; a first channel layer connecting the first source/drain element and the third source/drain element; a second channel layer disposed over the first channel layer connecting the second source/drain element and the fourth source/drain element; and a gate structure enclosing the first channel layer and the second channel layer. semiconductor structure claim 3 , further comprising a second isolation element disposed between the third source/drain element and the fourth source/drain element. semiconductor structure claim 3 or 4 , wherein the third source/drain element directly contacts the fourth source/drain element. Semiconductor structure according to one of claims 3 until 5 further comprising: a second power supply line disposed over the fourth source/drain element; and a first via connecting the second power supply line to the fourth source/drain element. The semiconductor structure of any preceding claim, further comprising a second via disposed over and connected to the second source/drain element. Procedure with the following steps: providing a structure, the structure comprising: a substrate a fin comprising a stack of first and second semiconductor layers alternately stacked over the substrate, a sacrificial gate structure over the fin, and gate spacers on sidewalls of the sacrificial gate structure; etching the fin adjacent to the gate spacers to create first and second source/drain trenches; laterally recessing the second semiconductor layers exposed in the first and second source/drain trenches to create gaps; Making interior spacers in the columns; epitaxially growing first and second source/drain elements in the first and second source/drain trenches, respectively; partially removing the first and second source/drain elements; after the partial removal, forming a hard mask so that it covers the second source/drain element and leaves the first source/drain element exposed; depositing an insulating material over the first source/drain element when the hard mask is in place; removing the hard mask; and epitaxially growing a third source/drain device over the insulating material and a fourth source/drain device over the second source/drain device, wherein the first and second source/drain devices have a first conductivity type and the third and fourth source/drain elements have a second conductivity type opposite to the first conductivity type. procedure after claim 8 , further comprising prior to epitaxially growing the first and second source/drain devices: performing an additional etch on the first source/drain trench; and after performing the additional etch, depositing a dummy material into the first source/drain trench, wherein the first source/drain element is grown over the dummy material. procedure after claim 8 or 9 , further comprising: removing the dummy material from a backside of the structure to create a backside via opening; and forming a via in the backside via opening. Procedure according to one of Claims 8 until 10 , further comprising replacing the sacrificial gate structure with a high-k metal gate. procedure after claim 11 , the replacing comprising: removing the sacrificial gate structure to create a gate trench; removing the second semiconductor layers exposed in the gate trench; depositing a high-k gate dielectric layer over each of the first semiconductor layers exposed in the gate trench; and depositing a metal gate electrode over the high-k gate dielectric layer. Procedure with the following steps: providing a structure comprising a substrate and first, second and third regions over the substrate, the third region comprising a stack of first and second semiconductor layers alternately stacked over the substrate; etching source/drain trenches in each of the first, second and third regions, the source/drain trenches in the third region being etched into the stack of the first and second semiconductor layers; fabricating a first hard mask to cover the first area and leave the second and third areas exposed; and epitaxially growing source/drain elements of a first type in the source/drain trenches in the second and third regions when the first hard mask is in place; fabricating a second hard mask to cover the second area and leave the third area exposed; partially recessing the source/drain elements in the third region when the first and second hard masks are in place; after the partial recess, fabricating a third hard mask such that it exposes a first of the source/drain elements in the third area and covers a second of the source/drain elements in the third area; and depositing an insulating material over the first of the source/drain elements in the third region when the first, second, and third hard masks are in place. procedure after Claim 13 , further comprising: removing the first and third hard masks; and forming source/drain devices of a second type in the source/drain trenches in the first region, over the insulating material and over the second of the source/drain devices in the third region when the second hard mask is at the correct location, the first and second types being opposite conductivity types. procedure after Claim 14 , where the first type is p-type and the second type is n-type. procedure after Claim 14 or 15 , further comprising removing the second hard mask after forming the second type of source/drain elements. Procedure according to one of Claims 13 until 16 , wherein also the first and the second region each have a stack of the first and the second semiconductor layers and also the source/drain trenches in the first and the second region are etched into the stack of the first and the second semiconductor layers. Procedure according to one of Claims 13 until 17 , further comprising, after etching the source/drain trenches and before forming the first hard mask: performing an additional etch on one of the source/drain trenches in the third region; and depositing a sacrificial semiconductor layer in the one of the source/drain trenches, wherein the first of the source/drain elements is grown on the sacrificial semiconductor layer in the third region. procedure after Claim 18 further comprising: thinning the substrate from a back side of the structure to expose the sacrificial semiconductor layer; removing the sacrificial semiconductor layer to create a via opening; and forming a via in the via opening. Procedure according to one of Claims 13 until 19 , wherein at least one of the first semiconductor layers connects the first and the second of the source/drain elements in the third region.

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