DE102020131642A1 - STRUCTURES AND TECHNIQUES OF DIRECTED SELF-ORGANIZATION - Google Patents

Abstract

Disclosed herein are structures and techniques that use directed self-assembly to fabricate microelectronic devices. A microelectronic structure can e.g. B. a patterned area including a first conductive line and a second conductive line, the second conductive line being adjacent to the first conductive line; and a disordered region having a disordered lamellar pattern, the disordered region being coplanar with the patterned region.

Description

Cross reference to related application

This application claims priority from U.S. Provisional Patent Application No. 63 / 033,721 , filed on June 2, 2020, entitled "CHEMICAL COMPOSITIONS & METHODS OF PATTERNING MICROELECTRONIC DEVICE STRUCTURES". This priority application is hereby fully incorporated by reference.

background

Conventional microelectronic manufacturing techniques may not be able to reliably pattern particularly small features. As a result, the size and performance of microelectronic devices have been limited.

Figure list

• 1A-1C sind verschiedene Ansichten einer mikroelektronischen Struktur, die Leitungen mit geringer Leitungskantenrauheit (LER) enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 2A-2L veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 1 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 3 veranschaulicht eine Stufe in einem weiteren beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 1 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 4A-4B sind verschiedene Ansichten einer weiteren mikroelektronischen Struktur, die Leitungen mit geringer (LER) enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 5A-5D veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 4 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 6A-6B sind verschiedene Ansichten einer weiteren mikroelektronischen Struktur, die Leitungen mit geringer LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 7A-7H veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 6 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 8A-8B sind verschiedene Ansichten einer mikroelektronischen Struktur, die Leitungen mit geringer LER und Leitungen mit hoher LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 9A-9M veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 8 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 10A-1 0B sind verschiedene Ansichten einer weiteren mikroelektronischen Struktur, die Leitungen mit geringer LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 11A-11H veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 10 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 12A-12B sind verschiedene Ansichten einer weiteren mikroelektronischen Struktur, die Leitungen mit geringer LER und Leitungen mit hoher LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 13A-13P veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 12 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 14A-14B sind verschiedene Ansichten einer weiteren mikroelektronischen Struktur, die Leitungen mit geringer LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 15A-15G veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 14 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 16A-16B sind verschiedene Ansichten einer weiteren mikroelektronischen Struktur, die Leitungen mit geringer LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 17A-17G veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 16 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 18 ist eine Draufsicht auf eine mikroelektronische Struktur, die Leitungen mit geringer LER in mehreren Abständen enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 19A-19E veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 18 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 20 veranschaulicht eine Stufe in einem weiteren beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 18 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 21 ist eine Seiten-Querschnittsansicht einer mikroelektronischen Struktur, die Durchkontaktierungen in leitfähigen Kontakt mit Leitungen mit geringer LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 22A-22F veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 21 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 23 ist eine Seiten-Querschnittsansicht einer weiteren mikroelektronischen Struktur, die Durchkontaktierungen in leitfähigen Kontakt mit Leitungen mit geringer LER enthält, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 24A-24C veranschaulichen die Stufen in einem beispielhaften Prozess zum Herstellen der mikroelektronischen Struktur nach 23 in Übereinstimmung mit verschiedenen Ausführungsformen.
• 25-27 sind Draufsichten auf mikroelektronische Strukturen, die Abstands-Teilungs-Artefakte enthalten, in Übereinstimmung mit verschiedenen Ausführungsformen.
• 28 ist eine Draufsicht auf einen Wafer und Dies, die irgendwelche der hier offenbarten mikroelektronischen Strukturen enthalten können.
• 29 ist eine Seiten-Querschnittsansicht einer mikroelektronischen Vorrichtung, die irgendwelche der hier offenbarten mikroelektronischen Strukturen enthalten kann.
• 30 ist eine Seiten-Querschnittsansicht einer mikroelektronischen Baugruppe, die irgendwelche der hier offenbarten mikroelektronischen Strukturen enthalten kann.
• 31 ist eine Seiten-Querschnittsansicht einer mikroelektronischen Vorrichtung, die irgendwelche der hier offenbarten mikroelektronischen Strukturen enthalten kann.
• 32 ist ein Blockschaltplan einer beispielhaften Rechenvorrichtung, die irgendwelche der hier offenbarten mikroelektronischen Strukturen enthalten kann.

The embodiments will be readily understood from the following detailed description in conjunction with the accompanying drawings. In order to facilitate this description, the same reference symbols denote the same structural elements. The embodiments are illustrated by way of example and not in a restrictive manner in the figures of the accompanying drawings.

• 1A-1C Fig. 13 are various views of a microelectronic structure containing lines with low line edge roughness (LER) in accordance with various embodiments.
• 2A-2L illustrate the steps in an exemplary process for fabricating the microelectronic structure 1 in accordance with various embodiments.
• 3 FIG. 10 illustrates a stage in another exemplary process for fabricating the microelectronic structure of FIG 1 in accordance with various embodiments.
• 4A-4B Fig. 13 are various views of another microelectronic structure including low lines (LER) in accordance with various embodiments.
• 5A-5D illustrate the steps in an exemplary process for fabricating the microelectronic structure 4th in accordance with various embodiments.
• 6A-6B Fig. 13 are various views of another microelectronic structure including low LER lines in accordance with various embodiments.
• 7A-7H illustrate the steps in an exemplary process for fabricating the microelectronic structure 6th in accordance with various embodiments.
• 8A-8B Figure 13 is various views of a microelectronic structure including low LER lines and high LER lines in accordance with various embodiments.
• 9A-9M illustrate the steps in an exemplary process for fabricating the microelectronic structure 8th in accordance with various embodiments.
• 10A-1 0B are various views of another microelectronic structure including low LER lines in accordance with various embodiments.
• 11A-11H illustrate the steps in an exemplary process for fabricating the microelectronic structure 10 in accordance with various embodiments.
• 12A-12B Figure 13 is various views of another microelectronic structure including low LER lines and high LER lines in accordance with various embodiments.
• 13A-13P illustrate the steps in an exemplary process for fabricating the microelectronic structure 12th in accordance with various embodiments.
• 14A-14B Fig. 13 are various views of another microelectronic structure including low LER lines in accordance with various embodiments.
• 15A-15G illustrate the steps in an exemplary process for fabricating the microelectronic structure 14th in accordance with various embodiments.
• 16A-16B Fig. 13 are various views of another microelectronic structure including low LER lines in accordance with various embodiments.
• 17A-17G illustrate the steps in an exemplary process for fabricating the microelectronic structure 16 in accordance with various embodiments.
• 18th Figure 12 is a top view of a microelectronic structure including low LER lines at multiple spacings, in accordance with various embodiments.
• 19A-19E illustrate the steps in an exemplary process for fabricating the microelectronic structure 18th in accordance with various embodiments.
• 20th FIG. 10 illustrates a stage in another exemplary process for fabricating the microelectronic structure of FIG 18th in accordance with various embodiments.
• 21 Figure 13 is a side cross-sectional view of a microelectronic structure including vias in conductive contact with low LER lines, in accordance with various embodiments.
• 22A-22F illustrate the steps in an exemplary process for fabricating the microelectronic structure 21 in accordance with various embodiments.
• 23 Figure 13 is a side cross-sectional view of another microelectronic structure including vias in conductive contact with low LER lines, in accordance with various embodiments.
• 24A-24C illustrate the steps in an exemplary process for fabricating the microelectronic structure 23 in accordance with various embodiments.
• 25-27 Figure 12 are top views of microelectronic structures containing space-division artifacts, in accordance with various embodiments.
• 28 Figure 13 is a top plan view of a wafer and dies that may include any of the microelectronic structures disclosed herein.
• 29 Figure 4 is a side cross-sectional view of a microelectronic device that may include any of the microelectronic structures disclosed herein.
• 30th Figure 4 is a side cross-sectional view of a microelectronic assembly that may include any of the microelectronic structures disclosed herein.
• 31 Figure 4 is a side cross-sectional view of a microelectronic device that may include any of the microelectronic structures disclosed herein.
• 32 Figure 13 is a block diagram of an exemplary computing device that may include any of the microelectronic structures disclosed herein.

Detailed description

Disclosed herein are structures and techniques that use directed self-assembly (DSA) to fabricate microelectronic devices. The structures and techniques disclosed here can achieve fine feature sizes with low roughness and low defect densities and can be particularly suitable for accompanying and improving extreme ultraviolet (EUV) lithography techniques.

Existing conventional lithography techniques, such as. Existing conventional EUV techniques, such as existing conventional EUV techniques, may not be able to form a pattern of features that are both sufficiently small and sufficiently flawed to be used in commercial microelectronic devices. Conventional EUV lithography can e.g. B. suffer from high roughness and excessive bridging defects at narrow distances (e.g. distances below 32 nanometers), which makes the use of EUV pattern formation techniques (e.g. spacer-based distance-division techniques with protective lacquer defined by EUV lithography) - "Backbones") can limit or effectively prevent. Conventional EUV lithography techniques also suffer from a compromise between the EUV dose and the resist thickness; Although higher EUV doses have the potential to form a pattern of lines with less roughness, such higher EUV doses typically require thinner protective lacquer layers in order to achieve a desired depth of field and avoid pattern collapse, but these thinner protective lacquer layers typically allow etching transfer ( that is, the transfer of a pattern in the protective varnish to one or more underlying layers) cannot withstand as well as thicker protective varnishes. These limitations have provided significant barriers to the adoption of EUV techniques in commercial microelectronic manufacturing processes.

Various of the embodiments disclosed herein can address the shortcomings of conventional EUV lithography techniques through the use of DSA operations. The DSA-based techniques can use the tendency of some materials to organize themselves into certain patterns under certain conditions, which patterns can be used in various ways to identify small and precise features in a microelectronic Manufacture device. It can e.g. For example, various of the embodiments disclosed herein include lines with low line edge roughness (LER) at varying spacings that can be reliably fabricated using DSA-based techniques.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, wherein like reference numerals designate like parts, and in which there are shown, for illustrative purposes, embodiments that may be practiced. It should be recognized that other embodiments can be used and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

Various operations, in turn, can be described as multiple discrete actions or operations in a manner that is most helpful to an understanding of the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily dependent on order. In particular, these operations cannot be performed in the order in which they are displayed. The operations described can be carried out in an order that differs from the embodiment described. In additional embodiments, various additional operations may be performed and / or described operations may be omitted.

For the purposes of the present disclosure, the term "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the term "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A , B and C). The term “A, B or C” means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). The drawings are not necessarily to scale. While many of the drawings illustrate straight line structures with flat walls and right angled corners, this is for ease of illustration only and actual devices made using these techniques will have rounded corners, surface roughness, and other features.

The description uses the terms "in one embodiment" or "in embodiments", each of which may refer to one or more of the same or different embodiments. Furthermore, the terms “comprising”, “containing”, “having” and the like, as used in relation to the embodiments of the present disclosure, are synonymous. As used herein, a “conductive” material refers to an electrically conductive material unless otherwise specified. When the term “between X and Y” is used to describe a range of dimensions, it represents an area that includes X and Y. For convenience, the expression " 1 “Used to refer to the collection of drawings of the 1A-1C to refer, the expression " 2 “Used to refer to the collection of drawings of the 2A-2L , etc. Although mask materials are referred to by different numerals that are repeated between different ones of the drawings (e.g., mask material 126 , Mask material 128 , Mask material 148 etc.), this is for ease of illustration only, with a mask material having a specific reference number referred to in any of the drawings (e.g., the mask material 128 , refer to that in the drawings 7th is referenced), need not be the same mask material as the mask material with the same reference number referred to in another of the drawings (e.g. the mask material 128 , refer to that in the drawings 9 referenced).

1A-1C are various views of an exemplary microelectronic structure 100 who have made the lines 140 contains that have a low LER; on such lines 140 can here as the lines 140 be referenced with a lower LER. 1A Figure 3 is a side cross-sectional view of the microelectronic structure 100 through section AA after 1 B , 1 B Figure 3 is a top view of the microelectronic structure 100 and 1C Figure 4 is a detailed top view of a disordered lamellar structure 138 a microelectronic structure 100 (which is discussed further below). The lines 140 with a low LER 1 can the edges 130 as shown. The term "minor" when referring to lines 140 Used with low LER is a relative term that indicates the LER of the lines 140 with a low LER smaller than the LER of other lines with a "high LER" (e.g. the lines discussed below 170 with high LER). The LER can measure a local deviation of a line edge from its center of mass; In some embodiments, the LER can be quantified as the deviation of the root mean square of a line edge from a line of best fit. In some embodiments, the lines 140 The low LER lines may be those patterned using various of the DSA-based techniques disclosed herein, while the high LER lines may be patterned using conventional ones Techniques (e.g. EUV lithography) can be provided with a pattern. In some embodiments, the LER can be a line 140 with a low LER be less than 1.2 nanometers, while the LER of a line with a high LER can be greater than 1.2 nanometers; in other embodiments, the LER may be a line 140 with a low LER can be smaller than 1.5 nanometers, while the LER of a line with a high LER can be larger than 1.5 nanometers, but these are simply examples, with different LERs (e.g. depending on the distance and the process) -Threshold values may apply. In some embodiments, the microelectronic structure can 100 after 1 be part of an interconnection layer in a microelectronic device (such as, for example, below with regard to 29 will be discussed).

The microelectronic structure 100 after 1 contains several lines 140 with a low LER resulting from parallel arrangements of the line material 120 through a dielectric material 102 are trained. The line material 120 may contain one or more layers of different materials, such as e.g. B. one or more layers of a lining material and a filling material. In some embodiments, a lining material may contain tantalum, tantalum nitride, titanium, titanium nitride, cobalt or ruthenium (e.g. combinations thereof), while a filler material may contain tungsten, cobalt (e.g. as cobalt silicide), ruthenium, molybdenum, copper, silver, Nickel (e.g., as nickel silicide), gold, aluminum, other metals or alloys, or other combinations of the materials. The dielectric material 102 may contain any suitable dielectric material. In some embodiments, the dielectric material can 102 z. B. contain an inorganic dielectric material such. B. silicon oxide, a carbon-doped oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, or insulating metal oxides, such as. B. hafnium oxide and zirconium oxide. In some embodiments, the dielectric material can 102 a porosity that is less than 50% (e.g. less than 30%) and / or have air gaps. In some embodiments, the distance can 172 of the lines 140 with a lower LER less than 30 nanometers (e.g. less than 24 nanometers), the line width 174 one line 140 with a low LER can be smaller than 15 nanometers (e.g. smaller than 12 nanometers) and / or the space between adjacent lines 140 with a low LER, be smaller than 15 nanometers (e.g. smaller than 12 nanometers).

The lines 140 with a low LER can be part of a patterned area 142 be, with the microelectronic structure 100 also one or more unpatterned areas 144 may contain. In some embodiments, when DSA-based techniques are used, the microelectronic structure 100 to produce, (such as in the following with regard to 2 the unpatterned areas 144 a disordered lamellar structure 138 like those included in 1C is illustrated. The disordered lamellar structure 138 can the line material 120 and the dielectric material 102 which is patterned according to the disordered lamellar structure of a DSA material, which was created during previous patterning operations (e.g. due to the lack of a patterned brush material over the unpatterned areas 144 as below regarding 2 is discussed) has not adopted an orderly structure. The presence of a disordered lamellar structure 138 like the one in 1C is illustrated in an unpatterned area 144 a microelectronic structure 100 may utilize a DSA-based technique during fabrication of the patterned area 142 indicate. The unpatterned area 144 may, in some embodiments, be part of a transition region of a die that comprises the microelectronic structure 100 are located under a guard ring of a die that defines the microelectronic structure 100 contains, or are in a frame of a die that forms the microelectronic structure 100 contains, (e.g. any of the dies 1502 , which are referred to below regarding 28 will be discussed).

the 2A-2L illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 1 in accordance with various embodiments. Although the operations of the procedure after 2 (and others of the methods disclosed herein) with respect to particular embodiments of the microelectronic structures disclosed herein 100 can be illustrated, the method according to 2 (and others of the methods disclosed herein) for making any suitable microelectronic structures 100 be used. The operations are each once and in a special order in 2 (and others of the drawings describing the methods disclosed herein), but the operations may be rearranged and / or repeated as appropriate (e.g. with different operations performed in parallel when multiple microelectronic structures 100 produced at the same time).

2A Figure 4 is a side cross-sectional view of an assembly containing a dielectric material 102 , a mask material 104 , a mask material 106 and a mask material 108 contains. In some embodiments, the mask material can 104 Contain titanium nitride. In some embodiments, may the mask material 106 Contain silicon nitride, silicon oxide or a silicon anti-reflective coating. In some embodiments, the mask material can 108 be a carbon-based hard mask or contain amorphous silicon. The specific number and arrangement of the mask materials, which are in the arrangement according to 2A (and others of the accompanying drawings) are simply illustrative and more or fewer mask materials can be arranged in any desired manner in accordance with the techniques disclosed herein.

2 B Figure 13 is a side cross-sectional view of an assembly subsequent to the formation of an initial brush 110 on the mask material 108 according to the arrangement 2A . The initial brush 110 may include a material that serves as a template for the DSA of a block copolymer (BCP), as described below, and, in some embodiments, may include one or more of the components of the BCP. For ease of discussion, the DSA-based techniques disclosed herein can rely on a BCP (e.g., the BCP discussed below 114 ) refer to the two components, a first component 116 and a second component 118 However, this is simply illustrative and a BCP having more than two components can be used in any of the techniques disclosed herein. An example of a BCP that is called the BCP 114 May serve in the operations disclosed herein is polystyrene-co-poly (methyl methacrylate) (PS-PMMA); when the BCP 114 PS-PMMA is can be the first component 116 Polystyrene (PS) while the second component 118 Polymethyl methacrylate (PMMA) can be. As mentioned above, the DSA-based techniques disclosed herein can use a brush 110 use one or more of the first component 116 and the second component 118 of a BCP 114 but is also simply illustrative, with any suitable material or materials in a brush 110 (e.g. materials that are not components of the BCP, those of the DSA on the brush 110 may be included. 2 B (and others of the accompanying drawings) can use a brush 110 illustrate the the first component 116 contains. Though the brush 110 it is illustrated as being the first component 116 contains, the brush can 110 also contain other materials as appropriate (the brush can 110 z. B. the second component 118 instead of or in addition to the first component 116 contain or can the brush 110 contain one or more materials that are different from the first component 116 and the second component 118 differentiate). As used herein, a “brush” can refer to any material that promotes the self-assembly of a DSA material thereon, and can include large polymers, small polymers, self-assembled monolayers (SAMs), and other suitable materials.

2C Figure 4 is a side cross-sectional view of an assembly subsequent to the initial brush patterning 110 according to the arrangement 2 B to the openings 178 in the brush 110 to build. The places of the openings 178 can choose the desired locations of the lines 140 with low LER in a microelectronic structure 100 correspond, although the roughness of the edges 130 of the openings 178 in the arrangement according to 2C cannot be “minor” as discussed below. In some embodiments, the brush can 110 even photolithographically provided with a pattern (the brush 110 z. B. be treated selectively to improve the properties of the brush 110 to change in accordance with a desired pattern, then parts of the brush 110 removed by appropriate etching or rinsing to provide the desired pattern). In some embodiments, the brush can 110 contain a component that can be subjected to chain cleavage reactions when exposed to photon or electron radiation (e.g. a PMMA protective lacquer). In other such embodiments, the brush 110 contain a surface anchoring group that can be cleaved by photon or electron irradiation or by reaction with a subsequent photoacid or base. In other embodiments, the brush 110 are subjected to a polarity change during photon or electron irradiation; Such a polarity change can produce either a 2-tone or a 3-tone brush contrast depending on the effect of the edge broadening. In other embodiments, the brush 110 patterned by applying a photoresist material (not shown), patterning the photoresist material, the pattern of the photoresist material into the brush 110 is transferred and then the photoresist material is removed. 2D FIG. 13 is a top plan view of the arrangement of FIG 2C that are the edges 130 of the openings 178 in the brush 110 illustrated. The illustration after 2C is by the section CC after 2D taken. As mentioned above, the openings 178 highly rough edges 130 exhibit; in case the pattern of openings 178 into the dielectric material 102 would be transferred and the transferred openings with the line material 120 were filled, the resulting lines would be similarly rough and thus would become lines with high LER (e.g., the lines discussed below with high LER 170 ) be.

2E Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a BCP 114 on the arrangement according to the 2C and 2D . As mentioned above, the brush can 110 and the BCP 114 be chosen to achieve a desired DSA behavior, as in the following with respect to 2F is discussed. In the embodiment according to 2 can the BCP 114 as mentioned above, a first component 116 and one (in 2E not shown) second component 118 contain.

2F FIG. 14 is a side cross-sectional view of an assembly following the treatment of the assembly of FIG 2E to get the BCP 114 to cause yourself to be in accordance with that by the brush 110 to organize the provided template yourself. In the special embodiment according to 2F contains the self-organization of the BCP 114 the self-segregation of its first component 116 and its second component 118 in ribbons that alternate vertically oriented areas of the first component 116 and the second component 118 in the patterned area 142 form. The dimensions and spacing of the openings 178 in the brush 110 can be chosen to match the size and spacing of the bands of the second component 118 of the BCP 114 as shown, while the dimensions and spacing of the first component 116 in the brush 110 may be chosen to match the size and spacing of the bands of the first component 116 of the BCP 114 match so the brush 110 a “template” for the self-organization of the BCP 114 provides the self-organized BCP 114 as desired with respect to the underlying brush 110 aligns. A BCP 114 may be able to take care of a nominal "inherent" space between the self-organized ligaments of the first component 116 / second component 118 to "stretch" or "shrink", which are both a range of dimensions of the self-assembled ligaments of the first component 116 / second component 118 as well as some tolerance to deviations in the pattern formation of the brush 110 made possible by their intended pattern. In the 2F The particular ribbon-like self-assembly illustrated is an example of a pattern that a BCP 114 can organize yourself; being some BCPs 114 Organize itself into other patterns, with different BCPs 114 self-organize into several different patterns under different conditions, as discussed below. Outside the patterned area 142 can the brush 110 do not provide a surface on which the BCP 114 easily in alternating vertically oriented areas of the first component 116 and the second component 118 organized itself, so instead the BCP 114 in the unpatterned areas 144 in disordered slats 132 the first component 116 and the second component 118 can organize yourself; the disordered slats 132 may have a structure like that shown in 1C is illustrated.

2G Figure 13 is a side cross-sectional view of an assembly following removal of the second component 118 according to the arrangement 2F . The first component 116 can remain in place, consequently the patterned area 142 a series of parallel openings 180 may contain. In some embodiments, the arrangement may be according to 2F treated with an ion implantation technique to make the first component 116 (e.g. PS) before removing the second component 118 (e.g. PMMA) to harden. In some embodiments, a suitable selective etching technique can be used to the second component 118 to remove while the first component 116 left in place. The removal of the second component 118 from the disordered slats 132 the unpatterned areas 144 can lead to partially etched disordered lamellae 134 that can maintain a structure like that found in 1C is illustrated. 2H FIG. 13 is a top plan view of the arrangement of FIG 2G that are the edges 130 of the openings 180 in the first component 116 illustrated. The illustration after 2G is through the section GG after 2H taken. These openings 180 can edges 130 with low LER; in case the pattern of openings 180 into the dielectric material 102 would be transferred (as discussed below) and the transferred openings with a conduit material 120 would be filled (as discussed below), the resulting lines are similarly rough, thus becoming lines with low LER 140 are. The process of performing a DSA-based technique on the "rough" openings 178 according to the arrangement 2D can lead to "smooth" openings 180 according to the arrangement 2H lead, and consequently it can be said that technology is based on 2 (and other of the DSA-based techniques disclosed herein) the "rough" openings 178 "Straightened". The ability of the DSA-based techniques disclosed herein to straighten rough lithographic features may enable lower dose EUV lithography to be used for fabrication; Because the additional roughness associated with EUV lithography with a lower dose (with respect to EUV lithography with a higher dose) can be eliminated by DSA operations, the advantages of EUV lithography with a lower dose (e.g. the ability to use thicker conformal lacquer materials) without the conventionally associated roughness disadvantage.

2I Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of openings 180 according to the order of the 2G and 2H into the one below Mask material 108 . Any suitable etching technique can be used. Transferring the pattern of the openings 180 into the mask material 108 can also transfer the disordered lamellar pattern of the partially etched disordered lamellae 134 in the unpatterned areas 144 into the underlying mask material 108 lead what the mask material provided with a pattern of disordered lamellas 136 supplies.

2Y Figure 4 is a side cross-sectional view of an assembly following removal of the first component 116 according to the arrangement 21 . Any suitable selective etching technique can be used (e.g. if the first component 116 PS, an ash technique can be used).

2K Figure 13 is a side cross-sectional view of an assembly subsequent to performing a side etch on the mask material 108 after 2Y to adjust the lateral size of the sections of mask material 108 to reduce and thereby the distance between adjacent sections of the mask material 108 to enlarge. This etching can be controlled in order to achieve a desired spacing between adjacent sections of the mask material. In some embodiments, the width can be 111 a portion of the mask material 108 between 10 nanometers and 12 nanometers.

2L Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of mask material 108 / of the mask material provided with a pattern of disordered lamellae 136 (through the mask materials in between 104 and 106 which are subsequently removed) into the dielectric material 102 according to the arrangement 2K and then the provision of line material 120 in the openings of the dielectric material 102 to the lines 140 to form with low LER. The pattern of the mask material provided with a pattern of disordered lamellas 136 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. The arrangement according to 2L can take the shape of the microelectronic structure 100 after 1 accept.

As mentioned above, a brush can 110 in some embodiments, include multiple different materials arranged in a desired pattern. 3 illustrates e.g. B. an arrangement following the deposition of the second component 118 in the openings 178 the brush 110 according to the arrangement 2C . The above regarding the 2E-2L operations discussed can be based on the arrangement 3 run to the microelectronic structure 100 after 1 to build. Using several different materials in one brush 110 can be a stronger "template" for the BCP 114 provide and can thereby improve the resulting self-organization and the lines 140 with a lower LER with an even lower LER.

In some embodiments, spacer-based techniques can be used to reduce the spacing 172 of the lines 140 with low LER in a patterned area 142 further decrease. the 4A-4B are z. B. different views of another microelectronic structure 100 , the lines 140 with low LER, in accordance with various embodiments. 4A Figure 3 is a side cross-sectional view of the microelectronic structure 100 through section AA after 4B , and 4B Figure 3 is a top view of the microelectronic structure 100 ; being the disordered lamellar structure 138 the microelectronic structure 100 after 4th in the 1C may take the illustrated form. The embodiment according to 4th uses a number of elements with the embodiment of FIG 1 together; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. With regard to the embodiment according to 1 can use the lines 140 with low LER according to the embodiment 4th a smaller distance 172 , a smaller line width 174 and / or a smaller gap 176 exhibit.

the 5A-5D illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 4th in accordance with various embodiments. 5A Figure 13 is a side cross-sectional view of an assembly subsequent to the formation of the spacers 124 on the side surfaces of the patterned mask material 108 according to the arrangement 2K . The spacers 124 may contain a dielectric material and can be deposited around the dielectric material using any suitable spacer technique (e.g., conformally depositing the dielectric material, such as by atomic layer deposition (ALD), followed by a "downward" etch horizontal surfaces and leave the dielectric material in place on the side surfaces).

5B Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition and patterning of a mask material 182 on the arrangement according to 5A to get the mask material 108 near the with a disordered lamellar pattern provided mask material 136 to cover, and then removing the remaining mask material 108 . Any suitable mask material can be used 182 , any suitable deposition techniques, any suitable patterning techniques, and any suitable etching techniques can be used.

5C Figure 13 is a side cross-sectional view of an assembly subsequent to the transfer of the pattern of mask material 108 / disordered lamellar patterned mask material 136 (through the mask materials in between 104 and 106 which are subsequently removed) into the dielectric material 102 according to the arrangement 5B and then the provision of line material 120 in the openings of the dielectric material 102 to the lines 140 to form with low LER. The pattern of the mask material provided with a disordered lamellar pattern 136 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. 5D FIG. 13 is a top plan view of the arrangement of FIG 5C that are the edges 130 of the lines 140 illustrated with low LER. The illustration after 5C is by the section CC after 5D taken. The arrangement according to the 5C and 5D can take the shape of the microelectronic structure 100 after 4th accept.

Spacer-based techniques can be used to fill in the gap 176 between the lines 140 with low LER in a microelectronic structure 100 in other ways to decrease. the 6A-6B are z. B. different views of another microelectronic structure 100 who have made the lines 140 with low LER, in accordance with various embodiments. 6A Figure 3 is a side cross-sectional view of the microelectronic structure 100 through section AA after 6B , and 6B Figure 3 is a top view of the microelectronic structure 100 ; being the disordered lamellar structure 138 the microelectronic structure 100 after 6th in the 1C may take the illustrated form. The embodiment according to 6th shares a number of elements with previous embodiments; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. With regard to the embodiment according to 1 can use the lines 140 with low LER according to the embodiment 6th a smaller gap 176 exhibit.

the 7A-7H illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 6th in accordance with various embodiments. 7A Figure 13 is a side cross-sectional view of an assembly subsequent to the provision and patterning of a mask material 128 in the unpatterned areas 144 an arrangement corresponding to that according to 2G is essentially similar, but with additional openings for illustrative purposes 180 between the outermost sections of the first component 116 and the disordered slats 132 . Any suitable mask material can be used 128 be used.

7B Figure 13 is a side cross-sectional view of an assembly subsequent to the formation of the spacers 124 on side faces of the first component 116 according to the arrangement 7A . The spacers 124 can take any of the forms disclosed herein.

7C Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a mask material 126 above the arrangement according to 7B . In some embodiments, the mask material can 126 contain amorphous silicon. The mask material 126 can open the openings in the disordered slats 132 fill in, being a lamellar material 184 is formed.

7D FIG. 13 is a side cross-sectional view of an assembly subsequent to the assembly of FIG 7C to avoid overloading the mask material 126 to remove. In some embodiments, a chemical mechanical polishing (CMP) technique can be used.

7E Figure 4 is a side cross-sectional view of an assembly following removal of the first component 116 and the spacer 124 according to the arrangement 7D . Any suitable selective etching technique (s) can be used (e.g., if the first component) 116 PS, an ash technique can be used). The removal of the first component 116 from the lamellar material 184 may result in the partially etched lamellar material 186 lead that a structure like that after 1C may have.

7F Figure 13 is a side cross-sectional view of an assembly subsequent to transferring the pattern of the partially etched lamellar material 186 / Mask material 126 according to the arrangement 7E into the mask material 108 . Transferring the pattern may include transferring the disordered lamellar patterns of the partially etched lamellar material 186 into the underlying mask material 108 in the unpatterned areas 144 contain what that disordered with mask material provided with a lamellar pattern 136 supplies.

7G Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of mask material 108 / of the mask material provided with a disordered lamellar pattern 136 according to the arrangement 7F (through the mask materials in between 104 and 106 which are subsequently removed) into the dielectric material 102 and then the provision of line material 120 in the openings of the dielectric material 102 to the lines 140 to form with low LER. The pattern of the mask material provided with a disordered lamellar pattern 136 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. 7H FIG. 13 is a top plan view of the arrangement of FIG 7G that are the edges 130 of the lines 140 illustrated with low LER. The illustration after 7G is through the section GG after 7H taken. The arrangement according to the 7G and 7H can take the shape of the microelectronic structure 100 after 6th accept.

In some embodiments, a microelectronic structure 100 the lines 140 with low LER and the lines 170 with high LER included. the 8A-8B are z. B. different views of another microelectronic structure 100 , the lines 140 with low LER, in accordance with various embodiments. 8A Figure 3 is a side cross-sectional view of the microelectronic structure 100 through section AA after 8B , and 8B Figure 3 is a top view of the microelectronic structure 100 ; being the disordered lamellar structure 138 the microelectronic structure 100 after 8th in the 1C may take the illustrated form. The embodiment according to 8th shares a number of elements with the previous embodiments; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. With regard to the embodiment according to 1 contains the microelectronic structure 100 after 8th a first patterned area 142-1 , the lines 140 with low LER, and a second patterned area 142-2 , the one (as shown) or multiple lines 170 with high LER contains.

As mentioned above, in some embodiments, the lines or the other features patterned by DSA-based techniques may differ from the lines or the other features identified by lithographic techniques (e.g., EUV lithography techniques ) have been provided with a pattern, can be distinguished by their LER; in particular, the lines or other features patterned by the DSA-based techniques disclosed herein may have a lower LER than the lines or other features patterned by lithographic techniques. Other markings may distinguish the lines or other features patterned by the DSA-based methods disclosed herein from the lines or other features patterned by lithographic techniques. In some embodiments, e.g. For example, the lines or other features patterned by conventional lithographic processes (e.g. EUV lithography techniques) have a line width roughness (LWR) equal to the LER of those lines or other features multiplied by that Square root of 2, is. This “lithographic property” may not apply to lines or other features that have been patterned by the DSA-based methods disclosed herein, and consequently the presence of this lithographic property may indicate whether a feature is using conventional lithographic techniques or not the DSA-based method disclosed herein has been patterned.

the 9A-9M illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 8th in accordance with various embodiments. 9A Figure 13 is a side cross-sectional view of an arrangement like the one in accordance with the present invention 2C who have favourited a patterned starter brush 110 contains. The arrangement according to 9A can be in accordance with any of the here regarding 2C discussed manufacturing techniques are formed. Like the arrangement after 2C can use the openings 178 in the first patterned area 142-1 the first component 116 may be formed as a pattern using lithographic techniques and consequently may have highly rough edges.

9B Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a BCP 114 on the arrangement according to 9A . The brush 110 and the BCP 114 can be chosen to achieve a desired behavior when the BCP 114 on the brush 110 self organized. In the embodiment according to 9 can the BCP 114 a first component 116 and a second component 118 contain.

9C FIG. 14 is a side cross-sectional view of an assembly subsequent to treating FIG Arrangement according to 9B to cause the BCP 114 in accordance with that by the brush 110 provided template organized by yourself. As above regarding 2 As discussed, the resulting arrangement can include alternating vertically oriented regions of the first component 116 and the second component 118 in the first patterned area 142-1 contain. Outside the first patterned area 142-1 can the brush 110 do not provide a surface on which the BCP 114 easily in alternating vertically oriented areas of the first component 116 and the second component 118 organized itself so that the BCP instead 114 in the unpatterned area 144 and the second patterned area 142-2 into the disordered slats 132 the first component 116 and the second component 118 can organize yourself; being the disordered lamellae 132 may have a structure like that shown in 1C is illustrated.

9D Figure 13 is a side cross-sectional view of an assembly following removal of the second component 118 according to the arrangement 9C . The first component 116 can remain in place, thus the first patterned area 142-1 a series of parallel openings 180 may contain. In some embodiments, the arrangement may be according to 9C treated with an ion implantation technique to make the first component 116 (e.g. PS) before removing the second component 118 (e.g. PMMA) to harden. in some embodiments, a suitable selective etching technique can be used to the second component 118 to remove. The removal of the second component 118 from the disordered slats 132 can lead to the partially etched disordered lamellae 134 that can maintain a structure like that found in 1C is illustrated. As above regarding the 2G and 2H As discussed, the process of performing a DSA operation on the "rough" openings 178 according to the arrangement 9A to the "smooth" openings 180 according to the arrangement 9D lead, and consequently it can be said that technology is based on 9 (and other of the DSA-based techniques disclosed herein) the "rough" openings 178 "Straightened".

9E Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition and patterning of a mask material 148 on the arrangement according to 9D to reveal the partially etched disordered lamellae 134 in the second patterned area 142-2 to cover. Any suitable mask material can be used 148 and any suitable patterning technique can be used.

9F Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of openings 180 according to the arrangement 9E into the underlying mask material 108 . Any suitable etching technique can be used. Transferring the pattern of the openings 180 into the mask material 108 can also be used to transfer the disordered lamellar pattern of the exposed partially etched disordered lamellae 134 into the underlying mask material 108 in the unpatterned area 144 lead what the mask material provided with a disordered lamellar pattern 136 supplies.

9G Figure 13 is a side cross-sectional view of an assembly following removal of the mask material 148 according to the arrangement 9F and then removing the first component 116 . Any suitable selective etching techniques can be used (e.g. if the first component 116 PS, an ash technique can be used).

9H Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a mask material 128 on the arrangement according to 9G . Any suitable mask material can be used 128 be used.

9I Figure 13 is a side cross-sectional view of an assembly subsequent to the formation of the pattern of the mask material 128 in the second patterned area 142-2 to make an opening 188 to form that of the line 170 with a high LER 8th is equivalent to. In some embodiments, the opening 188 may be formed using lithographic techniques and consequently may have rough edges.

9Y Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of mask material 128 according to the arrangement 9I into the mask material 108 and the mask material 106 . Any suitable etching techniques can be used.

9K Figure 13 is a side cross-sectional view of an assembly following removal of the mask material 128 according to the arrangement 9Y . Any suitable etching technique can be used.

9L Figure 13 is a side cross-sectional view of an assembly subsequent to transferring the pattern of mask material 108 / disordered lamellar patterned mask material 136 (through the mask materials in between 104 and 106 which are subsequently removed) into the dielectric material 102 and then the provision of line material 120 in the openings of the dielectric material 102 to the lines 140 with low LER and the line 170 with high LER form. The pattern of the mask material provided with a disordered lamellar pattern 136 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. 9M FIG. 13 is a top plan view of the arrangement of FIG 9L that are the edges 130 of the lines 140 with low LER and the line 170 illustrated with high LER. The illustration after 9L is through the section LL after 9M taken. The arrangement according to the 9L and 9M can take the shape of the microelectronic structure 100 after 8th accept.

In some embodiments, the gap can 176 between adjacent lines 140 with low LER can be enlarged by selective depopulation using a DSA-based technique. the 10A-10B are z. B. different views of another microelectronic structure 100 , the lines 140 with low LER, in accordance with various embodiments. 10A Figure 3 is a side cross-sectional view of the microelectronic structure 100 through section AA after 10B , and 10B Figure 3 is a top view of the microelectronic structure 100 ; being the disordered lamellar structure 138 the microelectronic structure 100 after 10 in the 1C may take the illustrated form. The embodiment according to 10 shares a number of elements with previous embodiments; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. With regard to the embodiment according to 1 contains the microelectronic structure 100 after 10 smaller interline gaps 150-1 and larger interline gaps 150-2 between adjacent lines 140 with low LER. The special arrangement of smaller interline spaces 150-1 and larger interline spaces 150-2 is simply illustrative of any desired arrangement in a microelectronic structure 100 may be included in accordance with the techniques disclosed herein.

the 11A-11H illustrate the steps in an exemplary process for fabricating the microelectronic structure 10 in accordance with various embodiments. 11A FIG. 13 is a side cross-sectional view of an arrangement like that of FIGS 2C and 9A who have favourited a patterned starter brush 110 contains. The arrangement according to 11A can be in accordance with any of the here regarding 2C discussed manufacturing techniques. Like the arrangement after 2C can use the openings 178 using lithographic techniques in the first component 116 can be formed as a pattern, and consequently they may have highly rough edges.

11B Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a BCP (e.g., a BCP, not shown 114 as discussed above) on the arrangement 11A and then treating the resulting assembly to cause the BCP to conform to that provided by the brush 110 provided template organized by yourself. The resulting arrangement contains alternating vertically oriented areas of the first component 116 and the second component 118 in the patterned area 142 . Outside the patterned area 142 can the brush 110 do not provide a surface on which the BCP can easily turn into alternating vertically oriented areas of the first component 116 and the second component 118 organized itself, which is why the BCP 114 instead, in the unpatterned area 144 into disordered slats 132 the first component 116 and the second component 118 can organize yourself; being the disordered lamellae 132 may have a structure like that shown in 1C is illustrated.

11C Figure 13 is a side cross-sectional view of an assembly following removal of the second component 118 according to the arrangement 11 B . The first component 116 can be left in place, leaving the patterned area 142 a series of parallel openings 180 may contain. In some embodiments, the arrangement may be according to 11B treated with an ion implantation technique to make the first component 116 (e.g. PS) before removing the second component 118 (e.g. PMMA) to harden. In some embodiments, a suitable selective etching technique can be used to the second component 118 to remove. The removal of the second component 118 from the disordered slats 132 can lead to the partially etched disordered lamellae 134 that can maintain a structure like that found in 1C is illustrated. As above regarding the 2G and 2H As discussed, the process of performing a DSA operation on the "rough" openings 178 according to the arrangement 11A to the "smooth" openings 180 according to the arrangement 11C lead, and consequently it can be said that technology is based on 11th (and other of the DSA-based techniques disclosed herein) the "rough" openings 178 "Straightened".

1 Figure 1D is a side cross-sectional view of a post-deposition assembly of a mask material 128 above the arrangement according to 11C . Any suitable mask material can be used 128 be used.

11E Figure 13 is a side cross-sectional view of an assembly subsequent to the patterning of the mask material 128 according to the arrangement 11D to the openings 180 to be covered in an area corresponding to the larger interline gap 150-2 between adjacent lines 140 with a low LER. Any suitable patterning technique can be used.

11F Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of exposed openings 180 according to the arrangement 11E into the underlying mask material 108 . Any suitable etching technique can be used. Transferring the pattern of the openings 180 into the mask material 108 can also be used to transfer the disordered lamellar pattern of the exposed partially etched disordered lamellae 134 into the underlying mask material 108 in the unpatterned area 144 lead what the mask material provided with a disordered lamellar pattern 136 supplies.

11G Figure 13 is a side cross-sectional view of an assembly following removal of the mask material 128 according to the arrangement 11 F. , the transfer of the pattern of the mask material 108 / of the mask material provided with a disordered lamellar pattern 136 (through the mask materials in between 104 and 106 which are subsequently removed) into the dielectric material 102 and then the provision of line material 120 in the openings of the dielectric material 102 to the lines 140 to form with low LER. The pattern of the mask material provided with a disordered lamellar pattern 136 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. 11H FIG. 13 is a top plan view of the arrangement of FIG 11G that are the edges 130 of the lines 140 with low LER, the smaller interline gaps 150-1 and a greater interline gap 150-2 illustrated. The illustration after 11G is through the section GG after 11H taken. The arrangement according to the 11G and 11H can take the shape of the microelectronic structure 100 after 10 accept.

the 1-24 illustrate exemplary microelectronic structures 100 and examples of the methods of manufacturing such microelectronic structures 100 . Each of the characteristics relating to any of the 1-24 discussed here can be combined with any other feature to form a microelectronic structure 100 to build. the 3 and 4th illustrate z. B. one embodiment in which spacer-based techniques are used to adjust the spacing of conduits 140 with low LER to decrease that 8th and 9 illustrate an embodiment that includes both conduits 140 with low LER as well as lines 170 with high LER contains, and the 10 and 11th illustrate an embodiment in which the spacing between different pairs of adjacent lines 140 with low LER is enlarged by selective depopulation. These characteristics according to the 3 , 4th , 8th , 9 , 10 and 11th can be combined so that a microelectronic structure 100 cables 140 with low LER with reduced spacing, both lines 140 with low LER as well as lines 170 with high LER and increased spaces between different pairs of lines 140 with low LER. Such an embodiment of a microelectronic structure 100 is in 12th Fig. 9 illustrates a process for fabricating the microelectronic structure 100 after 12th in 13th is illustrated. However, this particular combination is simply an example, and any combination can be used.

As mentioned above, the 12A-12B different views of another microelectronic structure 100 , the lines 140 with low LER and lines 170 with high LER, in accordance with various embodiments. 12A Figure 3 is a side cross-sectional view of the microelectronic structure 100 through section AA after 12B , and 12B Figure 3 is a top view of the microelectronic structure 100 ; being the disordered lamellar structure 138 the microelectronic structure 100 after 12th in the 1C may take the illustrated form. The embodiment according to 12th shares a number of elements with the previous embodiments; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. With regard to the embodiment according to 1 contains the microelectronic structure 100 cables 140 with low LER with reduced spacing, both lines 140 with low LER as well as lines 170 with a high LER and an enlarged gap 176 between different pairs of lines 140 with low LER.

the 13A-13P illustrate the steps in an exemplary process for fabricating the microelectronic structure 12th in accordance with various embodiments. 13A Fig. 3 is a side cross-sectional view an arrangement like that after the 2C , 9A and 11A who have favourited a patterned starter brush 110 contains. The arrangement according to 13A can be in accordance with any of the here regarding 2C discussed manufacturing techniques. As with the arrangement after 2C can use the openings 178 using lithographic techniques in the first component 116 can be formed as a pattern, and consequently they may have highly rough edges.

13B Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a BCP (e.g., a BCP, not shown 114 as described above) on the arrangement 13A and then treating the resulting assembly to cause the BCP to conform to that provided by the brush 110 provided template organized by yourself. The resulting arrangement contains alternating vertically oriented areas of the first component 116 and the second component 118 in the patterned area 142 . Outside the patterned area 142 can the brush 110 do not provide a surface on which the BCP can easily turn into alternating vertically oriented areas of the first component 116 and the second component 118 organized itself so that the BCP instead 114 in the unpatterned area 144 in disordered slats 132 the first component 116 and the second component 118 can organize yourself; being the disordered lamellae 132 may have a structure like that shown in 1C is illustrated.

13C Figure 13 is a side cross-sectional view of an assembly following removal of the second component 118 according to the arrangement 13B . The first component 116 can remain in place, consequently the patterned area 142 a series of parallel openings 180 may contain. In some embodiments, the arrangement may be according to 13B treated with an ion implantation technique to make the first component 116 (e.g. PS) before removing the second component 118 (e.g. PMMA) to harden. In some embodiments, a suitable selective etching technique can be used to the second component 118 to remove. The removal of the second component 118 from the disordered slats 132 can lead to the partially etched disordered lamellae 134 lead that have a structure like that after 1C can maintain. As above regarding the 2G and 2H As discussed, the process of performing a DSA operation on the "rough" openings 178 according to the arrangement 13A to the "smooth" openings 180 according to the arrangement 13C lead, and consequently it can be said that technology is based on 13th (and the other of the DSA-based techniques disclosed herein) the "rough" openings 178 "straighten".

13D Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of openings 180 according to the arrangement 13C into the underlying mask material 108 . Any suitable etching technique can be used. Transferring the pattern of the openings 180 into the mask material 108 can also transfer the disordered lamellar pattern of the partially etched disordered lamellae 134 into the underlying mask material 108 in the unpatterned area 144 lead what the mask material provided with a disordered lamellar pattern 136 supplies.

13E Figure 4 is a side cross-sectional view of an assembly following removal of the first component 116 (and consequently the partially etched disordered lamellae 134 ) from the arrangement 13D . It can be any suitable etching technique (e.g. an ash technique if the first component 116 PS contains).

13F Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a mask material 128 above the arrangement according to 13E and providing the mask material 128 with a pattern to the mask material 108 (and consequently the mask material provided with a disordered lamellar pattern 136 ) in the unpatterned area 144 and the first patterned area 142-1 to cover while the mask material 108 in the second patterned area 142-2 is exposed. Any suitable mask material can be used 128 be used.

13G Figure 13 is a side cross-sectional view of an assembly following removal of the exposed mask material 108 (in the second patterned area 142-2 ) according to the arrangement 13F . Any suitable etching technique can be used.

13H Figure 13 is a side cross-sectional view of an assembly following removal of the mask material 128 according to the arrangement 13G and forming the spacers 124 on the side surfaces of the remaining patterned mask material 108 . The spacers 124 may contain a dielectric material and can be made using any known spacer technique (e.g., conformal deposition of the dielectric material followed by a "downward" etch to remove the dielectric material on the horizontal surfaces and remove the dielectric material on the To leave side surfaces in place).

13I Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition and patterning of a mask material 148 on the arrangement according to 13H to selectively desired portions of the mask material 108 , the gaps between the mask material 108 and the portions of mask material 106 in the second patterned area 142-2 cover as shown. Any suitable mask material can be used 148 and any suitable selective etching technique can be used. The openings 188 in the mask material 128 in the second patterned area 142-2 correspond to lines with a high LER 170 after 12th . In some embodiments, the openings 188 may be formed using lithographic techniques and consequently may have rough edges.

13Y Figure 13 is a side cross-sectional view of an assembly subsequent to transferring the pattern of mask material 108 / spacer material 124 / mask material 148 according to the arrangement 13I into the underlying mask material 106 . Any suitable selective etching technique can be used. The pattern of the mask material provided with a disordered lamellar pattern 136 can in the mask material 106 in the unpatterned area 144 what the mask material provided with a disordered lamellar pattern 146 supplies.

13K Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a mask material 182 on the arrangement according to 13Y and then the recessing of the mask material 182 to remove the tops of the mask material 108 (and therefore the mask material provided with a disordered lamellar pattern 136 ) and the spacers 124 to expose. Any suitable mask material can be used 182 and any suitable recess technique can be used.

13L Figure 13 is a side cross-sectional view of an assembly following removal of the exposed mask material 108 (and therefore the mask material provided with a disordered lamellar pattern 136 ) according to the arrangement 13K , with the underlying mask material 106 is selectively exposed. Any suitable selective etching technique can be used.

13M Figure 13 is a side cross-sectional view of an assembly following removal of the exposed mask material 106 according to the arrangement 13L . Any suitable selective etching technique can be used.

13N Figure 13 is a side cross-sectional view of an assembly following removal of the spacers 124 and the mask material 182 according to the arrangement 13M . Any suitable selective etching techniques can be used.

13O Figure 13 is a side cross-sectional view of an assembly following the transfer of the pattern of mask material 106 / of the mask material provided with a disordered lamellar pattern 146 according to the arrangement 13N (through the mask material in between 104 which is subsequently removed) into the dielectric material 102 and then the provision of line material 120 in the openings of the dielectric material 102 to the lines 140 with low LER and the lines 170 with high LER form. The pattern of the mask material provided with a disordered lamellar pattern 146 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. 13P FIG. 13 is a top plan view of the arrangement of FIG 13O that both the edges 130 of the lines 140 with low LER and the line 170 with high LER as well as the selectively variable link gaps. The illustration after 13O is through the section OO after 13P taken. The arrangement according to the 13O and 13P can take the shape of the microelectronic structure 100 after 12th accept.

As mentioned above, a BCP may be able to organize itself into several different arrangements. For example, a BCP may be capable of forming both the vertically oriented repeating structures illustrated in several of the preceding drawings and horizontally oriented repeating structures. Whether such a BCP forms a vertically oriented repeating structure, a horizontally oriented repeating structure or a disordered structure can be determined by the pattern of the underlying brush 110 , the composition of the BCP and the conditions under which the BCP is subjected to the DSA; these variables can be adjusted to achieve a desired result. The ability to form horizontally oriented repeating structures can be used to create lines 140 with low LER to produce the different line widths 174 exhibit. the 14A-14B are z. B. different views of another microelectronic structure 100 who have made the lines 140 with a low LER that contains different line widths 174 in accordance with various embodiments. 14A is a Side cross-sectional view of the microelectronic structure 100 through section AA after 14B , and 14B Figure 3 is a top view of the microelectronic structure 100 ; being the disordered lamellar structure 138 the microelectronic structure 100 after 14th in the 1C may take the illustrated form. The embodiment according to 14th shares a number of elements with previous embodiments; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. With regard to the embodiment according to 1 contains the microelectronic structure 100 after 14th cables 140 with low LER with different line widths 174 (ie, being the middle line 140 with a lower LER a larger line width 174 than the neighboring lines 140 with low LER).

the 15A-15G illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 14th in accordance with various embodiments. 15A Figure 13 is a side cross-sectional view of an arrangement like the one in accordance with the present invention 2C who have favourited a patterned starter brush 110 contains; the initial brush 110 after 15A can the second component 118 instead of the first component 116 contain. The arrangement according to 15A may be in accordance with any of the here regarding 2C discussed manufacturing techniques are formed. As with the arrangement after 2C can use the openings 178 in the brush 110 may be formed as a pattern using lithographic techniques and consequently may have highly rough edges. It is indicated that the central section is the second component 118 the brush 110 wider than the other sections of the second component 118 in the patterned area 142 is.

15B Figure 4 is a side cross-sectional view of an assembly following "filling in" the openings 178 in the brush 110 after 15A with the first component 116 to the brush 110 to "complete" as above regarding 3 has been discussed. In other embodiments, this operation is not performed until proceeding to subsequent operations.

15C Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a BCP 114 on the arrangement according to 15B . As mentioned above, the brush can 110 and the BCP 114 can be selected in order to achieve a desired DSA behavior. In the embodiment according to 15th can the BCP 114 a first component 116 and a second component 118 contain.

15D FIG. 14 is a side cross-sectional view of an assembly following the treatment of the assembly of FIG 15C to cause the BCP 114 in accordance with that by the brush 110 provided template organized by yourself. The resulting arrangement contains both alternating vertically oriented areas of the first component 116 and the second component 118 as well as a horizontally oriented area of the first component 116 (the one above the "wider" section of the second component 118 in the patterned area 142 is trained). Outside the patterned area 142 can the brush 110 do not provide a surface on which the BCP 114 easily in alternating vertically oriented areas of the first component 116 and the second component 118 (or in alternating horizontally oriented areas of the first component 116 and the second component 118 ) self-organized, whereby the BCP 114 in the unpatterned area 144 so instead in disordered slats themselves 132 the first component 116 and the second component 118 can organize; being the disordered lamellae 132 may have a structure like that shown in 1C is illustrated.

15E FIG. 14 is a side cross-sectional view of an assembly following planarization of the assembly of FIG 15D to the top section of the first component 116 , the second component 118 and the disordered lamellas 132 (e.g. using a CMP technique).

15F Figure 13 is a side cross-sectional view of an assembly following removal of the second component 118 according to the arrangement 15E (e.g. using a suitable selective etching technique) to make openings in the first component 116 to make the "smoother" than the rough openings 178 are transferring the pattern of the first component 116 (through the masking materials 108 , 106 and 104 which are then removed) and then the provision of pipe material 120 in the openings of the dielectric material 102 to the lines 140 to form with low LER. The pattern of the disordered slats 132 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. 15G FIG. 13 is a top plan view of the arrangement of FIG 15F that are the edges 130 of the lines 140 illustrated with low LER. The illustration after 15F is through the section FF after 15G taken. The arrangement according to the 15F and 15G can take the shape of the microelectronic structure 100 after 14th accept.

The ability to form horizontally oriented repeating structures can be used to create lines 140 with low LER with different spaces 176 (instead of or in addition to different line widths 174 , as above regarding the 14th and 15th has been discussed). the 16A-16B are z. B. different views of another microelectronic structure 100 who have made the lines 140 with low LER with different spaces 176 contains therebetween, in accordance with various embodiments. 16A Figure 3 is a side cross-sectional view of the microelectronic structure 100 through section AA after 16B , and 16B Figure 3 is a top view of the microelectronic structure 100 ; being the disordered lamellar structure 138 the microelectronic structure 100 after 16 in the 1C may take the illustrated form. The embodiment according to 16 shares a number of elements with the previous embodiments; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. With regard to the embodiment according to 1 contains the microelectronic structure 100 after 16 the lines 140 with low LER with different spaces 176 (ie, being the middle gap 176 larger than the neighboring spaces 176 is).

the 17A-17G illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 16 in accordance with various embodiments. 17A Figure 13 is a side cross-sectional view of an arrangement like the one in accordance with the present invention 2C who have favourited a patterned starter brush 110 the first component 116 contains. The arrangement according to 17A may be in accordance with any of the here regarding 2C discussed manufacturing techniques are formed. As with the arrangement after 2C can use the openings 178 in the brush 110 may be formed as the pattern using lithographic techniques, and consequently may have highly rough edges. It is indicated that the central section is the first component 116 the brush 110 is wider than the other sections of the first component 116 in the patterned area 142 is.

17B Figure 13 is a side cross-sectional view of an assembly following "filling" of the openings 178 in the brush 110 after 17A with the second component 118 to the brush 110 to "complete" as above regarding 3 has been discussed. In other embodiments, this operation is not performed until proceeding to subsequent operations.

17C Figure 13 is a side cross-sectional view of an assembly subsequent to the deposition of a BCP 114 on the arrangement according to 17B . As mentioned above, the brush can 110 and the BCP 114 be selected in order to achieve a desired DSA behavior. In the embodiment according to 17th can the BCP 114 a first component 116 and a second component 118 contain.

17D FIG. 14 is a side cross-sectional view of an assembly following the treatment of the assembly of FIG 17C to cause the BCP 114 in accordance with that by the brush 110 provided template organized by yourself. The resulting arrangement contains both alternating vertically oriented areas of the first component 116 and the second component 118 as well as a horizontally oriented area of the second component 118 (the one above the "wider" section of the first component 116 in the patterned area 142 is trained). Outside the patterned area 142 can the brush 110 do not provide a surface on which the BCP 114 easily in alternating vertically (or horizontally) oriented areas of the first component 116 and the second component 118 self-organized, whereby the BCP 114 in the unpatterned area 144 so instead in the disordered slats 132 the first component 116 and the second component 118 can organize yourself; being the disordered lamellae 132 a structure like that after 1C can have.

17E FIG. 14 is a side cross-sectional view of an assembly following planarization of the assembly of FIG 17D to the top section of the first component 116 , the second component 118 and the disordered lamellas 132 (e.g. using a CMP technique).

17F Figure 13 is a side cross-sectional view of an assembly following removal of the second component 118 according to the arrangement 17E (e.g. using a suitable selective etching technique) to make openings in the first component 116 to make the "smoother" than the rough openings 178 are transferring the pattern of the first component 116 (through the masking materials 108 , 106 and 104 which are then removed) and then the provision of pipe material 120 in the openings of the dielectric material 102 to the lines 140 to form with low LER. The pattern of the disordered slats 132 can in the dielectric material 102 transferred to the disordered lamellar structure 138 to build. 17G FIG. 13 is a top plan view of the arrangement of FIG 17F who the edge 130 of the lines 140 illustrated with low LER. The illustration after 17F is through the section FF after 17G taken. The arrangement according to the 17F and 17G can take the shape of the microelectronic structure 100 after 16 accept.

In some embodiments, a BCP used in a DSA-based technique can be "stretchable" in that it transforms itself into repetitive patterns of variable size (e.g., around, depending on the dimensions and structure of the underlying brush) a nominal size). 18th is z. B. a plan view of a microelectronic structure 100 , the lines 140 with low LER at multiple pitches (including variable line widths and line spacings) in accordance with various embodiments. The microelectronic structure 100 after 18th contains a first set of lines 140-1 with low LER and a second set of lines 140-2 with low LER and the corresponding intermediate line spaces 150-1 respectively. 150-2 . The widths of the lines 140 with lower LER than over the lines 140 shown superimposed with low LER (e.g. 1x, 1.5x, 2x), with the widths of the intermediate line spaces 150 the interline gaps 150 are shown adjacent (e.g. 1x, 1,2x, 3x). The use of a stretchable BCP in a DSA-based technique, such as B. those that are discussed below in relation to 19th and 20th is discussed to be a microelectronic structure 100 Forming can result in features that have roughness that increase with feature size; furthermore, these features may not exhibit the lithographic property as discussed above, hence the use of a ductile BCP in the manufacture of a microelectronic structure 100 in the microelectronic structure 100 can be detected.

the 19A-19E illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 18th in accordance with various embodiments. 19A Figure 13 is a top plan view of an assembly incorporating a patterned metal 152 on a mask material 108 contains. Additional mask materials (e.g. the mask materials not shown 104 and 106 ) can under the mask material 108 lying, a (not shown) dielectric material 102 may be under the additional mask materials. In some embodiments, the metal 152 Contain titanium nitride or a metal oxide. The metal 152 can be patterned (and thus have rough edges) using a lithographic technique.

19B Figure 3 is a plan view of an arrangement following the provision of a brush 110 on the metal 152 according to the arrangement 19A . In some embodiments, the brush can 110 be a material that is selective on the metal 152 Deposits and adheres to the pattern of the metal 152 to replicate.

19C Figure 13 is a top plan view of an arrangement following the deposition of a BCP (e.g., the BCP, not shown 114 ), treating the resulting assembly to cause the BCP to align with that by the brush 110 provided stencil organizing itself, and then removing some of the organized BCP to make the BCP component 154 to leave behind. The BCP component 154 can be a "stretchable" component as it depends on the dimensions of the underlying brush 110 can organize into vertically oriented bands with different widths (e.g. 1 × and 1.2x). In some embodiments, a "stretchable" BCP can contain a triblock copolymer, such as. B. PMMA-b-PS-b-PMMA, PSb-PMMA-b-PS, PS-b- Poly (ethylene oxide) (PEO), PS-b-PEO-b-PS, PEO-b-PS-b- PEO, poly (styrene-b-2-vinylpyridine) (PSb-P2VP), PS-b-P2VP-b-PS, P2VP-b-PS-b-P2VP, PS-b-P4VP, PS-b-P4VP- b-PS, P4VP-b-PS-b-P4VP, polystyrene block polydimethylsiloxane (PS-b-PDMS), PDMS-b-PS-b-PDMS or PS-b-PDMS-b-PS.

19D Figure 13 is a top plan view of an assembly following removal of the exposed mask material 108 according to the arrangement 19C (e.g. by suitable selective etching), the patterning of the underlying dielectric material 102 the resulting arrangement in accordance with the pattern of the BCP component 154 and the brush 110 and then removing the BCP component 154 and the brush 110 (e.g. by suitable selective etching). The openings 190 in the dielectric material 102 can have "smooth" edges.

19E Figure 3 is a top plan view of an arrangement following the filling of the openings 190 according to the arrangement 19D with line material (e.g. the line material 120 ) to the lines 140 with low LER and the interline gaps 150 to build. The arrangement according to 19E can take the shape of the microelectronic structure 100 after 18th accept. It is stated that the drawings according to 18th and 19th are simply examples and the components of which can take any suitable form. The dielectric material 102 can e.g. B. be a multilayer dielectric and / or the interconnect gaps 150 can be replaced by dielectric spacers (e.g. silicon oxynitride, Silicon oxycarbide, aluminum oxide, silicon nitride or silicon oxide) may be provided on an intervening dielectric material (e.g. a carbon-doped oxide).

In some embodiments, a “ductile” BCP can be used in a DSA-based technique that has no underlying metal 152 used on which a brush 110 can be replicated. Instead, you can use the brush 110 can be patterned using other techniques (e.g., lithography). 20th is z. B. is a top plan view of an assembly incorporating a patterned brush 110 on a mask material 108 contains. An arrangement like the one after 20th can be used as above regarding the 19C-19E has been discussed to the microelectronic structure 100 after 18th to build.

In some embodiments, the lines 140 with low LER can be included in a metallization stack, as described below with respect to 29 is discussed. The lines 140 with low LER in accordance with one of the embodiments disclosed herein, e.g. B. be part of the M0, M1, M2 or other interconnection layers of a metallization stack. In some embodiments, the lines can be 140 with low LER are in contact through vias in a metallization stack. In some such embodiments, the vias may be formed using conventional techniques, e.g. B. by forming openings on the lines 140 arrive with a low LER using lithographic techniques and filling these openings with a conductive material. In other embodiments, such vias can be formed using self-alignment techniques to reduce the misalignment that can occur when using conventional approaches. 21 is z. B. a side cross-sectional view of a microelectronic structure 100 that have made the vias 166 in conductive contact with the lines 140 with low LER, in accordance with various embodiments. 21 (and others of the accompanying drawings) illustrate the vias 166 the line material 120 included, but the vias 166 may contain any suitable filling and / or lining materials.

In the microelectronic structure 100 after 21 contain the vias 166 a lower portion that extends through a second replication brush component 158 (which will be discussed further below), and a top portion that extends through a photoresist 162 extends. The photoresist 162 may be a dielectric material containing crosslinking elements that can be selectively activated by EUV irradiation, as discussed further below. An unpatterned area 144 the microelectronic structure 100 after 21 can have a disordered lamellar structure 138 as discussed above and a disordered dielectric material 160 on the disordered lamellar structure 138 contain.

22A-22F illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 21 in accordance with various embodiments. 22A Figure 13 is a side cross-sectional view of an assembly having a patterned area 142 with one or more lines 140 with low LER in a dielectric material 102 and an unpatterned area 144 with a disordered lamellar structure 138 contains. The arrangement according to 22A can take the form of any of the microelectronic structures 100 assume the above regarding the 1-20 have been discussed.

22B Figure 13 is a side cross-sectional view of an assembly subsequent to the formation of a replication brush 192 on the arrangement according to 22A . The replication brush 192 can be a first replication brush component 156 and a second replication brush component 158 contain. The first replication brush component 156 can preferably on the line material 120 of the lines 140 with a low LER, while the second replication brush component 158 preferably on the dielectric material 102 can be attached to a self-organized replication brush 192 to build. The replication brush 192 can also use the disordered dielectric material 160 which cannot have a self-organized structure or a disordered lamellar structure like the one after 1C may have. In some embodiments, the first replication brush component 156 (a metal-selective brush material) have a surface anchoring group, the phosphines, thiol, thiolate, thioacetate, disulfide, alkyl azide, aryl azide, nitrile, phosphate, silyl, alkyl and other phosphonate esters, phosphonamide, sulfonamides, sulfenate, sulfinate, sulfonate, boric acid, Phosphonic acids, carboxylic acids, phosphorus dichloride, alkenes or alkene material. In some embodiments, the second replication brush component 158 (a dielectric-selective brush material) have a surface anchoring group of hydroxyl, amines or a carboxylic acid group.

22C Fig. 3 is a side cross-sectional view of an assembly following Fig Deposition of a photoresist 162 on the arrangement according to 22B . The photoresist 162 may contain crosslinking elements which crosslink upon activation by EUV irradiation when they become in the presence of the first replication brush component 156 and otherwise not network. In some embodiments, the photoresist can 162 and / or the first replication brush component 156 Contain photoacid generator molecules (PAG molecules) that generate an acid when exposed to ultraviolet (UV) exposure (e.g. EUV exposure) in order to cross-link the photoresist 162 to cause; the networked photoresist 164 , which is discussed below, can then be selectively removed. In some embodiments, the photoresist can 162 and / or the second replication brush component 158 Contain extinguishing molecules which, when exposed to UV light, cause the penetration through the photoresist 162 acid generated in the areas above the second replication brush component 158 is deleted to the networking of the photoresist 162 in the areas above the second replication brush component 158 to prevent; the networked photoresist 164 , which is discussed below, can then be selectively removed. More generally, the first replication brush component 156 , the second replication brush component 158 and / or the photoresist 162 Contain catalysts that cross-link the photoresist 162 can selectively localize when exposed to UV radiation.

22D Figure 3 is a side cross-sectional view of an assembly following exposure of the photoresist 162 according to the arrangement 22C with EUV radiation (e.g. an EUV "flood"), which creates a cross-linked photoresist 164 in the volumes of the photoresist 162 near the first replication brush component 156 forms.

22E Figure 13 is a side cross-sectional view of an assembly following removal of the crosslinked photoresist 164 according to the arrangement 22D (e.g. using a suitable selective etching technique).

22F Figure 13 is a side cross-sectional view of an assembly following removal of the first replication brush component 156 according to the arrangement 22E (e.g. using a suitable selective etching technique) and then filling the openings with the lead material 120 to get the vias 166 to build. The arrangement according to 22F can take the shape of the microelectronic structure 100 after 21 accept.

the 21 and 22nd illustrate a microelectronic structure 100 that have made the vias 166 formed as a pattern by a technique including EUV flooding. In other embodiments, the vias 166 using the selective application of UV radiation as a pattern. 23 is z. B. a side cross-sectional view of another microelectronic structure 100 that have made the vias 166 in conductive contact with the lines 140 with low LER, in accordance with various embodiments. The microelectronic structure 100 after 23 uses many elements with the microelectronic structure 100 after 21 together; Description of these elements will not be repeated for ease of discussion, and these elements may take the form of any of the embodiments of those elements disclosed herein. In the embodiment according to 23 however, the vias 166 not over the lines 140 with low LER but can instead be centered at the intersection point between the volumes above the lines 140 with low LER and the area to which EUV radiation is selectively applied, as discussed below.

the 24A-24C illustrate the steps in an exemplary process for fabricating the microelectronic structure 100 after 23 in accordance with various embodiments. 24A Figure 3 is a side cross-sectional view of an assembly following exposure of the photoresist 162 according to the arrangement 22C with patterned EUV radiation (with the areas of EUV radiation indicated by the dashed lines), which is a crosslinked photoresist 164 at the point of intersection between the EUV radiation volumes and the volumes of the photoresist 162 near the first replication brush component 156 forms.

24B Figure 13 is a side cross-sectional view of an assembly following removal of the crosslinked photoresist 164 according to the arrangement 24A (e.g. using a suitable selective etching technique).

24C Figure 13 is a side cross-sectional view of an assembly following removal of the first replication brush component 156 according to the arrangement 24B (e.g. using a suitable selective etching technique) and then filling the openings with the lead material 122 what the through holes 166 forms. The arrangement according to 24C can take the shape of the microelectronic structure 100 after 23 accept.

The one above regarding the 4-5 , 6-7 and 12-13 The manufacturing process discussed includes spacer-based spacer-dividing techniques. The special spacing-division techniques according to the 5 , 7th and 13th are Space-halving techniques (using one round of spacer formation), but in other embodiments a space-quartering technique (using two rounds of spacer formation) can be used instead to obtain smaller feature sizes. The use of such pitch-sharing techniques in the process of forming conduits 140 with low LER in a patterned area 142 can be in a microelectronic structure 100 by the presence of space-division artifacts in the microelectronic structure 100 be proven. As a result of the way in which the widths of various elements are divided into the line widths by the spacing technique 174 and the interline spaces 176 spreads, the line widths 174 and the interline spaces 176 z. B. a periodicity over several of the lines 140 with a low LER. Such periodicity can be seen as a space-division artifact in the microelectronic structure 100 which provides evidence of the use of a pitch and pitch technique during manufacture. Another example of a space-sharing artifact residing in a microelectronic structure 100 can occur are nested and / or rounded half-ring patterns in the dielectric material 102 covering the ends of the spacers 124 correspond. the 25th , 26th and 27 are top views of the microelectronic structures 100 after the 4th , 6th respectively. 12th that have such nested and rounded patterns 168 near a perimeter of the patterned areas 142 illustrate; in the embodiments in which a pitch quarter technique is used instead of a pitch bisection technique, more "half-rings" can be part of the patterns 168 be. The presence of such nested and / or rounded patterns can be a space-division artifact in the microelectronic structure 100 which provides evidence of the use of a pitch and pitch technique during manufacture. Other pitch-sharing artifacts may be present in place of, or in addition to, one or more of these artifacts. The spacer-based spacing division as discussed above may have a single feature size (either a line width or a width of space between lines) defined by the ALD spacer deposit. The thickness of the ALD spacer deposit can determine this size.

The microelectronic structures disclosed here 100 can be included in any suitable electronic component. the 28-32 illustrate various examples of devices that incorporate any of the microelectronic structures disclosed herein 100 may contain.

28 Fig. 3 is a plan view of a wafer 1500 and the this 1502 that have one or more microelectronic structures 100 in accordance with any of the embodiments disclosed herein. The wafer 1500 can consist of a semiconductor material and can have one or more dies 1502 with microelectronic structures contained on a surface of the wafer 1500 are trained. Everyone of this 1502 may be a repeating unit of a semiconductor product containing any suitable microelectronic structure. After the manufacture of the semiconductor product is completed, the wafer can 1500 be subjected to a separation process in which the dies 1502 separated from each other to provide discrete “chips” of the semiconductor product. The Die 1502 can be both one or more microelectronic structures 100 (such as in the following regarding 29 is discussed), one or more transistors (e.g. some of the transistors 1640 after 29 (discussed below) and / or supporting circuitry to route electrical signals to the transistors, as well as any other circuit components. In some embodiments, the wafer 1500 or the die 1502 a storage device (e.g., a random access memory (RAM) device such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a device of the RAM with conductive bridging (CBRAM device), etc.), a logic device (e.g. an AND, OR, NAND or NOR gate) or any other suitable circuit element. Multiple of these devices can be used on a single die 1502 be combined. A memory array formed from a plurality of memory devices can e.g. B. on the same die 1502 such as a processing device (e.g., the processing device 1802 after 32 ) or some other logic that is configured to store information in the memory devices or to execute instructions stored in the memory arrangement.

29 Figure 3 is a side cross-sectional view of a microelectronic device 1600 that have one or more microelectronic structures 100 in accordance with any of the embodiments disclosed herein. One or more of the microelectronic devices 1600 can be in one or more dies 1502 ( 28 ) must be included. The microelectronic device 1600 can on a substrate 1602 (e.g. the wafer 1500 after 28 ) and can be formed in a die (e.g. the die 1502 after 28 ) must be included. That Substrate 1602 may be a semiconductor substrate which consists of semiconductor material systems which, for. B. contain n-type or p-type material systems (or a combination of both). The substrate 1602 can e.g. B. contain a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV can also be used to make the substrate 1602 to build. Although here are some examples of the materials that make up the substrate 1602 Any material that can be used as a basis for a microelectronic device 1600 can serve. The substrate 1602 can be part of an isolated die (e.g. the dies 1502 after 28 ) or a wafer (e.g. the wafer 1500 after 28 ) be.

The microelectronic device 1600 may be one or more device layers 1604 included that on the substrate 1602 are arranged. The device layer 1604 may have the characteristics of one or more transistors 1640 (e.g. Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs)) on the substrate 1602 are trained. The device layer 1604 can e.g. B. one or more source and / or drain (S / D) regions 1620 , a gate 1622 to control the flow of current in the transistors 1640 between the S / D areas 1620 to control, and one or more S / D contacts 1624 to get electrical signals to / from the S / D areas 1620 to direct, included. The transistors 1640 may include additional features not shown for clarity, such as: B. device isolation areas, gate contacts and the like. The transistors 1640 are inconsistent with the type and configuration included in 29 and may include a wide variety of other types and configurations such as: B. planar transistors, non-planar transistors, or a combination of both. The planar transistors can include bipolar transistors (BJT), heterojunction bipolar transistors (HBT), or high electron mobility transistors (HEMT). The non-planar transistors can be FinFET transistors, such as. B. double-gate transistors or three-gate transistors, and wrap-around or wrap-around gate transistors, such as. B. Nanoband and nanowire transistors included.

Every transistor 1640 can be a gate 1622 included, which is formed from at least two layers, a gate dielectric and a gate electrode. The gate dielectric can include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as B. hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium and zinc. The examples of the high-k materials that can be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium-silicon oxide, lanthanum oxide, lanthanum-aluminum oxide, zirconium oxide, zirconium-silicon oxide, tantalum oxide , Titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when a high-k material is used.

The gate electrode can be formed on the gate dielectric and, depending on whether the transistor 1640 be a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor, at least one p-type work function metal or an n-type Work function metal included. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers can be included for other purposes, such as e.g. B. as a barrier layer. For a PMOS transistor, the metals that can be used for the gate electrode include ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g. ruthenium oxide), and any of the metals discussed below with respect to an NMOS Transistors are discussed (z. B. for tuning the work function), but they are not limited to this. For an NMOS transistor, the metals that can be used for the gate electrode include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g. hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide ) and any of the metals discussed above in relation to a PMOS transistor (e.g., to tune the work function), but are not limited to these.

In some embodiments, the gate electrode when viewed as a cross section of the transistor 1640 viewed along the source-channel-drain direction, consist of a U-shaped structure having a bottom portion leading to the Surface of the substrate is substantially parallel, and includes two side wall portions that are substantially perpendicular to the top of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top of the substrate and does not include sidewall portions that are substantially perpendicular to the top of the substrate. In other embodiments, the gate electrode can consist of a combination of U-shaped structures and planar, non-U-shaped structures. The gate electrode can, for. B. consist of one or more U-shaped metal layers formed on top of one or more flat, non-U-shaped layers.

In some embodiments, a pair of sidewall spacers can be formed on opposite sides of the gate stack to clamp the gate stack. The side wall spacers can be made of materials such as. B. silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride and silicon oxynitride. The processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple pairs of spacers can be used; it can e.g. B. two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.

The S / D areas 1620 can within the substrate 1602 the gate 1622 each transistor 1640 be formed adjacent. The S / D areas 1620 can e.g. Be formed using an implantation / diffusion process or an etch / deposition process. In the former process, dopants such as. B. boron, aluminum, antimony, phosphorus or arsenic, into the substrate 1602 Ions are implanted to the S / D areas 1620 to build. The ion implantation process can be followed by an annealing process that activates the dopants and causes them to continue into the substrate 1602 to diffuse. In the latter process, the substrate can 1602 first to be etched to make cutouts at the locations of the S / D areas 1620 to build. An epitaxial deposition process can then be performed to fill the recesses with a material that will be used to form the S / D areas 1620 to manufacture. In some implementations, the S / D areas 1620 using a silicon alloy, such as. B. silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy can be coated in situ with dopants, such as. B. boron, arsenic or phosphorus, are doped. In some embodiments, the S / D areas 1620 using one or more alternative semiconductor materials, such as. B. germanium or a material or alloy of the group III-V can be formed. In further embodiments, one or more layers of metal and / or metal alloys can be used to define the S / D regions 1620 to build.

Electrical signals such as B. Power and / or input / output signals (I / O signals), may pass through one or more layers of interconnection that are on top of the device layer 1604 are arranged (which are in 29 than the interconnection layers 1606-1610 are illustrated), to and / or from the devices (e.g., the transistors 1640 ) the device layer 1604 be directed. The conductive features of the device layer 1604 (e.g. the gate 1622 and the S / D contacts 1624 ) can e.g. B. with the interconnection structures 1628 of the interconnection layers 1606-1610 be electrically coupled. The one or more interconnection layers 1606-1610 can use a metallization stack (also referred to as an "ILD stack") 1619 the microelectronic device 1600 form. Any of the microelectronic structures disclosed herein 100 may be in any of the interconnect layers of a metallization stack 1619 be included.

The interconnection structures 1628 can within the interconnection layers 1606-1610 be arranged to conduct electrical signals in accordance with a wide variety of designs (in particular, the arrangement is not limited to that in 29 The special configuration of the interconnection structures shown 1628 restricted). Although in 29 a specific number of interconnection layers 1606-1610 As illustrated, embodiments of the present disclosure include microelectronic devices with more or fewer interconnection layers than illustrated.

In some embodiments, the interconnection structures 1628 the lines 1628a and / or the vias 1628b coated with a conductive material such as B. a metal, are included. The lines 1628a may be arranged to conduct electrical signals in a direction of a plane leading to a surface of the substrate 1602 on which the device layer 1604 is formed is substantially parallel. The lines 1628a can e.g. B. electrical signals from the perspective 29 in one direction in and out of the page. Each of the lines 1628a in a metallization stack 1619 may take the form of the lines disclosed herein 140 accept with low LER; one or more of the lines 1628a in a Interconnection layer of a metallization stack 1619 can e.g. B. Lines 140 be with low LER. The vias 1628b can be arranged to conduct electrical signals in one direction of a plane facing the surface of the substrate 1602 on which the device layer 1604 is formed, is substantially perpendicular. In some embodiments, the vias 1628b the lines 1628a different interconnection layers 1606-1610 electrically couple with each other. Each of the vias 1628b in a metallization stack 1619 may take the form of the vias disclosed herein 166 accept.

The interconnection layers 1606-1610 can be a dielectric material 1626 included that between the interconnection structures 1628 is arranged as in 29 is shown. In some embodiments, the dielectric material can 1626 that is between the interconnection structures 1628 in various of the interconnection layers 1606-1610 arranged to have different compositions; in other embodiments, the composition of the dielectric material may be 1626 between different interconnection layers 1606-1610 be the same.

A first layer of interconnection 1606 can over the device layer 1604 be trained. In some embodiments, the first layer of interconnection 1606 the lines 1628a and / or the vias 1628b included as shown. The lines 1628a the first layer of interconnection 1606 can with the contacts (e.g. the S / D contacts 1624 ) the device layer 1604 be coupled. The first layer of interconnection 1606 may be referred to as the "MO" interconnection layer, with in some embodiments the M0 interconnection layer being any of the lines disclosed herein 140 with low LER. In some embodiments, the M0 interconnection layer can be any suitable portion of any of the microelectronic structures disclosed herein 100 contain.

A second layer of interconnection 1608 can be over the first layer of interconnection 1606 be trained. In some embodiments, the second layer of interconnection 1608 the vias 1628b included to the lines 1628a the second interconnection layer 1608 with the lines 1628a the first layer of interconnection 1606 to pair. Although the lines 1628a and the vias 1628b with a line within each interconnection layer (e.g., within the second interconnection layer) for clarity 1608 ) are delimited, the lines 1628a and the vias 1628b in some embodiments structurally and / or materially contiguous (e.g., being filled simultaneously during a dual damascene process). The second layer of interconnection 1608 may be referred to as the "M1" interconnection layer, with in some embodiments the M1 interconnection layer being any of the lines disclosed herein 140 with low LER. In some embodiments, the M1 interconnection layer can be any suitable portion of any of the microelectronic structures disclosed herein 100 contain.

A third layer of interconnection 1610 (and additional interconnection layers if desired) can be sequentially placed on the second interconnection layer 1608 may be formed in accordance with similar techniques and configurations associated with the second layer of interconnection 1608 or the first layer of interconnection 1606 have been described. The third layer of interconnection 1610 may be referred to as the "M2" interconnection layer, with in some embodiments the M2 interconnection layer being any of the lines disclosed herein 140 with low LER. In some embodiments, the M2 interconnection layer can be any suitable portion of any of the microelectronic structures disclosed herein 100 contain. In some embodiments, the interconnection layers that are “higher” in the metallization stack may be used 1619 in the microelectronic device 1600 (ie, further away from the device layer 1604 ) are thicker.

The microelectronic device 1600 can be a solder resist material 1634 (e.g. polyimide or similar material) and one or more conductive contacts 1636 included on the interconnection layers 1606-1610 are trained. In 29 is illustrated that the conductive contacts 1636 take the form of bond islands. The conductive contacts 1636 can with the interconnection structures 1628 be electrically coupled and configured, the electrical signals of the transistor (s) 1640 to other external devices. On the one or more conductive contacts 1636 can e.g. B. solder connections may be formed to a chip that the microelectronic device 1600 contains to mechanically and / or electrically couple with another component (e.g. a circuit board). The microelectronic device 1600 may contain additional or alternative structures to carry the electrical signals from the interconnection layers 1606-1610 to direct; the conductive contacts 1636 can e.g. E.g. contain other analog features (e.g. posts) that route the electrical signals to external components.

30th Figure 3 is a side cross-sectional view of an exemplary microelectronic assembly 1650 that have one or more microelectronic structures 100 in accordance with any of the embodiments disclosed herein. In some embodiments, the microelectronic assembly can 1650 be a system in an assembly (SiP).

The assembly substrate 1652 may be made of a dielectric material (e.g. a ceramic, a surface film, an epoxy film with filler particles therein, a glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed from various materials, etc.) and may have conductive paths extending between the surface 1672 and the area 1674 or between different places on the surface 1672 and / or between different locations on the surface 1674 extend through the dielectric material. These conductive paths can take the form of any of the above with respect to FIG 29 discussed interconnections 1628 accept.

The assembly substrate 1652 can make the conductive contacts 1663 containing conductive paths (not shown) through the assembly substrate 1652 are coupled, which allows the circuitry to be within the die 1656 and / or the "interposer" 1657 electrically to various of the conductive contacts 1664 (or to others not shown in the assembly substrate 1652 contained devices) can be coupled.

The microelectronic assembly 1650 can use an "interposer" 1657 included, the one via the conductive contacts 1661 of the "interposer" 1657 who have favourited interconnections 1665 first level and the conductive contacts 1663 of the assembly substrate 1652 to the assembly substrate 1652 is coupled. In the 30th illustrated interconnections 1665 first level are solder balls, but with any suitable interconnections 1665 first level can be used. In some embodiments, in the microelectronic assembly 1650 no "interposer" 1657 be included; instead, the dies 1656 through the interconnections 1665 first level directly to the conductive contacts 1663 on the surface 1672 be coupled. More generally, one or more dies 1656 via any suitable structure (e.g. a silicon bridge, an organic bridge, one or more waveguides, one or more "interposers", wire connections, etc.) to the assembly substrate 1652 be coupled.

The microelectronic assembly 1650 can be one or more dies 1656 included that via the conductive contacts 1654 the this 1656 who have favourited interconnections 1658 first level and the conductive contacts 1660 of the "interposer" 1657 to the "interposer" 1657 are coupled. The conductive contacts 1660 can through the "interposer" 1657 be coupled to conductive paths (not shown), which allows the circuitry within the dies 1656 to various of the conductive contacts 1661 (or to others not shown in the "Interposer" 1657 contained devices) are electrically coupled. In the 30th illustrated interconnections 1658 first level are solder balls, but with any suitable interconnections 1658 first level can be used. As used herein, a “conductive contact” may refer to a section of conductive material (e.g., a metal) that serves as an interface between various components; wherein the conductive contacts can be recessed from a surface of a component, can be flush with a surface of a component, or can extend from a surface of a component and take any suitable shape (e.g., a conductive pad or socket).

In some embodiments, an underfill material 1666 between the assembly substrate 1652 and the "interposer" 1657 about the interconnections 1665 be arranged first level, with a molding compound 1668 around the this 1656 and the "interposer" 1657 and in contact with the assembly substrate 1652 can be arranged. In some embodiments, the underfill material can be 1666 the same as the molding compound 1668 be. Exemplary materials used for the underfill material 1666 and the molding compound 1668 Epoxy molding materials as appropriate. The interconnections 1670 second level can connect to the conductive contacts 1664 be coupled. In the 30th illustrated interconnections 1670 second level are solder balls (e.g. for a ball grid array arrangement), but with any suitable interconnections 16770 second level (e.g. the pins in a pin grid arrangement or the "lands" in a "lands" grid arrangement) can be used. The interconnections 1670 second level can be used to hold the microelectronic assembly 1650 to another component, such as B. a printed circuit board (e.g. a motherboard), an "interposer" or another microelectronic Assembly, as is known in the art and as referred to below 31 is discussed.

The this 1656 may take the form of any of the embodiments of the die discussed herein 1502 assume (e.g., they may be any of the embodiments of the microelectronic device 1600 contain). In the embodiments in which the microelectronic assembly 1650 several dies 1656 contains, the microelectronic assembly 1650 referred to as a multi-chip assembly (MCP). The this 1656 may contain circuitry to perform any desired functionality. One or more of the dies 1656 can e.g. B. Logic dies (e.g. silicon-based dies), with one or more of the dies 1656 Storage-These can be (such as high bandwidth storage).

Although the in 30th illustrated microelectronic assembly 1650 is a flip-chip assembly, other assembly architectures can be used. The microelectronic assembly 1650 can e.g. B. a ball grid assembly (BGA) assembly such. B. an embedded ball grid array assembly at the wafer level (eWLB assembly). In a further example, the microelectronic assembly 1650 a chip-scale wafer-level assembly (WLCSP) or a panel branch (FO) assembly. Although in the microelectronic assembly 1650 after 30th two this 1656 illustrated can be a microelectronic assembly 1650 any number of dies desired 1656 contain. A microelectronic assembly 1650 additional passive components such as B. surface mount resistors, capacitors and inductors placed on the first surface 1672 or the second surface 1674 of the assembly substrate 1652 or on one of the surfaces of the "interposer" 1657 are arranged, included. More generally, a microelectronic assembly 1650 contain any other active or passive components known in the art.

31 Figure 3 is a side cross-sectional view of an assembly 1700 a microelectronic device that includes one or more microelectronic assemblies or other electronic components (e.g., a die) including one or more microelectronic structures 100 in accordance with any of the embodiments disclosed herein. The order 1700 A microelectronic device contains a number of components that are on a printed circuit board 1702 (which can for example be a motherboard) are arranged. The order 1700 A microelectronic device includes components that are on a first surface 1740 the circuit board 1702 and an opposite second surface 1742 the circuit board 1702 are arranged; in general, the components can be on one or both surfaces 1740 and 1742 be arranged. Each of the microelectronic assemblies, which are described below with regard to the arrangement 1700 of a microelectronic device, the shape of one of the embodiments of the microelectronic assembly may be discussed 1650 accept the above re 30th have been discussed (e.g. may be one or more microelectronic structures 100 contained in a die).

In some embodiments, the circuit board 1702 be a printed circuit board (PCB) containing multiple layers of metal separated by layers of dielectric material and interconnected by conductive vias. One or more of the metal layers can be formed in a desired circuit pattern to transmit electrical signals (optionally in conjunction with other metal layers) between the to the circuit board 1702 to conduct coupled components. In other embodiments, the circuit board 1702 be a non-PCB substrate.

In the 31 illustrated arrangement 1700 A microelectronic device includes an assembly-on-"interposer" structure 1736 that is secured by the coupling components 1716 to the first surface 1740 the circuit board 1702 is coupled. The coupling components 1716 can use the assembly-on-“interposer” structure 1736 electrically and mechanically to the circuit board 1702 couple and can solder balls (as in 31 shown), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

The assembly-on-“interposer” structure 1736 can be a microelectronic assembly 1720 included by the coupling components 1718 to an assembly "interposer" 1704 is coupled. The coupling components 1718 can be any form suitable for the application, e.g. B. those above regarding the coupling components 1716 take the forms discussed. Although in 31 a single microelectronic assembly 1720 shown, several microelectronic assemblies can be connected to the assembly "interposer" 1704 be coupled; in fact, additional "interposers" can be connected to the assembly "interposers" 1704 be coupled. The assembly "interposer" 1704 may provide an intermediate substrate that is used to hold the circuit board 1702 and the microelectronic assembly 1720 to bridge. The microelectronic assembly 1720 can e.g. B. a Die (the Die 1502 after 28 ), a microelectronic device (e.g., the microelectronic device 1600 after 29 ) or any other suitable Be or contain a component. In general, the assembly "interposer" 1704 extend a connection to a greater distance or redirect a connection to another connection. The assembly "interposer" 1704 can the microelectronic assembly 1720 (e.g. a die) to a set of conductive BGA contacts of the coupling components 1716 for coupling to the circuit board 1702 couple. In the in 31 The illustrated embodiment is the microelectronic assembly 1720 and the circuit board 1702 on opposite sides of the assembly "interposer" 1704 attached; in other embodiments, the microelectronic assembly 1720 and the circuit board 1702 on the same side of the assembly "interposer" 1704 be attached. In some embodiments, three or more components can be interposed through the assembly "interposer" 1704 be interconnected.

In some embodiments, the assembly "interposer" 1704 be designed as a PCB which contains several metal layers which are separated from one another by layers of dielectric material and interconnected by conductive vias. In some embodiments, the assembly "interposer" 1704 from an epoxy resin, a glass fiber reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material or a polymer material, such as. B. polyimide. In some embodiments, the assembly "interposer" 1704 be formed from alternately rigid or flexible materials, which may contain the same materials that have been described above for use in a semiconductor substrate, such as. B. silicon, germanium and other materials of group III-V and group IV. The assembly "interposer" 1704 can the metal lines 1710 and the vias 1708 Included, including, but not limited to, Silicon Through Vias (TSVs) 1706 . The assembly "interposer" 1704 can also use embedded devices 1714 including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and storage devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices can also be used on the assembly "interposer" 1704 be trained. The assembly-on-“interposer” structure 1736 may take the form of any of the assembly-on-"interposer" structures known in the art.

The order 1700 A microelectronic device can be a microelectronic assembly 1724 included that have coupling components 1722 to the first surface 1740 the circuit board 1702 is coupled. The coupling components 1722 may take the form of any of the embodiments described above with respect to the coupling components 1716 have been discussed, the microelectronic assembly 1724 may take the form of any of the embodiments described above with respect to the microelectronic assembly 1720 have been discussed.

In the 31 illustrated arrangement 1700 a microelectronic device includes an assembly-on-assembly structure 1734 by the coupling components 1728 to the second surface 1742 the circuit board 1702 is coupled. The assembly-on-assembly structure 1734 can be a microelectronic assembly 1726 and a microelectronic assembly 1732 included by the coupling components 1730 are coupled together so that the microelectronic assembly 1726 between the circuit board 1702 and the microelectronic assembly 1732 is arranged. The coupling components 1728 and 1730 may take the form of any of the coupling component embodiments discussed above 1716 assume the microelectronic assemblies 1726 and 1732 the shape of any of the microelectronic package embodiments discussed above 1720 can accept. The assembly-on-assembly structure 1734 may be configured in accordance with any of the assembly-on-assembly structures known in the art.

32 Figure 3 is a block diagram of an exemplary computing device 1800 that have one or more microelectronic structures 100 in accordance with any of the embodiments disclosed herein. It can e.g. B. any suitable components of the components of the computing device 1800 one or more of the arrangements disclosed herein 1700 a microelectronic device, microelectronic assemblies 1650 , microelectronic devices 1600 or this 1502 contain. In 32 illustrates a number of components included in the computing device 1800 are included, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components that are present in the computing device 1800 be attached to one or more motherboards. In some embodiments, some or all of these are Components manufactured on a single die of a system on a chip (SoC).

In addition, in various embodiments, the computing device 1800 one or more of the in 32 illustrated components not included, but the computing device 1800 may include interface circuitry for coupling to the one or more components. The computing device 1800 can e.g. B. no display device 1806 but may include display device interface circuitry (e.g., connector and driver circuitry) to which a display device 1806 can be coupled. In another set of examples, the computing device may 1800 no audio input device 1824 or no audio output device 1808 but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1824 or an audio output device 1808 can be coupled.

The computing device 1800 can be a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or a memory. The processing device 1802 can be one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more cryptoprocessors (specialized processors, the cryptographic algorithms within the hardware run), one or more server processors, or any other suitable processing device. The computing device 1800 can have a memory 1804 included, which itself has one or more storage devices, such as e.g. B. volatile memory (e.g. dynamic read-write memory (DRAM)), non-volatile memory (e.g. read-only memory (ROM)), flash memory, solid-state memory and / or a hard disk drive. In some embodiments, the memory 1804 a memory containing a die with the processing device 1802 shared. This memory can be used as a cache memory and can include embedded dynamic random access memory (eDRAM) or magnetic spin transfer torque random access memory (STT-MRAM).

In some embodiments, the computing device may 1800 a communication chip 1812 (e.g. one or more communication chips). The communication chip 1812 can e.g. For managing wireless communications for the transfer of data to and from the computing device 1800 configured. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium through the use of modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although in some embodiments they may not.

The communication chip 1812 may implement any number of wireless standards or protocols including, but not limited to, the Institute of Electrical and Electronic Engineering (IEEE standards) standards, including Wi-Fi (the IEEE 802.11 family), the IEEE 802.16 standards ( e.g. the addition of IEEE 802.16-2005), the long-term development project (LTE) together with any additions, updates and / or revisions (e.g. the further developed LTE project, the ultra-mobile broadband project (UMB) (also referred to as “3GPP2”, etc.). IEEE 802.16 Compatible Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that test for compliance and interoperability with the IEEE 802.16. Standards exist. The communication chip 1812 can operate in accordance with Global Mobile Communication System (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunication System (UMTS), High Speed Packet Access (HSPA), Developed HSPA (E-HSPA) or LTE network . The communication chip 1812 can work in accordance with the improved data for GSM development (EDGE), the GSM-EDGE radio access network (GERAN), the universal terrestrial radio access network (UTRAN) or the developed UTRAN (E-UTRAN). The communication chip 1812 can operate in accordance with both Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and derivatives thereof, as well as other wireless protocols known as 3G, 4G, 5G and beyond. The communication chip 1812 can in others Embodiments operate in accordance with other wireless protocols. The computing device 1800 can have an antenna 1822 included to promote wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip 1812 manage wired communications such as B. electrical, optical or other suitable communication protocols (e.g. Ethernet). As mentioned above, the communication chip can 1812 multiple communication chips included. A first communication chip 1812 can e.g. For short-range wireless communications, e.g. B. Wi-Fi or Bluetooth, while a second communication chip 1812 for longer range wireless communications such as B. the global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others can be dedicated. In some embodiments, a first communication chip 1812 be dedicated to wireless communications, while a second communications chip 1812 may be dedicated to the wired communications.

The computing device 1800 may include battery / power supply circuitry 1814 contain. The battery / power supply circuitry 1814 may include one or more energy storage devices (e.g. batteries or capacitors) and / or a circuit arrangement for coupling components of the computing device 1800 to one of the computing device 1800 Contain a separate energy source (e.g. AC mains power).

The computing device 1800 can be a display device 1806 (or equivalent interface circuitry as discussed above). The display device 1806 may contain any visual indicators such as B. a "head-up display", a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display or a flat panel display.

The computing device 1800 can be an audio output device 1808 (or equivalent interface circuitry as discussed above). The audio output device 1808 may include any device that produces an audible indicator, such as an audible indicator. B. speakers, headphones or earphones.

The computing device 1800 can be an audio input device 1824 (or equivalent interface circuitry as discussed above). The audio input device 1824 may include any device that generates a signal representing a tone, such as a B. microphones, microphone arrangements or digital instruments (z. B. instruments with an output of a digital musical instrument interface (MIDI output)).

The computing device 1800 can use a GPS device 1818 (or equivalent interface circuitry as discussed above). The GPS device 1818 can be in communication with a satellite-based system and can be a location of the computing device 1800 received as is known in the art.

The computing device 1800 can use a different output device 1810 (or equivalent interface circuitry as discussed above). The examples of the other output device 1810 may include an audio codec, video codec, printer, wired or wireless transmitter to provide information to other devices, or an additional storage device.

The computing device 1800 can use a different input device 1820 (or equivalent interface circuitry as discussed above). The examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image pickup device, a keyboard, a cursor control device, e.g. A mouse, stylus, touch pad, bar code reader, quick response (QR) code reader, any sensor, or radio frequency identification (RFID) reader.

The computing device 1800 can have any desired form factor, such as. A handheld or mobile computing device (e.g., cell phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server computing device or other networked computing component, a vehicle computing device (e.g. a vehicle control unit), a laptop computing device, a printer, a scanner, monitor, set-top box, entertainment controller, digital camera, digital video recorder, or portable computing device. In some embodiments, the computing device 1800 be any other electronic device that processes data.

The following sections provide various examples of the embodiments disclosed herein. Example 1 is a microelectronic structure that includes a patterned area containing a first conductive line and a second conductive line, the second conductive line being adjacent to the first conductive line, the first conductive line, and the second conductive line have a pitch that is less than 30 nanometers, the first conductive line has a line edge roughness that is less than 1.2 nanometers, and the second conductive line has a line edge roughness that is less than 1.2 nanometers.

Example 2 contains the subject matter of Example 1 and further specifies that the microelectronic structure further includes a disordered area with a disordered lamellar pattern, and the disordered area is coplanar with the patterned area.

Example 3 contains the subject matter of Example 2 and further specifies that the microelectronic structure is part of a die and the disordered area is part of a transition area of the die under a guard ring of the die or in a frame of the die.

Example 4 contains the subject matter of any of Examples 2-3 and further specifies that the first conductive line contains a conductive material and the disordered area contains a material having a material composition identical to that of the conductive material.

Example 5 contains the subject matter of any of Examples 2-4 and further specifies that the patterned area contains a dielectric material and the disordered area contains a material having the same material composition as the dielectric material.

Example 6 contains the subject matter of any of Examples 1-5 and further specifies that a gap between the first conductive line and the second conductive line is less than 15 nanometers.

Example 7 contains the subject matter of any of Examples 1-6 and further specifies that a gap between the first conductive line and the second conductive line is less than 12 nanometers.

Example 8 contains the subject matter of any of Examples 1-6 and further specifies that the first conductive line has a width that is less than 15 nanometers.

Example 9 contains the subject matter of any of Examples 1-8 and further specifies that the first conductive line has a width that is less than 12 nanometers.

Example 10 includes the subject matter of any of Examples 1-9 and further specifies that the second conductive line has a width that is less than 15 nanometers.

Example 11 contains the subject matter of any of Examples 1-10 and further specifies that the second conductive line has a width that is less than 12 nanometers.

Example 12 contains the subject matter of any of Examples 1-11 and further specifies that the first conductive line and the second conductive line are part of a set of conductive lines, the set of conductive lines includes more than two conductive lines and the spacing of the the first conductive line and the second conductive line is the same as a distance between adjacent ones of the conductive lines in the set of conductive lines.

Example 13 contains the subject matter of any of Examples 1-12 and further specifies that the microelectronic structure further includes space-division artifacts in the vicinity of the patterned area.

Example 14 includes the subject matter of Example 13 and further specifies that the pitch-pitch artifacts include one or more half-ring patterns in a dielectric material.

Example 15 includes the subject matter of any of Examples 1-14 and further specifies that the widths of at least some of the conductive lines in the patterned area across the conductive lines are periodic.

Example 16 includes the subject matter of any of Examples 1-15 and further specifies that the second conductive line has a width that is greater than a width of the first conductive line.

Example 17 includes the subject matter of Example 16 and further specifies that the line edge roughness of the second conductive line is greater than the line edge roughness of the first conductive line.

Example 18 includes the subject matter of Example 17 and further specifies that the patterned area includes a different conductive line, a width of the other conductive line is larger than a width of the second conductive line and a line edge roughness of the other conductive line is larger than the line edge roughness of the second conductive line.

Example 19 includes the subject matter of any of Examples 16-18 and further specifies that the width of the second conductive line is at least three times greater than a width of the first conductive line.

Example 20 includes the subject matter of any of Examples 1-15 and further specifies that the first conductive line has a width that is greater than a width of the second conductive line.

Example 21 includes the subject matter of Example 20 and further specifies that the line edge roughness of the first conductive line is greater than the line edge roughness of the second conductive line.

Example 22 includes the subject matter of Example 21, and further specifies that the patterned area includes another conductive line, a width of the other conductive line is greater than a width of the first conductive line, and a line edge roughness of the other conductive line is greater than is the line edge roughness of the first conductive line.

Example 23 includes the subject matter of Example 22 and further specifies that the width of the first conductive line is at least three times greater than a width of the second conductive line.

Example 24 includes the subject matter of any of Examples 1-23 and further specifies that a gap between the first conductive line and the second conductive line is larger than a gap between the second conductive line and a conductive line adjacent to the second conductive line.

Example 25 includes the subject matter of any of Examples 1-23 and further specifies that a gap between the first conductive line and the second conductive line is smaller than a gap between the second conductive line and a conductive line adjacent to the second conductive line.

Example 26 contains the subject matter of any of Examples 1-25 and further specifies that the patterned area is a first patterned area, the microelectronic structure further includes a second patterned area having a first conductive line and a second conductive line, wherein the second conductive line of the second patterned area is adjacent to the first conductive line of the second patterned area, the first conductive line of the second patterned area and the second conductive line of the second patterned area have a spacing that is greater than 24 nanometers.

Example 27 incorporates the subject matter of Example 26 and further specifies that the first conductive line of the second patterned area and the second conductive line of the second patterned area are spaced apart greater than 30 nanometers.

Example 28 contains the subject matter of any of Examples 26-27 and further specifies that the first conductive line of the second patterned region has a line edge roughness greater than 1.2 nanometers and the second conductive line has a line edge roughness, that is larger than 1.2 nanometers.

Example 29 includes the subject matter of any of Examples 26-28 and further specifies that the first conductive line of the second patterned region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of 2.

Example 30 includes the subject matter of any of Examples 26-29 and further specifies that the second conductive line of the second patterned region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of 2.

Example 31 contains the subject matter of any of Examples 26-30 and further specifies that the second patterned area is coplanar with the first patterned area.

Example 32 includes the subject matter of any of Examples 26-31 and further specifies that the second patterned area is in the same layer of a metallization stack as the first patterned area.

Example 33 includes the subject matter of any of Examples 1-32 and further specifies that the first conductive line has a line width roughness and the line width roughness of the first conductive line is not equal to the line edge roughness of the first conductive line multiplied by the square root of 2.

Example 34 includes the subject matter of any of Examples 1-33 and further specifies that the second conductive line has a line width roughness and the line width roughness of the second conductive line is not equal to the line edge roughness of the second conductive line multiplied by the square root of 2.

Example 35 includes the subject matter of any of Examples 1-34 and further specifies that the patterned area includes a third conductive line and a fourth conductive line, the third conductive line being between the second conductive line and the fourth conductive line , the third conductive line has a line edge roughness greater than 1.2 nanometers and the fourth conductive line has a line edge roughness less than 1.2 nanometers.

Example 36 contains the subject matter of any of Examples 1-35 and further specifies that the microelectronic structure further includes a via in conductive contact with the first conductive line.

Example 37 includes the subject matter of Example 36 and further specifies that the via is in a dielectric material and the dielectric material includes a photoacid generator.

Example 38 includes the subject matter of any of Examples 36-37 and further specifies that the dielectric material includes a quencher.

Example 39 includes the subject matter of any of Examples 36-38 and further specifies that the via has side surfaces that are self-aligned with the side surfaces of the first conductive line.

Example 40 includes the subject matter of any of Examples 36-38 and further specifies that the via is not in contact with the dielectric material adjacent to the first conductive line in the patterned area.

Example 41 contains the subject matter of any of Examples 1-40 and further specifies that the microelectronic structure further includes a via in conductive contact with the second conductive line.

Example 42 includes the subject matter of Example 41 and further specifies that the via is in a dielectric material and the dielectric material includes a photoacid generator.

Example 43 includes the subject matter of any of Examples 41-42 and further specifies that the dielectric material includes an eraser.

Example 44 includes the subject matter of any of Examples 41-43 and further specifies that the via has side surfaces that are self-aligned with the side surfaces of the first conductive line.

Example 45 includes the subject matter of any of Examples 41-43 and further specifies that the via is not in contact with the dielectric material adjacent to the second conductive line in the patterned area.

Example 46 includes the subject matter of any of Examples 1-45 and further specifies that the microelectronic structure further includes a device layer and the patterned area is included in an interconnection layer above or below the device layer.

Example 47 includes the subject matter of Example 46 and further specifies that the microelectronic structure further includes conductive contacts and the patterned area is between the conductive contacts and the device layer.

Example 48 includes the subject matter of any of Examples 1-47 and further specifies that the patterned area is included in an M0 interconnection layer.

Example 49 contains the subject matter of any of Examples 1-47 and further specifies that the patterned area is included in an M1 interconnection layer.

Example 50 includes the subject matter of any of Examples 1-47 and further specifies that the patterned area is included in an M2 interconnection layer.

Example 51 includes the subject matter of any of Examples 1-50 and further specifies that the first conductive line is parallel to the second conductive line.

Example 52 is a microelectronic structure that includes: a patterned area that includes a first conductive line and a second conductive line, the second conductive line being the first conductive Line is adjacent; and a disordered region having a disordered lamellar pattern, the disordered region being coplanar with the patterned region.

Example 53 includes the subject matter of Example 52 and further specifies that the first conductive line includes a conductive material and the disordered area includes a material having a material composition the same as the conductive material.

Example 54 includes the subject matter of any of Examples 52-53 and further specifies that the patterned area includes a dielectric material and the disordered area includes a material having a material composition the same as the dielectric material.

Example 55 includes the subject matter of any of Examples 52-54 and further specifies that a gap between the first conductive line and the second conductive line is less than 15 nanometers.

Example 56 includes the subject matter of any of Examples 52-55 and further specifies that a gap between the first conductive line and the second conductive line is less than 12 nanometers.

Example 57 includes the subject matter of any of Examples 52-55 and further specifies that the first conductive line has a width that is less than 15 nanometers.

Example 58 includes the subject matter of any of Examples 52-57 and further specifies that the first conductive line has a width that is less than 12 nanometers.

Example 59 includes the subject matter of any of Examples 52-58 and further specifies that the second conductive line has a width that is less than 15 nanometers.

Example 60 includes the subject matter of any of Examples 52-59 and further specifies that the second conductive line has a width that is less than 12 nanometers.

Example 61 contains the subject matter of any of Examples 52-60 and further specifies that the first conductive line and the second conductive line are part of a set of conductive lines, the set of conductive lines includes more than two conductive lines and a spacing of the the first conductive line and the second conductive line is the same as a distance between adjacent ones of the conductive lines in the set of conductive lines.

Example 62 includes the subject matter of any of Examples 52-61 and further specifies that the microelectronic structure further includes space-division artifacts in the vicinity of the patterned area.

Example 63 includes the subject matter of Example 62 and further specifies that the pitch-pitch artifacts include one or more half-ring patterns in a dielectric material.

Example 64 includes the subject matter of any of Examples 52-63 and further specifies that the widths of at least some of the conductive lines in the patterned area across the conductive lines are periodic.

Example 65 includes the subject matter of any of Examples 52-64 and further specifies that the second conductive line has a width that is greater than a width of the first conductive line.

Example 66 includes the subject matter of Example 65 and further specifies that a line edge roughness of the second conductive line is greater than a line edge roughness of the first conductive line.

Example 67 includes the subject matter of Example 66 and further specifies that the patterned area includes another conductive line, a width of the other conductive line is greater than a width of the second conductive line, and a line edge roughness of the other conductive line is greater than is the line edge roughness of the second conductive line.

Example 68 includes the subject matter of any of Examples 65-67 and further specifies that the width of the second conductive line is at least three times greater than a width of the first conductive line.

Example 69 includes the subject matter of any of Examples 52-64 and further specifies that the first conductive line has a width that is greater than a width of the second conductive line.

Example 70 includes the subject matter of Example 69 and further specifies that a line edge roughness of the first conductive line is greater than a line edge roughness of the second conductive line.

Example 71 includes the subject matter of Example 70, and further specifies that the patterned area includes another conductive line, a width of the other conductive line is greater than a width of the first conductive line, and a line edge roughness of the other conductive line is greater than is the line edge roughness of the first conductive line.

Example 72 includes the subject matter of Example 71 and further specifies that the width of the first conductive line is at least three times greater than a width of the second conductive line.

Example 73 includes the subject matter of any of Examples 52-72 and further specifies that a gap between the first conductive line and the second conductive line is larger than a gap between the second conductive line and a conductive line adjacent to the second conductive line.

Example 74 includes the subject matter of any of Examples 52-72 and further specifies that a gap between the first conductive line and the second conductive line is smaller than a gap between the second conductive line and a conductive line adjacent to the second conductive line.

Example 75 includes the subject matter of any of Examples 52-74 and further specifies that the patterned area is a first patterned area, the microelectronic structure further includes a second patterned area having a first conductive line and a second conductive line, wherein the second conductive line of the second patterned area is adjacent to the first conductive line of the second patterned area, the first conductive line of the second patterned area and the second conductive line of the second patterned area have a spacing that is greater than 24 nanometers.

Example 76 includes the subject matter of Example 75 and further specifies that the first conductive line of the second patterned area and the second conductive line of the second patterned area are spaced apart greater than 30 nanometers.

Example 77 contains the subject matter of any of Examples 75-76 and further specifies that the first conductive line of the second patterned region has a line edge roughness greater than 1.2 nanometers and the second conductive line has a line edge roughness, that is larger than 1.2 nanometers.

Example 78 includes the subject matter of any of Examples 75-77 and further specifies that the first conductive line of the second patterned region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of 2.

Example 79 includes the subject matter of any of Examples 75-78 and further specifies that the second conductive line of the second patterned region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of 2.

Example 80 includes the subject matter of any of Examples 75-79 and further specifies that the second patterned area is coplanar with the first patterned area.

Example 81 includes the subject matter of any of Examples 75-80 and further specifies that the second patterned area is in the same layer of a metallization stack as the first patterned area.

Example 82 includes the subject matter of any of Examples 52-81 and further specifies that the first conductive line has a line width roughness and the line width roughness of the first conductive line is not equal to the line edge roughness of the first conductive line multiplied by the square root of 2.

Example 83 includes the subject matter of any of Examples 52-82 and further specifies that the second conductive line has a line width roughness and the line width roughness of the second conductive line is not equal to the line edge roughness of the second conductive line multiplied by the square root of 2.

Example 84 includes the subject matter of any of Examples 52-83 and further specifies that the patterned area includes a third conductive line and a fourth conductive line, the third conductive line being between the second conductive line and the fourth conductive line , the third conductive line has a line edge roughness greater than 1.2 nanometers and the fourth conductive line has a line edge roughness less than 1.2 nanometers.

Example 85 includes the subject matter of any of Examples 52-84 and further specifies that the microelectronic structure further includes a via in conductive contact with the first conductive line.

Example 86 includes the subject matter of Example 85 and further specifies that the via is in a dielectric material and the dielectric material includes a photoacid generator.

Example 87 includes the subject matter of any of Examples 85-86 and further specifies that the dielectric material includes an eraser.

Example 88 includes the subject matter of any of Examples 85-87 and further specifies that the via has side surfaces that are self-aligned with the side surfaces of the first conductive line.

Example 89 includes the subject matter of any of Examples 85-87 and further specifies that the via is not in contact with the dielectric material adjacent to the first conductive line in the patterned area.

Example 90 includes the subject matter of any of Examples 52-89 and further specifies that the microelectronic structure further includes a via in conductive contact with the second conductive line.

Example 91 includes the subject matter of Example 90 and further specifies that the via is in a dielectric material and the dielectric material includes a photoacid generator.

Example 92 includes the subject matter of any of Examples 90-91 and further specifies that the dielectric material includes an eraser.

Example 93 includes the subject matter of any of Examples 90-92 and further specifies that the via has side surfaces that are self-aligned with the side surfaces of the first conductive line.

Example 94 includes the subject matter of any of Examples 90-92 and further specifies that the via is not in contact with the dielectric material adjacent to the second conductive line in the patterned area.

Example 95 includes the subject matter of any of Examples 52-94 and further specifies that the microelectronic structure further includes a device layer and the patterned area is included in an interconnection layer above or below the device layer.

Example 96 includes the subject matter of Example 95 and further specifies that the microelectronic structure further includes conductive contacts and the patterned area is between the conductive contacts and the device layer.

Example 97 includes the subject matter of any of Examples 52-96 and further specifies that the patterned area is included in an M0 interconnection layer.

Example 98 includes the subject matter of any of Examples 52-96 and further specifies that the patterned area is included in an M1 interconnection layer.

Example 99 contains the subject matter of any of Examples 52-96 and further specifies that the patterned area is included in an M2 interconnection layer.

Example 100 includes the subject matter of any of Examples 52-99 and further specifies that the first conductive line is parallel to the second conductive line.

Example 101 is a microelectronic structure that includes: a first patterned area containing a first conductive line; and a second patterned area including a second conductive line, the second patterned area being coplanar with the first patterned area, the first conductive line having a first line width roughness and a first line edge roughness, the first Line width roughness is not equal to the first line edge roughness multiplied by the square root of 2, the second conductive line has a second line width roughness and a second line edge roughness, and the second line width roughness is equal to the second line edge roughness multiplied by the square root of 2.

Example 102 includes the subject matter of Example 101 and further specifies that the microelectronic structure further includes a disordered region having a disordered lamellar pattern, and the disordered region is coplanar with the first patterned region.

Example 103 includes the subject matter of Example 102 and further specifies that the microelectronic structure is part of a die and the disordered area is part of a transition area of the die under a guard ring of the die or in a frame of the die.

Example 104 contains the subject matter of one of Examples 102-103 and further specifies that the first conductive line contains a conductive material and the disordered region contains a material with the same material composition as the conductive material.

Example 105 includes the subject matter of any of Examples 102-104 and further specifies that the first patterned region contains a dielectric material and the disordered region contains a material having a material composition identical to that of the dielectric material.

Example 106 includes the subject matter of any of Examples 101-105 and further specifies that a pitch of the conductive lines in the first patterned area is less than 30 nanometers.

Example 107 contains the subject matter of any of Examples 101-106 and further specifies that a pitch of the conductive lines in the first patterned area is less than 24 nanometers.

Example 108 includes the subject matter of any of Examples 101-106 and further specifies that the first conductive line has a width that is less than 15 nanometers.

Example 109 includes the subject matter of any of Examples 101-108 and further specifies that the first conductive line has a width that is less than 12 nanometers.

Example 110 includes the subject matter of any of Examples 101-109 and further specifies that the microelectronic structure further includes space-division artifacts in the vicinity of the first patterned area.

Example 111 includes the subject matter of Example 110 and further specifies that the pitch-pitch artifacts include one or more half-ring patterns in a dielectric material.

Example 112 includes the subject matter of any of Examples 101-111 and further specifies that the widths of at least some conductive lines in the first patterned area are periodic across the at least some conductive lines.

Example 113 includes the subject matter of any of Examples 101-112 and further specifies that the second conductive line has a width that is greater than a width of the first conductive line.

Example 114 includes the subject matter of Example 113 and further specifies that the second line edge roughness is greater than the first line edge roughness.

Example 115 includes the subject matter of Example 114 and further specifies that the second line edge roughness is greater than 1.2 nanometers.

Example 116 includes the subject matter of any of Examples 113-115 and further specifies that the first line edge roughness is less than 1.2 nanometers.

Example 117 includes the subject matter of any of Examples 101-112 and further specifies that the first conductive line has a width that is greater than a width of the second conductive line.

Example 118 includes the subject matter of any of Examples 101-117 and further specifies that a pitch of the conductive lines in the second patterned area is greater than 30 nanometers.

Example 119 includes the subject matter of any of Examples 101-118 and further specifies that the second patterned area is coplanar with the first patterned area.

Example 120 includes the subject matter of any of Examples 101-119 and further specifies that the second patterned area is in the same layer of a metallization stack as the first patterned area.

Example 121 includes the subject matter of any of Examples 101-120 and further specifies that the microelectronic structure further includes a via in conductive contact with the first conductive line.

Example 122 includes the subject matter of Example 121 and further specifies that the via is in a dielectric material and the dielectric material includes a photoacid generator.

Example 123 contains the subject matter of one of Examples 121-122 and further specifies that the dielectric material contains a quencher.

Example 124 includes the subject matter of any of Examples 121-123 and further specifies that the via has side surfaces that are self-aligned with the side surfaces of the first conductive line.

Example 125 includes the subject matter of any of Examples 121-123 and further specifies that the via is not in contact with the dielectric material adjacent to the first conductive line in the first patterned area.

Example 126 includes the subject matter of any of Examples 101-125 and further specifies that the microelectronic structure further includes a device layer and the first patterned area is included in an interconnection layer above or below the device layer.

Example 127 includes the subject matter of Example 126 and further specifies that the microelectronic structure further includes conductive contacts and the first patterned area is between the conductive contacts and the device layer.

Example 128 includes the subject matter of any of Examples 101-127 and further specifies that the first patterned area is included in an M0 interconnection layer.

Example 129 includes the subject matter of any of Examples 101-127 and further specifies that the first patterned area is included in an M1 interconnection layer.

Example 130 includes the subject matter of any of Examples 101-127 and further specifies that the first patterned area is included in an M2 interconnection layer.

Example 131 includes the subject matter of any of Examples 101-130 and further specifies that the first conductive line is parallel to the second conductive line.

Example 132 is a computing device that includes: a die that includes any of the microelectronic structures of any one of claims 1-131; and a circuit board, the die being communicatively coupled to the circuit board.

Example 133 contains the subject matter of example 132 and further specifies that the die is contained in an assembly and that the assembly is coupled to the circuit board in terms of communication technology.

Example 134 contains the subject matter of example 133 and further specifies that the assembly is communicatively coupled to the circuit board by a solder.

Example 135 contains the subject matter of any of Examples 132-134 and further specifies that the circuit board is a motherboard.

Example 136 includes the subject matter of any of Examples 132-135 and further specifies that the die is part of a processing device or a storage device.

Example 137 includes the subject matter of any of Examples 132-136 and further specifies that the computing device is a mobile computing device.

Example 138 includes the subject matter of any of Examples 132-136 and further specifies that the computing device is a laptop computing device.

Example 139 includes the subject matter of any of Examples 132-136 and further specifies that the computing device is a desktop computing device.

Example 140 includes the subject matter of any of Examples 132-136 and further specifies that the computing device is a portable computing device.

Example 141 includes the subject matter of any of Examples 132-136 and further specifies that the computing device is a server computing device.

Example 142 includes the subject matter of any of Examples 132-136 and further specifies that the computing device is a vehicle computing device.

Example 143 includes the subject matter of any of Examples 132-142 and further specifies that the computing device further include a display contains, which is communicatively coupled to the circuit board.

Example 144 includes the subject matter of any of Examples 132-143 and further specifies that the computing device further includes an antenna that is communicatively coupled to the circuit board.

Example 145 includes the subject matter of any of Examples 132-144 and further specifies that the computing device further includes a housing around the die and circuit board.

Example 146 includes the subject matter of Example 145 and further specifies that the housing includes a plastic material.

Example 147 includes one of the manufacturing methods disclosed herein.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 63/033721 [0001]

Claims (20)

Microelectronic structure, which includes: a patterned area including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line, the first conductive line and the second conductive line are spaced less than 30 nanometers apart , the first conductive line has a line edge roughness that is less than 1.2 nanometers, and the second conductive line has a line edge roughness that is less than 1.2 nanometers. Microelectronic structure according to Claim 1 wherein the microelectronic structure further includes a disordered area having a disordered lamellar pattern, and the disordered area is coplanar with the patterned area. Microelectronic structure according to Claim 1 wherein the microelectronic structure further includes space-division artifacts in the vicinity of the patterned area. Microelectronic structure according to one of the Claims 1 - 3 wherein the patterned area is a first patterned area, the microelectronic structure further includes a second patterned area including a first conductive line and a second conductive line, the second conductive line having the second a patterned portion of the first conductive line of the second patterned area is adjacent, the first conductive line of the second patterned area and the second conductive line of the second patterned area are spaced apart greater than 24 nanometers is. Microelectronic structure according to Claim 4 wherein the first conductive line of the second patterned region has a line edge roughness that is greater than 1.2 nanometers and the second conductive line has a line edge roughness that is greater than 1.2 nanometers. Microelectronic structure according to Claim 4 wherein the first conductive line of the second patterned region has a line width roughness and a line edge roughness, and the line width roughness is equal to the line edge roughness multiplied by the square root of 2. Microelectronic structure according to Claim 4 wherein the second patterned area is coplanar with the first patterned area. Microelectronic structure according to Claim 4 wherein the second patterned area is in the same layer of a metallization stack as the first patterned area. Microelectronic structure according to one of the Claims 1 - 3 wherein the first conductive line has a line width roughness and the line width roughness of the first conductive line is not equal to the line edge roughness of the first conductive line multiplied by the square root of 2. Microelectronic structure according to one of the Claims 1 - 3 wherein the patterned area includes a third conductive line and a fourth conductive line, the third conductive line is between the second conductive line and the fourth conductive line, the third conductive line has a line edge roughness greater than 1.2 nanometers, and the fourth conductive line has a line edge roughness less than 1.2 nanometers. Microelectronic structure, which includes: a patterned area including a first conductive line and a second conductive line, the second conductive line being adjacent to the first conductive line; and a disordered area having a disordered lamellar pattern, the disordered area being coplanar with the patterned area. Microelectronic structure according to Claim 11 wherein the first conductive line contains a conductive material and the disordered area contains a material with the same material composition as the conductive material. Microelectronic structure according to Claim 11 wherein the patterned area contains a dielectric material and the disordered area contains a material having the same material composition as the dielectric material. Microelectronic structure according to one of the Claims 11 - 13th , wherein a gap between the first conductive line and the second conductive line is less than 15 nanometers. Microelectronic structure according to one of the Claims 11 - 13th wherein the microelectronic structure further includes a device layer and the patterned area in a Interconnection layer is included above or below the device layer. Microelectronic structure, which includes: a first patterned area including a first conductive line; and a second patterned area including a second conductive line, the second patterned area being coplanar with the first patterned area, the first conductive line having a first line width roughness and a first line edge roughness, the first line width roughness is not equal to the first line edge roughness multiplied by the square root of 2, the second conductive line has a second line width roughness and a second line edge roughness, and the second line width roughness is equal to the second line edge roughness multiplied by the square root of 2. Microelectronic structure according to Claim 16 wherein the microelectronic structure further includes a via that is in conductive contact with the first conductive line. Microelectronic structure according to Claim 17 wherein the via is in a dielectric material and the dielectric material includes a photoacid generator. Microelectronic structure according to Claim 18 wherein the dielectric material includes an eraser. Microelectronic structure according to one of the Claims 17 - 19th wherein the via has side surfaces that are self-aligned with the side surfaces of the first conductive line.

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