DE102020130114A1 - Measuring device for measuring the bus current in a data bus line with intermediate storage of the offset voltage of a differential amplifier with a changeover switch - Google Patents

Abstract

The invention relates to a measuring device for detecting a digitized value for the bus current within the single-wire data bus line of a single-wire data bus (EDB) by means of a clocked circuit for amplifying an input signal, the circuit having two capacitors and several switches and an analog-to-digital converter. In a first phase the capacitances are precharged with the parasitic values of the circuit. In the second phase, the actual voltage is measured, amplified and passed on to the analog-to-digital converter.

Description

This application takes priority over the German patent application 10 2019 131 250.7 from 19.11.2019.

Generic term

The invention is directed to a clocked measuring device for bus current measurement of a single-wire data bus ( DB ) with intermediate storage of the offset voltage of a differential amplifier of the measuring device.

General introduction

The invention deals with the pre-amplification of the voltage drop at a bus shunt resistor that is external to the clocked amplifier circuit ( RS ) in a single-wire data bus line of a single-wire data bus. A full scale of 80mV, for example, regardless of temperature and mass offset, with an input offset of less than 40µV, for example, and a very low gain error and a very low input current for the subsequent conversion with a standard analog-to-digital converter should be achieved.

State of the art

• Zum Ersten sind voll differentielle, getaktete Systeme zu nennen, welche einen hohen Schaltungsaufwand (z.B. Chopper-Verfahren mit anschließender Filterung) aufgrund der Offsetanforderungen besitzen und typischerweise einen speziellen, differentiellen Analog-zu-Digital-Wandler umfassen, womit meist einhergeht, dass mehrere Analog-zu-Digital-Wandler im Gesamtsystem verbaut werden müssen.

Previous solutions to this problem:

• First of all, fully differential, clocked systems are to be mentioned, which have a high circuit complexity (e.g. chopper method with subsequent filtering) due to the offset requirements and typically include a special, differential analog-to-digital converter, which usually means that several analog -to-digital converter must be installed in the overall system.

Second, there are mixed systems with a differential clocked input stage, a filter and a differential-to-single-ended conversion, which can be used for standard analog-to-digital converters, but the last stage usually does not completely eliminate the offset can guarantee. Furthermore, the circuit complexity is also very large here.

Thirdly, clocked single-ended amplifiers should be mentioned, which are unsuitable for a mass offset, as always occurs in automobiles.

The scriptures are exemplary US 2018/0 062 595 A1 and EP 2 520 942 A2 called.

task

The proposal is therefore based on the object of creating a solution which does not have the above disadvantages of the prior art and has further advantages.

The amplifier circuit for measuring a bus current is intended to feed the input signal of a bus shunt resistor voltage to a bus shunt resistor ( RS ) of, for example, 0 ... 80mV as a differential signal with a common-mode component of, for example + -100mV (ground offset) for conversion with a subsequent standard analog-to-digital converter, with an input offset of, for example, <40µV and a gain error of, for example <0.5% for the entire measuring chain including the analog-to-digital converter and its reference would have to be observed. Since an input filter must typically be provided in front of the amplifier in the application circuit, care must be taken to ensure that the input current is low so that it does not generate additional errors during the measurement.

This object is achieved by a device according to claim 1.

Solution of the task

The proposed circuit mainly includes a bus shunt resistor ( RS ), a supply line, the clocked amplifier circuit and the analog-to-digital converter ( ADC ).

In the case of a clocked amplifier of the type described at the outset, the problem is solved according to the proposal in that storage of the offset voltage and storage of the input and output common-mode voltage in a first capacitor ( C1 ) and that amplification and the necessary differential-to-single-ended conversion via charge equalization with a second capacitance ( C2 ) takes place in a differential amplifier circuit.

The invention thus consists of a clocked differential amplifier circuit with two capacitances ( C1 , C2 ), which are synchronized with the clock ( CLK ) of the analog-to-digital converter ( ADC ) is working.

In the first phase (ϕ1) the first capacitance ( C1 ) the offset voltage of the differential amplifier via the switch position ( V ) as well as the input and output common mode voltage.

In the second phase (ϕ2), the actual conversion phase (start of the conversion of the input value of the analog-to-digital converter by the analog-to-digital converter ( ADC )), the voltage of the first capacitance becomes ( C1 ) to which the input differential voltage is transferred. The shifted charge is converted into a second capacitance by means of the differential amplifier circuit ( C2 ) saved. The ratio of the capacity values of the two capacities ( C1 , C2 ) determines the gain factor, which can be 40 in the example chosen. Through the differential amplifier ( V ) this voltage is now low-resistance at the output of the differential amplifier ( V ) to disposal. The conversion of the output value of the differential amplifier ( V ) must be synchronized with the conversion by the analog-to-digital converter ( ADC ) in the second phase (ϕ2), since the output signal of the differential amplifier ( V ) is only valid in this second phase (ϕ2). Ie the analog-to-digital converter ( ADC ) must be designed in such a way that it receives the output signal of the differential amplifier ( V ) evaluates only in these second phases (ϕ2).

In variant 1 ( 1 ) a residual error remains because the input offset voltage of the differential amplifier ( V ) at the output of the differential amplifier ( V ) is present during the first phase (ϕ1) and thus forms the starting point for reloading. This results in a total input offset voltage of the offset voltage of the differential amplifier ( V ) divided by the gain of the circuit, which is determined by the capacitance ratio of the first capacitance ( C1 ) to the second capacity ( C2 ) is set.

To eliminate this error, variant 4 has a fourth switch ( P4 ) and a fifth switch ( P5 ) and variant 5 has a sixth switch ( P6 ) in the form of a toggle switch to adjust the offset voltage on the second capacitance (1) in the first phase ( C2 ) save. This means that the starting point is exactly the reference voltage without the offset error.

The five basic variants of the invention thus resulting are described below. If it is said that two components are connected to one another, this means, unless otherwise stated, that they can exchange a signal. This can be done through a direct electrical connection or through an indirect connection via switches or other components or blocks, such as multiplexers.

FIRST VARIANT (not claimed)

The first variant relates to a clocked circuit for amplifying an input signal, with a first capacitance ( C1 ), a second capacity ( C2 ) and a differential amplifier ( V ). The input signal is the differential voltage that is generated via a bus shunt resistor ( RS ) falls. The differential amplifier ( V ) has a positive input ( + ) and a negative input ( - ) on. In addition, the differential amplifier ( V ) an input offset voltage, which can also be 0V. A reference potential ( VREFH ) is used, which can also be defined virtually. The circuit has a positive circuit input ( IP ) and a negative circuit input ( IN ). Between the positive circuit input ( IP ) and the negative circuit input ( IN ) is the parasitic coupling capacitance ( CK ). Via a first lead resistance ( RP ) is the positive circuit input ( IP ) with a first connection of the bus shunt resistor ( RS ) connected. Via a second lead resistor ( RN ) is the negative circuit input ( IN ) with a second connection of the bus shunt resistor ( RS ) connected. The bus shunt resistor ( RS ) is with its first connection and with its second connection in the single-wire data bus line of the single-wire data bus ( EDB ) whose bus current is to be recorded. With the single-wire data bus ( EDB ) it can be, for example, a LIN data bus or another automotive single-wire data bus ( EDB ) act in the same way as the LIN bus, whereby the ground return in the automobile is preferably carried out via the metal body of the car. The clocking of the clocked circuit has a first time phase (ϕ1) and a second time phase (ϕ2). The first temporal phase (ϕ1) and a second temporal phases (ϕ2) alternate in the course of time. Further time phases may be necessary in more complicated overall circuits. It is important that the first temporal phase (ϕ1) and the second temporal phase (ϕ2) follow one another in time for the duration of the operation, with further phases possibly being inserted. In the first phase (ϕ1) the first capacitance ( C1 ) with the sum of the input offset voltage of the differential amplifier ( V ) and the potential difference of the potential at the positive circuit input ( IP ) to the reference potential ( VREFH ) loaded. In this first phase (ϕ1) the second capacitance ( C2 ) discharged. In the second phase (ϕ2) the first capacitance ( C1 ) by the difference between the potential at the positive circuit input ( IP ) and the potential at the negative circuit input ( IP ) reloaded. The shifted charge is in this second phase (ϕ2) in the second capacitance ( C2 ), so that in this second phase (ϕ2) the magnitude of the output voltage of the differential amplifier ( V ) related to the reference potential ( VREFH ) essentially the amount of the potential difference between the potential at the positive circuit input ( IP ) minus the potential at the negative circuit input ( IN ) multiplied by the ratio of the first capacitance value of the first capacitance ( C1 ) to the second capacitance value of the second capacitance ( C2 ) minus the input offset voltage of the differential amplifier ( V ) is. In the first phase (ϕ1) this circuit analyzes its own offset and determines the neutralization values, while in the second phase (ϕ2) the actual amplification takes place and a valid amplification result at the output of the differential amplifier ( V ) is output. An analog-to-digital converter ( ADC ) converts the value of the signal at the output of the differential amplifier ( V ) into a digital current measurement value.

SECOND VARIANT (not claimed)

The second variant relates to a clocked circuit for amplifying an input signal with a first capacitance ( C1 ), a second capacity ( C2 ) and a differential amplifier ( V ), where the differential amplifier ( V ) a positive input ( + ) and a negative input ( - ) and an input offset voltage, which can also be 0V. The input signal is the differential voltage that is generated via a bus shunt resistor ( RS ) falls. Furthermore, the clocked circuit has a reference potential ( VREFH ), a positive circuit input ( IP ) and a negative circuit input ( IN ) on. Between the positive circuit input ( IP ) and the negative circuit input ( IN ) is the parasitic coupling capacitance ( CK ). Via a first lead resistance ( RP ) is the positive circuit input ( IP ) with a first connection of the bus shunt resistor ( RS ) connected. Via a second lead resistor ( RN ) is the negative circuit input ( IN ) with a second connection of the bus shunt resistor ( RS ) connected. The bus shunt resistor ( RS ) is with its first connection and with its second connection in the single-wire data bus line of the single-wire data bus ( EDB ) whose bus current is to be recorded. With the single-wire data bus ( EDB ) it can be, for example, a LIN data bus or another automotive single-wire data bus analogous to the LIN bus, with the ground return in the automobile preferably taking place via the metal body of the car. The clocking of the clocked circuit again comprises a first time phase (ϕ1) and a second time phase (ϕ2), which typically follow one another during the duration of operation. Reference is made to the above statements. In the first phase (ϕ1) the first capacitance ( C1 ) with the sum of the input offset voltage of the differential amplifier ( V ) and the potential difference of the potential at the positive circuit input ( IP ) to the reference potential ( VREFH ) loaded. In this first phase (ϕ1) the second capacitance ( C2 ) with the input offset voltage of the differential amplifier ( V ) loaded. In the second phase (ϕ2) the first capacitance ( C1 ) by the voltage difference from the potential at the positive circuit input ( IP ) minus the potential at the negative circuit input ( IN ) reloaded. In the second phase (ϕ2) the shifted charge in the second capacitance ( C2 ) saved. In this second phase (ϕ2) the magnitude of the output voltage of the amplifier ( V ) related to the reference potential ( VREFH ) the input voltage difference is essentially the amount of the potential difference between the potential at the positive circuit input ( IP ) minus the potential at the negative circuit input ( IN ) multiplied by the ratio of the first capacitance value of the first capacitance ( C1 ) to the second capacitance value of the second capacitance ( C2 ) minus the input offset voltage of the differential amplifier ( V ). An analog-to-digital converter ( ADC ) converts the value of the signal at the output of the differential amplifier ( V ) into a digital current measurement value.

THIRD VARIANT (not claimed)

The third variant relates to a clocked circuit for amplifying an input signal with a first capacitance ( C1 ), which has a first connection and a second connection, a second capacitance ( C2 ), which has a first connection and a second connection, a first switch ( P1 ), a second switch ( P2 ), a third switch ( P3 ), a differential amplifier ( V ), which has a positive input ( + ) and a negative input ( - ) and an input offset voltage, which can also be 0V, a reference potential ( VREFH ), a positive circuit input ( IP ) and a negative circuit input ( IN ). The input signal is the differential voltage that is generated via a bus shunt resistor ( RS ) falls. Between the positive circuit input ( IP ) and the negative circuit input ( IN ) is the parasitic coupling capacitance ( CK ). Via a first lead resistance ( RP ) is the positive circuit input ( IP ) with a first connection of the bus shunt resistor ( RS ) connected. Via a second lead resistor ( RN ) is the negative circuit input ( IN ) with a second connection of the bus shunt resistor ( RS ) connected. The bus shunt resistor ( RS ) is with its first connection and with its second connection in the single-wire data bus line of the single-wire data bus ( EDB ) whose bus current is to be recorded. With the single-wire data bus ( EDB ) it can be, for example, a LIN data bus or another automotive single-wire data bus analogous to the LIN bus, with the ground return in the automobile preferably taking place via the metal body of the car. The clocking of the clocked circuit has a first time phase (ϕ1) and a second time phase (ϕ2), which typically follow one another during the duration of operation. Reference is made here to the above. The negative input ( - ) of the differential amplifier ( V ) is with the first connection of the first capacitance ( C1 ) directly or indirectly connected. The second connection of the first capacitance ( C1 ) is via a first switch ( P1 ) with the positive circuit input ( IP ) connected. The second connection of the first capacitance ( C1 ) is via a second switch ( P2 ) with the negative circuit input ( IN ) connected. The first connection of the second capacitance ( C2 ) is connected to the negative input of the differential amplifier ( V ) connected. The second connection of the second capacitance ( C2 ) is connected to the output of the differential amplifier ( V ) connected. The third switch ( P3 ) is between the first of the second capacitance ( C2 ) and the second connection of the second capacitance ( C2 ) switched that it connects the first connection of the second capacitance ( C2 ) with the second connection of the second capacitance ( C2 ) can connect. The positive input ( + ) of the differential amplifier ( V ) is with the reference potential ( VREFH ) directly or indirectly connected. The first switch ( P1 ) and the third switch ( P3 ) are closed in the first phase (ϕ1). The first switch ( P1 ) and the third switch ( P2 ) are open in a second phase (ϕ2). The second switch ( P2 ) is closed in the second phase (ϕ2). The second switch ( P2 ) is open in the first phase (ϕ1). In the second phase (ϕ2) the amount of the output voltage at the output of the differential amplifier ( V ) related to the reference potential ( VREFH ) the amount of the input voltage difference between the potential of the positive circuit input ( IP ) minus the potential of the negative circuit input ( IN ) multiplied by the ratio of the capacity value of the first capacity ( C1 ) to the capacity value of the second capacity ( C1 ) minus the input offset voltage of the differential amplifier ( V ). An analog-to-digital converter ( ADC ) converts the value of the signal at the output of the differential amplifier ( V ) into a digital current measurement value.

FOURTH VARIANT (not claimed)

The fourth variant relates to a clocked circuit for amplifying an input signal with a first capacitance ( C1 ), which has a first connection and a second connection, a second capacitance ( C2 ), which has a first connection and a second connection, a first switch ( P1 ), a second switch ( P2 ), a third switch ( P3 ), a fourth switch ( P4 ), a fifth switch ( P5 ), a differential amplifier ( V ), which has a positive input ( + ) and a negative input ( - ) and an input offset voltage, which can also be 0V, a reference potential ( VREFH ), a positive circuit input ( IP ) and a negative circuit input ( IN ). The input signal is the differential voltage that is generated via a bus shunt resistor ( RS ) falls. Between the positive circuit input ( IP ) and the negative circuit input ( IN ) is the parasitic coupling capacitance ( CK ). Via a first lead resistance ( RP ) is the positive circuit input ( IP ) with a first connection of the bus shunt resistor ( RS ) connected. Via a second lead resistor ( RN ) is the negative circuit input ( IN ) with a second connection of the bus shunt resistor ( RS ) connected. The bus shunt resistor ( RS ) is with its first connection and with its second connection in the single-wire data bus line of the single-wire data bus ( EDB ) whose bus current is to be recorded. With the single-wire data bus ( EDB ) it can be, for example, a LIN data bus or another automotive single-wire data bus ( EDB ) act in the same way as the LIN bus, whereby the ground return in the automobile is preferably carried out via the metal body of the car. The clocking of the clocked circuit has a first time phase (ϕ1) and a second time phase (ϕ2), each of which follows one another during the duration of operation. Reference is made to the statements above in this regard. The negative input ( - ) of the differential amplifier ( V ) is with the first connection of the first capacitance ( C1 ) connected. The second connection of the first capacitance ( C1 ) is via the first switch ( P1 ) with the positive circuit input ( IP ) connected. The second connection of the first capacitance ( C1 ) is via the second switch ( P2 ) with the negative circuit input ( IN ) connected. The first connection of the second capacitance ( C2 ) is with the negative input ( - ) of the differential amplifier ( V ) connected. The second connection of the second capacitance ( C2 ) is via a fourth switch ( P4 ) with the output of the differential amplifier ( V ) connected. The second connection of the second capacitance ( C2 ) is via a fifth switch ( P5 ) with the reference potential ( VREFH ) connected. The third switch ( P3 ) is between the negative input ( - ) of the differential amplifier ( V ) and the output of the differential amplifier ( V ) switched. The positive input ( + ) of the differential amplifier ( V ) is with the reference potential ( VREFH ) connected. The the first switch ( P1 ) and the third switch ( P2 ) and the fifth switch ( P5 ) are closed in the first phase (ϕ1). The first switch ( P1 ) and the third switch ( P2 ) and the fifth switch ( P5 ) are open in the second phase (ϕ2). The second switch ( P2 ) and the fourth switch ( P4 ) are closed in the second phase (ϕ2). The second switch ( P2 ) and the fourth switch ( P4 ) are open in the first phase (ϕ1). In the second phase (ϕ2) the amount of the output voltage at the output of the differential amplifier ( V ) related to the reference potential ( VREFH ) the amount of the input voltage difference between the potential of the positive circuit input ( IP ) minus the potential of the negative circuit input ( IN ) multiplied by the ratio of the capacity value of the first capacity ( C1 ) to the capacity value of the second capacity ( C1 ). An analog-to-digital converter ( ADC ) converts the value of the signal at the output of the differential amplifier ( V ) into a digital current measurement value.

FIFTH VARIANT (claimed)

The fifth variant relates to a clocked circuit for amplifying an input signal with a first capacitance ( C1 ), which has a first connection and a second connection, a second capacitance ( C2 ), which has a first connection and a second connection, a first switch ( P1 ), a second switch ( P2 ), a third switch ( P3 ), a sixth switch ( P6 ), which is a changeover switch between the connection of a first connection of the sixth switch ( P6 ) with a second connection of the sixth switch ( P6 ) on the one hand and the connection of the first connection of the sixth switch ( P6 ) with a third connection of the sixth switch ( P6 ) is a differential amplifier ( V ), which has a positive input ( + ) and a negative input ( - ) and an input offset voltage, which can also be 0V, a reference potential ( VREFH ), a positive circuit input ( IP ) and a negative circuit input ( IN ). The input signal is the differential voltage that is generated via a bus shunt resistor ( RS ) falls. Between the positive circuit input ( IP ) and the negative circuit input ( IN ) is the parasitic coupling capacitance ( CK ). Via a first lead resistance ( RP ) is the positive circuit input ( IP ) with a first connection of the bus shunt resistor ( RS ) connected. Via a second lead resistor ( RN ) is the negative circuit input ( IN ) with a second connection of the bus shunt resistor ( RS ) connected. The bus shunt resistor ( RS ) is with its first connection and with its second connection in the single-wire data bus line of the single-wire data bus ( EDB ) whose bus current is to be recorded. With the single-wire data bus ( EDB ) it can be, for example, a LIN data bus or another automotive single-wire data bus ( EDB ) act in the same way as the LIN bus, whereby the ground return in the automobile is preferably carried out via the metal body of the car. The clocking of the clocked circuit has a first time phase (ϕ1) and a second time phase (ϕ2), which typically follow one another during the duration of operation. Reference is made to what has been said above. The negative input ( - ) of the differential amplifier ( V ) is with the first connection of the first capacitance ( C1 ) connected. The second connection of the first capacitance ( C1 ) is via the first switch ( P1 ) with the positive circuit input ( IP ) connected. The second connection of the first capacitance ( C1 ) via the second switch ( P2 ) is connected to the negative circuit input ( IN ) connected. The first connection of the second capacitance ( C2 ) is with the negative input ( - ) of the differential amplifier ( V ) connected. The second connection of the second capacitance ( C2 ) is connected to the first connection of the sixth switch ( P6 ) connected. The second connection of the second capacitance ( C2 ) can be connected via the second connection of the sixth switch ( P6 ) with the output of the differential amplifier ( V ) get connected. The second connection of the second capacitance ( C2 ) can also be done via the third connection of the sixth switch ( P6 ) with the reference potential ( VREFH ) get connected. The third switch ( P3 ) is between the negative input ( - ) of the differential amplifier ( V ) and the output of the differential amplifier ( V ) switched. The positive input ( + ) of the differential amplifier ( V ) is with the reference potential ( VREFH ) connected. The first switch ( P1 ) and the third switch ( P2 ) are closed in the first phase (ϕ1). The first switch ( P1 ) and the third switch ( P2 ) are open in the second phase (ϕ2). The second switch ( P2 ) is closed in the second phase (ϕ2). The second switch ( P2 ) is open in the first phase (ϕ1). The sixth switch ( P6 ) connects the second connection of the second capacitance ( C2 ) with the reference potential ( VREFH ) in the first phase (ϕ1) and the second connection of the second capacitance ( C2 ) with the output of the differential amplifier ( V ) in the second phase (ϕ2). In the second phase (ϕ2) the amount of the output voltage at the output of the differential amplifier ( V ) related to the reference potential ( VREFH ) the amount of the input voltage difference between the potential of the positive circuit input ( IP ) minus the potential of the negative circuit input ( IN ) multiplied by the ratio of the capacity value of the first capacity ( C1 ) to the capacity value of the second capacity ( C1 ). An analog-to-digital converter ( ADC ) converts the value of the signal at the output of the differential amplifier ( V ) into a digital current measurement value.

DESIGN VARIANTS (claimed)

In addition to these five basic variants, other characteristics can now be named that can be applied to these basic variants in variable combinations.

The clocked circuit preferably comprises the said analog-to-digital converter ( ADC ), where the output of the differential amplifier ( V ) with the input of the analog-to-digital converter ( ADC ) is connected and wherein the temporal phase position of the first phase (ϕ1) and the phase position of the second phase (ϕ2) are at least temporarily in a fixed time phase relationship and / or at least temporarily synchronous with the clock of a clocked analog-to-digital converter, so that the analog-to-digital converter ( ADC ) the output of the differential amplifier ( V ) is only evaluated at times within the second phase (ϕ2) when the output signal of the differential amplifier ( V ) is valid and stable.

The first capacity is preferred ( C1 ) formed by the parallel connection of several individual, similarly designed partial capacities and the second capacitance ( C2 ) formed by connecting several such partial capacities in series. In this way, the gain can easily be set independently of process fluctuations as a ratio of preferably whole positive numbers.

The clocked circuit preferably comprises an analog-to-digital converter ( ADC ), where the output of the differential amplifier ( V ) with the input of the analog-to-digital converter ( ADC ) is connected and where the reference potential ( VREFH ) of the amplifier the reference potential of the clocked analog-to-digital converter ( ADC ) is. In this way, independence from a possible mass offset is achieved.

The first capacity is preferred ( C1 ) designed as an interconnection of at least two partial capacitances, the clocked circuit having a seventh switch ( P7 ) and wherein the gain of the clocked circuit can be adjusted by the first capacitance value of the first capacitance ( C1 ) using the seventh switch ( P7 ) by bridging or disconnecting one or more partial capacities of the first capacity ( C1 ) is modified. This allows the circuit to be easily adapted to changing requirements during operation.

The second capacity is preferred ( C2 ) designed as an interconnection of at least two partial capacitances, the clocked circuit having an eighth switch ( P8 ) and wherein the gain of the circuit can be adjusted by changing the second capacitance value of the second capacitance ( C2 ) using the eighth switch ( P8 ) by bridging or disconnecting one or more partial capacities of the second capacity ( C2 ) is modified. This also allows the circuit to be easily adapted to changing requirements during operation.

For the purposes of this disclosure, two-wire data buses typically consist of two single-wire data buses run in parallel.

advantage

The amplifier circuit can do this by the voltage drop at the bus shunt resistor ( RS ) in the single-wire data bus line of the single-wire data bus ( EDB ) generated input differential signal with a common mode component other than zero for conversion with a standard analog-to-digital converter ( ADC ) process. A very small input offset is used for the subsequent analog-to-digital converter circuit ( ADC ) and a very small gain error for the entire measuring chain including the analog-to-digital converter ( ADC ) and its reference adhered to. A low input current ensures that it does not generate any additional errors in the input filter during the measurement. Only a single phase transition is necessary for each analog-to-digital conversion. This results in a very small input current, which does not generate any additional errors in the input filter during the measurement.

By storing the input common-mode voltage, the clocked amplifier proposed here can be applied to the positive circuit input in a very wide range, especially with potentials below ground potential ( IP ) and / or at the negative circuit input ( IN ) can be used. These potentials are only limited by the functionality of the switches. The gain is only due to the capacity ratios of the first capacity ( C1 ) and the second capacity ( C2 ) and thus achieves a very high linearity. In semiconductor processes, the ratio of capacitances can be set very precisely, so that the chosen architecture enables a very high accuracy of the amplification. The proposed, clocked amplifier always works at the same operating point on the input side, since both the positive input and the negative input of the differential amplifier ( V ) in both phases (ϕ1, ϕ2) almost at the potential of the reference potential ( VREFH ) are independent of the potential of the positive circuit input ( IP ) and the potential of the negative circuit input ( IN ) and thus independent of the input differential voltage of the overall circuit, so that here too the influence of parasitic variables is minimal. The proposed clocked amplifier always works at the same operating point on the input side, so that here too the influence of parasitic variables is minimal. According to the proposal described so far, the voltage reference is supplied from the outside and is used in the differential amplifier ( V ) and in the analog-to-digital converter ( ADC ) is used to obtain the full dynamic range for positive input voltages. This can be deviated from. The differential amplifier can be operated with half the reference voltage of the analog-to-digital converter ( ADC ) can be operated in order to avoid negative input differential voltages at the analog-to-digital converter ( ADC ) to be able to map.

The selected output common-mode voltage can preferably be the reference for the subsequent analog-to-digital converter ( ADC ) so that the full dynamic range is available. The built-in differential-to-single-ended conversion is also based on the topology of the circuit without the disadvantage of the resulting offset. Furthermore, no complex chopper amplifier with a subsequent filter is required to eliminate the offset.

The clocking only takes place during conversion. This means that only one phase change per conversion is required as clocking, so that a minimal input current is guaranteed. This is also directly proportional to the input differential voltage, so that at the most critical point of very small input differences, the input current is also minimal.

Parasitic capacitances at the entrance do not disturb the result, since they are not part of the charge path. The parasitic capacitance at the differential amplifier input is also irrelevant, since the voltage at this point does not change during the conversion. The parasitic capacitance at the output of the differential amplifier ( V ) also has no influence due to the low-resistance differential amplifier output. Accordingly, there is little influence from parasitic paths within the circuit.

Due to the simple structure of only one differential amplifier ( V ), two capacities ( C1 , C2 ) and a few switches ( P1 to P8 ) the structure is also significantly smaller than previous solutions and at the same time significantly better performing. The advantages are not limited to this.

Figure list

• 1 shows the proposed pulsed amplifier circuit in the third variant without bus shunt resistor.
• 2 shows the proposed clocked amplifier circuit in the third variant with an exemplary circuit for measuring a shunt resistor (RS).
• 3 shows the proposed clocked amplifier circuit in the third variant with an exemplary circuit for measuring a shunt resistor (RS) in the first phase (ϕ1).
• 4th shows the proposed clocked amplifier circuit in the third variant with an exemplary circuit for measuring a shunt resistor (RS) in the second phase (ϕ2).
• 5 shows the proposed clocked amplifier circuit in the fourth variant.
• 6th shows the proposed clocked amplifier circuit in the fourth variant with an exemplary circuit for measuring a shunt resistor (RS).
• 7th shows the proposed clocked amplifier circuit in the fourth variant with an exemplary circuit for measuring a shunt resistor (RS) in the first phase (ϕ1).
• 8th shows the proposed clocked amplifier circuit in the fourth variant with an exemplary circuit for measuring a shunt resistor (RS) in the second phase (ϕ2).
• 9 shows the proposed clocked amplifier circuit in the fifth variant.
• 10 shows the proposed clocked amplifier circuit in the fifth variant with an exemplary circuit for measuring a shunt resistor (RS).
• 11 shows the proposed clocked amplifier circuit in the fifth variant with an exemplary circuit for measuring a shunt resistor (RS) in the first phase (ϕ1).
• 12th shows the proposed clocked amplifier circuit in the fifth variant with an exemplary circuit for measuring a shunt resistor (RS) in the second phase (ϕ2).

Description of the figures

Figure 1

1 shows the proposed clocked amplifier circuit in the third variant in a simplified and schematic example. The first switch ( P1 ) is connected to the negative circuit input ( IN ) and a first connection of the first capacitance ( C1 ) connected. The second switch ( P2 ) is connected to the positive circuit input ( IP ) and the first connection of the first capacitance ( C1 ) connected. The second connection of the first capacitance ( C1 ) is with the negative input ( - ) of the differential amplifier ( V ) connected. The negative input of the differential amplifier ( V ) is connected to a first connection of the second capacitance ( C2 ) and connected to a first connection of the third switch ( P3 ) connected. The second connection of the third switch ( P3 ) and the second connection of the second capacitance ( C2 ) are connected to the output of the differential amplifier ( V ) connected. The positive connection of the differential amplifier ( V ) is with the reference potential ( VREFH ) connected. The output of the differential amplifier ( V ) is also connected to the input of the analog-to-digital converter ( ADC ) connected. The analog-to-digital converter ( ADC ) is played with one measure ( CLK ) clocked, which has a fixed phase relationship to the first phase signal for signaling the first phase (ϕ1) and to the second phase signal for signaling the second phase (ϕ2). The first switch ( P1 ) and the third switch ( P3 ) close in the first phase (ϕ1) and open in the second phase (ϕ2). The second switch closes in the second phase (ϕ2) and opens in the first phase (ϕ1). The analog-to-digital converter ( ADC ) converts the potential value at its input into a digitized measured value within the second phase (ϕ2) and transmits this preferably via a data bus ( DB ) out.

Figure 2

The 2 largely corresponds to 1 . It shows the proposed clocked amplifier circuit in the third variant with an exemplary circuit for measuring a shunt resistor ( RS ). The voltage at the shunt resistor ( RS ) is connected via two lead resistors ( RP , RN ) and a coupling capacity ( CK ) e.g. the supply line with the positive circuit input ( IP ) and the negative circuit input ( IN ) connected.

Figure 3

aufgeladen. Die Ausgangsspannung des Differenzverstärkers (V) ist dann: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)$$

The 3 equals to 2 . The switch positions in the first phase (ϕ1) are now shown. The first switch ( P1 ) and the third switch ( P3 ) are now closed. The second capacity ( C2 ) is discharged to the capacitance voltage V (C2) = OV. The first capacity ( C1 ) is based on the capacitance voltage $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IN}\right)$$

charged. The output voltage of the differential amplifier ( V ) is then: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)$$

Figure 4

The 4th equals to 2 . The switch positions in the second phase (ϕ2) are now shown. The second switch ( P2 ) is now closed.

umgeladen.The first capacity ( C1 ) is now on the tension $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IP}\right)$$

reloaded.

Die Ausgangsspannung des Differenzverstärkers (V) beträgt dann: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1/C}2-\text{V}\left(\text{OFFSET}\right)$$

Somit kann der Spannungsabfall über den Shunt-Widerstand (RS) mit einer sehr gut fertigungstechnisch einstellbaren Verstärkung von C1/C2 erfasst werden.The voltage across the second capacitance ( C2 ) is then: $$\text{V}\left(\text{C2}\right)=\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1 / <figure-callout id="2" label="C" filenames="DE102020130114A1\_0019.png,DE102020130114A1\_0020.png" state="{{state}}">C</figure-callout>}2$$

The output voltage of the differential amplifier ( V ) is then: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1 / C}2-\text{V}\left(\text{OFFSET}\right)$$

Thus, the voltage drop across the shunt resistor ( RS ) can be recorded with a gain of C1 / C2 that can be adjusted very well in terms of production technology.

Figure 5

5 shows the proposed clocked amplifier circuit in the fourth variant. It largely corresponds to 1 with the difference that the second connection of the second capacitance is now in the first phase (ϕ1) with the reference potential ( VREFH ) and in the second phase (ϕ2) with the output of the differential amplifier ( V ) is connected.

Figure 6

The 6th largely corresponds to 5 . It shows the proposed clocked amplifier circuit in the fourth variant with an exemplary circuit for measuring a shunt resistor ( RS ). The voltage at the shunt resistor ( RS ) is connected via two lead resistors ( RP , RN ) and a coupling capacity ( CK ) e.g. the supply line with the positive circuit input ( IP ) and the negative circuit input ( IN ) connected.

Figure 7

geladen. Die erste Kapazität (C1) wird auf die Kapazitätsspannung $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IN}\right)$$

aufgeladen. Die Ausgangsspannung des Differenzverstärkers (V) ist dann: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)$$

The 7th equals to 6th . The switch positions in the first phase (ϕ1) are now shown. The first switch ( P1 ) and the third switch ( P3 ) and the fifth switch ( P5 ) are now closed. The second capacity ( C2 ) is based on the capacitance voltage $$\text{V}\left(\text{C2}\right)=\text{V}\left(\text{OFFSET}\right)$$

loaded. The first capacity ( C1 ) is based on the capacitance voltage $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IN}\right)$$

charged. The output voltage of the differential amplifier ( V ) is then: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)$$

Figure 8

The 8th equals to 6th . The switch positions in the second phase (ϕ2) are now shown. The second switch ( P2 ) and the fourth switch ( P4 ) are now closed.

umgeladen.The first capacity ( C1 ) is now on the tension $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IP}\right)$$

reloaded.

Die Ausgangsspannung des Differenzverstärkers (V) beträgt dann: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1/C}2$$

Somit kann der Spannungsabfall über den Shunt-Widerstand (RS) nun jedoch offsetfrei mit einer sehr gut fertigungstechnisch einstellbaren Verstärkung C1/C2 erfasst werden.The voltage across the second capacitance is then: $$\text{V}\left(\text{C2}\right)=\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1 / <figure-callout id="2" label="C" filenames="DE102020130114A1\_0019.png,DE102020130114A1\_0020.png" state="{{state}}">C</figure-callout>}2+\text{V}\left(\text{OFFSET}\right)$$

The output voltage of the differential amplifier ( V ) is then: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1 / <figure-callout id="2" label="C" filenames="DE102020130114A1\_0019.png,DE102020130114A1\_0020.png" state="{{state}}">C</figure-callout>}2$$

Thus, the voltage drop across the shunt resistor ( RS ) but now offset-free with a gain that can be adjusted very well in terms of production technology C1 / C2 are recorded.

Figure 9

9 shows the proposed clocked amplifier circuit in the fifth variant. It largely corresponds to 5 . Instead of the fourth switch ( P4 ) and the fifth switch ( P6 ), however, is now a toggle switch ( P6 ) as the sixth switch ( P6 ) is used.

Figure 10

10 shows the proposed clocked amplifier circuit in the fifth variant with an exemplary circuit for measuring a shunt resistor ( RS ). It essentially corresponds to 6th . Instead of the fourth switch ( P4 ) and the fifth switch ( P6 ), however, is now a toggle switch ( P6 ) is used.

Figure 11

geladen. Die erste Kapazität (C1) wird auf die Kapazitätsspannung $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IN}\right)$$

aufgeladen. Die Ausgangsspannung des Differenzverstärkers (V) ist dann: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)$$

The 11 equals to 10 . The switch positions in the first phase (ϕ1) are now shown. The first switch ( P1 ) and the third switch ( P3 ) are now closed. The sixth switch ( P6 ) connects the second connection of the second capacitance ( C2 ) now with the reference potential ( VREFH ). The second capacity ( C2 ) is based on the capacitance voltage $$\text{V}\left(\text{C2}\right)=\text{V}\left(\text{OFFSET}\right)$$

loaded. The first capacity ( C1 ) is based on the capacitance voltage $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IN}\right)$$

charged. The output voltage of the differential amplifier ( V ) is then: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)$$

Figure 12

The 12th equals to 10 . The switch positions in the second phase (ϕ2) are now shown. The second switch ( P2 ) is now closed. The sixth switch ( P6 ) now connects the second connection of the second capacitance ( C2 ) with the output of the differential amplifier ( V ).

umgeladen.The first capacity ( C1 ) is now on the tension $$\text{V}\left(\text{C1}\right)=\text{V}\left(\text{VREFH}\right)-\text{V}\left(\text{OFFSET}\right)-\text{V}\left(\text{IP}\right)$$

reloaded.

Die Ausgangsspannung des Differenzverstärkers (V) beträgt dann: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1/C}2$$

Somit kann der Spannungsabfall über den Shunt-Widerstand (RS) nun jedoch offsetfrei mit einer sehr gut fertigungstechnisch einstellbaren Verstärkung C1/C2 erfasst werden.The voltage across the second capacitance is then: $$\text{V}\left(\text{C2}\right)=\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1 / <figure-callout id="2" label="C" filenames="DE102020130114A1\_0019.png,DE102020130114A1\_0020.png" state="{{state}}">C</figure-callout>}2+\text{V}\left(\text{OFFSET}\right)$$

The output voltage of the differential amplifier ( V ) is then: $$\text{V}\left(\text{OUT}\right)=\text{V}\left(\text{VREFH}\right)-\left(\text{V}\left(\text{IP}\right)-\text{V}\left(\text{IN}\right)\right)\ast \text{C1 / <figure-callout id="2" label="C" filenames="DE102020130114A1\_0019.png,DE102020130114A1\_0020.png" state="{{state}}">C</figure-callout>}2$$

Thus, the voltage drop across the shunt resistor ( RS ) but now offset-free with a gain that can be adjusted very well in terms of production technology C1 / C2 are recorded.

List of reference symbols

+

positive input of the differential amplifier (V);

-

negative input of the differential amplifier (V);

ADC

Analog-to-digital converter;

C1

first capacity;

C2

second capacity;

CK

parasitic coupling capacitance of a supply line;

CLK

Analog-to-digital converter clock;

DB

Data bus;

EDB

Single wire data bus;

IP

positive circuit input;

IN

negative circuit input;

ϕ1

first phase signal of the first phase or first phase;

ϕ2

second phase signal of the second phase or second phase;

P1

first switch;

P2

second switch;

P3

third switch;

P4

fourth switch;

P5

fifth switch;

P6

sixth switch, which is a changeover switch;

P7

seventh switch;

P8

eighth switch;

RN

second lead resistance;

RP

first lead resistance;

RS

Shunt resistance;

V

Differential amplifier;

VREFH

Reference potential (or reference potential line);

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• DE 102019131250 [0001]
• US 2018/0062595 A1 [0007]
• EP 2520942 A2 [0007]

Claims (4)

Measuring device for recording a digitized value for the bus current within the single-wire data bus line of a single-wire data bus (EDB), - with a first capacitance (C1), - the first capacitance (C1) having a first connection and a second connection, and - with a second capacitance (C2), - wherein the second capacitance (C2) has a first connection and a second connection, and - with a first switch (P1) and - with a second switch (P2) and - with a third switch (P3) and - with a sixth switch (P6), which is a changeover switch between the connection of a first connection of the sixth switch (P6) to a second connection of the sixth switch (P6) on the one hand and the connection of the first connection of the sixth switch (P6) to a third connection of the sixth switch (P6), and - with a differential amplifier (V), - wherein the differential amplifier (V) has a positive input (+) and a negative input (-) aufwe and - the differential amplifier (V) has an input offset voltage, which can also be 0V, and - with a reference potential (VREFH) and - with a positive circuit input (IP) and - with a negative circuit input (IN) and - with an analog -to-digital converter (ADC) and - with a first lead resistor (RP) and - with a second lead resistor (RN) and - with a coupling capacitance (CK) and - with a bus shunt resistor (RS) and - with a single-wire data bus (EDB), - wherein the analog-to-digital converter (ADC) is clocked with a clock rate of the analog-to-digital converter (ADC) and - wherein the bus shunt resistor has a first connection and a second connection and - wherein the single-wire data bus (EDB) is divided into a first part of the single-wire data bus (EDB) and a second part of the single-wire data bus (EDB) and - wherein the bus shunt resistor (RS) is inserted into the single-wire data bus (EDB), - that the first connection of the bus shun t-resistor (RS) is connected to the first part of the single-wire data bus (EDB) and - that the second connection of the bus shunt resistor (RS) is connected to the second part of the single-wire data bus (EDB), - so that the bus current of the single-wire data bus (EDB) causes a voltage drop across the bus shunt resistor (RS), and - the first connection of the bus shunt resistor (RS) being connected to the positive circuit input (IP) via a first lead resistor (RP) and - The second connection of the bus shunt resistor (RS) is connected to the negative circuit input (IN) via a second lead resistor (RN) and - the clocking of the clocked circuit has a first time phase (ϕ1) and a second time phase ( ϕ2), which follow one another during the duration of operation, and - wherein the negative input (-) of the differential amplifier (V) is connected to the first terminal of the first capacitance (C1) and - the two ite connection of the first capacitance (C1) is connected to the positive circuit input (IP) via the first switch (P1) and - the second connection of the first capacitance (C1) to the negative circuit input (IN) via the second switch (P2) and - wherein the first connection of the second capacitance (C2) is connected to the negative input (-) of the differential amplifier (V) and - wherein the second connection of the second capacitance (C2) is connected to the first connection of the sixth switch (P6) and - the second connection of the second capacitance (C2) can be connected to the output of the differential amplifier (V) via the second connection of the sixth switch (P6) and - the second connection of the second capacitance (C2) via the third Connection of the sixth switch (P6) can be connected to the reference potential (VREFH) and - wherein the third switch (P3) is connected between the negative input (-) of the differential amplifier (V) and the output of the differential amplifier (V) and - wherein the positive input (+) of the differential amplifier (V) is connected to the reference potential (VREFH) and - wherein the first switch (P1) and the third switch (P2) are closed in the first phase (ϕ1) and - wherein the first switch (P1) and the third switch (P2) are open in the second phase (ϕ2) and - where the second switch (P2) is closed in the second phase (ϕ2) and - where the second switch (P2) is open in the first phase (ϕ1) and - where the sixth switch (P6) is the second terminal of the connects the second capacitance (C2) to the reference potential (VREFH) in the first phase (ϕ1) and - the sixth switch (P6) connecting the second connection of the second capacitance (C2) to the output of the differential amplifier (V) in the second phase ( ϕ2) connects and - whereby in the second phase (ϕ2) the bet The output voltage at the output of the differential amplifier (V) based on the reference potential (VREFH) is the amount of the input voltage difference between the potential of the positive circuit input (IP) minus the potential of the negative circuit input (IN) multiplied by the ratio of the capacitance value of the first capacitance (C1 ) to the capacitance value of the second capacitance (C1) minus the input offset voltage of the differential amplifier (V) and - wherein the clocked circuit comprises an analog-to-digital converter (ADC) and - wherein the output of the differential amplifier (V) with the input of the Analog-to-digital converter (ADC) is connected and - wherein the reference potential (VREFH) of the amplifier is the reference potential of the clocked analog-to-digital converter (ADC) and - wherein the temporal phase position of the first phase and the phase position of the second phase at least at times in a fixed temporal phase relationship and / or at least at times in synchronism with the said takt t of a clocked analog-to-digital converter (ADC) and - where the analog-to-digital converter (ADC) converts the value of the output signal at the output of the differential amplifier (V) into a digital value for the bus current through the single-wire data bus ( EDB) converts and outputs and / saves and / or holds ready as a digitized value for the bus current within the single-wire data bus line of a single-wire data bus (EDB). Measuring device according to Claim 1 - wherein the first capacitance (C1) is formed by the parallel connection of a plurality of individual partial capacitances designed in the same way and the second capacitance (C2) is formed by a series connection of a plurality of such partial capacities. Measuring device according to one or more of the Claims 1 to 2 - wherein the first capacitance (C1) is an interconnection of at least two partial capacitances and - wherein the clocked circuit has a seventh switch (P7) and - wherein the gain of the circuit can be set by the first capacitance value of the first capacitance (C1) is modified by means of the seventh switch (P7) by bridging or disconnecting one or more partial capacitances of the first capacitance (C1). Measuring device according to one or more of the Claims 1 to 3 - the second capacitance (C2) is an interconnection of at least two partial capacitances and - the clocked circuit has an eighth switch (P8) and - the gain of the circuit can be set by the second capacitance value of the second capacitance (C2) is modified by means of the eighth switch (P8) by bridging or disconnecting one or more partial capacitances of the second capacitance (C2).

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