DE102020112821A1 - DUMMY GATE INTERSECTION PROCESS AND RESULTING GATE STRUCTURES - Google Patents

Abstract

One method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer that extends into the opening, and depositing a second dielectric layer on the first dielectric layer, wherein the second dielectric layer extends into the opening. A planarization process is then performed to form a gate isolation region having the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposite sides of the gate isolation region. The method further comprises performing a first etching process to remove sidewall sections of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

Description

PRIORITY CLAIM AND CROSS REFERENCE

This application claims priority from U.S. provisional patent application filed on October 29, 2019 with application number 62 / 927,559 entitled "Metal Gate Fill Process and Resulting Gate Structures," which is hereby incorporated by reference.

TECHNICAL BACKGROUND

Metal-oxide-semiconductor (MOS) devices are fundamental devices in integrated circuits. A MOS device typically has a gate electrode comprising polysilicon doped with p-type or n-type impurities through doping processes such as ion implantation or thermal diffusion. The work function of the gate electrode was adapted to the band edge of the silicon. In an N-metal oxide semiconductor (NMOS) device, the work function can be set close to the band edge of the silicon. For a PMOS device, the work function can be set close to the valence band of silicon. The adjustment of the work function of the polysilicon gate electrode can be achieved by the selection of suitable impurities.

MOS devices with polysilicon gate electrodes exhibit a carrier depletion effect, which is also referred to as the poly-depletion effect. The poly-depletion effect occurs when the applied electric fields displace charge carriers from gate regions close to gate dielectrics and form depletion layers. In an n-doped polysilicon layer, the depletion layer contains ionized immobile donor sites, and in a p-doped polysilicon layer the depletion layer contains ionized immobile acceptor sites. The depletion effect leads to an increase in the effective thickness of a gate dielectric, which makes it more difficult to produce an inversion layer on the surface of the semiconductor.

The poly-depletion problem can be solved by forming metal gate electrodes or metal-silicide gate electrodes, and the metal gates used in NMOS devices and PMOS devices can also have band edge work functions. Since the NMOS devices and PMOS devices have different work function requirements, dual gate CMOS devices are used.

When forming the metal gate electrodes, a long dummy gate is first formed, which is then etched so that sections of the long dummy gate are separated from one another. A dielectric material can then be filled into the opening left by the etched section of the long dummy gate. The dielectric material is then polished, leaving a portion of the dielectric material between the remaining portions of the dummy gate. The cut-off sections of the dummy gate are then replaced by metal gates.

Figure list

• 1-4, 5A, 5B, 6, 7A, 7B, 7C, 8A, 8B-1, 8B-2, 8C, 9A, 9B, 10, 11A, 11B, 12A, 12B und 12C veranschaulichen Querschnittsansichten, Draufsichten und perspektivische Ansichten von Zwischenstadien bei der Herstellung von Finnen-Feldeffekttransistoren (FinFETs) und Gateisolationsgebieten auf einer Dummy-Finne gemäß einigen Ausführungsformen.
• 13, 14A, 14B und 15-19 veranschaulichen Querschnittsansichten und perspektivische Ansichten von Zwischenstadien bei der Herstellung von Finnen-Feldeffekttransistoren (FinFETs) und einem Gateisolationsgebiet auf einem Flachgrabenisolationsgebiet gemäß einigen Ausführungsformen.
• 20 bis 23 veranschaulichen Querschnittsansichten bei der Bildung von Gate-All-Around-Transistoren (GAA-Transistoren) und Gateisolationsgebieten gemäß einigen Ausführungsformen.
• 24 und 25 veranschaulichen die Bildung von Gateisolationsgebieten mit mehreren Schichten gemäß einigen Ausführungsformen.
• 26 veranschaulicht einen Prozessablauf zur Herstellung von FinFETs und Gateisolationsgebieten gemäß einigen Ausführungsformen.

Aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features can be increased or decreased arbitrarily for the sake of clarity of explanation.

• 1-4 , 5A , 5B , 6th , 7A , 7B , 7C , 8A , 8B-1 , 8B-2 , 8C , 9A , 9B , 10 , 11A , 11B , 12A , 12B and 12C 10 illustrate cross-sectional, top, and perspective views of intermediate stages in the manufacture of fin field effect transistors (FinFETs) and gate isolation regions on a dummy fin in accordance with some embodiments.
• 13th , 14A , 14B and 15-19 10 illustrate cross-sectional and perspective views of intermediate stages in the manufacture of fin field effect transistors (FinFETs) and a gate isolation region on a shallow trench isolation region in accordance with some embodiments.
• 20th to 23 10 illustrate cross-sectional views in forming gate all around transistors (GAA transistors) and gate isolation regions in accordance with some embodiments.
• 24 and 25th illustrate the formation of gate isolation regions with multiple layers in accordance with some embodiments.
• 26th illustrates a process flow for fabricating FinFETs and gate isolation regions in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples of implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are of course only examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are between the first and second Feature can be formed so that the first and second features may not be in direct contact. In the present disclosure, reference numerals may also be repeated in the various examples. This repetition is for the purpose of simplicity and clarity and does not per se dictate a relationship between the various embodiments and / or configurations discussed herein.

In addition, for the sake of simplicity, spatially relative terms such as “below”, “below”, “below”, “above”, “above”, “above” and the like can be used here to describe the relationship of an element or feature to one or more Describe other elements or features as shown in the illustrations. The spatially relative terms are intended to include various orientations of the device in use or operation in addition to the orientation shown in the figures. The device can be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here can also be designed accordingly.

Gate isolation regions, fin field effect transistors (FinFETs) and a method for their production in accordance with various embodiments are provided. The intermediate steps in forming the gate isolation regions in accordance with some embodiments are illustrated. Some variations of some embodiments are discussed. The embodiments discussed herein are intended to provide examples to enable the manufacture or use of the subject matter of this disclosure, and one skilled in the relevant art will readily appreciate what modifications can be made within the contemplated scope of the various embodiments. Like (or similar) reference characters are used to refer to like elements throughout the several views and illustrative embodiments. Although embodiments of the method may be discussed herein in a particular order, other embodiments of the method may be practicable in any logical order.

According to some embodiments of the present disclosure, the production of gate isolation regions includes etching a dummy gate to form an opening, filling the opening with a first dielectric layer and a second layer, and performing a planarization process. The gate dummy is then removed. A first etch process is performed to remove the exposed sidewall portions of the first dielectric layer. A second etching process is then carried out in order to thin the second dielectric layer so that the resulting gate insulation region has a concave shape in plan view. Replacement gates are then formed on opposite sides of the gate isolation regions.

1-4 , 5A , 5B , 6th , 7A , 7B , 7C , 8A , 8B-1 , 8B-2 , 8C , 9A , 9B , 10 , 11A , 11B , 12A , 12B and 12C Figure 10 illustrates the cross-sectional views of the intermediate stages in the formation of FinFETs and gate isolation regions on a dummy fin. The corresponding processes are also shown schematically in the process flow 26th reproduced.

1 Figure 11 illustrates a perspective view of a first structure. The starting structure has a wafer 10 on who further a substrate 20th having. Substrate 20th may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed from other semiconductor materials. Substrate 20th can be doped with a p- or an n-type impurity. Isolation areas 22nd such as shallow trench isolation (STI) regions are formed so as to extend from a top surface of the substrate 20th into the substrate 20th extend. The associated process is called a process 202 in the process flow 200 in 26th shown. The sections of the substrate 20th between neighboring STI areas 22nd are called semiconductor strips 24 designated. According to some embodiments of the present disclosure, the semiconductor strips are 24 Parts of the original substrate 20th , and therefore the material is the semiconductor strip 24 the same as that of substrate 20th . In accordance with alternative embodiments of the present disclosure, the semiconductor strips are 24 Replacement strips made by etching the sections of the substrate 20th between the STI areas 22nd for forming recesses and performing an epitaxial process for regrowth of another semiconductor material in the recesses. Accordingly, the semiconductor strips become 24 formed from a semiconductor material that is different from the material of the substrate 20th is different. According to some embodiments, the semiconductor strips are 24 formed from Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs or the like.

The STI areas 22nd may contain a liner oxide (not shown), which may be a thermal oxide produced by the thermal oxidation of a surface layer of the substrate 20th is formed. The lining oxide can also be a deposited silicon oxide layer formed, for example, by atomic layer deposition (ALD), chemical vapor deposition with high density plasma (HDPCVD), chemical vapor deposition (CVD), or the like. The STI areas 22nd may also include a dielectric material over the liner oxide, which dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

2 illustrates the fabrication of the dummy dielectric strip 25th made by etching one of the semiconductor strips 24 to form a recess and then filling the recess with a dielectric material. The associated process is called a process 204 in the process flow 200 in 26th shown. The dielectric material can contain or be a high-k dielectric such as silicon nitride, for example. Also the material of the dielectric dummy strip 25th is selected so that there is a high etch selectivity in relation to the materials of the metal gates (such as tungsten and titanium nitride) and the materials of the STI regions 22nd (such as silicon oxide). According to some embodiments of the present disclosure, the material of the dummy strip comprises 25th a silicon-based material such as SiN, SiON, SiOCN, SiC, SiOC, SiO2, or the like. In accordance with alternative embodiments of this disclosure, the material of the dummy strip includes 25th a metal-based material (oxide or nitride) such as TaN, TaO, HfO, or the like. The bottom surface of the dummy dielectric strip 25th may be higher, level with, or lower than the lower surfaces of the STI areas 22nd be.

Regarding 3 become the STI areas 22nd deepened. The associated process is called a process 206 in the process flow 200 in 26th shown. The top portions of the semiconductor strips 24 and the dummy dielectric strip 25th stand higher than the upper surfaces 22A the remaining sections of the STI areas 22nd protruding semiconductor fins 24 ' dielectric dummy fins 25 ' to build. The etching can be carried out by means of a dry etching process, with HF ₃ and NH ₃ being used as etching gases. In accordance with alternative embodiments of the present disclosure, the deepening of the STI areas 22nd carried out by means of a wet etching process. The etching chemical can contain HF solution, for example. The height H1 the dummy dielectric fin 25 ' can be equal to, greater than or less than the height H2 of the foregoing Finns 24 ' be. In accordance with some embodiments of the present disclosure, the altitude is H1 the dummy dielectric fin 25th in a range between about 50 Å and about 1,500 Å. The width W1 the dummy dielectric fin 25th can range between about 5 Å and about 500 Å.

In the embodiments illustrated above, the fins can be structured using any suitable method. For example, the fins can be patterned by one or more photolithography processes, including double or multiple patterning processes. In general, in double or multiple structuring processes, photolithography and self-aligning methods are combined, whereby structures can be produced which, for example, have smaller pitches than those which can otherwise be achieved by a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and patterned by a photolithography process. In addition to the structured sacrificial layer, spacers are formed through a self-aligning process. The sacrificial layer is then removed and the remaining spacers or mandrels can then be used to structure the fins.

With further reference to 3 become dummy gate stacks 30th on the top surfaces and side walls of the (protruding) fins 24 ' and 25 ' educated. The associated process is called a process 208 in the process flow 200 in 26th shown. The dummy gate stacks 30th can use dummy gate dielectrics 32 and dummy gate electrodes 34 via dummy gate dielectrics 32 contain. Dummy gate electrodes 34 can be formed using polysilicon, for example, and other materials can also be used. Each of the dummy gate stacks 30th can also have one (or more) hard mask layer 36 over the dummy gate electrode 34 contain. The hard mask layers 36 can be formed from silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stacks 30th can have one or more protruding fins 24 ' and 25 ' and STI areas 22nd cross. Dummy gate stacks 30th also have longitudinal directions that are perpendicular to the longitudinal directions of the protruding fins 24 ' run away.

Next will be gate spacers 38 on the side walls of dummy gate stacks 30th educated. The associated process is also called a process 208 in the process flow 200 in 26th shown. According to some embodiments of the present disclosure, the Gate spacers 38 formed from a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride or the like, and may have a single-layer structure or a multilayer structure with a plurality of dielectric layers.

In accordance with some embodiments of the present disclosure, an etching step is performed to the portions of the protruding fins 24 ' to etch that doesn't go through the dummy gate stack 30th and the gate spacers 38 are covered, leading to the in 4th structure shown. The associated process is called a process 210 in the process flow 200 in 26th shown. The depression can be anisotropic, and so can the sections of the fins 24 ' that are directly below the dummy gate stacks 30th and the gate spacers 38 are therefore protected and are not etched. The top surfaces of the recessed semiconductor strips 24 may be lower than the top surfaces, according to some embodiments 22A of the STI areas 22nd be. The spaces created by the etched portions of the protruding fins 24 ' remain are called indentations 40 designated. During the etching process, the dielectric blind fin becomes 25 ' not etched. For example, protruding fins 24 ' be etched with SiCONi (NF ₃ and NH ₃ ), Certas (HF and NH ₃ ) or similar.

Next, epitaxial areas (source / drain areas) 42 by selective growth of a semiconductor material from depressions 40 formed, resulting in the structure in 5A results. The associated process is called a process 212 in the process flow 200 in 26th shown. According to some embodiments, the include epitaxial regions 42 Silicon-germanium, silicon, silicon-carbon or the like. Depending on whether the resulting FinFET is a p-FinFET or an n-FinFET, a p-type or an n-type impurity can be doped in-situ when the epitaxy is carried out. For example, if the resulting FinFET is a p-FinFET, silicon germanium boron (SiGeB), GeB, or the like can be grown. On the other hand, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown. According to alternative embodiments of the present disclosure, the epitaxial regions 42 formed from a III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof or multiple layers thereof. After the epitaxial areas 42 the depressions 40 have completely filled, the epitaxial areas begin 42 expand horizontally and facets can be formed.

5B illustrates the formation of enveloping source / drain regions 42 in accordance with alternative embodiments of the present disclosure. According to these embodiments, the protruding fins are 24 ' , as in 4th shown, not recessed, and the epitaxial areas 41 are on the protruding fins 24 ' grew up. The material of the epitaxial areas 41 can be the material of the epitaxial semiconductor material 42 , as in 5A shown, depending on whether the resulting FinFET is a p- or an n-FinFET. Accordingly, include source / drains 42 protruding fins 24 ' and the epitaxial area 41 . An implant may (or may not) be performed to implant an n-type impurity or a p-type impurity.

6th 10 shows a perspective view of the structure after contact etch stop layer (CESL) 46 and interlayer dielectric (ILD) 48 are formed. The associated process is called a process 214 in the process flow 200 in 26th shown. The CESL 46 may be formed from silicon nitride, silicon carbonitride, or the like. The CESL 46 can be formed by a conformal deposition process such as ALD or CVD. The ILD 48 may contain a dielectric material made, for example, by FCVD, spin-on coating, CVD, or some other deposition process. The ILD 48 can also be an oxygen-containing dielectric material or contain one based on silicon oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG) or the like. A planarization process such as chemical mechanical polishing (CMP) or mechanical grinding process is performed to the top surfaces of the ILD 48 , the dummy gate stack 30th and the gate spacer 38 to level with each other. In accordance with some embodiments of the present disclosure, the planarization process ends on the top surface of the hard mask 36 . According to alternative embodiments, the hard mask 36 is also removed during the planarization process, and the planarization process stops on the top surface of the dummy gate electrode 34 . Thus, in some of the drawings below, the hard mask 36 shown with a dashed line to indicate that it may or may not exist.

Regarding 7A becomes a dummy gate cutting process by etching dummy gate stacks 30th performed to openings 50 to build. The associated process is called a process 216 in the process flow 200 in 26th shown. The dummy gate stacks 30th are thus separated into separate sections. To carry out the dummy gate cutting process, an etching mask, which can contain a photoresist (not shown), can be formed and patterned. 7B shows one Cross-section from the reference cross-section 7B-7B as in 7A shown is received. The dummy gate cutting process becomes dummy gate stacks 30th etched in anisotropic processes until the dielectric dummy fin 25 ' is exposed. As a result, a portion of the dummy gate stack becomes 30th away. The long dummy gate stack 30th is thus in two separate sections 30A and 30B cut that are separated from each other. Each separate section of the dummy gate stack 30th can have one, two or more protruding fins 24 ' cross to form a FinFET with one or more fins. After etching the dummy gate stack 30th the etching mask is removed, for example, in an ashing process.

7C FIG. 11 shows a top view of a portion of the 7A structure shown. Any of the openings 50 is between the respective gate spacer sections 38A and 38B formed, the parallel opposite portions of the gate spacer 38 are. The gate spacer sections 38A and 38B have side walls that face the opening 50 are exposed. Dielectric dummy fin 25 ' lie through the openings 50 free.

Next up are the openings 50 with layers / areas 52-1 and 52-2 filled the gate isolation areas 52 form, as in 8A shown. The associated process is called a process 218 in the process flow 200 in 26th shown. The layers / areas 52-1 and 52-2 can be formed from dielectric materials and are therefore referred to below as dielectric layers / regions, while they can also be formed from non-dielectric materials. Dielectric layers 52-1 and 52-2 are formed from different dielectric materials or from the same materials with different properties, such as different density values. The dielectric layers 52-1 and 52-2 may be selected from the same group of dielectric materials, which may include, but are not limited to, oxide-based dielectric materials, nitride-based dielectric materials, oxynitride-based dielectric materials, oxycarbide-based dielectric materials, carbide-based dielectric materials, etc. For example, the dielectric layers 52-1 and 52-2 be formed from materials selected from SiN, SiON, SiOCN, SiC, SiOC, SiO2 or the like. The layers 52-1 and 52-2 can also be formed from non-dielectric materials such as SiGe. According to some embodiments, the dielectric layer is 52-1 formed of an oxide such as silicon oxide, and the dielectric layer 52-2 is formed from a nitride such as silicon nitride. According to alternative embodiments, the dielectric layers 52-1 and 52-2 formed from the same material as silicon oxide, but have different porosity values, and thus different density values. According to some embodiments, the dielectric layer is 52-1 denser (with a lower porosity) than the dielectric layer 52-2 . Also the dielectric layers 52-1 and 52-2 can be formed from the same material but under different process conditions. For example, the dielectric layer 52-1 and the dielectric layer 52-2 be formed under a high temperature and a lower temperature, respectively. For example, if the dielectric layer 52-1 and the dielectric layer 52-2 are formed from silicon oxide, the higher temperature can be in a range between about 400 ° C and about 600 ° C and the lower temperature in a range between about 200 ° C and about 400 ° C. In addition, the higher temperature can be greater than the lower temperature by a difference of more than about 50 ° C, and the difference can be in a range between about 50 ° C and about 300 ° C. When materials other than silicon oxide are used, the higher temperature range and the lower temperature range may be different from those of the silicon oxide. According to alternative embodiments, as in 24 shown, the gate insulation 52 have more than two layers, such as three, four, five, etc., up to ten layers. Regardless of whether they are formed from different materials or the same material, dielectric layers 52-1 and 52-2 be distinguishable from one another, for example by X-ray diffraction, transmission electron microscopy (TEM) or the like.

8B-1 and 8B-2 illustrate the processes for forming the gate isolation region 52 . According to some embodiments, as in 8B-1 shown is the dielectric layer 52-1 formed by a conformal deposition process, and therefore the thickness is T2 ( 8B-2 ) of their vertical sections close to the thickness T1 their horizontal sections (e.g. with a thickness difference of less than about 20 percent). According to some embodiments, the dielectric layer is 52-1 by means of atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), chemical low-pressure vapor deposition (LPCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) or other applicable deposition processes. Each of the lower layers (such as 52-1 or 52-2 when multiple layers are formed) may have a thickness according to some embodiments T1 / T2 in a range between about 3 Å and about 500 Å. The dielectric layer / dielectric area 52-2 fills the remaining space of the opening 50 ( 7A) that is not through the dielectric layer 52-1 is filled. The dielectric layers 52-1 and 52-2 have some portions that are higher than the top surfaces of the dummy gate stacks 30A and 30B .

Regarding 8B-2 A planarization process is performed to remove excess portions of the dielectric layers 52-1 and 52-2 remove so that the gate isolation area 52 remains. The sections of the dielectric layers 52-1 and 52-2 that are higher than the top surfaces of the dummy gate stacks 30A and 30B are removed. As a result, the dummy gate stacks become 30A and 30B exposed as in 8C shown. At the same time, the ILD 48 ( 8A) may be exposed in accordance with some embodiments. The remaining portions of the dielectric layers 52-1 and 52-2 are hereinafter collectively referred to as gate isolation regions 52 denotes, to which the remaining portions of the dielectric layers 52-1 and 52-2 belong.

As in 8C shown, separate the gate isolation regions 52 the respective dummy gate stacks 30A and 30B from each other. The gate isolation areas 52 and the dummy gate stacks 30A and 30B in combination form elongated strips in a plan view, and each of the elongated strips lies between the opposing portions 38A and 38B of the gate spacer 38 .

The dummy gate stacks 30A and 30B are then removed by etching, and the resulting structure is in 9A and 9B shown. The associated process is called a process 220 in the process flow 200 in 26th shown. In accordance with some embodiments, the dummy gate dielectric becomes 32 away. According to alternative embodiments, the dummy gate dielectric is used 32 not removed during this process and will be used after removing the dummy gate electrodes 34 exposed. Accordingly, in 9B and 10 the dummy gate dielectric 32 shown in dashed lines to indicate that it may or may not be present in the respective structure. In these embodiments, the dummy gate dielectric 32 be removed when the dielectric layer 52-2 in the process of 11A and 11B is etched, or it can be after the process of 11A and 11B and removed before replacement gates are formed. The openings 54A and 54B are formed in the space formed by the removed dummy gate electrodes 34 (and possibly dummy gate dielectrics 32 ) remains. As in 9A shown is each of the openings 54A and 54B through the gate isolation region 52 and the gate spacers 38 defined, and the openings 54A and 54B are through the gate isolation area 52 further separated from each other. 9B Figure 13 shows a cross-sectional view resulting from the reference cross-section 9B-9B in 9A was obtained. According to some embodiments of the present disclosure, as shown in FIG 9B shown is the gate isolation region 52 wider than the underlying dielectric dummy fin 25 ' . According to alternative embodiments, the gate isolation region can 52 the same width as the dummy dielectric fin 25 ' or narrower than the dummy dielectric fin 25 ' be.

Regarding 10 becomes a first etching process 56 performed to the outer sidewall portions of the dielectric layer 52-1 remove, leaving the sidewalls of the dielectric layer 52-2 are exposed. The associated process is called a process 222 in the process flow 200 in 26th shown. The etching process is isotropic and can be carried out using dry etching or wet etching. The etchant becomes the materials of the dielectric layers 52-1 and 52-2 selected accordingly, so that there is a high etching selectivity ER52-1 / ER52-2, which is, for example, higher than approximately 4, the etching selectivity ER52-1 / ER52-2 being the etching rate of the dielectric layer 52-1 the etching rate of the dielectric layer 52-2 is. As a result, the dielectric layer becomes 52-2 in the first etching process 56 not etched.

Regarding 11A and 11B becomes a second etching process 58 on the thin dielectric layer 52-2 performed so that the profile of the dielectric layer 52-2 is modified. The associated process is called a process 224 in the process flow 200 in 26th shown. The etching process is isotropic and can be carried out using dry etching or wet etching. The etchant becomes the materials of the dielectric layers 52-1 and 52-2 selected accordingly, so that a relatively high etching selectivity ER52-2 / ER52-1 (the etching rate of the dielectric layer 52-2 the etching rate of the dielectric layer 52-1 ) is present. As a result, the dielectric layer becomes 52-2 at a higher rate than the first etching process 56 etched. On the other hand, the etching selectivity ER52-2 / ER52-1 cannot be kept too high, so that the corners of the dielectric layer 52-1 in the second etching process 58 can still be rounded off. According to some embodiments, the etch selectivity ER52-2 / ER52-1 is in a range between about 2 and about 20. According to some embodiments of the present disclosure, the dummy gate dielectric may be 32 ( 10 ), if not in the in 9A and 9B shown process already removed in the second etching process 58 removed.

According to some embodiments, when performing one of the etching processes 56 and 58 depending on the materials of the dielectric layers 52-1 and 52-2 the etching gas can be selected from the group consisting of C12, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, HF, NH3, NF3 and combinations thereof. In addition, gases such as N2, O2, CO2, SO2, CO, SiCl4 or combinations thereof can be added to improve the etch selectivity. Inert gases such as Ar, He, Ne, etc. can be added as dilute gases (carrier gas). For example, in one embodiment, the dielectric layer 52-1 made of SiN and the dielectric layer 52-2 formed of SiO2, a fluorine-containing gas such as a mixture of CF ₄ , O ₂ and N2, a mixture of NF3 and O2, SF6 or a mixture of SF6 and O2, or the like for etching the dielectric layer 52-1 may be used while the mixture of NF3 and NH ₃ , the mixture of HF and NH ₃ or the like for thinning the dielectric layer 52-2 can be used. During the first etching process 56 and the second etching process 58 the power of the plasma source can be in a range between about 10 watts and about 3,000 watts, the power of the plasma bias voltage can be less than about 3,000 watts. The pressure of the etching gas can be in a range between approximately 1 mTorr and approximately 800 mTorr. The flow rate of the etching gas can be in a range between approximately 1 sccm and approximately 5000 sccm.

When a wet etching in the first etching process 56 and the second etching process 58 is carried out, the respective etching solution for etching the corresponding dielectric layers 52-1 and 52-2 HF solution (with fluorine dissolved in it ( F2 )), H2SO4, HCl, HBr, NH3 or the like or combinations thereof, furthermore depending on the materials of the dielectric layers 52-1 and 52-2 . The solvent can include deionized water, alcohol, acetone, or the like.

According to alternative embodiments, instead of carrying out two etching processes using different etching chemicals, one and the same etching process can be carried out around both the dielectric layer 52-1 as well as the dielectric layer 52-2 to etch. The etchant is chosen so that the first dielectric layer 52-1 has a lower etching rate than the dielectric layer 52-2 . In the initial phase, the sidewall portions of the dielectric layer 52-1 etched while the dielectric layer 52-2 through the sidewall portions of the dielectric layer 52-1 is protected. After the sidewall portions of the dielectric layer 52-1 removed are the sidewalls of the dielectric layer 52-2 exposed, and the two dielectric layers 52-1 and 52-2 are etched. As the dielectric layer 52-2 a higher etching rate than the dielectric layer 52-1 it becomes laterally faster than the dielectric layer 52-1 deepened, creating the profile as in 11B shown is formed. It is conceivable that, according to these embodiments, the etching selectivity ER52-1 / ER52-2 (the etching rate of the dielectric layer 52-1 to the etching rate of the dielectric layer 52-2 ) is less than 1.0 and is chosen so that it lies in a certain range that is neither too high nor too low. If the etch selectivity ER52-1 / ER52-2 is too high, the sidewalls are the gate isolation region 52 convex (opposite to what is in 11B shown) and not concave. If the etching selectivity ER52-1 / ER52-2 is too low, there is a risk that the dielectric layer 52-2 is etched through or even completely removed. According to some embodiments, the etch selectivity ER52-1 / ER52-2 is in a range between about 0.05 and about 1.

Dielectric layers 52-1 and 52-2 can also be formed from the same material with different properties. For example, the two dielectric layers 52-1 and 52-2 be formed from silicon oxide, the dielectric layer 52-2 more porous than the dielectric layer 52-1 is. Thus, instead of two etching processes with different etching chemicals, one and the same etching process can be carried out around both the dielectric layer 52-1 as well as the dielectric layer 52-2 to etch. At the beginning of the etching process, the side wall sections of the dielectric layer are made 52-1 etched while the dielectric layer 52-2 through the sidewall portions of the dielectric layer 52-1 is protected. After the sidewall portions of the dielectric layer 52-1 have been removed, the sidewalls of the dielectric layer lie 52-2 free, and the two dielectric layers 52-1 and 52-2 are etched. As the dielectric layer 52-2 a lower density than the dielectric layer 52-1 has, has the dielectric layer 52-2 a higher etching rate than the dielectric layer 52-1 on. Consequently, the resulting gate isolation region 52 also the profile as in 11A and 11B shown.

By etching the dielectric layers 52-1 and 52-2 As mentioned above, the profiles shown in 11-A and 11B are shown. As in 11A shown are the bottom width of the dielectric layer 52-2 , the bottom width of the dielectric layer 52-1 and the top width of the dummy dielectric fin 25 ' labeled LD1, LD2 and LD3. According to some embodiments, the lower width LD1 is smaller than the lower width LD2. The lower width LD2 can be equal to or smaller than the upper width LD3. The lower portions of the sidewalls of the gate isolation region 52 can have a concave shape. Furthermore, the lower portions of the side walls are the gate isolation region 52 curved and flat. This flat and concave profile facilitates the later formation of replacement gates, since there is no There is an undercut that is difficult to fill. For example, dashed lines illustrate 60 the curved bottom of a gate isolation region formed by a conventional method in which the gate isolation region is formed from a homogeneous material. The dashed lines 60 illustrate that sharp undercuts are formed directly under the edge sections of the gate insulation area, which can only be filled with a replacement gate with great difficulty.

11B Figure 13 shows a top view of the structure of Figure 1 11A . The gate isolation areas 52 have concave side walls in accordance with the etching process illustrated above. For example, the middle section can be the gate isolation region 52 be the narrowest, while the edge portion of the gate isolation region 52 holding the gate spacers 38 contacted, is broadest. In 11B the width (lateral dimension) LD4 is larger than the width LD5, and the width LD5 is larger than the width LD6. In some embodiments, the width difference (LD4 - LD5) can be greater than about 5 Å and the ratio (LD4 - LD5) / LD4 can be greater than about 0.05 and range between about 0.05 and about 1. Likewise, the width difference (LD5-LD6) can be greater than about 5 Å and the ratio (LD5-LD6) / LD5 can be greater than about 0.05 and range between about 0.05 and about 1.

Furthermore, the angle θ made between the sidewalls is the gate isolation region 52 and the side walls of the corresponding parts of the goal spacers 38 is equal to or greater than 90 degrees and can be in a range between 90 degrees and about 160 degrees. This right or obtuse angle also makes it easier to fill with replacement gates in the subsequent processes.

12A , 12B and 12C Figure 12 shows a perspective view, a cross-sectional view, and a top view in forming the replacement gate stacks 66A and 66B . The associated process is called a process 226 in the process flow 200 in 26th shown. This is how the FinFETs 68A and 68B formed with the gate stack 66A and 66B the replacement gate stacks of the FinFETs 68A and 68B are. The replacement gates 66A and 66B share the common gate spacers 38A and 38B . In addition, the two replacement gates border 66A and 66B to the gate isolation region 52 .

The replacement gate stacks 66A and 66B exhibit gate dielectrics 62 and gate electrodes 64 on. Gate dielectrics 62 may contain a high-k dielectric such as hafnium oxide, zirconium oxide, lanthanum oxide or the like and may also contain a silicon oxide layer as an interface layer between the high-k dielectric and protruding fins 24 ' contain. According to some embodiments of the present disclosure, the gate electrodes 64 formed from a metal, a metal alloy, a metal silicide, a metal nitride or the like and may have a composite structure with a plurality of layers of TiN, TiAl, Co, Al and / or the like. The particular metals and structure are selected so that the resulting replacement gate electrodes 64 have suitable work functions. If the resulting FinFET is an n-FinFET, the work function is the gate electrode 60 for example, lower than 4.5 eV, and if the resulting FinFET is a p-FinFET, the work function is the gate electrode 60 for example higher than 4.5 eV.

12B Figure 13 shows a cross-sectional view resulting from the reference cross-section 12B-12B in 12A is preserved. As in 12B shown are the gate dielectrics 62 in contact with the two dielectric layers 52-1 and 52-2 of the gate isolation area 52 . 12C Figure 13 shows a top view of the structure of Figure 1 12A . 12C illustrates the angle θ and the associated complementary angle α. The angle α can be equal to or greater than 90 degrees and can be in a range between 90 degrees and approximately 160 degrees. As the sections of the spare gate stacks 66 that with the gate isolation area 52 come in contact, have convex shapes, it is easy to stack the replacement gate 66 to fill in without leaving voids.

13th , 14A , 14B and 15-19 10 illustrate cross-sectional and perspective views of the intermediate stages in the formation of FinFETs and a gate isolation region in accordance with some embodiments. These embodiments are similar to the embodiments disclosed above, except that the gate isolation region 52 in the STI field 22nd instead of the dummy dielectric fin 25 ' lands. Unless otherwise stated, the materials and the manufacturing processes of the components in these embodiments (and the in 20-25 embodiments shown) are essentially the same as the similar components, which are denoted by the same reference numerals in the respective drawings of the embodiments explained above. The details regarding the creation process and the materials of the in 13th , 14A , 14B and 15-19 Components shown can therefore be found in the explanation of the above embodiments.

13th shows a first semiconductor strip 24 and a second semiconductor strip 24 , with a continuous STI area 22nd from the first semiconductor strip 24 up to the second semiconductor strip 24 extends. Next up are the processes 3-6 and 7A carried out. The Process off 2 is skipped and thus a dummy dielectric fin is not formed.

14A Fig. 10 shows a structure after a CESL is made 46 and an ILD 48 . There will also be openings 50 formed to dummy gate stack 30th into shorter sections 30A and 30B to cut. 14B shows a cross-section that is derived from the reference cross-section 14B-14B in 14A is preserved. The opening 50 extends to the STI area 22nd so that the dummy gate stack 30A physically and electrically from the dummy gate stacks 30B is separated. The shapes of the structure in the top view of the 14A and 14B are essentially the same as the one in 7C , with the exception that no dielectric dummy fins 25 ' are formed and the STI area 22nd to the openings 50 are exposed.

Next, as in 15th shown is the gate isolation region 52 in the opening 50 educated. The details and materials of manufacture are with reference to the explanation of the 8B-1 and 8B-2 to find. Next up are the dummy gate stacks 30A and 30B removed to either a dummy gate dielectric 32 or protruding fins 24 ' to expose, depending on whether the dummy gate dielectric 32 removed or not at that time. The resulting structure is in 16 shown.

17th illustrates the first etching process 56 , in which the sidewall portions of the dielectric layer 52-1 removed and the sidewalls of the dielectric layer 52-2 to the openings 54A and 54B be exposed. 18th illustrates the second etching process 58 so that in 18th Profile shown is formed. The values of the widths LD1, LD2 and LD3 and the relationship (such as the (mathematical) relationships) between the widths LD1, LD2 and LD3 may be similar to those described above with reference to FIG 11A explained and will not be repeated. The shape of the gate isolation area 52 in plan view may be substantially the same as in FIG 11B shown. 19th illustrates the manufacture of the replacement gate stacks 66A and 66B . This is how the FinFETs 68A and 68B educated.

The methods for producing gate isolation regions can also be applied to the production of transistor types other than FinFETs. The processes can be used, for example, when cutting dummy gates for planar transistors, gate-all-around transistors (GAA transistors) or the like. 20th to 23 illustrate the exemplary implementations in which gate isolation regions for GAA transistors are formed.

Regarding 20th will be two stacked layers 114 and 114 ' educated. Each of the stacked layers 114 and 114 ' has channel layers 110 and victim films 112 on. The total number of channel layers 110 and the total number of victim films 112 can range between 1 and about 10. The material of the channel layers 110 and the victim films 112 are different. According to some embodiments, the channel layers include 110 Si, SiGe or the like or are formed from such. The sacrificial layers 112 may contain or be formed from SiGe, SiP, SiOCN, SiC or the like. The stacked layers 114 and 114 ' overlap the respective semiconductor strips 24 . The dummy gate stacks 30th who have favourited the dummy gate dielectric 32 who have favourited dummy gate electrodes 34 and the hard masks 36 have to be stacked on top of the layers 114 and 114 ' educated. The opening 50 is made by etching dummy gate stacks 30th educated.

According to some embodiments, the shape of the structure in perspective view and in plan view are as in FIG 20th shown essentially the same as in 14A and 7C except that no dielectric dummy fins 25 ' are formed and the protruding fins 24 ' through stacked layers 114 and 114 ' are replaced. The manufacturing processes can be considered with reference to the previous embodiments.

Regarding 21 becomes the gate isolation area 52 educated. Then the dummy gate stacks 30A and 30B removed, making the trenches 54A and 54B be formed as in 22nd shown. Subsequent processes will be the first etching process 56 ( 17th ) and the second etching process 58 ( 18th ) performed to the profile of the gate isolation area 52 to modify. The shape of the structure in plan view as in 22nd shown is similar to in 11B except that the protruding fins 24 ' out 11B through stacked layers 114 are replaced.

In subsequent processes, victim films become 112 removed, followed by the formation of replacement gates 66A and 66B who have favourited Gate Dielectrics 62 which are the channel layers 110 surrounded, and gate electrodes 64 have, which are the remaining spaces between the channel layers 110 to complete. This is how the GAA transistors become 68A ' and 68B ' educated.

According to some embodiments of the present disclosure, the gate isolation region comprises 52 two layers, such as the layers 52-1 and 52-2 . According to alternative embodiments, the gate isolation region can 52 further layers, for example three, four, five and up to ten layers. For example illustrates 24 a top view of gate isolation regions 52 , the layer 52-1 , Shift 52-n and the layers 52-2 to 52- (n-1) (not shown), where n is an integer of at least 2 and up to 10. The manufacturing process includes the deposition of the layers 52-1 to 52- (n-1) using conformal deposition processes, the materials of the layers 52-1 to 52-n are different from one another, the deposition of the dielectric layer 52-n and performing a planarization process. 25th Figure 3 shows a top view of the transistors 68A and 68B after the gate isolation areas 52 are formed. The profile is similar to the one referring to 11B is explained, wherein the outer layers of the gate isolation region 52 are increasingly wider than the respective inner layers.

The embodiments of the present disclosure have several advantageous features. The profiles of the corner regions of the gate insulation regions are formed by the formation of multi-layer gate insulation regions and the etching of the several layers, with no undercuts and sharp corners being formed. The manufacture of replacement gates is therefore easier and the formation of voids is less likely.

According to some embodiments of the present disclosure, a method includes forming a dummy gate stack; etching the dummy gate stack to form an opening; depositing a first dielectric layer extending into the opening; depositing a second dielectric layer on the first dielectric layer extending into the opening; performing a planarization process to form a gate isolation region having the first dielectric layer and the second dielectric layer; removing portions of the dummy gate stack on opposite sides of the gate isolation region to form trenches; performing a first etch process to remove sidewall portions of the first dielectric layer; performing a second etch process to thin the second dielectric layer; and forming replacement gates in the trenches. In one embodiment, the first dielectric layer has a higher etching rate in the first etching process than the second dielectric layer, and the first dielectric layer has a lower etching rate in the second etching process than the second dielectric layer. In one embodiment, the first etching process and the second etching process have the effect that the gate insulation region has concave side walls that face the trenches. In one embodiment, the method further includes forming a dummy dielectric fin protruding from the isolation regions located on opposite sides of the dummy dielectric fin, and the gate isolation region has a bottom surface that is in contact with the dummy dielectric fin . In one embodiment, the method further comprises forming a shallow trench isolation region that extends into a semiconductor substrate, wherein the gate isolation region has a bottom surface that contacts the shallow trench isolation region. In one embodiment, the dummy gate stack extends onto two adjacent semiconductor fins. In one embodiment, the dummy gate stack extends over two adjacent stacks of stacked layers, and each stack of the stacked layers includes alternating channel layers and sacrificial films, and the method further includes removing the sacrificial films.

According to some embodiments of the present disclosure, a structure includes a first semiconductor region and a second semiconductor region; a first gate stack and a second gate stack on the first semiconductor region and the second semiconductor region; a dielectric region between the first semiconductor region and the second semiconductor region; and a gate isolation region between the first gate stack and the second gate stack, wherein a lower surface of the gate isolation region contacts the dielectric region, and wherein the gate isolation region has concave sidewalls in contact with the first gate stack and the second gate stack in a plan view. In one embodiment, the structure furthermore has a first gate spacer and a second gate spacer, which are arranged on opposite sides of the gate isolation region and contact the latter. In one embodiment, the first gate spacer and the second gate spacer contact the first gate stack and the second gate stack. In one embodiment, the gate isolation region has a lower portion that contacts the dielectric region, the upper portions of the lower part being narrower than the respective lower portions of the lower part. In one embodiment, the gate insulation region has a first dielectric layer and a second dielectric layer. The first dielectric layer has a lower portion and two sidewall portions overlying the lower portion and connected to opposite ends of the lower portion. The second dielectric layer lies between the two side wall sections. In one embodiment, the first dielectric layer and the second dielectric layer are formed from different materials. In one embodiment, the first dielectric layer and the second dielectric layer are formed from the same material, and the first dielectric layer and the second dielectric layer have different porosity values.

According to some embodiments of the present disclosure, a structure includes a first gate stack and a second gate stack. The first gate stack has a first gate dielectric and a first gate electrode that overlaps a first lower portion of the first gate dielectric. The second gate stack has a second gate dielectric; and a second gate electrode overlapping a second lower portion of the second gate dielectric. The structure further includes a first gate spacer; and a gate isolation region between the first gate stack and the second gate stack, the gate isolation region having a first dielectric layer having a lower portion and two sidewall portions over and connected to opposite ends of the lower portion, the first dielectric layer being a first Forms an interface with the first gate stack and a second interface with the first gate spacer, and the first interface and the second interface form an acute angle; and a second dielectric layer between the two sidewall portions. In one embodiment, the structure further comprises a second gate spacer, wherein both the first gate spacer and the second gate spacer contact the gate isolation region. In one embodiment, the first dielectric layer and the second dielectric layer are formed from different materials. In one embodiment, the first dielectric layer and the second dielectric layer are formed from the same material and have different density values. In one embodiment, both the first dielectric layer and the second dielectric layer contact both the first gate stack and the second gate stack. In one embodiment, the structure furthermore has a dielectric region which lies beneath the gate insulation region and makes contact therewith, wherein the dielectric region forms a first interface with the gate insulation region and the lower section of the first dielectric layer forms a second interface with the second dielectric layer and the second interface is shorter than the first interface.

The foregoing outlines the features of various embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure can readily be used as a basis for designing or changing other processes and structures in order to achieve the same purposes and / or achieve the same advantages of the embodiments presented here. It should also be recognized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 62/927559 [0001]

Claims (20)

Procedure comprising: Forming a dummy gate stack; Etching the dummy gate stack to form an opening; Depositing a first dielectric layer extending into the opening; Depositing a second dielectric layer on the first dielectric layer, the second dielectric layer extending into the opening; Performing a planarization process to form a gate isolation region with the first dielectric layer and the second dielectric layer; Removing portions of the dummy gate stack on opposite sides of the gate isolation region to form trenches; Performing a first etching process to remove sidewall portions of the first dielectric layer; Performing a second etching process for thinning the second dielectric layer; and Forming replacement gates in the trenches. Procedure according to Claim 1 wherein in the first etching process the first dielectric layer has a higher etching rate than the second dielectric layer, and in the second etching process the first dielectric layer has a lower etching rate than the second dielectric layer. Procedure according to Claim 1 wherein the first etching process and the second etching process result in the gate isolation region having concave side walls which face the trenches. Procedure according to Claim 1 Further comprising: forming a dummy dielectric fin protruding from isolation regions located on opposite sides of the dummy dielectric fin, and the gate isolation region having a bottom surface that contacts the dummy dielectric fin. Procedure according to Claim 1 Further comprising: forming a shallow trench isolation region that extends into a semiconductor substrate, wherein the gate isolation region has a bottom surface that contacts the shallow trench isolation region. Procedure according to Claim 1 , wherein the dummy gate stack extends onto two adjacent semiconductor fins. Procedure according to Claim 1 wherein the dummy gate stack extends to two adjacent stacks of stacked layers, and each stack of the stacked layers comprises alternating channel layers and sacrificial films, and the method further comprising: removing the sacrificial films. Having structure: a first semiconductor region and a second semiconductor region; a first gate stack on the first semiconductor region and a second gate stack on the second semiconductor region; a dielectric region between the first semiconductor region and the second semiconductor region; and a gate insulation region between the first gate stack and the second gate stack, wherein a bottom surface of the gate insulation region contacts the dielectric region, the gate insulation region having concave sidewalls in contact with the first gate stack and the second gate stack in a plan view. Structure according to Claim 8 , further comprising: a first gate spacer and a second gate spacer on opposite sides of the gate isolation region and in contact with the gate isolation region. Structure according to Claim 9 wherein each of the first gate spacer and the second gate spacer further contacts the first gate stack and the second gate stack. Structure according to Claim 8 wherein the gate isolation region has a lower portion that is in contact with the dielectric region, and wherein the upper portions of the lower portion are narrower than the respective lower portions of the lower portion. Structure of Claim 11 wherein the gate isolation region comprises: a first dielectric layer comprising: a lower portion; and - two side wall sections over, and in connection with, the opposite ends of the lower section; and a second dielectric layer between the two sidewall sections. Structure according to Claim 12 wherein the first dielectric layer and the second dielectric layer are formed from different materials. Structure according to Claim 12 wherein the first dielectric layer and the second dielectric layer are formed from the same material and the second dielectric layer is more porous than the first dielectric layer. Having structure: a first gate stack comprising: a first gate dielectric; and a first gate electrode overlapping a first lower portion of the first gate dielectric; a second gate stack comprising: a second gate dielectric; and a second gate electrode overlapping a second lower portion of the second gate dielectric; a first gate spacer; and a gate isolation region between the first gate stack and the second gate stack, the gate isolation region comprising: a first dielectric layer having a lower portion and two sidewall portions over and in connection with opposite ends of the lower portion, the first dielectric layer forms a first interface with the first gate stack and a second interface with the first gate spacer, and the first interface and the second interface form an acute angle; and a second dielectric layer between the two side wall sections. Structure according to Claim 15 , further comprising: a second gate spacer, wherein both the first gate spacer and the second gate spacer contact the gate isolation region. Structure according to Claim 15 wherein the first dielectric layer and the second dielectric layer are formed from different materials. Structure according to Claim 15 wherein the first dielectric layer and the second dielectric layer are formed from the same material and have different density values. Structure according to Claim 15 wherein both the first dielectric layer and the second dielectric layer are in contact with both the first gate stack and the second gate stack. Structure according to Claim 15 , further comprising a third dielectric layer between the first dielectric layer and the second dielectric layer.

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