DE102020109307A1 - Modified JTAG interface with password protected memory access - Google Patents

Abstract

The invention relates to a JTAG test interface for testing integrated circuits and / or for testing microsystems. The JTAG test interface and / or the integrated circuit and / or the microsystem have a protected memory area (MEM). The JTAG test interface has a memory access logic (MAL) as a data register (DR) of the JTAG test interface, which controls the access to the protected memory. The JTAG test interface comprises a customer password register (CPWR) and a password register (PWR). The customer password register (CPWR) contains a customer password. The password register (PWR) can be written with a password using the JTAG test interface. Access to the protected memory area (MEM) via the memory access logic (MAL) is only possible if the customer password in the customer password register (CPWR) matches the password in the password register (PWR) in a predetermined manner.

Description

Generic term

The invention is directed to a JTAG test interface with a password-protected memory access, with protected information being protected via a multi-level password process so that different suppliers in a supply chain can protect their respective software know-how in different value-added stages of a supply chain. The invention also encompasses the protection of analog information.

General introduction

When using integrated circuits with programmable finite machines, programmable logics (FPGAs) and programmable computer systems, in particular with non-volatile memories, those who use these systems need to protect their programming against unauthorized access by third parties. From the user's point of view, this also includes the manufacturers of these semiconductor circuits. On the other hand, modern quality management methods require firstly full testability of integrated circuits and secondly that these circuits can be fully analyzed. Testability is generally referred to as the proportion of nodes that can be stimulated in a controlled manner multiplied by the proportion of observable nodes, the only requirement being that an incorrect value at a node leads to an observable deviation at the connections of the integrated circuit. In the simplest case, it is sufficient if, in the event of a faulty node value, a connection of the integrated circuit shows a faulty value at any point in time of the production test. In contrast, the analysability has stricter conditions. Analyzability is generally the proportion of nodes that can be stimulated in a controlled manner multiplied by the proportion of observable nodes multiplied by the proportion of localizable errors. For a continuous improvement of the production quality, as it is required by all current quality management methods today, it is necessary in the event of a failure of a produced part, regardless of whether it happened in our own production or after delivery, to determine the exact defect of the component and the causes for determine this discrepancy and safely interrupt this new chain of causes for the future. For this purpose, it must be possible to precisely localize the deviation within the integrated circuit.

This means that the very data that the semiconductor manufacturer's customer would like to keep secret can be accessed through such analyzability.

The proposal presented here seeks a technical solution for this.

State of the art

The JTAG protocol is known from the prior art. The JTAG protocol has become one of the leading tools for programming, testing, debugging, and emulating integrated circuits. In a process known as boundary scan, a host processor can check the status of an integrated circuit over the JTAG bus. In particular, the host processor as a bus master is able to program the integrated circuit appropriately and, if necessary, initialize it via a special interface, the JTAG interface according to the IEEE 1149 standard. Furthermore, the host processor is able to read out the state of the integrated circuit after a predetermined number of system clock periods of the JTAG interface according to the IEEE 1149 standard or upon detection of a predetermined event or to change it during the operation of the integrated circuit. This also includes stopping the integrated circuit or the forced change to other states or changing memory contents. The JTAG protocol is a point-to-point connection. The prior art also includes a chaining of JTAG test interfaces with the property right EP 503 117 B1 known for a long time. the EP 503 117 B1 but does not disclose how access to protected areas of the logic can be prevented.

1. 1. mindestens einen seriellen Dateneingang (Testdateneingang) TDI,
2. 2. mindestens einen seriellen Datenausgang (Testausgang) TDO,
3. 3. mindestens einen Mode-Eingang (Testmode-Eingang) TMS,
4. 4. mindestens einen Takteingang (Testtakteingang) TCK,
5. 5. einen optionalen Rücksetzeingang (Testrücksetzeingang) TRST.

A standard JTAG interface has a test data port with typically four test connections:

1. 1. at least one serial data input (test data input) TDI ,
2. 2. at least one serial data output (test output) TDO ,
3. 3. at least one mode input (test mode input) TMS ,
4. 4. at least one clock input (test clock input) TCK ,
5. 5. an optional reset input (test reset input) TRST .

Since the process has been known for several decades, reference is made at this point to the corresponding specialist literature and to the corresponding patent and published documents (IEEE 1149 standards).

Let me just briefly describe it so much: The JTAG protocol according to the IEEE 1149 standard comprises five signal groups in the basic standard, which are between the emulation unit, which contains the host processor and thus functions as a bus master, and the integrated circuit as a slave. The TCK signal represents the system clock ( TCK ) and synchronizes the internal state machine of the test controller ( TAPC ) the JTAG test interface according to the IEEE 1149 standard of the integrated circuit. The TMS signal controls the state of this test controller ( TAPC ) the JTAG interface of the bus node. Depending on the state of the test controller ( TAPC ) the JTAG test interface of the bus node performs different operations. The TDI input represents a serial data input. The TDO output represents a serial data output. The two inputs TMS and TDI are typically but not necessarily sampled with the rising TCK edge. The data output ( TDO ) its date typically also changes with the falling edge of the TCK signal. The individual TCK, TMS and TDI signals form the test data input signals in the prior art. In the context of this disclosure, they form the data input signals. The TDO signal represents the output signal. With the rising system clock edge (TCK edge) and with a suitable setting of a test controller ( TAPC ) internal instruction register ( IR ) the data is sent serially via the serial data input ( TDI ) shifted into different shift register chains, so-called scan paths, into the integrated circuit. At the same time, the original content of the relevant scan chain is displayed on the serial data output ( TDO ) issued. State vectors of finite automata within the integrated circuit can be part of the scan chain. It is therefore easy to change the contents and states or to control these contents and states of the memory cells of the scan chains via this interface in the prior art, which causes the problem. Reference is made here again to the specialist literature.

Figure 1 (state of the art)

1 shows the standardized state diagram for a JTAG test controller ( TAPC ) according to the state of the art and the relevant standards. After resetting the system, the test controller is located ( TAPC ) in the "reset test logic" state ( TLR ). It remains in this mode as long as the test mode signal ( TMS ) corresponds to a logical 1. Takes the test mode signal ( TMS ) has the logical value 0, the test controller changes ( TAPC ) synchronous to the system clock ( TCK ) into the "waiting state" ( RUN ). In this "waiting state" ( RUN ) remains the test controller ( TAPC ) until the test mode signal ( TMS ) a logical 1 is present. Then the test controller changes ( TAPC ) to the state "Start of data register shifting" ( SDRS ). If the test mode signal ( TMS ) shows a logical 1 again the next time, the test controller changes ( TAPC ) then to the state "Start shifting instruction register" ( SIRS ). Provided that with the next cycle there is a logical 1 on the test mode signal ( TMS ) is present, the test controller changes ( TAPC ) back to the "reset test logic" state ( TLR ) and resets the data interface logic.

However, it is in the "Start of instruction register shifting" state ( SIRS ) a logical 0 on the test mode signal ( TMS ), the test controller changes ( TAPC ) to the "Load instruction register data" state ( CIR ) in which the data available in an instruction shadow register is transferred to the instruction register ( IR , please refer 2 ) Loading. In this respect, the instruction register ( IR ) a two-stage register in which the foreground is formed by a shift register and the actual data is in a shadow register that is only read in this state. The shift register of the instruction register ( IR ) is used to feed and discharge the data, while the shadow register of the instruction register ( IR ) contains the actual, valid data. This two-stage nature typically applies to all registers, especially the data registers ( DR ), the JTAG interface, also the registers according to the invention of the interface according to the invention described below. The data registers ( DR ) typically also include those scan path chains that are used for testing and analyzing the integrated circuit. Access to these data registers ( DR ) is part of the problem 2 are some data registers ( DR ) specially shown separately. For the sake of simplicity, only one data register ( DR ) shown. As standard, an integrated circuit can have several data registers ( DR ) exhibit. If necessary, the shadow register of the instruction register ( IR ) can be completely or partially divided into one for reading and one for writing. Further changes in visibility and access options depending on internal conditions are of course possible. Is in the "Load instruction register data" state ( CIR ) at the next cycle of the test mode signal ( TMS ) a logical 1, the test controller jumps ( TAPC ) directly to the state "instruction register Exit 1" (described later) ( EIR1 ). However, if there is a logical 0, the test controller changes ( TAPC ) to the state "Shift instruction register" ( SIR ), in which it remains as long as a logical 0 on the test mode signal ( TMS ) is present. The shift register of the instruction register ( IR ) operated in the function of a shift register and its data content with each cycle of the system clock ( TCK ) by one bit in the direction of the serial data output ( TDI ) with which the last memory cell of the shift register of the instruction register ( IR ) connected is. The shadow register of the Instruction register ( IR ) is of course not subjected to this sliding process. The at the data input ( TDI ) pending data information is transferred with each cycle of the system cycle ( TCK ) into the first cell of the shift register of the instruction register ( IR ) is loaded and transported from there with each additional cycle while it is being pushed. If, however, a logical 1 is applied to the test mode signal for a cycle, the test controller exits ( TAPC ) the state "shift instruction register" ( SIR ) and changes to the previously mentioned state "Instruction register Exit 1" ( EIR1 ). If again a logical 1 for the next cycle of the system cycle ( TCK ) is present, the test controller changes ( TAPC ) to the "write instruction register" state ( UIR2 ) for which the value of the shift register part of the instruction register ( IR ) into the shadow register of the instruction register ( IR ) is written. However, it is in the "Instruction register Exit 1" state ( EIR1 ) a logical 0 on the test mode signal ( TMS ), the test controller changes ( TAPC ) to the state "Pause instruction register" ( PIR ), where it remains as long as a logical 0 on the test mode signal ( TMS ) is present. Is in the "Pause instruction register" state ( PIR ) a logical 1 on the test mode signal ( TMS ), the test controller changes ( TAPC ) to the status "instruction register Exit 2" ( EIR2 ). If with the next system cycle ( TCK ) a logical 0 on the test mode signal ( TMS ) is present, the test controller changes ( TAPC ) back to the already described state "shift instruction register" ( SIR ) return. If, however, in the status "Instruction register Exit 2" ( EIR2 ) with the next system cycle ( TCK ) a logical 1 on the test mode signal ( TMS ) is present, the test controller changes ( TAPC ) to the "write instruction register" state ( UIR2 ). In the next cycle the test controller changes ( TAPC ) to the state "Start of data register shifting" ( SDRS ), if a logical 1 on the test mode signal ( TMS ) is present and in the "Waiting" state ( RUN ) if a logical 0 is present.

Is in the state "Start of data register shifting" ( SDRS ) a logical 0 on the test mode signal ( TMS ), the test controller changes ( TAPC ) to the "Load data register data" state ( CDR ) in which the data that are available in a data shadow register are transferred to the respective data register ( DR ) Loading. Which data register ( DR ) is selected from several data registers, at least some of the valid bits of the shadow register of the data register ( DR ). Here, too, is typically the data register ( DR ) a two-stage register in which the foreground is formed by a shift register and the actual data is in a shadow register that is only read in this state. The shift register of the data register ( DR ) also serves to feed and discharge the data, while the shadow register of the data register ( DR ) contains the actual data. As already mentioned, this two-stage preferably applies to all registers of the JTAG interface, including the registers according to the invention of the interface according to the invention, which are described below and which are formally standardized as data registers ( DR ) are executed. If necessary, the shadow register of the data register ( DR ) again be completely or partially divided into one for read and one for write processes. Further changes in visibility and access options depending on internal conditions are of course also possible here. Is in the "Load data register data" state ( CDR ) at the next cycle of the test mode signal ( TMS ) a logical 1, the test controller jumps ( TAPC ) directly to the later described state "Data register Exit 1" ( EDR1 ). However, if there is a logical 0, the test controller changes ( TAPC ) to the state "Shift data register" ( SDR ) in which it remains as long as a logical 0 on the test mode signal ( TMS ) is present. The shift register of the data register ( DR ) operated in the function of a shift register and its data content with each cycle of the system clock ( TCK ) by one bit in the direction of the serial data output ( TDI ) with which the last memory cell of the shift register of the data register ( DR ) connected is. The shadow register of the data register ( DR ) is of course not subjected to this sliding process. The at the data input ( TDI ) pending data information is transferred with each cycle of the system cycle ( TCK ) into the first cell of the shift register of the data register ( DR ) is loaded and transported from there with each additional cycle while it is being pushed. If, however, there is a logical 1 on the test mode signal ( TMS ) is present, the test controller exits ( TAPC ) the state "shift data register" ( SDR ) and changes to the previously mentioned state "Data register Exit 1" ( EDR1 ). If again a logical 1 for the next cycle of the system cycle ( TCK ) is present, the test controller changes ( TAPC ) to the "write data register" state ( UDR2 ) for which the value of the shift register part of the data register ( DR ) into the shadow register of the data register ( DR ) is written. However, it is in the "Data register Exit 1" state ( EDR1 ) a logical 0 on the test mode signal ( TMS ), the test controller changes ( TAPC ) to the "Pause data register" state ( PDR ), where it remains as long as a logical 0 on the test mode signal ( TMS ) is present. Is in the "Pause data register" state ( PDR ) a logical 1 on the test mode signal ( TMS ), the test controller changes ( TAPC ) to the status "Data register Exit 2" ( EDR2 ). If with the next system cycle ( TCK ) a 0 on the test mode signal ( TMS ) is present, the test controller changes ( TAPC ) back to the already described state "shift data register" ( SDR ) return. If, however, in the status “Data register Exit 2 "( EDR2 ) with the next system cycle ( TCK ) a logical 1 on the test mode signal ( TMS ) is present, the test controller changes ( TAPC ) to the "write data register" state ( UDR2 ). In the next cycle the test controller changes ( TAPC ) to the state "Start of data register shifting" ( SDRS ), if a logical 1 on the test mode signal ( TMS ) is present and in the "Waiting" state ( RUN ) if a logical 0 is present.

It is particularly useful to use this status scheme of the IEEE 1149 JTAG standard in order to remain compatible with the standard that is already in extensive use at the software level. Of course, deviations from this JTAG standard are conceivable. In describing the invention, however, we assume that this JTAG standard for the state diagram of the test controller ( TAPC ) is adhered to.

Figure 2

2 shows an exemplary system of a JTAG-compatible test system. The system is started using the system clock ( TCK ) and the test mode signal ( TMS ) operated and controlled as previously described. The data is entered serially via the serial data input ( TDI ). The data is output serially via the serial data output ( TDO ). The test controller ( TAPC ) controls the test device of the integrated circuit by means of the system clock ( TCK ) depending on the test mode signal ( TMS ), as described above. The test controller ( TAPC ) controls the first multiplexer ( MUX1 ), which determines whether the serial data output ( TDO ) the output of the shift register of the instruction register ( IR ) or the output of one of the n data registers ( D1 to Dn ) with n as a whole positive number.

Via the instruction register ( IR ) commands can be loaded into the test system. These are set by the command decoder ( IRDC ) converted into control signals and / or control signal sequences. In addition, the command decoder controls depending on the logical content of the instruction register ( IR ) preferably a second multiplexer ( MUX2 ), which determines which of the output bits of which data register ( BR , DR1 to DRn) at the serial data output ( TDO ) at the corresponding position of the first multiplexer ( MUX1 ) is output.

A bypass register ( BR ) with a length of one bit is intended as a dummy data register. Theoretical data registers are not absolutely necessary if the test of the integrated circuit can be carried out via signaling at the connections of the integrated circuits. Typically, however, this is unusual.

task

The proposal is therefore based on the object of creating a solution which does not have the above disadvantages of the prior art and has further advantages.

This object is achieved by a device according to claims 1, 2 and 3.

Solution of the task

The proposed solution is made with the help of the 3 explained. One of the data registers is the customer password register ( CPWR ). In the customer password register ( CPWR ) the customer of the semiconductor manufacturer can store his customer password in the form of a predefined serial bit sequence in a non-volatile shadow register. If a protected memory area is to be read out, the person who wants to read out the protected memory area enters the password register ( PWR ) enter the password in the form of the predefined serial bit sequence, which is matched with the serial bit sequence of the customer password register ( CPWR ) must match the stored customer password in order to allow access to the protected memory area.

It is conceivable that different passwords are provided for access to different protected memory areas. It is conceivable that different passwords are provided for access to several and / or all different protected memory areas.

It is conceivable that different passwords are provided for different types of access, such as write access and / or delete access and / or reset access and / or read access to the protected memory area being addressed. The types of access to different protected memory areas can be different.

It is conceivable that by means of a predefined customer password or by means of predefined information at predefined positions in the customer password in the customer password register ( CPWR ) the write and / or read access to one or more protected memory areas is completely prevented, the shadow register of the customer password register that contains the valid customer password is preferably a non-volatile memory.

The customer password register is preferred ( CPWR ) a protected memory area that cannot be read or written once it has been written to by the customer and / or if a customer password is locked within the Customer password register ( CPWR ) and / or in a customer password access register ( CPAR ) has been set once. Either the customer password lock is in the customer password access register ( CPAR ) designed so that it can only be set once and then can no longer be deleted or it is designed so that the customer password in the customer password register ( CPWR ) when changing the customer password access register ( CPAR ) in such a way that read and / or write access to the customer password register ( CPWR ) is allowed, deleted or reset to a predefined basic password. Such a process preferably also leads to the deletion of the content of the other protected memory areas, since these can then be accessed by a third party. Alternatively, it can also be provided that certain protected memory areas cannot be accessed even after the customer password has been entered, but this is likely to be counterproductive.

It is conceivable that the input of password sequences is provided for enabling read and / or write access to protected memory areas.

Such a protected memory area can be the logical values of individual flip-flops or latches, registers, memory blocks or entire memory units, but also physical values of circuit parameters that are set, for example, by means of laser trimming, etc. In the broadest sense, these are parameters of the integrated circuit that should be protected from access by unauthorized third parties.

The customer password access register ( CPAR ) can also be wholly or partially part of the instruction register ( IR ) be.

A password control logic ( PWCL ) then controls depending on the content of the customer password register and the content of the password register ( PWR ) access to the protected areas. The customer password in the customer password register is preferred ( CPWR ) stored in encrypted form. The password control logic ( PWCL ) preferably decrypts the customer password, in the case of such encryption, and compares it with the content of the password register ( PWR ). The password register is preferably a shift register that is fed back with a simple primitive polynomial, so that the content of the password register can also be decrypted when the password is read in. Which primitive polynomial is used for the feedback can be specified, for example, via a command in the instruction register. If necessary, this information can also be stored in a further data register, not shown, which is non-volatile and is itself a protected area.

This means that the password cannot be reconstructed even if a key is lost due to sabotage.

A memory is stored via a memory interface register ( ME ) addressed. In this case, access then only takes place via a memory access logic ( TIMES ). The memory access logic controls the write and / or delete and / or read access to a protected memory ( MEM ).

The password control logic ( PWCL ) controls the write and / or delete and / or read access to the customer password register ( CPWR ).

It can make sense to use different, i.e. several customer password registers ( CPWR ) with different customer passwords, whereby the customer password of a customer password register ( CPWR ) is preferably assigned to one or more combinations of access method and protected memory area.

The password control logic ( PWCL ) allows access with a specific access method to such a customer password register ( CPWR ) if the password is in the password register ( PWR ) such an access by matching the customer password assigned to this access method and this protected memory area in the corresponding customer password register ( CPWR ) and if appropriate information in the customer password access register ( CPAR ) for this customer password and this memory area and this access method.

It can be useful if for the duration of half a period of the system clock or longer than half a period of the system clock and / or temporally longer than one period of the system clock and / or temporally longer than two periods of the system clock and / or temporally longer than three periods of the system clock, a reset of the protected memory areas to a predefined or deleted value is triggered if the password is a password for analysis purposes.

It is possible for different users in the supply chain to set different customer passwords assigned to them, so that the analysis capability in the supply chain to the end customer decreases because the analysis of the protected areas is only permitted for those areas that are still unprotected when they are delivered to a supplier in the supply chain.

It therefore makes sense if a device has more than one customer password. Preferably, at least one of the customer passwords can be reserved for the semiconductor manufacturer so that this semiconductor manufacturer can program certain information, such as a serial number, into the integrated circuit and protect it from modification and / or readout. It is then actually a manufacturer password, which in the following is referred to as the customer password for the sake of simplicity.

The protected areas can also be the content of an operating time counter that records the operating times.

The protected areas can also be a memory area for operating parameters recorded by an analog-to-digital converter, for example, which are stored in the protected area with the current value of the operating time counter when the operating parameter leaves a predefined operating parameter area and / or lies in a predefined operating parameter range. An example would be exceeding the recommended operating voltage or exceeding a temperature etc.

If a scan path test is carried out via a corresponding data register by means of a command in the instruction register ( IR ) and / or using a suitable password in the password register ( PWR ) is activated, preference is given to one or more periods of the system clock ( TCK ) a reset process and / or an erase process for predetermined, preferably all resettable or erasable protected memory areas are given. This includes in particular the protected storage nodes of the protected storage areas, which can be reached directly as part of the scan path or indirectly by stimulation and reading out by means of the scan path.

the 4th largely corresponds to 3 with the difference that for a better overview the access to the memory ( MEM ) was not drawn. Instead, it shows several internal analog signals ( AV1 to AVm ) the micro-integrated circuit, which is controlled by an analog multiplexer ( AMUX ) to a connection ( ATO ) of the micro-integrated circuit can be output. The analog multiplexer ( AMUX ) only outputs this analog data if the password is in the password register ( PWR ) with the customer password in an associated customer password register ( CPWR ) matches in a predetermined manner.

This match of a customer password of a customer password register ( CPWR ) and the password of the password register ( PWR ) means in the sense of this document that the password control logic ( PWCL ) in a preferably unambiguous way with the help of the customer password of the relevant customer password register ( CPWR ) can determine that the password is in the password register ( PWR ) has the logical content to initiate the releases that are provided for this customer password.

These principles can also be used in an analogous manner for other interfaces. As a rule, modern circuits have the aforementioned JTAG test interface. In addition, they usually have other interfaces.

SPI interface

Thus, an SPI interface for integrated circuits and / or for microsystems can be proposed which has similar properties. The SPI interface is then preferably provided and set up to control a scan path for test purposes. The scan input and output are typically not part of the scan path. A general clock of the integrated circuit or of the microsystem is typically used as the system clock. In a first variant, the SPI interface has a customer password register ( CPWR ) and a password register ( PWR ) having. The customer password register ( CPWR ) again contains a customer password or is intended to contain one. The password register ( PWR ) can now typically be written with a password in this variant using the SPI interface. According to the proposal, access to the scan path is only possible in this variant if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

The SPI interface proposed here preferably also includes a customer password access register in a manner analogous to the JTAG test interface proposed above ( CPAR ). The customer password register ( CPWR ) in this variant can only be written and / or read and / or deleted and / or reset via the SPI interface if the customer password lock is in the customer password access register ( CPAR ) is not set. The customer password lock in the customer password access register ( CPAR ) is analogous to the above-described case of a JTAG test interface by writing the customer password lock in the customer password access register ( CPAR ) by means of direct access to the customer password access register ( CPAR ) set via the SPI interface and / or by writing a customer password in the customer password access register ( CPAR ) set.

In a third variant of this SPI interface, the customer password lock is in the customer password access register ( CPAR ) typically more than once writing of a customer password in the customer password access register ( CPAR ) set.

In a fourth variant of the SPI interface, at least part of the digital part of the integrated circuit, in particular some or all of the memory nodes of the digital part, is reset when the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

In a fifth variant of the SPI interface, the SPI interface has a first customer password register ( CPWR ) as a customer password register ( CPWR ) and a second customer password register ( CPWR ) from the first customer password register ( CPWR ) is different. This results in the advantages already mentioned in the description of the JTAG test interface. In this variant, the SPI interface preferably has a password register ( PWR ) on. Again the first customer password register contains ( CPWR ) a first customer password as a customer password and / or is intended to contain one. Now, however, the second customer password register also contains ( CPWR ) a second customer password as a customer password and / or is intended to contain one. This means that different levels of the value chain in the supply chain can use their own passwords. The password register ( PWR ) can now be written with a password in this variant using the SPI interface. As in the case of the JTAG test interface, access to the scan path is only possible if the first customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. Here, too, the second customer password register and possibly other protected memory areas can preferably be reset and / or deleted if the first customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

• - erstmaliges Einschreiben des Kundenpassworts in das Kundenpasswortregister (CPWR);
• - Auslesen des Inhalts des Kundenpasswortregisters (CPWR);
• - Vergleich des ausgelesenen Inhalts des Kundenpasswortregisters (CPWR) mit dem eingeschriebenen Kundenpasswort
• - Setzen der Kundenpasswortsperre im Kundenpasswortzugriffsregister (CPAR)
  • - durch Einschreiben der Kundenpasswortsperre im Kundenpasswortzugriffsregister (CPAR) durch einen direkten Zugriff auf das Kundenpasswortzugriffsregister (CPAR) über die SPI-Schnittstelle und/oder
  • - durch nochmaliges Einschreiben eines Kundenpassworts im Kundenpasswortzugriffsregister (CPAR)

umfasstIn a manner analogous to the method that was described above in connection with the JTAG test interface, the method for setting a customer password lock in the customer password access register ( CPAR ) in an SPI interface that describes the steps

• - First writing of the customer password in the customer password register ( CPWR );
• - Reading out the content of the customer password register ( CPWR );
• - Comparison of the read content of the customer password register ( CPWR ) with the registered customer password
• - Setting the customer password lock in the customer password access register ( CPAR )
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the SPI interface and / or
  • - by rewriting a customer password in the customer password access register ( CPAR )

includes

As with the description of the JTAG test interface, a seventh variant can be specified as an SPI interface for testing integrated circuits and / or for testing microsystems that have a protected memory area ( MEM ) having. The protected memory area can be a general memory area of the integrated circuit or the microsystem. The SPI interface preferably has a memory access logic ( TIMES ) the SPI interface. This memory access logic ( TIMES ) controls access to the protected memory. The SPI interface has a customer password register in a manner analogous to the JTAG interface described above ( CPWR ) and a password register ( PWR ), whereby the customer password register ( CPWR ) again contains a customer password and / or is intended to contain one. The password register ( PWR ) can now typically be written with a password again using the SPI interface. Access to the protected memory area is preferred again ( MEM ) via the memory access logic ( TIMES ) only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

In a manner analogous to the JTAG test interface, an SPI interface for integrated circuits and / or for microsystems can now be specified here, in which the SPI interface and / or the integrated circuit and / or the microsystem have a first protected memory area ( MEM ) and a second protected memory area ( MEM ) that is different from the first protected memory area. Furthermore, the SPI interface preferably has a first customer password register ( CPWR ), a second customer password register ( CPWR ) and a password register ( PWR ) on. The first customer password register ( CPWR ) preferably contains a first customer password or is at least intended to contain one. The second customer password register ( CPWR ) contains a second customer password and / or is at least intended to contain one. The password register ( PWR ) is preferably writable with a password in the same way as the JTAG test interface by means of the SPI interface. Access to the first protected memory area in a first access type is then typically only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and access to the second protected memory area in a second type of access is only possible if the customer password is in the second customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. The first type of access and the second type of access can be the same.

In a similar way to the JTAG test interface, a further variant of the SPI interface for integrated circuits and / or for microsystems can now be specified, the SPI interface again having a protected memory area. The protected memory area can be accessed in a first access method via the SPI interface under the first conditions described below. In addition, the protected memory area can also be accessed in a second access method via the SPI interface under the second conditions described below. The SPI interface preferably has a first customer password register ( CPWR ), a second customer password register ( CPWR ) and a password register ( PWR ) on. The first customer password register ( CPWR ) contains a first customer password or is intended to contain one. The second customer password register ( CPWR ) contains a second customer password or is intended to contain one. The password register ( PWR ) can be written with a password using the SPI interface. Access to the protected memory area in a first access type is only possible if the first customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner, and access to the protected memory area in a second type of access is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. The first type of access and the second type of access are again different. Reference is made to the comments on the analog case with the JTAG test interface.

Preferably, the logical content of the protected memory area is reset or deleted before or immediately when the access is made possible, for example by logic when the protected memory area is accessed by means of the first access type. Access is preferred only after more than one period of the system clock ( TCK ) the SPI interface is permitted by the SPI interface.

Finally, in a manner analogous to the JTAG test interface described above, an SPI interface for integrated circuits and / or for microsystems can also be specified, the SPI interface again preferably being part of a microintegrated circuit. The micro-integrated circuit here includes at least one internal analog signal ( AV1 to AVm ). The SPI interface again has a customer password register ( CPWR ) and a password register ( PWR ) on. The customer password register ( CPWR ) contains a customer password or is intended to contain one. The password register ( PWR ) can be written with a password using the SPI interface. The output of the value of the analog signal through an analog connector ( ATO ) of the micro-integrated circuit is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

UART interface

Likewise, a UART interface for integrated circuits and / or for microsystems can be proposed which has similar properties. The UART interface is then preferably provided and set up to control a scan path for test purposes. The scan input and output are typically not part of the scan path. A general clock of the integrated circuit or of the microsystem is typically used as the system clock. In a first variant, the UART interface has a customer password register ( CPWR ) and a password register ( PWR ) having. The customer password register ( CPWR ) again contains a customer password and / or is intended to contain one. The password register ( PWR ) can now typically be written with a password in this variant using the UART interface. According to the proposal, access to the scan path is only possible in this variant if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

The UART interface proposed here preferably also comprises a JTAG test interface in a manner analogous to the above proposed Customer Password Access Register ( CPAR ). The customer password register ( CPWR ) in this variant can only be written and / or read and / or deleted and / or reset via the UART interface if the customer password lock is in the customer password access register ( CPAR ) is not set. The customer password lock in the customer password access register ( CPAR ) is analogous to the above-described case of a JTAG test interface by writing the customer password lock in the customer password access register ( CPAR ) by means of direct access to the customer password access register ( CPAR ) set via the UART interface and / or by writing a customer password in the customer password access register ( CPAR ) set.

In a third variant of this UART interface, the customer password lock is in the customer password access register ( CPAR ) typically more than once writing of a customer password in the customer password access register ( CPAR ) set.

In a fourth variant of the UART interface, at least part of the digital part of the integrated circuit, in particular some or all of the memory nodes of the digital part, is reset when the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

In a fifth variant of the UART interface, the UART interface has a first customer password register ( CPWR ) as a customer password register ( CPWR ) and a second customer password register ( CPWR ) from the first customer password register ( CPWR ) is different. This results in the advantages already mentioned in the description of the JTAG test interface. In this variant, the UART interface preferably has a password register ( PWR ) on. Again the first customer password register contains ( CPWR ) a first customer password as a customer password and / or is intended to contain one. Now, however, the second customer password register also contains ( CPWR ) a second customer password as a customer password and / or is intended to contain one. This means that different levels of the value chain in the supply chain can use their own passwords. The password register ( PWR ) can now be written with a password in this variant using the UART interface. As in the case of the JTAG test interface, access to the scan path is only possible if the first customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. Here, too, the second customer password register and possibly other protected memory areas can preferably be reset and / or deleted if the first customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

• - erstmaliges Einschreiben des Kundenpassworts in das Kundenpasswortregister (CPWR);
• - Auslesen des Inhalts des Kundenpasswortregisters (CPWR);
• - Vergleich des ausgelesenen Inhalts des Kundenpasswortregisters (CPWR) mit dem eingeschriebenen Kundenpasswort
• - Setzen der Kundenpasswortsperre im Kundenpasswortzugriffsregister (CPAR)
  • - durch Einschreiben der Kundenpasswortsperre im Kundenpasswortzugriffsregister (CPAR) durch einen direkten Zugriff auf das Kundenpasswortzugriffsregister (CPAR) über die UART-Schnittstelle und/oder
  • - durch nochmaliges Einschreiben eines Kundenpassworts im Kundenpasswortzugriffsregister (CPAR)

umfasstIn a manner analogous to the method that was described above in connection with the JTAG test interface, the method for setting a customer password lock in the customer password access register ( CPAR ) that the steps are described in a UART interface

• - First writing of the customer password in the customer password register ( CPWR );
• - Reading out the content of the customer password register ( CPWR );
• - Comparison of the read content of the customer password register ( CPWR ) with the registered customer password
• - Setting the customer password lock in the customer password access register ( CPAR )
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the UART interface and / or
  • - by rewriting a customer password in the customer password access register ( CPAR )

includes

As with the description of the JTAG test interface, the seventh variant is a UART interface for testing integrated circuits and / or for testing microsystems that have a protected memory area ( MEM ) having. The protected memory area can be a general memory area of the integrated circuit or the microsystem. The UART interface preferably has a memory access logic ( TIMES ) of the UART interface. This memory access logic ( TIMES ) controls access to the protected memory. The UART interface has a customer password register analogous to the JTAG interface described above ( CPWR ) and a password register ( PWR ), whereby the customer password register ( CPWR ) again contains a customer password and / or is intended to contain one. The password register ( PWR ) can now typically be written with a password again using the UART interface. Access to the protected memory area is preferred again ( MEM ) via the memory access logic ( TIMES ) only possible if the customer password is in Customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

In a manner analogous to the JTAG test interface, a UART interface for integrated circuits and / or for microsystems can now be specified here, in which the UART interface and / or the integrated circuit and / or the microsystem have a first protected memory area ( MEM ) and a second protected memory area ( MEM ) that is different from the first protected memory area. Furthermore, the UART interface preferably has a first customer password register ( CPWR ), a second customer password register ( CPWR ) and a password register ( PWR ) on. The first customer password register ( CPWR ) preferably contains a first customer password or is at least intended to contain one. The second customer password register ( CPWR ) contains a second customer password and / or is at least intended to contain one. The password register ( PWR ) can preferably be written with a password in a manner analogous to the JTAG test interface by means of the UART interface. Access to the first protected memory area in a first access type is then typically only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and access to the second protected memory area in a second type of access is only possible if the customer password is in the second customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. The first type of access and the second type of access can be the same.

In a manner similar to the JTAG test interface, a further variant of the UART interface for integrated circuits and / or for microsystems can now be specified, the UART interface again having a protected memory area. The protected memory area can be accessed in a first access method via the UART interface under the first conditions described below. In addition, the protected memory area can also be accessed in a second access method via the UART interface under the second conditions described below. The UART interface preferably again has a first customer password register ( CPWR ), a second customer password register ( CPWR ) and a password register ( PWR ) on. The first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one. The second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one. The password register ( PWR ) can be written with a password using the UART interface. Access to the protected memory area in a first access type is only possible if the first customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner, and access to the protected memory area in a second type of access is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. The first type of access and the second type of access are again different. Reference is made to the comments on the analog case with the JTAG test interface.

Preferably, the logical content of the protected memory area is reset or deleted before or immediately when the access is made possible, for example by logic when the protected memory area is accessed by means of the first access type. Access is preferred only after more than one period of the system clock ( TCK ) of the UART interface through the UART interface.

Finally, in a manner analogous to the JTAG test interface described above, a UART interface for integrated circuits and / or for microsystems can also be specified, the UART interface again preferably being part of a microintegrated circuit. The micro-integrated circuit here includes at least one internal analog signal ( AV1 to AVm ). The UART interface again has a customer password register ( CPWR ) and a password register ( PWR ) on. The customer password register ( CPWR ) contains a customer password and / or is intended to contain one. The password register ( PWR ) can be written with a password using the UART interface. The output of the value of the analog signal through an analog connector ( ATO ) of the micro-integrated circuit is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Access via these three interfaces can be combined with one another, which further increases security.

An integrated circuit and / or a microsystem comprising at least two of the following three interfaces UART interface, SPI interface and JTAG test interface is therefore proposed. One of the three interfaces is preferably provided and set up to control a scan path for test purposes. One of the three interfaces shows a Customer password register ( CPWR ) on. One of the three interfaces has a password register ( PWR ) on. It is now important, however, that neither the first interface nor the second interface have the customer password register ( CPWR ) and the password register ( PWR ) and at the same time are also provided and set up to control a scan path for test purposes. A corresponding test of the integrated circuit or the microsystem using these interfaces therefore always requires two interfaces to be used in whole or in part. The customer password register ( CPWR ) contains a customer password and / or is intended to contain one. The password register ( PWR ) can be written with a password using the relevant interface. Access to the scan path is preferably only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

A refinement relates to an integrated circuit and / or microsystem, as described above, where an interface is a customer password access register ( CPAR ) includes. The customer password register ( CPWR ) can now be written and / or read and / or deleted and / or reset via this interface if the customer password lock in the customer password access register ( CPAR ) is not set. Neither the first interface nor the second interface include the customer password register at the same time ( CPWR ), the password register ( PWR ) and the customer password access register ( CPAR ) and are also intended and set up to control a scan path for test purposes, so that a test always uses two interfaces in whole or in part. The customer password lock in the customer password access register ( CPAR ) is confirmed by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the relevant interface and / or by writing a customer password in the customer password access register ( CPAR ) set.

In one variant, the customer password lock is stored in the customer password access register ( CPAR ) by writing a customer password more than once in the customer password access register ( CPAR ) set.

At least part of the digital part of the integrated circuit, in particular all or some storage nodes, is preferably reset when the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

The relevant interface preferably has a first customer password register ( CPWR ) as a customer password register ( CPWR ), a password register ( PWR ) and a second customer password register ( CPWR ) from the first customer password register ( CPWR ) is different. Neither the first interface nor the second interface have A) at the same time the customer password register ( CPWR ) and the second customer password register ( CPWR ) and the password register ( PWR ) and are B) at the same time also intended and set up to control a scan path for test purposes, so that a test always uses two interfaces in whole or in part. The first customer password register ( CPWR ) contains a first customer password as a customer password and / or is intended to contain one. The second customer password register ( CPWR ) contains a second customer password as a customer password and / or is intended to contain one. The password register ( PWR ) can be written with a password using the relevant interface. Access to the scan path is only possible if the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. The second customer password register and possibly other protected memory areas are reset and / or deleted when the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

• - erstmaliges Einschreiben des Kundenpassworts in das Kundenpasswortregister (CPWR);
• - Auslesen des Inhalts des Kundenpasswortregisters (CPWR);
• - Vergleich des ausgelesenen Inhalts des Kundenpasswortregisters (CPWR) mit dem eingeschriebenen Kundenpasswort
• - Setzen der Kundenpasswortsperre im Kundenpasswortzugriffsregister (CPAR)
  • - durch Einschreiben der Kundenpasswortsperre im Kundenpasswortzugriffsregister (CPAR) durch einen direkten Zugriff auf das Kundenpasswortzugriffsregister (CPAR) über die betreffende-Schnittstelle und/oder
  • - durch nochmaliges Einschreiben eines Kundenpassworts im Kundenpasswortzugriffsregister (CPAR).

As already described above for the individual interfaces, a procedure for setting a customer password lock in the customer password access register ( CPAR ) are specified in the relevant interface of an integrated circuit and / or a microsystem. It includes the steps:

• - First writing of the customer password in the customer password register ( CPWR );
• - Reading out the content of the customer password register ( CPWR );
• - Comparison of the read content of the customer password register ( CPWR ) with the registered customer password
• - Setting the customer password lock in the customer password access register ( CPAR )
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the relevant interface and / or
  • - by rewriting a customer password in the customer password access register ( CPAR ).

In a manner analogous to the individual interfaces described above, an interface system is now here that comprises at least two interfaces, a first interface and a second interface, the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface, specified. An interface or an integrated circuit of which the interface system is part, or a microsystem of which the interface system is part, a protected memory area ( MEM ) having. An interface has a memory access logic ( TIMES ) of the interface system. The memory access logic ( TIMES ) controls access to the protected memory. An interface has a customer password register ( CPWR ) on. An interface has a password register ( PWR ) on.

None of the at least two interfaces has the memory access logic ( TIMES ) of the interface system, the customer password register ( CPWR ) and the password register ( PWR ) on. The customer password register ( CPWR ) contains a customer password or is intended to contain one. The password register ( PWR ) can be written with a password using the relevant interface. Access to the protected memory area ( MEM ) via the memory access logic ( TIMES ) is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Likewise, an interface system that comprises at least two interfaces, a first interface and a second interface, the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface, can be specified, with an interface or an integrated A circuit, part of which is the interface system, or a microsystem, part of which the interface system is, has a first protected memory area. An interface and / or the integrated circuit, part of which is the interface system, and / or the microsystem, part of which the interface system is, has a second protected memory area which is different from the first protected memory area. An interface has a first customer password register ( CPWR ) on. One interface has a second customer password register ( CPWR ) on. An interface has a password register ( PWR ) on. None of the at least two interfaces have the first customer password register at the same time ( CPWR ) and the second customer password register ( CPWR ) and the password register ( PWR ) on. The first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one. The second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one. The password register ( PWR ) can be written with a password using the relevant interface. Access to the first protected memory area in a first access type is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. Access to the second protected memory area in a second access type is only possible if the customer password is in the second customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner. The first type of access and the second type of access can again be the same.

Likewise, an interface system for an integrated circuit and / or a microsystem, which comprises at least two interfaces, a first interface and a second interface, of the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface, to be discribed. The integrated circuit and / or the microsystem has a protected memory area. The protected memory area can again be accessed in a first access method via an interface under the first conditions described below. The protected memory area can be accessed in a second access method via an interface under the second conditions described below. An interface has a first customer password register ( CPWR ) on. One interface has a second customer password register ( CPWR ) on. An interface has a password register ( PWR ) on. None of the at least two interfaces is preferably designed at the same time in such a way that the protected memory area in the first access method can be accessed via the interface under the first conditions described below, and the protected memory area in the second can also be accessed via this interface under the second conditions described below Access method can be accessed. None of the at least two interfaces is preferably designed at the same time in such a way that the interface simultaneously contains the first customer password register ( CPWR ) and the second customer password register ( CPWR ) and the password register ( PWR ) having. The first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one. The second customer password register ( CPWR ) preferably contains a second customer password and / or is intended to contain one. The password register ( PWR ) can be written with a password using the relevant interface. Access to the protected memory area in a first access type is only possible if the first customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and access to the protected memory area in a second type of access is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) coincides in a predetermined manner, the first type of access and the second type of access being different. When the protected memory area is accessed by means of the first type of access, the logical content of the protected memory area is preferably reset or deleted before or immediately when the access is made possible. Access is preferred only after more than half a period of the system clock ( TCK ) an interface is permitted by the relevant interface.

In a further variant, the interface system comprises at least two interfaces, a first interface and a second interface, the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface, with the micro-integrated circuit and / or the microsystem at least one internal analog signal ( AV1 to AVm ) having. One interface has a customer password register ( CPWR ) on. An interface has a password register ( PWR ) on. None of the at least two interfaces have the customer password register ( CPWR ) and the password register ( PWR ). The customer password register ( CPWR ) contains a customer password or is intended to contain one. The password register ( PWR ) can be written with a password using the relevant interface. The value of the analog signal is output via an analog connection ( ATO ) of the micro-integrated circuit and / or the microsystem only if the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Features of the invention

The features of the invention can be freely combined with one another, insofar as this makes sense. The stress results from the claims.

Feature 1: JTAG test interface for testing integrated circuits and / or for testing microsystems

• - where the JTAG test interface uses a scan path as a data register ( DR ) the JTAG test interface and
• - where the JTAG test interface is a customer password register ( CPWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a password register ( PWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the customer password register ( CPWR ) contains a customer password and
• - where the password register ( PWR ) can be written with a password using the JTAG test interface and
• - Access to the scan path is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Feature 2: JTAG test interface according to feature 1

• - where the JTAG test interface is a customer password access register ( CPAR ) includes and
• - where the customer password register ( CPWR ) can be written and / or read and / or deleted and / or reset via the JTAG test interface if the customer password lock in the customer password access register ( CPAR ) is not set and
• - with the customer password lock in the customer password access register ( CPAR ) is set
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the JTAG test interface and / or
  • - by writing a customer password in the customer password access register ( CPAR ).

Feature 3: JTAG test interface according to feature 2

• - with the customer password lock in the customer password access register ( CPAR ) is set
  • - by writing a customer password more than once in the customer password access register ( CPAR ).

Feature 4: JTAG test interface according to feature 2 or 3

• - at least part of the digital part of the integrated circuit is reset when the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 5: JTAG test interface according to one or more of features 1 to 4

• - where the JTAG test interface is a first customer password register ( CPWR ) as a customer password register ( CPWR ) within the meaning of claim 1, which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a second customer password register ( CPWR ) having,
  • - the one from the first customer password register ( CPWR ) is different and
  • - the whole or part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a password register ( PWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the first customer password register ( CPWR ) contains a first customer password as a customer password within the meaning of claim 1 and
• - where the second customer password register ( CPWR ) contains a second customer password as the customer password and
• - where the password register ( PWR ) can be written with a password using the JTAG test interface and
• - Access to the scan path is only possible if the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - whereby the second customer password register and possibly other protected memory areas are reset and / or deleted when the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 6: Procedure for setting customer password lock in the customer password access register ( CPAR ) in a JTAG interface according to feature 2 or 3 comprising the steps

• - First writing of the customer password in the customer password register ( CPWR );
• - Reading out the content of the customer password register ( CPWR );
• - Comparison of the read content of the customer password register ( CPWR ) with the registered customer password
• - Setting the customer password lock in the customer password access register ( CPAR )
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the JTAG test interface and / or
  • - by rewriting a customer password in the customer password access register ( CPAR ).

Feature 7: JTAG test interface for testing integrated circuits and / or for testing microsystems

• - whereby the JTAG test interface has a protected memory area ( MEM ) and
• - where the JTAG test interface is a memory access logic ( TIMES ) as a data register ( DR ) the JTAG test interface and
• - where the memory access logic ( TIMES ) controls access to the protected memory and
• - where the JTAG test interface is a customer password register ( CPWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a password register ( PWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the customer password register ( CPWR ) contains a customer password and
• - where the password register ( PWR ) can be written with a password using the JTAG test interface and
• - whereby access to the protected memory area ( MEM ) via the memory access logic ( TIMES ) is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Feature 8: JTAG test interface for testing integrated circuits and / or for testing microsystems

• - The JTAG test interface having a first protected memory area and
• - The JTAG test interface having a second protected memory area which is different from the first protected storage area, and
• - where the JTAG test interface is a first customer password register ( CPWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a second customer password register ( CPWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a password register ( PWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the first customer password register ( CPWR ) contains a first customer password and
• - where the second customer password register ( CPWR ) contains a second customer password and
• - where the password register ( PWR ) can be written with a password using the JTAG test interface and
• - Access to the first protected memory area in a first type of access is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the second protected memory area in a second type of access is only possible if the customer password is in the second customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access can be the same.

Feature 9: JTAG test interface for testing integrated circuits and / or for testing microsystems

• - The JTAG test interface has a protected memory area and
• - The protected memory area can be accessed in a first access method via the JTAG test interface under the first conditions described below, and
• - The protected memory area can be accessed in a second access method via the JTAG test interface under the second conditions described below, and
• - where the JTAG test interface is a first customer password register ( CPWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a second customer password register ( CPWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a password register ( PWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the first customer password register ( CPWR ) contains a first customer password and
• - where the second customer password register ( CPWR ) contains a second customer password and
• - where the password register ( PWR ) can be written with a password using the JTAG test interface and
• - Access to the protected memory area in a first type of access is only possible if the first customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the protected memory area in a second access type is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access are different.

Feature 10: JTAG test interface for testing integrated circuits and / or for testing microsystems according to feature 9

• - With an access to the protected memory area by means of the first type of access, the logical content of the protected memory area is reset or deleted before or immediately when the access is made possible.

Feature 11: JTAG test interface for testing integrated circuits and / or for testing microsystems according to feature 10

• - whereby the access is only possible after more than one period of the system clock ( TCK ) the JTAG test interface is permitted by the JTAG test interface.

Feature 12: JTAG test interface for testing integrated circuits and / or for testing microsystems

• - The JTAG test interface is part of a micro-integrated circuit and
• - where the micro-integrated circuit has at least one internal analog signal ( AV1 to AVm ) and
• - where the JTAG test interface is a customer password register ( CPWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the JTAG test interface has a password register ( PWR ), which is also wholly or partially part of a data register and / or the instruction register ( IR ) can be, and
• - where the customer password register ( CPWR ) contains a customer password and
• - where the password register ( PWR ) can be written with a password using the JTAG test interface and
• - where the output of the value of the analog signal via an analog connection ( ATO ) of the micro-integrated circuit is only possible if the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

SPI interface

Feature 13: SPI interface for integrated circuits and / or for microsystems

• - The SPI interface is provided and set up to control a scan path for test purposes and
• - where the SPI interface is a customer password register ( CPWR ) and
• - whereby the SPI interface has a password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the SPI interface and
• - Access to the scan path is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Feature 14: SPI interface according to feature 13

• - where the SPI interface is a customer password access register ( CPAR ) includes and
• - where the customer password register ( CPWR ) can be written and / or read and / or deleted and / or reset via the SPI interface if the customer password lock in the customer password access register ( CPAR ) is not set and
• - with the customer password lock in the customer password access register ( CPAR ) is set
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the SPI interface and / or
  • - by writing a customer password in the customer password access register ( CPAR ).

Feature 15: SPI interface according to feature 14

• - with the customer password lock in the customer password access register ( CPAR ) is set
  • - by writing a customer password more than once in the customer password access register ( CPAR ).

Feature 16.SPI interface according to feature 14 or 15

• - at least part of the digital part of the integrated circuit is reset when the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 17. SPI interface according to one or more of features 13 to 16

• - whereby the SPI interface has a first customer password register ( CPWR ) as a customer password register ( CPWR ) in the sense of feature 1 and
• - whereby the SPI interface has a second customer password register ( CPWR ) having,
  • - that from the first customer password register ( CPWR ) is different and
• - whereby the SPI interface has a password register ( PWR ) and
• - where the first customer password register ( CPWR ) contains a first customer password as a customer password within the meaning of feature 1 and / or is intended to contain such, and
• - where the second customer password register ( CPWR ) contains a second customer password as a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the SPI interface and
• - Access to the scan path is only possible if the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - whereby the second customer password register and possibly other protected memory areas are reset and / or deleted when the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 18.Method of setting a customer password lock in the customer password access register ( CPAR ) in an SPI interface according to feature 14 or 15 comprising the steps

• - First writing of the customer password in the customer password register ( CPWR );
• - Reading out the content of the customer password register ( CPWR );
• - Comparison of the read content of the customer password register ( CPWR ) with the registered customer password
• - Setting the customer password lock in the customer password access register ( CPAR )
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the SPI interface and / or
  • - by rewriting a customer password in the customer password access register ( CPAR ).

Feature 19. SPI interface for integrated circuits and / or for microsystems

• - where the SPI interface and / or the integrated circuit and / or the microsystem have a protected memory area ( MEM ) and
• - where the SPI interface has a memory access logic ( TIMES ) the SPI interface and
• - where the memory access logic ( TIMES ) controls access to the protected memory and
• - where the SPI interface is a customer password register ( CPWR ) and
• - whereby the SPI interface has a password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the SPI interface and
• - whereby access to the protected memory area ( MEM ) via the memory access logic ( TIMES ) is only possible if the customer password is in Customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Feature 20. SPI interface for integrated circuits and / or for microsystems

• - the SPI interface and / or the integrated circuit and / or the microsystem having a first protected memory area ( MEM ) and
• - the SPI interface and / or the integrated circuit and / or the microsystem having a second protected memory area ( MEM ) that is different from the first protected memory area, and
• - whereby the SPI interface has a first customer password register ( CPWR ) and
• - whereby the SPI interface has a second customer password register ( CPWR ) and
• - whereby the SPI interface has a password register ( PWR ) and
• - where the first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one, and
• - where the second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the SPI interface and
• - Access to the first protected memory area in a first type of access is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the second protected memory area in a second type of access is only possible if the customer password is in the second customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access can be the same.

Feature 21. SPI interface for integrated circuits and / or for microsystems

• - where the SPI interface and / or the integrated circuit and / or the microsystem have a protected memory area ( MEM ) and
• - being via the SPI interface under the first conditions described below the protected memory area can be accessed in a first access method and
• - The protected memory area can be accessed in a second access method via the SPI interface under the second conditions described below, and
• - whereby the SPI interface has a first customer password register ( CPWR ) and
• - whereby the SPI interface has a second customer password register ( CPWR ) and
• - whereby the SPI interface has a password register ( PWR ) and
• - where the first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one, and
• - where the second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the SPI interface and
• - Access to the protected memory area in a first type of access is only possible if the first customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the protected memory area in a second access type is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access are different.

Feature 22. SPI interface for integrated circuits and / or for microsystems according to feature 21

• - With an access to the protected memory area by means of the first type of access, the logical content of the protected memory area is reset or deleted before or immediately when the access is made possible.

Feature 23: SPI interface for integrated circuits and / or for microsystems according to feature 22

• - whereby the access is only possible after more than one period of the system clock ( TCK ) the SPI interface is permitted by the SPI interface.

Feature 24: SPI interface for integrated circuits and / or for microsystems

• - The SPI interface is part of a micro-integrated circuit and
• - where the micro-integrated circuit has at least one internal analog signal ( AV1 to AVm ) and
• - where the SPI interface is a customer password register ( CPWR ) and
• - whereby the SPI interface has a password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the SPI interface and
• - where the output of the value of the analog signal via an analog connection ( ATO ) of the micro-integrated circuit is only possible if the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

UART interface

Feature 25: UART interface for testing integrated circuits and / or for testing microsystems

• - The UART interface is provided and set up to control a scan path for test purposes and
• - where the UART interface is a customer password register ( CPWR ) and
• - whereby the UART interface has a password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the UART interface and
• - Access to the scan path is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Feature 26: UART interface according to feature 25

• - where the UART interface is a customer password access register ( CPAR ) includes and
• - where the customer password register ( CPWR ) can be written and / or read and / or deleted and / or reset via the UART interface if the customer password lock in the customer password access register ( CPAR ) is not set and
• - with the customer password lock in the customer password access register ( CPAR ) is set
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the UART interface and / or
  • - by writing a customer password in the customer password access register ( CPAR ).

Feature 27 UART interface according to feature 26

• - with the customer password lock in the customer password access register ( CPAR ) is set
• - by writing a customer password more than once in the customer password access register ( CPAR ).

Feature 28: UART interface according to feature 26 or 27

• - at least part of the digital part of the integrated circuit is reset when the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 29: UART interface according to one or more of features 25 to 28

• - whereby the UART interface has a first customer password register ( CPWR ) as a customer password register ( CPWR ) in the sense of feature 1 and
• - whereby the UART interface has a second customer password register ( CPWR ) having,
  • - the one from the first customer password register ( CPWR ) is different and
• - whereby the UART interface has a password register ( PWR ) and
• - where the first customer password register ( CPWR ) contains a first customer password as a customer password within the meaning of feature 1 and / or is intended to contain such, and
• - where the second customer password register ( CPWR ) contains a second customer password as a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the UART interface and
• - Access to the scan path is only possible if the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - whereby the second customer password register and possibly other protected memory areas are reset and / or deleted when the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 30: Procedure for setting a customer password lock in the customer password access register ( CPAR ) in a UART interface according to feature 2 or 3 comprising the steps

• - First writing of the customer password in the customer password register ( CPWR );
• - Reading out the content of the customer password register ( CPWR );
• - Comparison of the read content of the customer password register ( CPWR ) with the registered customer password
• - Setting the customer password lock in the customer password access register ( CPAR )
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the UART interface and / or
  • - by rewriting a customer password in the customer password access register ( CPAR ).

Feature 31: UART interface for testing integrated circuits and / or for testing microsystems

• - whereby the UART interface has a protected memory area ( MEM ) and
• - where the UART interface has a memory access logic ( TIMES ) the UART interface and
• - where the memory access logic ( TIMES ) controls access to the protected memory and
• - where the UART interface is a customer password register ( CPWR ) and
• - whereby the UART interface has a password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the UART interface and
• - whereby access to the protected memory area ( MEM ) via the memory access logic ( TIMES ) is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Feature 32: UART interface for testing integrated circuits and / or for testing microsystems

• - wherein the UART interface has a first protected memory area and
• - wherein the UART interface has a second protected memory area which is different from the first protected memory area, and
• - whereby the UART interface has a first customer password register ( CPWR ) and
• - whereby the UART interface has a second customer password register ( CPWR ) and
• - whereby the UART interface has a password register ( PWR ) and
• - where the first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one, and
• - where the second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the UART interface and
• - Access to the first protected memory area in a first type of access is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the second protected memory area in a second type of access is only possible if the customer password is in the second customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access can be the same.

Feature 33: UART interface for testing integrated circuits and / or for testing microsystems

• - The UART interface has a protected memory area and
• - The protected memory area can be accessed in a first access method via the UART interface under the first conditions described below, and
• - The protected memory area can be accessed in a second access method via the UART interface under the second conditions described below, and
• - whereby the UART interface has a first customer password register ( CPWR ) and
• - whereby the UART interface has a second customer password register ( CPWR ) and
• - whereby the UART interface has a password register ( PWR ) and
• - where the first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one, and
• - where the second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the UART interface and
• - Access to the protected memory area in a first type of access is only possible if the first customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the protected memory area in a second access type is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access are different.

Feature 34: UART interface for testing integrated circuits and / or for testing microsystems according to feature 33

• - With an access to the protected memory area by means of the first type of access, the logical content of the protected memory area is reset or deleted before or immediately when the access is made possible.

Feature 35: UART interface for testing integrated circuits and / or for testing microsystems according to feature 34

• - whereby the access is only possible after more than one period of the system clock ( TCK ) the UART test interface is permitted by the UART interface.

Feature 36: UART interface for testing integrated circuits and / or for testing microsystems

• - The UART interface is part of a micro-integrated circuit and
• - where the micro-integrated circuit has at least one internal analog signal ( AV1 to AVm ) and
• - where the UART interface is a customer password register ( CPWR ) and
• - whereby the UART interface has a password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the SPI interface and
• - where the output of the value of the analog signal via an analog connection ( ATO ) of the micro-integrated circuit is only possible if the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Interface system

Feature 37: Integrated circuit and / or microsystem comprising at least two of the following three interfaces: a UART interface and / or an SPI interface and / or a JT AG test interface,

• - One of the three interfaces is provided and set up to control a scan path for test purposes, and
• - where one of the three interfaces is a customer password register ( CPWR ) and
• - whereby one of the three interfaces has a password register ( PWR ) and
• - whereby neither the first interface nor the second interface simultaneously contains the customer password register ( CPWR ) and the password register ( PWR ) and is provided and set up for this purpose, a scan path to control for test purposes so that a test always uses two interfaces in whole or in part,
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the relevant interface and
• - Access to the scan path is only possible if the customer password is in the Customer password register ( CPWR ) with the Password in the password register ( PWR ) matches in a predetermined manner.

Feature 38: Integrated circuit and / or microsystem according to feature 37

• - where an interface is a customer password access register ( CPAR ) includes and
• - where the customer password register ( CPWR ) can be written and / or read and / or deleted and / or reset via this interface if the customer password lock in the customer password access register ( CPAR ) is not set and
• - whereby neither the first interface nor the second interface simultaneously contains the customer password register ( CPWR ) and the password register ( PWR ) and the customer password access register ( CPAR ) and at the same time is provided and set up to control a scan path for test purposes, so that a test always uses two interfaces in whole or in part, with the customer password lock in the customer password access register ( CPAR ) is set
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the relevant interface and / or
  • - by writing a customer password in the customer password access register ( CPAR ).

Feature 39: Integrated circuit and / or microsystem according to feature 38

• - with the customer password lock in the customer password access register ( CPAR ) is set
  • - by writing a customer password more than once in the customer password access register ( CPAR ).

Feature 40: Integrated circuit and / or microsystem according to feature 38 or 39

• - at least part of the digital part of the integrated circuit is reset when the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 41: Integrated circuit and / or microsystem according to one or more of features 37 to 40

• - where the relevant interface is a first customer password register ( CPWR ) as a customer password register ( CPWR ) in the sense of feature 1 and
• - whereby the relevant interface has a password register ( PWR ) and
• - where one interface has a second customer password register ( CPWR ) having,
  • - the one from the first customer password register ( CPWR ) is different and
• - whereby neither the first interface nor the second interface simultaneously contains the customer password register ( CPWR ) and the second customer password register ( CPWR ) and the password register ( PWR ) and is provided and set up to control a scan path for test purposes so that a test always uses two interfaces in whole or in part,
• - where the first customer password register ( CPWR ) contains a first customer password as a customer password within the meaning of feature 1 and / or is intended to contain such, and
• - where the second customer password register ( CPWR ) contains a second customer password as a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the relevant interface and
• - Access to the scan path is only possible if the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - whereby the second customer password register and possibly other protected memory areas are reset and / or deleted when the first customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and thus access to the scan path is enabled.

Feature 42: Procedure for setting a customer password lock in the customer password access register ( CPAR ) in the relevant interface of an integrated circuit and / or a microsystem according to feature 38 or 39 comprising the steps

• - First writing of the customer password in the customer password register ( CPWR );
• - Reading out the content of the customer password register ( CPWR );
• - Comparison of the read content of the customer password register ( CPWR ) with the registered customer password
• - Setting the customer password lock in the customer password access register ( CPAR )
  • - by writing the customer password lock in the customer password access register ( CPAR ) through direct access to the customer password access register ( CPAR ) via the relevant interface and / or
  • - by rewriting a customer password in the customer password access register ( CPAR ).

Feature 43: Interface system which comprises at least two interfaces, a first interface and a second interface, of the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface,

• - where an interface or an integrated circuit, part of which is the interface system, or a microsystem, part of which the interface system is, a protected memory area ( MEM ) and
• - where an interface is a memory access logic ( TIMES ) of the interface system and
• - where the memory access logic ( TIMES ) controls access to the protected memory and
• - where one interface is a customer password register ( CPWR ) and
• - where one interface has a password register ( PWR ) and
• - whereby none of the at least two interfaces simultaneously control the memory access logic ( TIMES ) of the interface system and the customer password register ( CPWR ) and the password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the relevant interface and
• - whereby access to the protected memory area ( MEM ) via the memory access logic ( TIMES ) is only possible if the customer password is in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

Feature 44: Interface system which comprises at least two interfaces, a first interface and a second interface, the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface,

• - wherein an interface has a first protected memory area and
• an interface having a second protected memory area which is different from the first protected memory area, and
• - where an interface has a first customer password register ( CPWR ) and
• - where one interface has a second customer password register ( CPWR ) and
• - where one interface has a password register ( PWR ) and
• - whereby none of the at least two interfaces simultaneously have the first customer password register ( CPWR ) and the second customer password register ( CPWR ) and the password register ( PWR ) and
• - where the first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one, and
• - where the second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the relevant interface and
• - Access to the first protected memory area in a first type of access is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the second protected memory area in a second type of access is only possible if the customer password is in the second customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access can be the same.

Feature 45: Interface system for an integrated circuit and / or a microsystem, which comprises at least two interfaces, a first interface and a second interface, the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface,

• - The integrated circuit and / or the microsystem having a protected memory area and
• - The protected memory area can be accessed in a first access method via an interface under the first conditions described below, and
• - The protected memory area can be accessed in a second access method via an interface under the second conditions described below, and
• - where an interface has a first customer password register ( CPWR ) and
• - where one interface has a second customer password register ( CPWR ) and
• - where one interface has a password register ( PWR ) and
• - whereby none of the at least two interfaces is simultaneously designed in such a way that the protected memory area in the first access method can be accessed via the interface under the first conditions described below and the protected memory area in the second can be accessed via the interface under the second conditions described below Access method can be accessed and that at the same time the interface has the first customer password register ( CPWR ) and the second customer password register ( CPWR ) and the password register ( PWR ), and
• - where the first customer password register ( CPWR ) contains a first customer password and / or is intended to contain one, and
• - where the second customer password register ( CPWR ) contains a second customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the relevant interface and
• - Access to the protected memory area in a first type of access is only possible if the first customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and.
• - Access to the protected memory area in a second access type is only possible if the customer password is in the first customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner and
• - The first type of access and the second type of access are different.

Feature 46: Interface system for an integrated circuit and / or a microsystem according to feature 45

• - With an access to the protected memory area by means of the first type of access, the logical content of the protected memory area is reset or deleted before or immediately when the access is made possible.

Feature 47: Interface system for an integrated circuit and / or a microsystem according to feature 46

• - whereby the access only takes place after more than half a period of the system clock ( TCK ) an interface is permitted by the relevant interface.

Feature 48: Interface system for an integrated circuit and / or a microsystem

• - wherein the interface system comprises at least two interfaces, a first interface and a second interface, of the following three interfaces, UART interface and / or SPI interface and / or JTAG test interface
• - the micro-integrated circuit and / or the microsystem at least one internal analog signal ( AV1 to AVm ) and
• - where one interface is a customer password register ( CPWR ) and
• - where one interface has a password register ( PWR ) and
• - whereby none of the at least two interfaces simultaneously use the customer password register ( CPWR ) and the password register ( PWR ) and
• - where the customer password register ( CPWR ) contains a customer password and / or is intended to contain one, and
• - where the password register ( PWR ) can be written with a password using the relevant interface and
• - where the output of the value of the analog signal via an analog connection ( ATO ) of the micro-integrated circuit and / or the microsystem is only possible if the customer password in the customer password register ( CPWR ) with the password in the password register ( PWR ) matches in a predetermined manner.

advantage

Such a JTAG test interface makes it possible, at least in some implementations, that a supplier in the supply chain can test the software components for which he is responsible without having to disclose them to his customer and / or his own supplier. The advantages are not limited to this.

Figure list

• 1 shows the state diagram of a test controller according to the IEEE 1149 standard. the 1 was explained in the introduction.
• 2 shows a prior art JTAG test interface.
• 3 shows a schematically simplified example of a proposed JTAG test interface.
• 4th shows a schematically simplified example of a proposed JTAG test interface with protected output of analog internal values of the microintegrated circuit.

List of reference symbols

AMUX

analog multiplexer, which is controlled by the command decoder ( IRDC ) is controlled and only then an analog signal of the analog signals ( AV1 to AVm ) at its inputs to an output ( ATO ) of the micro-integrated circuit outputs if a password is in the password register ( PWR ) with the corresponding customer password in the customer password register ( CPWR ) matches and the corresponding command in the instruction register ( IR ) is active.

ATO

in particular, the analog output of the micro-integrated circuit

AV1

first analog signal of the micro-integrated circuit, part of which is the proposed JTAG test interface;

AV2

second analog signal of the micro-integrated circuit, part of which is the proposed JTAG test interface;

AVm

m-th analog signal of the micro-integrated circuit, with m as a positive integer, part of which is the proposed JTAG test interface;

BR

Bypass register;

CIR

"Load instruction register data" state of the test controller ( TAPC ) the JT AG test interface;

CDR

"Load data register data" state of the test controller ( TAPC ) the JTAG test interface;

CPAR

Customer password access register;

CPWR

Customer password register;

D1

first data register;

D2

second data register;

D3

third data register;

D (n-1)

(n-1) th data register;

Dn

nth data register;

DR

Data register;

EDR1

Status "data register Exit 1" of the test controller ( TAPC ) the JTAG test interface;

EDR2

Status "data register Exit 2" of the test controller ( TAPC ) the JTAG test interface;

EIR1

Status "instruction register Exit 1" of the test controller ( TAPC ) the JTAG test interface;

EIR2

Status "instruction register Exit 2" of the test controller ( TAPC ) the JTAG test interface;

FPGA

Field Programmable Gate Array;

IR

Instruction register;

IRDC

Command decoder;

TIMES

Memory access logic;

MEM

Storage;

ME

Memory interface register;

MUX1

first multiplexer;

MUX2

second multiplexer;

PDR

"Pause data register" state of the test controller ( TAPC ) the JTAG test interface;

PIR

"Pause instruction register" state of the test controller ( TAPC ) the JTAG test interface;

PWCL

Password control logic;

PWR

Password register;

RS

Reset circuit. If necessary, the reset circuit can be activated by entering a suitable password in the password register ( PWR ) can be activated if the password is in the password register ( PWR ) with a customer password in a customer password register ( CPWR ) matches. In that case the reset circuit generates a reset signal ( RST ) for resetting and / or deleting a predetermined protected memory area. The connections to this reset signal ( RST ) are in the 3 not shown for a better overview.

RST

Reset signal. If necessary, the reset circuit can be activated by entering a suitable password in the password register ( PWR ) can be activated if the password is in the password register ( PWR ) with a customer password in a customer password register ( CPWR ) matches. In that case the reset circuit generates ( RS ) a reset signal for resetting and / or deleting a predetermined protected memory area. The connections to this reset signal are in the 3 not shown for a better overview

RUN

State "waiting state" or equivalent "waiting" of the test controller ( TAPC ) the JTAG test interface;

SDR

Status "shift data register" of the test controller ( TAPC ) the JTAG test interface;

SDRS

Status "start of data register shifting" of the test controller ( TAPC ) the JT AG test interface;

SdT

State of the art;

SIR

State "Shift instruction register" of the test controller ( TAPC ) the JT AG test interface;

SIRS

Status "start shifting instruction register" of the test controller ( TAPC ) the JTAG test interface;

TAPC

JTAG test interface test controller;

TCK

System clock of the JTAG test interface according to the IEEE 1149 standard;

TDI

serial test data input of the JTAG interface according to IEEE 1149 standard;

TDO

serial test data output of the JTAG interface according to the IEEE 1149 standard;

TLR

"Reset test logic" state of the test controller ( TAPC ) the JTAG test interface;

TMS

Test mode signal of the JTAG interface according to the IEEE 1149 standard;

TRST

optional reset input of the JTAG interface according to IEEE 1149 standard;

UDR2

"Write data register" state of the test controller ( TAPC ) the JTAG test interface;

UIR2

"Write instruction register" state of the test controller ( TAPC ) the JT AG test interface;

glossary

Protected memory area

In the context of this document, such a protected memory area can be the logical values of individual or multiple memory nodes, flip-flops or latches, registers, memory blocks or entire memory units, but also digital or analog physical values of circuit parameters, which can be generated, for example, by means of laser Trim, etc., act. The output can therefore also take place in an analog manner via an analog data bus, the analog data bus being able to include analog multiplexers which use the JTAG test interface using the instruction register ( IR ) together with the command decoder ( IRDC ) being controlled. The analog signal is output via a connection on the integrated circuit if the customer password is in a customer password register ( CPWR ) with the password in the password register ( PWR ) coincides in a predetermined manner.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• EP 503117 B1 [0005]

Claims (5)

JTAG test interface for testing integrated circuits and / or for testing microsystems - The JTAG test interface and / or the integrated circuit and / or the microsystem having a protected memory area (MEM) and - The JTAG test interface having a memory access logic (MAL) as a data register (DR) of the JTAG test interface and - wherein the memory access logic (MAL) controls the access to the protected memory and - The JTAG test interface having a customer password register (CPWR), which can also be wholly or partially part of a data register and / or the instruction register (IR), and - The JTAG test interface having a password register (PWR) which can also be wholly or partially part of a data register and / or the instruction register (IR), and - wherein the customer password register (CPWR) contains a customer password and / or is intended to contain such, and - The password register (PWR) can be written with a password using the JTAG test interface, and - Access to the protected memory area (MEM) via the memory access logic (MAL) is only possible if the customer password in the customer password register (CPWR) matches the password in the password register (PWR) in a predetermined manner. JTAG test interface for testing integrated circuits and / or for testing microsystems - the JTAG test interface having a first protected memory area and - the JTAG test interface having a second protected memory area that is different from the first protected memory area The JTAG test interface has a first customer password register (CPWR), which can also be wholly or partially part of a data register and / or the instruction register (IR), and the JTAG test interface has a second customer password register (CPWR), which can also be wholly or partly part of a data register and / or the instruction register (IR), and - wherein the JTAG test interface has a password register (PWR) which is also wholly or partly part of a data register and / or of the instruction register (IR), and - wherein the first customer password register (CPWR) contains a first customer password and / or is intended to contain such, and - wherein the second customer password register (CPWR) contains a second customer password and / or is intended to contain such, and - wherein the password register (PWR) by means of the JTAG test -Interface can be described with a password and - access to the first protected memory area in a first access type is only possible if the customer password in the first customer password register (CPWR) with the password in Password register (PWR) matches in a predetermined manner and. - Access to the second protected memory area in a second access type is only possible if the customer password in the second customer password register (CPWR) matches the password in the password register (PWR) in a predetermined manner and - the first access type and the second access type are the same can. JTAG test interface for testing integrated circuits and / or for testing microsystems - The JTAG test interface has a protected memory area and - The protected memory area can be accessed in a first access method via the JTAG test interface under the first conditions described below, and - The protected memory area can be accessed in a second access method via the JTAG test interface under the second conditions described below, and - The JTAG test interface having a first customer password register (CPWR), which can also be wholly or partially part of a data register and / or the instruction register (IR), and - The JTAG test interface having a second customer password register (CPWR), which can also be wholly or partially part of a data register and / or the instruction register (IR), and - The JTAG test interface having a password register (PWR) which can also be wholly or partially part of a data register and / or the instruction register (IR), and - wherein the first customer password register (CPWR) contains a first customer password and / or is intended to contain one, and - wherein the second customer password register (CPWR) contains a second customer password and / or is intended to contain one, and - The password register (PWR) can be written with a password using the JTAG test interface, and - Access to the protected memory area in a first type of access is only possible if the first customer password in the first customer password register (CPWR) matches the password in the password register (PWR) in a predetermined manner and. - Access to the protected memory area in a second type of access is only possible if the customer password in the first customer password register (CPWR) matches the password in the password register (PWR) in a predetermined manner and - The first type of access and the second type of access are different. JTAG test interface for testing integrated circuits and / or for testing microsystems Claim 3 - With an access to the protected memory area by means of the first access type, the logical content of the protected memory area is reset or deleted before or immediately when the access is made possible. JTAG test interface for testing integrated circuits and / or for testing microsystems Claim 4 - Access is only permitted by the JTAG test interface after more than one period of the system clock (TCK) of the JTAG test interface.

Images