DE102020108777A1 - Field effect transistor - Google Patents

Abstract

The invention relates to a field effect transistor with lower and upper semiconductor layers, with a charge carrier reservoir layer being formed below the upper semiconductor layer at a distance from the upper semiconductor layer, which has an increased charge carrier density compared to the surroundings and ensures that radiation-induced damage only has a small influence on the electrical characteristics of the field effect transistor.

Description

Field effect transistors are used, for example, for amplifier and control applications. There are different designs, for example with metal-semiconductor gate contacts or with metal-insulator-gate contacts in silicon, in which a gate voltage controls the conductivity between a source contact and a drain contact. In compound semiconductors, such transistors are mostly implemented as heterostructures in which the conductive channel is created at the hetero interface of two materials with different band gaps. There, for example, in group III nitrides, the different polarization of the materials can lead to an accumulation of charge carriers. In group III arsenides and in phosphides, for example, by doping in the material with the larger band gap, charge carriers can be generated which accumulate at the interface. In the ideal case, a two-dimensional electron gas forms there, which has a high charge carrier mobility and is predestined for high-frequency applications and efficient voltage converters.

In particular, components that are based on group III nitrides, but also other components are of great interest for applications at high temperatures or even under high doses of ionizing radiation, such as those found in space in particular. Although the basic function of these components is maintained for a long time even under extreme conditions, the characteristics of transistors change at high doses. For example, a current can drop, i.e. a channel resistance can increase. Furthermore, a threshold voltage can change at which the voltage applied to the gate, depending on the design of the component, opens or closes the channel. As a result of this change, a circuit can lose its actual function after long exposure or precautions must be taken to adapt a control voltage of the gate to the changed component properties.

In the case of field effect transistors, the main reason for this change seems to be the entry of defects in the area under the channel, such defects catching charge carriers from the environment, whereby the charge carrier density decreases and the threshold voltage shifts.

It is an object of the present invention to provide a field effect transistor as an alternative, for example with improved radiation resistance. This is achieved according to the invention by a field effect transistor according to claim 1. Advantageous refinements can be found in the subclaims, for example. The content of the claims is made part of the description by express reference.

The invention relates to a field effect transistor. The field effect transistor has a lower semiconductor layer with a first band gap. The field effect transistor has an upper semiconductor layer with a second band gap. The second band gap is different from the first band gap. The upper semiconductor layer is arranged on the lower semiconductor layer.

The field effect transistor has a source contact which makes contact with the lower semiconductor layer. The field effect transistor has a drain contact which makes contact with the lower semiconductor layer. Furthermore, the field effect transistor has a gate structure which is arranged on the upper semiconductor layer.

Below the upper semiconductor layer, at a distance from the upper semiconductor layer, a charge carrier reservoir layer is formed, which has an increased charge carrier density compared to the surroundings.

By means of such a field effect transistor, the resistance to ionizing radiation, which occurs, for example, in space, can be significantly increased. This is due to the fact that the charge carrier reservoir layer provides a reservoir of charge carriers which transform into defects that are formed due to radiation and can thus neutralize the defects. This prevents the defects from having significant effects on the electrical properties of the field effect transistor due to a possible capture of charge carriers from outside the charge carrier reservoir layer.

The terms “lower semiconductor layer” and “upper semiconductor layer” introduce spatial orientation in the field effect transistor. This can mean, for example, that in a real arrangement the lower semiconductor layer is actually arranged below the upper semiconductor layer. However, this is not mandatory. These designations only serve to define the spatial relationships in the field effect transistor and are independent of the position of the field effect transistor relative to the earth's surface. If the field effect transistor is rotated, for example, the lower semiconductor layer can also be located above the upper semiconductor layer, based on an external reference system such as the earth's surface, for example. In typical growth processes, however, the lower semiconductor layer, for example, is first grown and then the upper semiconductor layer is grown on it, although this is also not mandatory and can also be done in other geometrical orientations.

Due to the difference between the two band gaps mentioned, a charge carrier channel, for example an electron channel or a hole channel, is typically formed in the lower semiconductor layer. For example, the respective charge carriers can form a two-dimensional electron gas or a two-dimensional hole gas. This can also be supported, for example, by additional doping, for example as will be described in more detail below.

Source contact and drain contact typically serve to achieve an electrical connection of a channel formed in the lower semiconductor layer. They are typically designed in such a way that they contact the conductive channel or a formed electron gas or hole gas. For example, an electrical voltage can be applied to the drain contact relative to the source contact, with the current flow being able to be controlled by means of the field effect transistor. For this purpose, a control voltage can be applied in particular by means of the gate structure, whereby, for example, when a charge carrier channel is formed in the basic state (which corresponds to an embodiment as a transistor switched on in the basic state, also referred to as "normally on"), a high-resistance state can be achieved by displacing these charge carriers, whereas there is good conductivity in the ground state. However, the opposite design is also possible. The gate structure can in particular have a heterojunction and / or a non-electrically conductive or poorly electrically conductive layer such as, for example, a dielectric, in order to achieve decoupling from the semiconductor layers. Typically, a highly electrically conductive material is formed on the gate structure, by means of which a gate voltage can be applied as a control voltage. The mentioned good electrically conductive material can be electrically isolated from the rest of the field effect transistor in particular by means of the mentioned heterojunction and / or by means of the mentioned dielectric or another poorly electrically conductive layer. The material with good electrical conductivity can also be referred to as a gate contact. The gate structure or the gate contact is typically formed between the source contact and the drain contact, for example laterally between the source contact and the drain contact.

The upper semiconductor layer can, for example, be thinned under the gate structure or a gate contact, for example partially etched away. It can also be considerably thinned or almost completely etched away. Such designs can be used in particular for an enhancement type field effect transistor.

The increased charge carrier density can, for example, have a value of at least 1 × 10 ¹⁷ cm ^-3 , at least 5 × 10 ¹⁷ cm ^-3 , at least 1 × 10 ¹⁸ cm ^-3 or at least 5 × 10 ¹⁸ cm ^-3 . In particular, it can also have a value of at most 5 × 10 ¹⁷ cm ^-3 , at most 1 × 10 ¹⁸ cm ^-3 , at most 5 × 10 ¹⁸ cm ^-3 or at most 1 × 10 ¹⁹ cm ^-3 . A value between 5 × 10 ¹⁸ cm ^-3 and 1 × 10 ¹⁹ cm ^-3 has proven to be particularly preferred for typical designs. However, other values, in particular with the lower and / or upper values specified here, can also be used.

The distance between the charge carrier reservoir layer and the upper semiconductor layer can be, for example, at least 5 nm, at least 10 nm, at least 20 nm, at least 30 nm or at least 40 nm. The distance between the charge carrier reservoir layer and the upper semiconductor layer can also be at most 10 nm, at most 20 nm, at most 30 nm, at most 40 nm or at most 50 nm. In particular, the distance between the charge carrier reservoir layer and the upper semiconductor layer can be between 5 nm and 50 nm.

The charge carrier reservoir layer can in particular have a thickness of at least 5 nm, at least 10 nm, at least 20 nm, at least 30 nm or at least 40 nm. The charge carrier reservoir layer can also have a thickness of at most 10 nm, at most 20 nm, at most 30 nm, at most 40 nm or at most 50 nm. In particular, the thickness can be between 5 nm and 50 nm.

In principle, all of the lower values mentioned can be combined with all of the higher upper values mentioned in order to form suitable intervals.

The areas just mentioned of the distance between the charge carrier reservoir layer and the upper semiconductor layer and the thickness of the charge carrier reservoir layer have proven to be advantageous for typical applications.

The charge carrier reservoir layer can in particular be formed in the lower semiconductor layer. This is particularly the case with the distances and thicknesses just mentioned.

The distance between the charge carrier reservoir layer and the upper semiconductor layer can in particular be a distance between the upper semiconductor layer, which can for example be delimited from the lower semiconductor layer by a different material, and a point or area at which the doping or charge carrier density of the charge carrier ^{reservoir layer} exceeds ^{a threshold value of, for example, 1 × 10 17} cm -3. The thickness of the charge carrier reservoir layer can be viewed, for example, as a distance between two points or areas at which such a threshold value of, for example, 1 × 10 ¹⁷ cm ^{-3 is} reached. In principle, however, other definitions are also possible here.

The charge carrier reservoir layer can in particular be formed by doping. For this purpose, a dopant can be introduced which leads to an increased charge carrier density. The doping can be implemented with silicon, germanium, sulfur, selenium and / or tellurium, for example. Such dopants have proven to be advantageous for the formation of typical charge carrier reservoir layers. The doping can be introduced into the lower semiconductor layer, for example.

The charge carrier reservoir layer can alternatively or additionally also be formed by a semiconductor heterojunction. A higher charge carrier density can also be achieved by means of such a semiconductor heterojunction.

The semiconductor heterojunction can in particular be arranged at a distance of at least 20 nm, at least 30 nm or at least 40 nm from the upper semiconductor layer. It can also be arranged at a distance of at most 30 nm, at most 40 nm or at most 50 nm from the upper semiconductor layer. In particular, the semiconductor heterojunction can be arranged at a distance of 20 nm to 50 nm from the upper semiconductor layer. Such values have proven to be advantageous for typical applications.

A semiconductor junction can in particular be subdivided into two junctions. In this case, for example, a transition can serve the functionality of the component, and a further transition can serve to form a reservoir.

According to one embodiment, the charge carrier reservoir layer has a charge carrier density that increases with increasing distance from the upper semiconductor layer. As a result, the charge carrier density in the vicinity of a channel can still be kept rather low, in particular in order to avoid impairment of the mobility of charge carriers in the channel. With increasing distance from the upper semiconductor layer and thus also from the channel, the influence of doping or other measures to increase the charge carrier density on the mobility of the charge carriers in the channel decreases, so that more charge carriers can be formed there as reservoirs.

According to one embodiment, the charge carrier reservoir layer has a delta-shaped charge carrier density. As a result, the charge carrier density can be accommodated in a very narrow area with a high concentration, as a result of which a small extent or a small thickness can be achieved.

According to one embodiment, the charge carrier reservoir layer has a constant charge carrier density. In this way, for example, a uniform doping process can be used, which simplifies production.

According to one embodiment, the field effect transistor also has a substrate and, expediently, a buffer layer between the substrate and the lower semiconductor layer. The buffer layer can in particular have a higher resistance than the lower semiconductor layer. In particular, the buffer layer can have a specific resistance of more than 10 ⁷ Ωcm. The buffer layer can, for example, represent electrical insulation between the semiconductor layers already mentioned and a substrate. The substrate can be, for example, a wafer or some other substrate on which the other layers, that is to say in particular the buffer layer and the semiconductor layers, are grown or applied in some other way.

The second band gap can in particular be larger than the first band gap. As a result, a channel can advantageously be formed in the lower semiconductor layer at the interface with the upper semiconductor layer.

For example, when using nitrides, the second band gap can be at least 0.3 eV, preferably at least 0.5 eV larger than the first band gap. For example, aluminum gallium nitride (AlGaN) or aluminum indium nitride (AlInN) can be used for this as the upper semiconductor layer, and gallium nitride (GaN), for example, can be used for this as the lower semiconductor layer.

When using gallium arsenide (GaAs) and other III-V semiconductor systems, the second band gap can preferably be at least 0.1 eV larger than the first band gap.

The charge carrier channel is preferably formed in the lower semiconductor layer at an interface with the upper semiconductor layer. According to a typical embodiment, this charge carrier channel is present in the basic state, i.e. already without applied voltages, so that the field effect transistor is then typically switched on in the basic state, i.e. it is conductive. The charge carriers of the charge carrier channel can in particular be electrons or holes.

According to one embodiment, the charge carrier reservoir layer has the same charge as the charge carrier channel. According to an alternative embodiment to this, the charge carrier reservoir layer has charge carriers of opposite charge to the charge carrier channel. The choice of charge carriers can in particular result in charge carriers of the corresponding polarity being available and, in the case of expected defects, for example due to cosmic radiation, neutralizing these defects so that there is no shift in the threshold voltage or at least only a slight shift .

According to a preferred embodiment, a doped layer is formed in the upper semiconductor layer. The doped layer can, for example, have a distance of 1 nm to 5 nm from the lower semiconductor layer. This doped layer can in particular provide additional charge carriers for the charge carrier channel and preferably has the same polarity as the charge carrier channel. It can in particular be designed as a delta-doped layer, but also, for example, as a spatially doped layer.

For example, when using nitrides or oxides as semiconductor material, the doped layer can have a doping of at least 1 × 10 ¹⁸ cm ^-3 with spatial doping and / or of at least 5 × 10 ¹² cm ^-2 with delta doping. When arsenides are used as semiconductor material, the doped layer can in particular have a doping of more than 5 × 10 ¹⁰ cm ⁻² in the case of delta doping. Such values have proven to be advantageous for typical applications, since they support the construction of the charge carrier channel and thus lead to an improvement in the electrical properties of the field effect transistor.

The lower semiconductor layer can preferably be a binary system. In particular, gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP) and gallium oxide (Ga ₂ O ₃ ) come into consideration. Such material systems have proven to be particularly advantageous for use as a lower layer. The upper layer can in particular be a ternary system, but can also be a binary system.

When using gallium nitride (GaN) as the lower layer, in particular the upper layer can be formed from the aluminum gallium indium nitride system (Al (Ga, In) N).

When using gallium arsenide (GaAs) as the lower layer, the upper layer can in particular be made from the aluminum gallium arsenide system (AIGaAs) or as a binary system made from pure aluminum arsenide (AlAs).

When using indium phosphide (InP) as the lower layer, the upper layer can in particular be formed from the aluminum gallium indium arsenide phosphide system (AlGalnAsP) or from aluminum indium arsenide (AllnAs).

When using gallium oxide (Ga ₂ O ₃ ) as the lower layer, the upper layer can in particular be formed from aluminum gallium oxide (AlGaO) or from aluminum gallium indium oxide (AlGalnO).

The mentioned material systems and in particular the mentioned combinations of material systems have proven to be advantageous for typical applications. As a result, good electrical properties of a field effect transistor can be achieved, with these properties being able to be adapted to the respective purpose through the choice of the material system.

A boundary layer between the upper semiconductor layer and the lower semiconductor layer can in particular be flat. For example, the boundary layer can be designed to be flat. This enables a simple structure. However, other designs are also possible here.

In general, it can be said that an improved transistor component can be realized in which the electrical properties change as little as possible due to ionizing radiation. This can be achieved, for example, by introducing charge carriers into a layer at a distance of, for example, 5 nm to 50 nm from the hetero interface of the component on which a conductive channel is formed, the thickness of the layer enriched in charge carriers being between 5 nm and Can be 50 nm.

Such a layer can be implemented in different ways. For example, it can be designed as constant doping or also as graded doping with ideally increasing doping in depth, since then any charge carrier scattering of the charge carriers in the channel can best be suppressed. Charge carriers can also be introduced, for example, by introducing a further heterostructure at a distance of, for example, 20 nm to 50 nm from the original hetero interface and this, for example, either generates an accumulation of charge carriers at the hetero interface due to the material properties or this through doping in the hetero material below the channel is produced.

Degradation of a field effect transistor or other semiconductor component by ionizing radiation is usually based on the ionizing radiation producing defects in the material which act as charge carrier sinks. As a result, the position of the Fermi level changes and this is pinned at various points of interference in the event of higher radiation doses. To counteract this, charge carriers can be introduced that compensate for these defects. As a result, depending on the doping level, the threshold voltage of the transistor can be kept almost constant over a wide dose range, since in the ideal case the Fermi level remains constant due to these charge carriers introduced. Although the initial threshold voltage may change to higher voltages as a result of this procedure, it then remains constant over a wide dose range, which enables reliable operation of the component or the field effect transistor.

Typically, in the embodiment described here, only a small area near the conductive channel is doped, to be precise with a significantly higher concentration. If too broad an area were doped, this could, depending on the design, lead to a higher reverse current or an excessively high necessary reverse voltage at the gate. The local doping in a limited area prevents excessive change in the threshold voltage at high dose rates. A charge carrier density that increases in depth is particularly advantageous here, but this is preferably only introduced in an overall thin layer in order not to allow the transistor parameters, in particular the threshold voltage without irradiation, to deviate too much from the value without doping. The concentration of these additionally introduced charge carriers is advantageously lower than that of the channel charge carriers and is ideally only so high that the expected change in charge due to the damage caused by ionizing radiation is a maximum of 50%. When using gallium nitride (GaN) -based heterostructures, for example, the structure described herein enables operating times, for example of a satellite in the Van Allen Belt, of several thousand years without significant impairment of the circuit properties. There are more extreme conditions, especially in orbits near the Sun, where correspondingly high radiation damage occurs over shorter periods of time. It is particularly advantageous here if group III nitrides are used, since they can be used to operate the electronics at temperatures well above 400 ° C. Circuits based on this material can therefore be used for long-term missions and under extreme conditions where other materials such as silicon or gallium arsenide (GaAs) would fail relatively early. But even with the latter materials and with group III oxides, the doping described here can lead to a significant increase in the circuit life.

Semiconductors with high binding energy are particularly suitable, in particular silicon carbide (SiC) and diamond (C) or layers containing at least two of the elements silicon (Si), germanium (Ge) or carbon (C) in one layer or from group III Nitrides or group III oxides. In particular, the group III nitrides, i.e. binary, ternary and quaternary compounds, in the aluminum gallium indium nitride (AlGalnN) system have recently proven themselves very well in this regard and there are signs of extreme component lifetimes that allow decades of use in space. The same can be expected from group III oxides such as gallium oxide (Ga ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ) and indium oxide (In ₂ O ₃ ) and their mixed crystals.

To put it another way, for example, in a field effect transistor with a conductive channel controllable by a gate contact at a hetero interface, charge carriers can be introduced, for example at a distance of 5 nm to 50 nm below the hetero interface forming the conductive channel. The introduction of charge carriers can in particular take place by means of a dopant. It can also take place through a charge carrier-generating heterostructure. The material of the component layers can in particular contain at least two of the elements silicon, germanium or carbon in one layer or of group III nitrides or group III oxides.

• 1: einen Feldeffekttransistor gemäß einem ersten Ausführungsbeispiel,
• 2: einen Feldeffekttransistor gemäß einem zweiten Ausführungsbeispiel, und
• 3: einen zum Feldeffekttransistor der 2 zugehörigen Verlauf von Energiebändern.

The person skilled in the art will learn further features and advantages from the exemplary embodiments described below with reference to the accompanying drawings. Show:

• 1 : a field effect transistor according to a first embodiment,
• 2 : a field effect transistor according to a second embodiment, and
• 3 : one to the field effect transistor of the 2 associated course of energy bands.

The ones in the 1 and 2 The illustrated exemplary embodiments are to be understood essentially in such a way that they indicate the spatial structure of layers and other components. Exemplary materials are described below.

1 shows a field effect transistor 10 according to a first embodiment of the invention. This has a substrate 100 on, which can be in the form of a wafer, for example, on which the others are shown Layers are grown. On the substrate 100 there is a buffer layer 101 , which can also be a sequence of different layers and is ideally designed with high resistance. Over the buffer layer 101 is a lower semiconductor layer 102 applied, which can be formed in particular from a binary compound semiconductor material. The thickness of the lower semiconductor layer 102 is preferably between 50 nm and 200 nm. The lower semiconductor layer 102 can also be referred to as a channel layer. The lower semiconductor layer 102 has a first band gap.

Immediately on the lower semiconductor layer 102 there is an upper semiconductor layer 103 , which has a second band gap, the second band gap being larger than the first band gap. For this purpose, for example, a suitable binary or ternary material can be used as the upper semiconductor layer 103 be used.

Between the lower semiconductor layer 102 and the upper semiconductor layer 103 there is an interface 111 , being immediately below the interface 111 In a basic state, a two-dimensional electron gas is formed, which has a charge carrier channel 104 forms. This is present in the basic state, so that it is a normally switched-on field effect transistor. For example, the charge carrier channel is created 104 in the case of group III nitrides, directly at the interface 111 , in the case of other semiconductors such as a GaAs-AlGaAs heterojunction, in particular, an additional doped layer 105 be introduced, which is highly doped with a donor to electrons at the interface 111 to make available and thus the charge carrier channel 104 to train or at least to support its training.

Over the top semiconductor layer 103 is a top layer 106 formed, which in the present case consists of a dielectric. There is a source contact above it 107 , a drain contact 108 as well as a gate contact 109 . Top layer 106 and gate contact 109 together form a gate structure. The source contact 107 and the drain contact 108 are electrical with the lower semiconductor layer 102 connected so that the carrier channel 104 so that it can be contacted in two places. The gate contact 109 is only located above the top layer 106 so that with it the carrier channel 104 can be influenced in a targeted manner by applying a voltage. Is the carrier channel 104 for example formed from electrons and is at the gate contact 109 If a negative voltage is applied, the charge carrier channel is depleted 104 and the resistance between source contact 107 and drain contact 108 becomes significantly higher.

In the lower semiconductor layer 102 is also a charge carrier reservoir layer 110 educated. This is in 1 shown hatched. For this purpose, additional dopants were introduced, which form the charge carrier reservoir layer 110 form and their density with increasing distance from the interface 111 increases. This is in a separate diagram in 1 shown, in which the doping density N is plotted as a function of the height z of the component. As shown, the doping increases from 10 ¹⁶ cm ^-3 at the upper edge to a little over 10 ¹⁹ cm ^-3 at the lower edge.

Will the field effect transistor 10 When exposed to ionizing radiation, which occurs, for example, when used in space, this typically occurs in the lower semiconductor layer 102 and in the buffer layer 101 Defects which form electron sinks. Would be the charge carrier reservoir layer 110 not present, the charge carriers required to fill these imperfections would be from the charge carrier channel 104 would be withdrawn and would no longer be used to conduct electrical current between the source contact 107 and the drain contact 108 be available. This would lead to a significant change in the transistor characteristics.

Due to the presence of the charge carrier reservoir layer 110 the charge carriers required to fill the imperfections with charge carriers are primarily from the charge carrier reservoir layer 110 taken, which leads to a significantly smaller or no longer perceptible change in the transistor characteristics. The load carrier channel 104 remains essentially identical despite the occurrence of defects due to ionizing radiation, so that overall the resistance of the field effect transistor 10 against ionizing radiation is increased significantly.

2 shows a field effect transistor 10 according to a second embodiment. In contrast to the first exemplary embodiment, the charge carrier reservoir layer is not formed by doping, but by a further semiconductor heterojunction. Regarding the other components, please refer to 1 and the associated description.

The material system shown and the associated bands, namely conduction band Ec and valence band Ev, as well as the Fermi energy E _F , are in 3 shown. The lower semiconductor layer 102 is made of gallium nitride (GaN). The top semiconductor layer 103 is made of aluminum gallium nitride (AIGaN). In the lower semiconductor layer 102 is a charge carrier reservoir layer 112 in the form of a layer of indium gallium nitride (InGaN) located therein. Corresponding the in 3 A two-dimensional electron gas is thus formed at the interface 111 between lower semiconductor layer 102 and upper semiconductor layer 103 . Furthermore, however, an increased charge carrier density also forms in the charge carrier reservoir layer 112 , since the conduction band Ec is here significantly closer to the Fermi energy E _F. Corresponding structures are also formed in the valence band Ev, as shown in 3 is shown.

Due to the much greater proximity of the conduction band Ec to the Fermi energy E _F in the charge carrier reservoir layer 112 there is a significantly higher charge carrier density there, which has the same effects as with regard to the charge carrier reservoir layer 110 from 1 has been described. In this case, too, a significantly higher resistance to ionizing radiation can be achieved.

It should be mentioned that when the charge carrier reservoir layer is formed 112 from aluminum gallium nitride (AIGaN) instead of indium gallium nitride (InGaN), an accumulation of holes at the interface with gallium nitride (GaN) can also be achieved. This can be used, for example, for a radiation-stabilized enhancement type transistor. Even with an according to 2 formed charge carrier reservoir layer, different curves of the charge carrier density are possible therein, for example, as shown on the basis of the band diagram of FIG 3 can be understood.

In the two exemplary embodiments shown, a lower charge carrier accumulation can also be formed from the opposite charge carrier type, which ensures depletion of the component without an applied voltage, that is to say effects an enrichment-type transistor. Preferably, a doping used for this tends to be further from the channel 104 removed than with the same type of charge carrier introduced, i.e. at the upper limit of the specified range. In particular, the distance can be at least 50 nm or at least 100 nm. Here too, if the doping concentration is sufficiently high, which is above the expected doping from ionizing radiation, a significant change in the threshold voltage can be suppressed.

As an alternative embodiment, a layer, for example with a thickness between 5 nm and 100 nm, with a larger band gap between doping and channel can be used as a barrier for decoupling. In this way, for example, the minimum distance with the barrier layer in between can be reduced to 20 nm.

The doping is preferably selected in such a way that it compensates for the radiation damage that occurs. For this purpose, hole doping can be used in particular for the main formation of deep donors, and / or electron doping can be used in the main formation of deep acceptors.

As a top layer 106 Alternatively, for example, both aluminum gallium nitride (AlGaN) and aluminum indium nitride (AlInN) or, in general, the aluminum gallium indium nitride material system (AlGalnN) can be used. A dielectric can also be used, as has already been described. The lower semiconductor layer 102 is preferably designed so that it enables high charge carrier mobility, for example made of gallium nitride (GaN). Becomes a heterostructure for the charge carrier reservoir layer 112 is used, this can be selected in particular in the aluminum gallium indium nitride (AlGalnN) system. As an alternative to nitrides, the same also applies to oxides.

In particular, the embodiments disclosed herein can be applied to all lateral transistor components in which a layer sequence is grown on a substrate and in which the current flow runs at least for the most part parallel to the surface. Ionizing radiation includes in particular alpha, beta and gamma radiation, as well as all high-energy particles such as elementary particles and heavier atoms or ions that can penetrate matter and cause local crystal defects or become embedded as foreign atoms. With the mechanisms presented here and in particular the exemplary embodiments just described, it is possible to prevent such damage from affecting the electrical characteristics of the transistor.

It should be pointed out that features can be described in combination in the claims and in the description, for example to facilitate understanding, although these can also be used separately from one another. The person skilled in the art recognizes that such features can also be combined with other features or combinations of features independently of one another.

References back in subclaims can identify preferred combinations of the respective features, but do not exclude other combinations of features.

List of reference symbols

10:

Field effect transistor

100:

Substrate

101:

Buffer layer

102:

lower semiconductor layer

103:

upper semiconductor layer

104:

Load carrier channel

105:

additional doped layer

106:

Top layer

107:

Source contact

108:

Drain contact

109:

Gate contact

110:

Charge carrier reservoir layer

111:

Interface

112:

Charge carrier reservoir layer

Claims (15)

Field effect transistor (10), having - A lower semiconductor layer (102) with a first band gap, - an upper semiconductor layer (103) with a second band gap which is different from the first band gap, the upper semiconductor layer (103) being arranged on the lower semiconductor layer (102), - A source contact (107) which contacts the lower semiconductor layer (102), - A drain contact (108) which contacts the lower semiconductor layer (102), - A gate structure (106, 109) which is arranged on the upper semiconductor layer (103), - With a charge carrier reservoir layer (110, 112) being formed below the upper semiconductor layer (103) at a distance from the upper semiconductor layer (103), which has an increased charge carrier density compared to the surroundings. Field effect transistor (10) according to Claim 1 - the increased charge carrier density having a value of at least 1 × 10 ¹⁷ cm ^-3 or of at least 5 × 10 ¹⁸ cm ^-3 and / or of at most 1 × 10 ¹⁹ cm ^-3 . Field effect transistor (10) according to one of the preceding claims, - The distance between the charge carrier reservoir layer (110, 112) and the upper semiconductor layer (103) being 5 nm to 50 nm. Field effect transistor (10) according to one of the preceding claims, - wherein the charge carrier reservoir layer (110, 112) has a thickness between 5 nm and 50 nm. Field effect transistor (10) according to one of the preceding claims, - wherein the charge carrier reservoir layer (110) is formed by doping. Field effect transistor (10) according to Claim 5 - The doping is formed with silicon, germanium, sulfur, selenium and / or tellurium. Field effect transistor (10) according to one of the preceding claims, - wherein the charge carrier reservoir layer (112) is formed by a semiconductor heterojunction. Field effect transistor (10) according to Claim 7 - wherein the semiconductor heterojunction is arranged at a distance of 20 nm to 50 nm from the upper semiconductor layer (103). Field effect transistor (10) according to one of the preceding claims, - wherein the charge carrier reservoir layer (110, 112) has a charge carrier density that increases with increasing distance from the upper semiconductor layer (103). Field effect transistor (10) according to one of the Claims 1 until 8th - wherein the charge carrier reservoir layer (110, 112) has a delta-shaped charge carrier density. Field effect transistor (10) according to one of the Claims 1 until 8th - wherein the charge carrier reservoir layer (110, 112) has a constant charge carrier density. Field effect transistor (10) according to one of the preceding claims, - which also has a substrate (100) and a buffer layer (101) between substrate (100) and lower semiconductor layer (102), - The buffer layer (101) having a higher resistance than the lower semiconductor layer (102). Field effect transistor (10) according to one of the preceding claims, - A charge carrier channel (104) being formed in the lower semiconductor layer (102) at an interface (111) to the upper semiconductor layer (103). Field effect transistor (10) according to Claim 13 - wherein the charge carrier reservoir layer (110, 112) has charge carriers with the same charge as the charge carrier channel (104). Field effect transistor (10) according to Claim 13 - wherein the charge carrier reservoir layer (110, 112) has charge carriers of opposite charge than the charge carrier channel (104).

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