DE102020004679A1 - Machine emulation using a multilevel inverter with variable voltage potentials - Google Patents

Abstract

Power electronics (100) for the function test of a switchable i-phase inverter with j voltage stages (10), the power electronics having: i circuit arrangements (110, 210, 310) for generating an i-th function test voltage (UEMU_1, UEMU_2, UEMU_3) at one i-th connection (120, 220, 320) of the power electronics; each of the i circuit arrangements being configured to generate n variable, low-pass filtered intermediate voltages (U1,1, U1,2, U1,3, U1,4), which each have a different voltage level and which can each be connected to the i-th connection; and wherein in each case one of the n intermediate voltages is present at the i-th connection of the power electronics; and where i ≥ 1, j ≥ 2, n ≥ 2 and i, j, n ∈ N.

Description

The invention relates to power electronics for the function test of a single- or multi-phase inverter and its use in a machine emulator, a machine emulator for emulating a three-phase machine for the function test of a single- or multi-phase inverter, a method for the function test of a single- or multi-phase inverter and a method for emulation an induction machine for functional testing of a single- or multi-phase inverter.

A rotary field machine is understood to be a machine in which a magnetic field rotates continuously about an axis of rotation, such as in single-phase AC motors, multi-phase three-phase motors or rotary field magnets. To operate an induction machine, the induction machine must be connected to an electrical supply device and supplied with an operating voltage. For this purpose, induction machine inverters and/or induction machine control devices are used as electrical supply devices. In the following, the induction machine inverters and the inverters in general are examples of all electrical supply devices for induction machines.

An electro-mechanical machine test bench is usually used to test the functionality of inverters. The inverter under test is connected to a real induction machine and the induction machine is mechanically loaded by a controllable load machine. For this purpose, the load machine is controlled in such a way that it simulates typical mechanical load scenarios of the induction machine and applies these load scenarios to the induction machine. The inverter under test must then supply the induction machine with the appropriate electrical voltages and currents on the electro-mechanical machine test bench in order to operate the induction machine at its mechanical operating points.

However, an electro-mechanical machine test bench that simulates the load conditions to be tested as realistically as possible represents a very complex system that is difficult to implement and causes high costs. In addition, such machine test benches are not flexible enough to be able to be adapted to variable settings of the induction machine.

As an alternative to an electro-mechanical machine test bench, a purely electrical machine emulator can be used, which is able to simulate the electrical behavior of a mechanically loaded induction machine in order to be able to electrically test an inverter under test according to the operating points of the induction machine. Such a machine emulator consists of a machine model, which calculates the actual machine behavior in real time, and power electronics. This power electronics has the task of setting a previously calculated counter-voltage so that the same currents form at the connections of the machine emulator and at the connections of the inverter to be tested as would occur in the test on an electro-mechanical machine test bench. In this case, the operating behavior of the power electronics used, in particular in the case of clocked operation, should not introduce any disturbances in the form of an additional current fluctuation range into these currents. In the following, the term functional test voltage is used synonymously with the term counter-voltage for the voltage at the connections of the power electronics of the machine emulator during the functional test of an inverter.

Traditional machine emulators often use inverters to operate their power electronics and set the bump test voltage. Various approaches are known for counteracting the clocked mode of operation of these inverters.

In a first approach, the switching frequency of the inverters used is increased in order to achieve a reduction in the additionally introduced, undesired current fluctuation range. An increase in the switching frequency can be achieved by actually increasing the switching operations in the inverter. Another possibility is the parallel operation of several half-bridges in the inverter, which are controlled offset from one another, with an effective switching frequency at the output of the inverter increasing. Increasing the switching frequency can reduce the current fluctuation range, but not eliminate it completely. In addition, an increase in the switching frequency also causes an increase in the switching losses, which are proportional to the selected switching frequency. An increase in switching operations also causes an increase in interference coupling, especially with steep switching edges.

Another approach envisages the use of low-pass filters after the inverters used. The stepped and/or square-wave course of the inverter output voltage caused by the inverters of the power electronics is smoothed in this case. However, this smoothing reduces the frequency bandwidth of the output voltage that can be generated. However, since the desired function test voltage at the connections of the power electronics also exhibits discontinuous behavior such as the stepped and/or square-wave voltage profile at the connection of the inverter under test, simulating the desired function test voltage also requires high-frequency voltage components. However, these high-frequency voltage components can only be set approximately by the smoothed inverter output voltage.

In order to avoid the influence of the clocking mode of operation of an inverter in the power electronics, linear amplifiers without clocking behavior are also used to set the function test voltage. However, the output signal from linear amplifiers is also band-limited, which means that the function test voltage can only be set approximately. Due to the continuous operation of the transistors used, the operation of linear amplifiers is also very lossy and not very efficient, especially in high power classes.

Thus, with the known approaches, it is not even theoretically possible to exactly simulate the induction machine, since the actual function test voltage at the connections of the power electronics cannot be set to the function test voltage previously calculated on the machine model due to influences of the power electronics with increased switching losses, interference couplings and a band limitation .

It is therefore an object of the present invention to provide a function test voltage for the function test of a switchable single-phase or multi-phase inverter, which simulates a calculated function test voltage with high accuracy.

This problem is solved by the subjects of the independent claims. Advantageous embodiments are the subject matter of the dependent claims.

Unless otherwise stated, the term “connect” is always understood to mean an electrical connection in the context of the present description.

One aspect of solving the problem relates to power electronics for the function test of a switchable i-phase inverter with j voltage levels, the power electronics having: i circuit arrangements for generating an i-th function test voltage at an i-th connection of the power electronics; each of the i circuit arrangements being configured to generate n variable, low-pass filtered intermediate voltages which each have a different voltage level and which can each be connected to the i-th connection; and wherein in each case one of the n intermediate voltages is present at the i-th connection of the power electronics; and where i ≥ 1, j ≥ 2, n ≥ 2 and i, j, n ∈ N.

The power electronics offer the advantage that the topology described can be easily and modularly adapted for function tests on a large number of switchable inverters with a different number of phases and voltage stages. Through a two-stage generation of one or more function test voltages in the power electronics, a plurality of low-frequency intermediate voltages of different voltage levels can be generated in a first step per phase, in which the interference of a clocked generation in the circuit arrangements of the power electronics is almost completely eliminated by the use of low-pass filters . In a second step, it is then possible to switch between voltage levels of the intermediate voltages at high frequency per phase in order to be able to simulate the switching behavior of the inverter.

An inverter is always to be understood as an electrical supply device that can be used as an induction machine inverter and/or induction machine control device. Here, i denotes the number of phases of the inverter and the induction machine, j the number of DC voltage stages of the inverter and n the number of counter voltage stages per phase that are required for a machine emulation in order to be able to simulate the switching behavior of the inverter. The number of intermediate voltages in the power electronics depends on the number n of counter-voltage stages.

The inverters that can be tested by the power electronics can be single- or multi-phase. In the case of a single-phase inverter, a connection voltage is generated from a DC voltage, with the inverter switching between at least two DC voltage levels, referred to simply as voltage levels here. However, the connection voltage of the inverter can also be generated by switching between more than two voltage levels. Due to the clocked operation of the inverter, a stepped sinusoidal connection voltage averaged over a pulse period is synthesized using a pulse width modulated square-wave voltage. In this case, the connection voltage consists of a low-frequency, sinusoidal component, which is required to operate a single-phase induction machine, and a high-frequency component, which is introduced as an interference effect through the clocked operation of the inverter. Both frequency components of the connection voltage of the inverter are taken into account by the power electronics during a functional test of the inverter. In the case of a multi-phase inverter, several connection voltages are generated which differ only in terms of a phase shift. The phase shifts add up to 360° when running through all phases of the inverter.

In a function test of the inverter to be tested, the power electronics must first be configured in such a way that the number of power electronics connections at which a function test voltage can be tapped corresponds to the number of phases of the inverter to be tested. In this case, the i-th connection of the power electronics is coupled to an i-th connection of the inverter to be tested. The connections of the power electronics can serve both as an input and as an output during the function test, since the power electronics and the inverter influence each other. A power flow is bidirectional possible.

The i circuit configurations of the power electronics for generating an i-th function test voltage are operated in parallel and, apart from a common DC voltage source, have no influence on one another.

The n variable, low-pass filtered intermediate voltages generated in each of the i circuit arrangements preferably all have an approximately uniform voltage curve of the same frequency and amplitude, which forms a low-frequency component of the intermediate voltage. This portion is required in order to be able to simulate the operation of the induction machine in the i-th function test voltage.

The n intermediate voltages essentially only differ in each case by a different voltage level or a different DC voltage component. The n different DC voltage components form a step function in which, starting from the first intermediate voltage, a DC voltage of approximately the same magnitude is always added at the next intermediate voltage. The maximum difference in the direct voltage component between the first and the nth intermediate voltage is preferably designed such that the maximum interference effect of the high-frequency switching behavior of the inverter to be tested can be simulated in the i-th function test voltage.

The i circuit arrangements are also configured to connect or disconnect each of the n intermediate voltages to the i-th connection of the power electronics, with exactly one of the n intermediate voltages being present at the i-th connection of the power electronics. In this case, the i circuit arrangements are configured in such a way that two or more intermediate voltages are not connected to the i-th connection at the same time. Because exactly one intermediate voltage is present at the i-th connection of the power electronics, the low-frequency component of the intermediate voltages is also always present at the i-th connection of the power electronics, and high-frequency switching between the n intermediate voltages means that the high-frequency switching behavior of the inverter to be tested is in the i-th function test voltage can be simulated.

In a preferred embodiment of the power electronics, each of the i circuit arrangements has: n switchable, single-phase inverters each with a downstream low-pass filter for generating the nth intermediate voltage and n switching devices for isolating and connecting a low-pass filter output of the nth inverter to the i-th connection of power electronics.

In each of the i circuit configurations of the power electronics, the n single-phase inverters in each case work preferably comparable to the inverter of the i-th phase without the downstream low-pass filtering.

In a further preferred embodiment of the power electronics, the number n of intermediate voltages for each of the i circuit arrangements results from the following formula: n=((j-1)*i)+1.

A number n of intermediate voltages according to the above formula offers the possibility of simulating the high-frequency switching behavior of the inverter to be tested in the i-th function test voltage with high accuracy.

In a further preferred embodiment of the power electronics, the number i of phases and the number j of voltage stages of the inverter to be tested is i=3 and j=2, and the number of intermediate voltages n for each of the i circuit arrangements of the power electronics is n=4.

The configuration of power electronics with four intermediate voltages in each of the 3 circuit arrangements covers the important application case in which a three-phase two-level inverter can be functionally tested with the power electronics.

In a further preferred embodiment of the power electronics, the n inverters of the i circuit arrangements can be switched in such a way that the n intermediate voltages generated in each case have an approximately sinusoidal time profile within a first period, the first period corresponding to an electrical period of an induction machine to be emulated during a function test; wherein the respective n switching devices of the i circuit arrangements can be switched in such a way that all n low-pass filter outputs of the n inverters are connected at least once to the i-th connection of the power electronics within a second period, the second period being a switching period of the switchable i-phase under test standing inverter; and wherein the first period is a multiple of the second period.

As with the i phases of the inverter under test, the respective n inverters of the i circuit configurations of the power electronics synthesize a step-shaped sinusoidal voltage averaged over a pulse period using a pulse-width-modulated square wave voltage, which is then filtered through the low-pass filter by the high-frequency interference of the clocked operation of the n inverter is freed. The respective n intermediate voltages of the i circuit configurations of the power electronics generated from the combination of inverter and low-pass filter accordingly have only a low-frequency, sinusoidal component. In order to be able to simulate the i operating voltages of the i-phase induction machine during a function test, all n intermediate voltages of the i circuit arrangements of the power electronics have a corresponding low-frequency. The periods of the low-frequency sinusoidal component of the n intermediate voltages of the i circuit arrangements of the power electronics thus correspond to the electrical periods of an i-phase induction machine to be emulated during a function test.

Since all n low-pass filter outputs of the n inverters are connected at least once to the i-th connection of the power electronics within a switching period of the switchable i-phase inverter to be tested, all high-frequency interference caused by the switching of the inverters can also be simulated with high accuracy, without influencing the low-frequency sinusoidal components of the n intermediate voltages of the i circuit arrangements of the power electronics and thus also the low-frequency sinusoidal component of the i function test voltages.

The switching frequencies of conventional inverters extend over a wide frequency spectrum. In most induction machine inverters, the switching frequency is around 10 kHz, although switching frequencies from 5 kHz to 100 kHz are also used. Inverters with higher switching frequencies of up to 1 MHz are usually not used as machine inverters. The low-frequency component of the function test voltages can be up to around 300 Hz for a very high-speed rotating field machine, which corresponds to a rotation speed of 18,000 rpm for a single-pole ^machine .

In a further preferred embodiment of the power electronics, all i circuit arrangements are operated with a DC voltage source. Additionally or optionally, the respective n inverters of the i circuit arrangements are designed as step-down converters that are operated with MOSFETs. Additionally or optionally, the low-pass filters of the n inverters in each case are designed as passive filters with filter inductance and filter capacitance. Additionally or optionally, the respective n circuit devices of the i circuit arrangements are designed as two bidirectional, anti-parallel MOSFETs.

The use of MOSFETs for switching the step-down converter and the switching devices enables very abrupt switching and thus simulation of discontinuous and/or high-frequency voltage curves. The limit frequencies of the passive low-pass filter result from the maximum rotational speed of the induction machine to be emulated multiplied by the number of pole pairs. The maximum rotational speed of the induction machine to be emulated can thus be used to determine the limit frequency of the low-pass filter.

In a further preferred embodiment of the power electronics, each of the i circuit arrangements has a first freewheeling diode between a first output of the DC voltage source and the i-th connection of the power electronics and a second freewheeling diode between the i-th connection of the power electronics and the second output of the DC voltage source.

A dead time is preferably provided during the switching between the n intermediate voltages of the i circuit arrangements of the power electronics, during which none of the low-pass filter outputs of the n-th inverter is connected to the i-th connection of the power electronics. In this way, short circuits between two intermediate voltage levels can be avoided during the switching process. During these dead times, a connection current can flow at the respective i-th connection, depending on the direction of the current, via the first or via the second freewheeling diode. In order to keep an error in the i function test voltages at the i terminals as small as possible, the dead time is preferably very small. The exact calculation of the dead times to be set depends significantly on the switching on and off behavior of the components used, in particular the switching devices and their switches. This usually results in a customary dead time of about 50 ns to 100 ns and when designed with a sufficiently large tolerance, a dead time of about 1 μs.

A further aspect for solving the problem relates to a machine emulator for emulating an induction machine for functional testing of a switchable i-phase inverter with j voltage levels, the machine emulator having: power electronics according to the first aspect and its preferred embodiments; an emulator unit configured to generate n reference function voltages for the i circuit arrangements, respectively; and a control and/or regulation unit; and wherein the control and/or regulating unit is configured to regulate the n intermediate voltages and switching between the n intermediate voltages of the i circuit arrangements of the power electronics in such a way that function test voltages with the respective n reference function voltages for the i circuit arrangements are applied to the i terminals of the power electronics be generated.

In a preferred embodiment of the machine emulator, the emulator unit has: a model unit for calculating i reference currents in the i phases of the induction machine to be emulated; and a reference value calculation unit for calculating the respective n reference functional voltages for the i circuit arrangements, taking into account the i reference currents calculated in the model unit.

The model unit calculates the electrical and mechanical behavior of the induction machine under test in real time. A linear or a non-linear machine model can be used. Voltages of the inverter under test are measured at its terminals as input signals of the model unit.

In a further preferred embodiment of the machine emulator, each of the i circuit arrangements of the power electronics has: n switchable, single-phase inverters each with a downstream low-pass filter for generating the nth intermediate voltage in each case; and n switching devices for isolating and connecting a low-pass filter output of the n-th inverter to the i-th connection of the power electronics. The open-loop and/or closed-loop control unit has: a voltage regulator for determining n inverter switching signals for the n inverters of the i circuit configurations of the power electronics, taking into account the n reference functional voltages calculated in the reference value calculation unit for the i circuit configurations; and a phase selection unit for determining n switch switching signals for the respective n circuit devices of the i circuit arrangements of the power electronics.

In a further preferred embodiment of the machine emulator, the machine emulator has i coupling inductances which are respectively coupled to the i-th connection of the power electronics and can be coupled to a connection of the i-th phase of the inverter.

In a further preferred embodiment of the machine emulator, the emulator unit takes into account a constant phase resistance, a variable phase inductance and a sinusoidal reverse voltage induced by an electric field of the induction machine to be emulated for each of the i phases.

A further aspect for solving the problem concerns the use of power electronics according to the first aspect and its preferred embodiments in a machine emulator for emulating an induction machine for functional testing of a switchable i-phase inverter with j voltage levels.

A further aspect of solving the problem relates to a method for functional testing of a switchable i-phase inverter with j voltage stages, the method having: providing i circuit arrangements each with an i-th connection, the method having the following steps for each of the i circuit arrangements : generating n variable, low-pass filtered intermediate voltages, each of which has a different voltage level; disconnecting one of the n intermediate voltages from the i th terminal and applying another of the n intermediate voltages to the i th terminal; one of the n intermediate voltages being present at the i-th connection; providing an i-th function test voltage at the i-th connection; where i ≥ 1, j ≥ 2, n ≥ 2 and i, j, n ∈ ℕ.

A further aspect of solving the problem relates to a method for emulating an induction machine for the functional test of a switchable i-phase inverter with j voltage levels, the method having: generating n reference functional voltages for the i circuit configurations based on a machine model; performing the method steps according to the previous aspect; the generation of the n intermediate voltages and the switching between the n intermediate voltages of the i circuit arrangements being controlled in such a way that function test voltages with the respective n reference function voltages for the i circuit arrangements are generated at the i connections of the power electronics.

The statements made above or below regarding the embodiments of the respective other aspects also apply to the above-mentioned aspects and in particular to embodiments that are preferred in this regard.

In the following, individual embodiments for solving the problem are described by way of example with reference to the figures. Some of the individual embodiments described have features that are not absolutely necessary to implement the claimed subject matter, but which provide desired properties in certain applications. Thus, embodiments that do not have all the features of the embodiments described below are also to be regarded as being disclosed as falling under the technical teaching described. Furthermore, in order to avoid unnecessary repetition, certain features are only mentioned in relation to individual embodiments described below. It is pointed out that the individual embodiments should therefore not only be considered individually, but should also be viewed as a whole.

Based on this synopsis, the person skilled in the art will recognize that individual embodiments can also be modified by incorporating individual or multiple features of other embodiments. It is pointed out that a systematic combination of the individual embodiments with individual or multiple features that are described in relation to other embodiments can be desirable and useful and should therefore be considered and should also be regarded as covered by the description.

character list

• 1 shows a schematic representation of an electro-mechanical machine test bench for induction machines compared to a test bench with machine emulation.
• 2 shows a simplified representation of a switching arrangement of a three-phase permanent magnet synchronous machine.
• 3 shows a time course of a reference functional test voltage for a three-phase two-level inverter.
• 4 shows a schematic representation of a four-stage power electronics according to the present invention.
• 5 Figure 12 shows an overview of a configuration for a machine emulator according to the present invention.
• 6 12 shows a block diagram of a reference value calculation unit according to the present invention.
• 7 Figure 12 shows a block diagram of a voltage regulator according to the present invention.
• 8th Figure 12 shows an allocation table for a phase selection unit according to the present invention.
• 9 12 shows a time course of simulation results of a step response according to the present invention.
• 10 shows a time course with a difference representation between reference current and current current according to the present invention.
• 11 12 shows a detailed time history of a machine current and a functional test voltage according to the present invention.
• 12 shows a table for simulation parameters.

Detailed description of the drawings

the 1 shows a schematic representation of an electro-mechanical machine test bench for induction machines in comparison to a test bench with machine emulation. In general, induction machine systems consist of a single-phase or multi-phase inverter 10 with several voltage levels and an electromechanical induction machine 40, which is electrically supplied by the inverter 10. When developing new inverters 10 for induction machine systems, the new inverters 10 must be tested in interaction with existing induction machines 40 . In a conventional electro-mechanical machine test stand, as in the upper part of the 1 shown, the inverter 10 to be tested is connected to an induction machine 30 set under test conditions in the test bench. For this purpose, the induction machine 40 is placed under load test conditions by a load machine 50 during the test bench test. In order to be able to carry out different load scenarios, the load machine 50 is electrically supplied and controlled by a load inverter 60 for this purpose. The induction machine under test 30 is thus composed of the induction machine 40 , the load machine 50 and the load inverter 60 under test stand conditions.

In order to avoid the complex and costly construction of a real electro-mechanical machine test bench, an inverter 10 can be tested, as shown in the lower part of FIG 1 shown, the induction machine under test 30 can be replaced by a machine emulator 20. The machine emulator 20 must simulate the machine behavior under load as precisely as possible in a machine model and also provide power electronics 100, which places the same electrical requirements on the connections of the inverter under test as the real induction machine under test 30.

the 2 shows a simplified representation of a switching arrangement of a three-phase permanent magnet synchronous machine 70 as an example of an induction machine 40. For the three-phase permanent magnet synchronous machine 70 for all three phases, their phase resistances 72, 82, 92, their variable Phase inductances 74, 84, 94 and their reverse voltages U _{ind_1} , U _{ind_2} and U _{ind_3} caused by the electromagnetic fields of the induction machine are taken into account. In the star point of the three phases of the three-phase permanent magnet synchronous machine 70 there is a machine neutral point potential φ*. Due to the switching operation of the inverter under test 10, the input voltages at the three-phase permanent magnet synchronous machine 70 change in steps. As a result, the machine neutral point potential φ* jumps with each switching operation of the inverter 10 and, as a consequence, the voltages across the phase inductances 74, 84, 94 also change in stages. In contrast, the reverse voltages U _{ind_1} , U _{ind_2} and U _{ind_3} caused by the electromagnetic fields of the induction machine change continuously. In order to be able to emulate this behavior, the power electronics 100 of the machine emulator 20 must be able to emulate discontinuous reverse voltages. The number of counter-voltage stages n per phase to be adapted depends on the number of different machine neutral point potentials φ* that occur in a switching period of the inverter 10 . In this case, an increase in the number of phases i and/or voltage stages j of the inverter 10 also causes the number of different machine neutral point potentials φ*. With the increase in different machine neutral point potentials φ*, however, the number n of counter-voltage levels to be adjusted also increases. To a common machine neutral point, the minimum number n of counter-stress levels to be adjusted is calculated as follows: $$\text{n}=\left(\left(\text{j}-1\right)*\text{i}\right)+1$$

the 3 shows an example of a time course of a reference function test voltage for a three-phase two-level inverter 10. According to the above formula, with i=3 and j=2, there is a minimum number of counter-voltage stages to be adapted of n=4. During a switching period duration T _PWM of the inverter 10, a counter-voltage to be emulated, which is referred to below as a reference functional test voltage, registers six discontinuous jumps between four voltage levels. These voltage levels are assigned to the different machine neutral point potentials φ* and the switching states in the inverter 10 respectively. The discontinuous jumps in the course of time of the reference functional test voltage express the sudden voltage changes across the phase inductances 74, 84, 94 of the three-phase permanent magnet synchronous machine 70. The voltage of each of the four voltage levels changes sinusoidally and slowly in relation to the abrupt voltage changes within an electrical period T _el of the induction machine. This sinusoidal curve represents the reverse voltages U _{ind_1} , U _{ind_2} and U _{ind_3} and variable machine inductances. The reference functional test voltage thus has a high-frequency component caused by the switching of the inverter 10 and a low-frequency component given by the induction machine 40 .

the 4 shows a schematic representation of a four-stage power electronics 100 according to the present invention. The four-stage power electronics 100 are designed, which in 3 discussed reference function test voltage for a function test of a three-phase inverter 10 with two voltage levels to emulate as exactly as possible.

The power electronics 100 has three circuit arrangements 110, 210 and 310 connected in parallel to a DC voltage source 102, each of which is connected at its output via the connections 120, 220 and 320 of the power electronics 100 to one of the connections 12, 14, 16 of one of the three phases of the Inverter 10 using coupling chokes 590, 592, 594 can be coupled. Each of the three circuit arrangements 110, 210 and 310 is divided into four parallel paths, each path having an inverter with a downstream low-pass filter and a switching device in series. All four switching devices of the four parallel paths are designed to connect and disconnect the respective path with the respective connections 120, 220 and 320 of the power electronics 100. In this case, only one of the four paths is always connected to one of the connections 120, 220 and 320 via its switching device.

FIG 4 the four paths with the inverters 122, 142, 162 and 182, the low-pass filters 126, 146, 166 and 186 and the switching devices 130, 150, 170 and 190. The inverters 122, 142, 162 and 182 shown are as step-down converters with one each first switches 123, 143, 163 and 183 and a second switch 124, 144, 164 and 184, all switches being MOSFETs (metal-oxide-semiconductor field-effect transistors). The inverters 122, 142, 162 and 182 are each controlled by an inverter switching signal SWR _1.1 , SWR _1.2 , SWR _1.3 , SWR _1.4 . The low-pass filters 126, 146, 166 and 186 of the inverters 122, 142, 162 and 182 are configured as passive low-pass filters consisting of a filter capacitance 127, 147, 167 and 187 and a filter inductance 128, 148, 168 and 188, respectively. The intermediate voltages U _1.1 , U _1.2 , U _1.3 , U _1.4 are present at the outputs of the low-pass filters 126, 146, 166 and 186, across the filter capacitors 127, 147, 167 and 187, and the Intermediate currents I _1.1 , I _1.2 , I _1.3 , I _1.4 . The intermediate voltages U _1.1 , U _1.2 , U _1.3 , U _1.4 have different voltage levels that correspond to the four voltage levels of the reference functional test voltage 3 correspond.

The four inverters 122, 142, 162, 182 use the respective inverter switching signals SWR _1,1 , SWR _1,2 , SWR _1,3 , SWR _1,4 to generate the intermediate voltages U _1,1 , U _1,2 , U _{1 3} , U _1.4 with the four different voltage levels. In this case, the inverters 122, 142, 162, 182 for the intermediate voltages U _1.1 , U _1.2 , U _1.3 , U _1.4 initially only form the low-frequency, sinusoidal component of the reference functional test voltage from the 3 according to which the influence of the reverse voltages U _{ind_1} , U _{ind_2} , U _{ind_3} , the phase resistances 72, 82, 92 and the variable machine inductances from the 2 taken into account. For this reason, the cut-off frequency of the low-pass filters 126, 146, 166, 186 can be set much lower than the switching frequency of the inverter switches 123, 124, 143, 144, 163, 164, 183 and 184 in order to reduce their disturbing influence on the sinusoidal signal to be generated almost completely removed by the low-pass filter. The intermediate voltages U _1,1 , U _1,2 , U _1,3 , U _1,4 smoothed in this way change their voltage value approximately sinusoidally periodically. The frequency to be generated by the inverters 122, 142, 162, 182 results from the rotational speed of the induction machine multiplied by the number of pole pairs and is referred to below as the electrical frequency. The maximum rotational speed of the induction machine and its number of pool pairs can thus be used to determine the limit frequency of the low-pass filters 126, 146, 166, 186.

The intermediate voltages of all four paths of the three circuits 110, 210 and 310 can, as later for the 5 and 7 described, are regulated by a cascaded control circuit with the inverter switching signals SWR _1.1 , SWR _1.2 , SWR _1.3 , SWR _1.4 as a manipulated variable from a voltage regulator 560 in order to compensate for further external interference. The intermediate currents of all four paths of the three circuit arrangements 110, 210 and 310 can also be used as feedback for the control circuit.

Since the intermediate voltages of all four paths of the three circuit arrangements 110, 210 and 310 do not yet have the high-frequency interference of the sudden voltage changes across the phase inductances 74, 84, 94 caused by the switching inverter 10, this interference must be simulated in a second step. The respective switching devices of the four paths of the respective circuit arrangements 110, 210 and 310 are used for this purpose.

FIG 4 one switching device 130, 150, 170, 190 for each of the four paths. The switching devices 130, 150, 170, 190 each have a first switch 131, 151, 171, 191 and a second switch 132, 152, 172, 192, all switches being MOSFETs and the first and second switches being bidirectional and arranged antiparallel. These switching devices 130, 150, 170, 190 allow abrupt switching between the four voltage levels of the intermediate voltages U _1.1 , U _1.2 , U _1.3 , U _1.4 and connecting the respective low-pass filter output to the first terminal 120 of the power electronics. 100. Only one of the four intermediate voltages U _1.1 , U _1.2 , U _1.3 , U _1.4 is always active. This intermediate voltage is present at the first connection 120 of the power electronics 100 and transmits the entire output current. Thus, by abruptly switching between the four voltage levels of the intermediate voltages U _1.1 , U _1.2 , U _1.3 , U _1.4 at the terminal 120 of the power electronics 100, a function test voltage can be generated in which the low-frequency component of each intermediate voltage U _1.1 , U _1.2 , U _1.3 , U _1.4 nor the high-frequency interference of the switching inverter 10 is modulated.

In order to avoid short circuits between voltage levels of two intermediate voltages, a dead time is provided in each case during switching between the intermediate voltages U _1,1 , U _1,2 , U _1,3 , U _1,4 . During these dead times, a connection current can flow at connection 120 of the power electronics via one of the two freewheeling diodes 194 and 196 . The first freewheeling diode 194 is arranged between the positive pole of the direct voltage source 102 and the connection 120 of the power electronics and the second freewheeling diode 196 is arranged between the connection 120 of the power electronics and the negative pole of the direct voltage source 102 . In order to keep an error in the function test voltages at the terminals 120, 220 and 320 as small as possible, the dead time is preferably very small.

the 5 Figure 12 shows an overview of a configuration for a machine emulator 20 in accordance with the present invention. To use the power electronics 100 in a machine emulator 20, first the terminals 12, 14, 16 of the three phases of the inverter 10 from the 1 and 2 each coupled via one of the coupling inductances 590, 592, 594 to the three terminals 120, 220, 320 of the power electronics 100. The power electronics 100 is then controlled and/or regulated by a signal processing system, which calculates the required state variables. In this case, the signal processing system has an emulator unit 500 for emulating a real-time machine model and a control and/or regulating unit 550 for controlling the power electronics 100 .

The emulator unit 500 is divided into a model unit 510 and a reference value calculation unit 520. The model unit 510 calculates in real time the electrical and mechanical behavior of the induction machine under test 30, and thus the electrical and mechanical behavior of the induction machine 40, the load machine 50 and the load machine inverter 60. For the implementation of the model unit 510, a linear or a non-linear machine model can be used. In the following, the model unit 510 takes into account the phase resistances 72, 82, 92, the phase inductances 74, 84, 94 and the reverse voltages U _{ind_1} , U _{ind_2} , U _{ind_3} of the three-phase permanent magnet synchronous machine 70. The voltages U _Mess1 , U _Mess2 , U _Mess3 of the inverter 10 at its connections 12 , 14 , 16 are measured as input signals of the model unit 510 . Regardless of the type of machine model, the model unit 510 calculates the currents in the induction machine under test 30, which are then used as reference currents I _1,ref , I _2,ref , I _3,ref for the entire signal processing system.

The reference value calculation _unit 520 _calculates a reference _{function test voltage U ref_1 ,} U _{ref_2} , U _{ref_3} . In the block diagram of 6 the reference value calculation unit 520 will be described in more detail.

The control and/or regulating unit 550 is divided into a voltage regulator 560 and a phase selection unit 580. The voltage regulator 560 determines the respective inverter switching signals SWR _1.1 , SWR _1.2 , SWR _1.3 , SWR _1.4 of the circuit arrangements 110, 210 and 310. Each path of the circuit arrangements 110, 210 and 310 has an associated voltage regulator which regulates the intermediate voltages U _1.1 , U _1.2 , U _1.3 , U _1.4 of the circuit arrangements 110 , 210 and 310 in each case . The block diagram of such a voltage regulator is in the 7 described.

The phase selection unit 580 determines the respective switch switching signals SC _1,1 , SC _1,2 , SC _1,3 , SC _1,4 of the circuit arrangements 110, 210 and 310 and is 8th described.

$${\text{U}}_{\text{ref\_i}}={\text{U}}_{\text{Mess\_i}}-\text{Lc}\cdot \frac{\text{dIref\_}1}{\text{d}t}$$

the 6 FIG. 5 shows a block diagram of a reference value calculation unit 520 according to the present invention. The reference function test voltages U _{ref_1} , U _{ref_2} , U _{ref_3} result in: $$u_{Mess\_i}-u_{EMu\_i}=Lc\cdot \frac{\mathrm{i.e}Ii}{\text{i.e}t}{\text{with I}}_{\text{i}}={\text{I}}_{\text{ref\_i}}{\text{and U}}_{\text{EMU\_i}}={\text{u}}_{\text{ref\_i}}\text{and i}=\mathrm{1,}\mathrm{2,}3$$

$${\text{u}}_{\text{ref\_i}}={\text{u}}_{\text{Mess\_i}}-\text{<figure-callout id="1" label="Lc ⋅ dIref\_" filenames="DE102020004679A1\_0007.png,DE102020004679A1\_0009.png" state="{{state}}">Lc</figure-callout>}\cdot \frac{\text{dIref\_}}{}\frac{1}{\text{i.e}t}$$

In addition, a proportionally working current regulator 570 with a correction parameter Kcorr can compensate for the difference between the reference currents I _{ref_1} , I _{ref_2} , I _{ref_3} and the measured currents I ₁ , I ₂ , I ₃ . In this case, the current controller 570 does not need an integral element because the system to be controlled already exhibits an integral behavior.

The reference functional test voltages U _{ref_1} , U _{ref_2} , U _{ref_3} each have a discontinuous voltage curve due to the switching inverter 10 and the abrupt curve of the machine neutral point potential φ* caused thereby.

In order to achieve a continuous voltage profile, the reference function test voltage U _{ref_1} , U _{ref_2} , U _{ref_3} of one phase is divided into four reference voltages U _i,1,ref , U _i,2,ref , U _i,3,ref , U _{i, 4,ref} , which are each intended for the four paths of the circuit arrangements 110, 210 and 310. The respective selection of one of the four reference voltages U _1,n,ref , U _2,n,ref , U _3,n,ref depends on the switching state of the inverter 10, with a variable SW having the values 0 to 3 specifying a number of high side MOSFETs of the inverter 10 in a switched state. As a consequence of this, each path of the circuit arrangements 110, 210 and 310 only receives a reference voltage when a corresponding switching state of the inverter 10 is active. As long as the switching state is different, the reference voltage U _1,n,ref , U _2,n,ref , U _3,n,ref remains unchanged. Although the course of the reference voltages U _{ref_1} , U _{ref_2} , U _{ref_3 jumps} discontinuously with six jumps per switching period duration T _PWM of the inverter, the course of the subdivided reference voltages U _1,n,ref , U _2,n,ref , U _3,n changes _,ref relatively slowly with the electrical period duration T _el of the induction machine. Clocked buck converters with low-pass filters can be used to generate these reference voltages U _{1,n,ref ,} U _2,n,ref , U _3,n,ref , and their limit frequency can again be based on the maximum rotational speed of the induction machine and the number of pooled pairs. In theory, if each path had to generate unsteady voltages, the cutoff frequency would be infinite.

the 7 5 shows a block diagram of a voltage regulator 560 according to the present invention. The voltage regulator 560 is designed as a cascaded control system, with the reference voltages U _1.n.ref , U _2,n,ref , U _3,n,ref and the measured intermediate voltages U _1,1 , U _1,2 , U _{1, 3} , U _1,4 serve as input variables in order to generate a reference intermediate current I _1,n,ref , I _2,n,ref , I _3,n,ref of the circuit arrangements 110, 210 and 310, which is fed into the respective filter capacitance 127 , 147, 167, 187 flows. For the calculation who the two setting parameters K ₁ and K ₂ are selected in order to improve the step response of the controller. The controller has a step response of a critically damped low-pass filter. In addition, an integrator with bypass and a time constant T ₁ is configured to avoid drifts for a steady state. The downstream control loop must regulate the intermediate current I _1,n , I _2,n , I _3,n , which flows into the respective filter capacitance 127, 147, 167, 187. Particularly after a switching operation between two paths, the respective filter inductances 128, 148, 168, 188 in a switched-off path continue to drive a current to or from the respective filter capacitance 127, 147, 167, 187. This disturbing current must be compensated for as quickly as possible. In this context, a time-triggered two-point controller is configured to control the capacitance current. The reference intermediate current I _1,n,ref , I _2,n,ref , I _3,n,ref of the circuit arrangements 110, 210 and 310 is in each case compared with the current intermediate current I _1,n , I _2,n , I _{3 ,n} compared. If the reference value is greater than the current value, the high-side MOSFET of the corresponding half-bridge must be in a switched state. Otherwise, the low-side MOSFET of the corresponding half-bridge must be in a switched state. By feeding the current back into the respective filter capacitance 127, 147, 167, 187 instead of the current flow through the respective filter inductances 128, 148, 168, 188, the influence of the output current as a disturbance variable is minimized. In order to limit the switching frequency of the MOSFETs, the desired switching signal is passed to a clocked D flip-flop unit. The trigger frequency should be as high as possible. However, it is limited by the switching speed of the MOSFETs used and their gate drivers. The output signal of the flip-flop unit is the respective current inverter switching signal SWR _i,1 , SWR _1,2 , SWR _1,3 , SWR _1,4 of the circuit arrangements 110, 210 and 310.

the 8th Figure 12 shows an allocation table for a phase selection unit 580 according to the present invention. The phase selection unit 580 counts the number of high-side MOSFETs of the inverter 10 that are in a switched state to determine the variable SW. Based on the assignment table, the phase selection unit 580 generates the switch switching signals SC _1.1 , SC _1.2 , SC _1.3 , SC _1.4 for the respective circuit devices 130, 150, 170, 190 of the circuit arrangements 110, 210 and 310 Path of the respective circuit arrangements 110, 210 and 310 connected to its terminals 120, 220, 320, which provides the currently required function test voltage U _EMU _ ₁ , U _EMU _ ₂ , U _{EMU_3} . In addition, a dead time is configured when switching between two voltage levels in order to avoid compensating currents between the voltage levels.

the 9 until 12 relate to simulation results of the power electronics 100 according to the present invention, the power electronics 100 being configured in such a way to emulate induction machines which are operated by an automotive on-board operating voltage of 12V to 24V and by a three-phase two-level inverter. 12 shows the simulation parameters. The values for the passive filters of the circuit configurations and the coupling inductances were selected in such a way that the deviations between the reference currents and the current currents are as small as possible. The cut-off frequencies of the low-pass ^filters were dimensioned for an induction machine with a maximum rotation speed of 3000 rpm.

the 9 12 shows a time course of simulation results of a step response according to the present invention. The step response can be seen as the time profile of the reference current I _{ref_1} and the current current I ₁ .

the 10 shows a time course with a difference representation between reference current I _{ref_1} and current current I ₁ according to the present invention. Although the currents each have a maximum value of 58 A, the difference between the two currents is less than 0.2 A.

the 11 shows a detailed time course of a machine current I ₁ and a function test voltage U _{EMU_1} according to the present invention. It can be seen here that the machine emulator 20 is also able to simulate the edge steepness of the currents. This is possible because the power electronics 100 is able to follow the reference functional test voltage U _{Ref_1} almost exactly. The four stress levels are also visible over time. Since the reference voltage was calculated according to Equation (3), the simulation shows a serial progression. In this case, the reference current I _{ref_1} cannot be calculated before the function test voltage U _{EMU_1} is calculated and the switching signals are determined. For this reason, the calculation of the reference current I _{ref_1} must be delayed by one cycle of the simulation tool.

the 12 shows a table for simulation parameters to the components of the machine emulator 20 and the inverter to be tested 10 from the indicated simulation from the 9 until 11 to be able to configure.

Reference List

i

Number of phases inverter and induction machine

j

Number of DC voltage steps inverter

n

Number of reverse voltage levels and intermediate voltages per phase

10

i-phase inverter with j voltage levels

12, 14, 16

i-th connection of the inverter

20

machine emulator

30

Three-phase machine under test

40

induction machine

50

load machine

60

load machine inverter

70

i-phase permanent magnet synchronous machine (PMSM)

72, 82, 92

i-th phase resistance,

74, 84, 94

ith phase inductance

100

power electronics

102

DC voltage source

110, 210, 310

i-th circuit arrangement

120, 220, 320

i-th connection of the power electronics

122, 142, 162

nth inverter of the i-th circuit arrangement

182 123, 143, 163

first switch of the nth inverter

183 124, 144, 164

second switch of the nth inverter

184 126, 146, 166

nth low-pass filter of the i-th circuit arrangement

186 127, 147, 167

Filter capacity of the nth low-pass filter

187 128, 148, 168

Filter inductance of the nth low-pass filter

188 130, 150, 170

nth circuit device of the i-th circuit arrangement

190 131, 151, 171

first switch of the nth switching device

191 132, 152, 172

second switch of the nth switching device

192 194

first freewheeling diode of the i-th circuit arrangement

196

first freewheeling diode of the i-th circuit arrangement

500

emulator unit

510

model unit

520

reference value calculation unit

550

Control and/or regulation unit

560

voltage regulator

570

current regulator

580

phase selection unit

590, 592, 594

i-th coupling inductance

Uind_i

i-th return voltage

UEMU_i

i-th function test voltage

URef_i

i-th reference function test voltage

Ui,n

n-th intermediate voltage of the i-th circuit arrangement

Ui,n,ref

nth reference functional voltage of the i-th circuit arrangement

UMess_i

i-th output voltage of the inverter under test

Iref_i

ith reference current

left,n

n-th intermediate current of the i-th circuit arrangement

Ii,n,ref

nth reference intermediate current of the i-th circuit arrangement

SWRi,n

nth inverter switching signal of the i-th circuit arrangement

SCi,n

nth switch switching signal of the ith circuit arrangement

φ*

Machine neutral point potentials

TPWM

Switching period duration of the inverter

phone

electrical period of the induction machine

corr

Correction parameters of the voltage regulator

K1, K2

Adjustment parameters of the voltage regulator

T1

Voltage regulator time constant

Claims (15)

Power electronics (100) for the function test of a switchable i-phase inverter with j voltage stages (10), the power electronics having: i circuit arrangements (110, 210, 310) for generating an i-th function test voltage (U _{EMU_1} , U _{EMU_2} , U _{EMU_3} ) at an i-th connection (120, 220, 320) of the power electronics; wherein each of the i circuit arrangements is configured to generate n variable, low-pass filtered intermediate voltages (U _1,1 , U _1,2 , U _1,3 , U _1,4 ), which each have a different voltage level and which each have the i-th connection are connectable; and wherein in each case one of the n intermediate voltages is present at the i-th connection of the power electronics; and where i ≥ 1, j ≥ 2, n ≥ 2 and i, j, n ∈ ℕ. Power electronics (100) according to claim 1 , each of the i circuit arrangements (110, 210, 310) having: n switchable, single-phase inverters (122, 142, 162, 182) each with a downstream low-pass filter (126, 146, 166, 186) for generating the respective nth intermediate voltage ( _U1,1 , _U1,2 , _U1,3 , _U1,4 ); and n switching devices (130, 150, 170, 190) for isolating and connecting a low-pass filter output of the n-th inverter (122, 142, 162, 182) to the i-th connection (120, 220, 320) of the power electronics. Power electronics (100) according to claim 1 or 2 , where the number n of intermediate voltages (U _1,1 , U _1,2 , U _1,3 , U _1,4 ) for each of the i circuit arrangements (110, 210, 310) results from the following formula: $$\text{n}=\left(\left(\text{j}-1\right)*\text{i}\right)+1.$$

Power electronics (100) according to one of Claims 1 until 3 , where the number i of phases and the number j of voltage stages of the inverter (10) to be tested is i = 3 and j = 2 and the number of intermediate voltages (U _1,1 , U _1,2 , U _1,3 , U _1.4 ) n for each of the i circuit arrangements (110, 210, 310) of the power electronics is n=4. Power electronics (100) according to one of claims 2 until 4 , wherein the n inverters (122, 142, 162, 182) of the i circuit arrangements (110, 210, 310) can be switched in such a way that the n intermediate voltages (U _1,1 , U _1,2 , U _1,3 , U _1.4 ) an approximately sinusoidal time course within having a first period (T _el ), the first period (T _el ) corresponding to an electrical period of an induction machine (30) to be emulated during a function test; wherein the respective n switching devices of the i circuit arrangements (110, 210, 310) can be switched in such a way that all n low-pass filter outputs of the n inverters (122, 142, 162, 182) are connected to the i at least once within a second period (T _PWM ). th terminal (120, 220, 320) of the power electronics are connected, wherein the second period (T _PWM ) corresponds to a switching period of the switchable i-phase inverter (10); and wherein the first period (T _el ) is many times greater than the second period (T _PWM ). Power electronics (100) according to one of claims 2 until 5 , wherein all i circuit arrangements (110, 210, 310) are operated with a DC voltage source (102); and/or wherein the respective n inverters (122, 142, 162, 182) of the i circuit arrangements are designed as step-down converters which are operated with MOSFETs (123, 124; 143, 144; 163, 164); and/or wherein the low-pass filters (126, 146, 166, 186) of the respective n inverters (122, 142, 162, 182) are designed as passive filters with filter inductance (128, 148, 168) and filter capacitance (127, 147, 167). are; and/or wherein the respective n circuit devices (130, 150, 170, 190) of the i circuit arrangements are designed as two bidirectional, anti-parallel MOSFETs (131, 132; 151, 152; 171, 172). Power electronics (100) according to claim 6 , Each of the i circuit arrangements (110, 210, 310) having a first freewheeling diode (194) between a first output of the DC voltage source (102) and the i-th connection (120, 220, 320) of the power electronics and a second freewheeling diode (196) between the i-th connection (120, 220, 320) of the power electronics and the second output of the DC voltage source (102). Machine emulator (20) for emulating an induction machine (30) for functional testing of a switchable i-phase inverter with j voltage stages (10), the machine emulator having: power electronics (100) according to one of Claims 1 until 5 ; an emulator unit (400) configured to generate in each case n reference function voltages (U _1,n,ref , U _2,n,ref , U _3,n,ref ) for the i circuit arrangements (110, 210, 310) of the power electronics; and a control and/or regulation unit (550); wherein the control and/or regulating unit is configured to control the n intermediate voltages (U _1,1 , U _1,2 , U _1,3 , U _1,4 ) and switching between the n intermediate voltages of the i circuit arrangements (110, 210, 310 ) of the power electronics in such a way that function test voltages (U _{EMU_1} , U _EMU _ ₂ , U _{EMU_3} ) with the respective n reference function voltages (U _1,n,ref , U _2,n,ref , U _3,n,ref ) can be generated for the i circuit configurations. Machine emulator (20) after claim 8 , wherein the emulator unit (500) has: a model unit (510) for calculating i reference currents (I _1,ref , I _2,ref , I _3,ref ) in the i phases of the induction machine (30) to be emulated; and a reference value calculation unit (520) for calculating the respective n reference functional voltages (U _1,n,ref , U _2,n,ref , U _3,n,ref ) for the i circuit configurations, taking into account the values stored in the model unit (510 ) calculated i reference currents. Machine emulator (20) after claim 9 , wherein each of the i circuit arrangements (110, 210, 310) of the power electronics (100) has: n switchable, single-phase inverters (122, 142, 162, 182) each with a downstream low-pass filter (126, 146, 166, 186) for generating the each nth intermediate voltage (U _1.1 , U _1.2 , U _1.3 , U _1.4 ); and n switching devices (130, 150, 170, 190) for isolating and connecting a low-pass filter output of the n-th inverter to the i-th connection (120, 220, 320) of the power electronics; and wherein the control and/or regulation unit (550) has: a voltage regulator (560) for determining n inverter switching signals (SWR _1.1 , SWR _1.2 , SWR _1.3 , SWR _1.4 ) for the respective n inverters the i circuit configurations of the power electronics including the respective n reference functional voltages (U _1,n,ref , U _2,n,ref , U _3,n,ref ) calculated in the reference value calculation unit (520) for the i circuit configurations; and a phase selection unit (580) for determining n switch switching signals (SC _1,1 , SC _1,2 , SC _1,3 , SC _1,4 ) for the respective n circuit devices of the i circuit arrangements of the power electronics. Machine emulator (20) according to one of Claims 8 until 10 , wherein the machine emulator has i coupling inductances (590, 592, 594), which are respectively connected to the i-th connection (120, 220, 320) of the circuit Device electronics coupled and at a terminal of the i-th phase (12, 14, 16) of the inverter (10) can be coupled. Machine emulator (20) according to one of Claims 8 until 11 , The emulator unit (500) each having a constant phase resistance (72, 82, 92), a variable phase inductance (74, 84, 94) and a sinusoidal reverse voltage (U _{ind_1} , U _{ind_2} , U _{ind_3} ) induced by an electric field of the to emulating induction machine (30) for each of the i phases. Use of power electronics (100) according to one of Claims 1 until 5 in a machine emulator (20) for emulating an induction machine (30) for functional testing of a switchable i-phase inverter with j voltage stages (10). Method for functional testing of a switchable i-phase inverter with j voltage levels (10), the method comprising: providing i circuit arrangements (110, 210, 310) each with an i-th connection (120, 220, 320), the method has the following steps for each of the i switching arrangements: generating n variable, low-pass filtered intermediate voltages (U _1,1 , U _1,2 , U _1,3 , U _1,4 ) which each have a different voltage level; disconnecting one of the n intermediate voltages from the i th terminal and applying another of the n intermediate voltages to the i th terminal; one of the n intermediate voltages being present at the i-th connection; Providing in each case an i-th function test voltage (U _{EMU_1} , U _{EMU_2} , U _{EMU_3} ) at the i-th connection; where i ≥ 1, j ≥ 2, n ≥ 2 and i,j, n ∈ ℕ. Method for emulating an induction machine (30) for the function test of a switchable i-phase inverter with j voltage stages (10), the method having: generating n reference function voltages (U _1,n,ref , U _2,n,ref , U _3,n,ref ) for the i circuit arrangements (110, 210, 310) based on a machine model; Carrying out the procedural steps Claim 14 ; wherein the generation of the n intermediate voltages (U _1,1 , U _1,2 , U _1,3 , U _1,4 ) and the switching between the n intermediate voltages of the i circuit arrangements (110, 210, 310) is regulated in such a way that on the i connections (120, 220, 320) of the power electronics function test voltages (U _{EMU_1} , U _{EMU_2} , U _{EMU_3} ) with the respective n reference function voltages (U _1,n,ref , U _2,n,ref , U _{3,n, ref} ) can be generated for the i circuit arrangements.

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