DE102019135821A1 - SEMICONDUCTOR ENCLOSURE WITH HEAT SINK - Google Patents

Abstract

In one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, a semiconductor die bonded to the second surface of the substrate, and a molding encapsulating the semiconductor die and a majority of the substrate, wherein at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of the preliminary U.S. Patent Application No. 62 / 811,147 , filed on February 27, 2019, and taking advantage of non-provisional U.S. Patent Application No. 16 / 506,405 , filed on July 9, 2019, which the priority and benefit of the preliminary U.S. Patent Application No. 62 / 811,147 claimed, the respective contents of which are incorporated herein by reference in their entirety.

TECHNICAL AREA

This description relates to a semiconductor housing with a heat sink.

BACKGROUND

Conventional semiconductor packages can use relatively long wires to connect between various components in the package. These conventional semiconductor packages can suffer from relatively high resistance and inductance losses, and the heat generated in these wires can be relatively high.

SHORT VERSION

In one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, a semiconductor chip bonded to the second surface of the substrate, and a molded part encapsulating the semiconductor chip and a majority of the substrate, wherein at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink.

In some aspects, the semiconductor package includes one or more of the following features (or any combination thereof). The semiconductor package may include a metal trace coupled to the first surface of the substrate, and at least a portion of the metal trace is exposed through the molding. The substrate can include a via extending between the first surface and the second surface. The semiconductor package may include a first leadframe section coupled to the second surface of the substrate and a second leadframe section coupled to the second surface of the substrate, the semiconductor chip being disposed between the first leadframe section and the second leadframe section. In some examples, the semiconductor die is a first semiconductor die, and the semiconductor package further includes a second semiconductor die coupled to the second surface of the substrate and a third semiconductor die coupled to the second surface of the substrate. The semiconductor package may include a first metal line coupled to the second surface of the substrate and a second metal line coupled to the first metal line, wherein the semiconductor chip is coupled to the second metal line. The semiconductor package may include a passive component coupled to the substrate and a metal trace coupled to the second surface of the substrate, the passive component coupled to the metal trace. The semiconductor package may include a leadframe section coupled to the substrate and a passive component coupled to the leadframe section.

In one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, a leadframe portion coupled to the substrate, a first metal trace coupled to the first surface of the substrate, at least one second metal trace, coupled to the second surface of the substrate, a semiconductor chip coupled to at least one second metal trace and a molding encapsulating the semiconductor chips and a majority of the substrate, at least a portion of the first metal trace being exposed by the molding so that the substrate is configured to function as a heat sink.

In some aspects, the semiconductor package may include one or more of the above / below features (or any combination thereof). The substrate includes a via that connects the leadframe section to the first metal track. The at least one second metal track can include two stacked metal tracks. The semiconductor package may include a capacitor coupled to the leadframe portion or the substrate. The semiconductor chip may be a first semiconductor chip, wherein the semiconductor package further includes a second semiconductor chip that is coupled to at least one second metal line and a third semiconductor chip that is coupled to at least one second metal line. The first semiconductor chip can be a low-side semiconductor chip, the second semiconductor chip can be a high-side semiconductor chip, and the third semiconductor chip can be an integrated driver circuit (IC) chip.

In one aspect, a semiconductor package includes a substrate having a first surface and a second surface opposite the first surface, and the substrate has a via extending between the first surface and the second surface. The semiconductor package includes a leadframe section that is coupled to the second surface of the substrate, a metal track that is coupled to the first surface of the substrate, wherein the via connects the metal track to the leadframe section, a high-side semiconductor chip that is connected to the second Surface of the substrate is coupled, a lowside semiconductor chip that is coupled to the second surface of the substrate, and a molded part that encapsulates the semiconductor chip and a majority of the substrate, wherein at least a portion of the metal track is exposed by the molded part, so that the Substrate is configured to function as a heat sink.

In some aspects, the semiconductor package includes one or more of the above / below features (or any combination thereof). The semiconductor package may include a first passive component coupled to the substrate and a second passive component coupled to the substrate. The semiconductor package may include an integrated driver circuit (IC) chip coupled to the second surface of the substrate. The high-side semiconductor chip and the low-side semiconductor chip can be coupled to the second surface of the substrate via a second metal line and a third metal line, and the driver IC chip can be coupled to the second surface of the substrate via the second metal line but not the third metal line be coupled.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings and from the claims.

Figure list

• 1 Fig. 10 illustrates a semiconductor package in accordance with one aspect.
• 2A to 2H illustrate a semiconductor package in accordance with another aspect.
• FIGS. 3A and 3B illustrate the exposure of a substrate through a molded part of a semiconductor package in accordance with one aspect.
• 4A and 4B illustrate a semiconductor package in accordance with another aspect.
• 5A and 5B illustrate a semiconductor package in accordance with another aspect.
• 6A and 6B illustrate a semiconductor package in accordance with another aspect.
• 7A to 7C illustrate a semiconductor package in accordance with another aspect.
• 8A and 8B illustrate a semiconductor package in accordance with another aspect.
• 9A and 9B illustrate a semiconductor package in accordance with another aspect.
• 10A to 10C illustrate a semiconductor package in accordance with another aspect.
• 11 Fig. 10 illustrates a semiconductor package in accordance with another aspect.
• 12 Fig. 10 illustrates a semiconductor package in accordance with another aspect.
• 13 Fig. 10 illustrates a semiconductor package in accordance with another aspect.
• 14th Fig. 10 illustrates a semiconductor package in accordance with another aspect.
• 15th Fig. 10 illustrates a semiconductor package in accordance with another aspect.
• 16 Fig. 10 illustrates a semiconductor package in accordance with another aspect.
• 17th Fig. 10 illustrates a semiconductor package in accordance with another aspect.
• 18th Fig. 10 illustrates a semiconductor package in accordance with another aspect.

DETAILED DESCRIPTION

The present disclosure relates to a semiconductor package having a substrate (e.g. a ceramic substrate) in which a portion of the surface of the substrate is exposed by a molded part so that the substrate can be used as a heat sink for one or more heat-generating (e.g. active) Components of the case works. The substrate includes a first surface and a second surface, and one or more semiconductor chips are coupled to the second surface of the substrate via one or more redistribution layers (e.g. metal traces). In some examples, a redistribution layer is coupled to the first surface of the substrate and at least a portion of the redistribution layer is exposed on the first surface through the molding. In some examples, the redistribution layer is solder plated on the first surface. The semiconductor package discussed herein can increase the resistance and inductance of the Reduce interconnects for at least some of the components of the housing and may provide an exit path for heat generated when the semiconductor housing is activated.

1 Fig. 11 illustrates a semiconductor package 100 according to one aspect. The semiconductor package 100 may reduce the resistance and inductance of the interconnectors for at least some of the components of the housing, and may provide a pathway for exhausting heat generated when the semiconductor package 100 is activated.

For example, the semiconductor package closes 100 a substrate 102 that is configured to function as a heat sink by adding at least a portion of the substrate 102 through a molded part 112 exposed, a. In some examples the substrate closes 102 insert a ceramic insert, and the ceramic insert is configured to function as a heat dissipating material. In some examples, when a portion of the substrate 102 through the molding 112 is exposed, a heat dissipation path can be provided through the substrate 102 which allows the release of heat by heat generating components associated with the substrate 102 are coupled. In some examples, the dielectric material becomes a first surface 105 of the substrate 102 through the molding 112 exposed on the outside of the housing. In some examples, a metal track 114 (e.g. a redistribution layer) with the first surface 105 of the substrate 102 coupled, and at least a portion of the metal web 114 is through the molding 112 exposed on the outside of the housing. In some examples, exposing the metal path 114 through the molding 112 allow the substrate 102 works as a heat sink to remove heat from the semiconductor package 100 to release. In some examples, exposing the metal path 114 through the molding 112 in connection with a via 125 that stretch through the substrate 102 extends, the substrate 102 allow to act as a heat sink to remove heat from the semiconductor package 100 to release. In some examples, the connection may be the via 125 with a leadframe section 140 (which is thereby connected to one or more heat-generating components via one or more redistribution layers) allow the substrate 102 works as a heat sink to remove heat from the semiconductor package 100 to release.

In some examples, the metal track is 114 solder-plated. For example, solder plating on the metal track may be used during the lead completion process 114 to be deposited. In some examples, the solderable is exposed metal trace 114 configured to be connected to another heat sink. In some examples, the first surface 105 of the substrate 102 or the metal track 114 by grinding along the molding 112 exposed to the metal track 114 or the first surface 105 of the substrate 102 to expose. In some examples there is a recess in the molding 112 formed to at least a portion of the first surface 105 or the metal track 114 to expose.

The molding 112 encapsulates at least a large part (for example, greater than 50%, greater than 75%, greater than 85% or greater than 90%) of the components of the semiconductor housing 100 in terms of the surface area of components passing through the molding 112 are covered, opposite the surface of components that are not covered by the molding 112 are covered. In some examples, the molded part encapsulates 112 all components of the semiconductor package 100 except for a portion of the substrate 102 (and the lines that extend from the molding 112 from extend). In some examples the molding closes 112 an inorganic material. In some examples the molding closes 112 an organic material. In some examples the molding closes 112 a combination of one or more organic materials and / or one or more inorganic materials. In some examples the molding closes 112 an epoxy material formed from epoxy resins. In some examples the molding closes 112 a gel material (e.g., silicone gel).

The semiconductor package 100 closes a semiconductor chip 104 that with a second surface 107 of the substrate 102 is coupled, a. In some examples, the semiconductor chip is 104 with the second surface 107 coupled via one or more redistribution layers (e.g. one metal track or two or more metal tracks). In some examples, the semiconductor chip is 104 with a redistribution layer on the second surface 107 Coupled (e.g. soldered) via one or more conductive components (e.g. pillars, humps, etc.). In some examples, the semiconductor chip is 104 in a flip chip configuration with the substrate 102 coupled. In some examples, the semiconductor chip closes 104 a transistor (e.g. bipolar transistor, field effect transistor, metal-oxide-semiconductor field effect transistor (MOSFET)). In some examples, the semiconductor chip closes 104 one or more integrated circuits (ICs). In some examples, the semiconductor chip closes 104 a field effect transistor (FET). In some examples, the semiconductor chip closes 104 a gallium nitride low-side or high-side semiconductor chip (GaN low-side or high-side semiconductor chip). In some examples, the semiconductor chip closes 104 a driver IC chip. In some examples, there are multiple semiconductor chips with the second surface 107 of the substrate coupled.

The semiconductor package 100 closes a leadframe section 140 and a leadframe section 142 a. The leadframe section 140 and the leadframe section 142 are with the second surface 107 of the substrate 102 coupled. In some examples, the leadframe section is 140 and the leadframe section 142 with the second surface 107 of the substrate coupled via one or more redistribution layers.

In some examples, the substrate closes the via 125 that stretch through the substrate 102 extends, a. In some examples, the substrate closes multiple vias 125 a. In some examples the via is 125 a hole with metal filling. In some examples the via is 125 a copper filled hole that allows the metal track 114 is solder plated. In some examples the via is 125 with the leadframe section 140 coupled. The via 125 can the metal track 114 with the leadframe section 140 connect, thereby enabling a current path during electrolytic solder plating. In some examples, the metal track creates 114 , the via 125 and the connection of the via 125 with the leadframe section 140 (and the exposure of at least a portion of the metal track 114 through the molding 112 ) a heat dissipation path that allows the heat to escape from the semiconductor package 100 leaks to help prevent the semiconductor package from falling 100 overheating and possibly causing damage to its components.

2A Fig. 11 illustrates a semiconductor package 200 according to one aspect. 2 B Figure 11 illustrates a cross-sectional view of the semiconductor package 200 along the line 201 according to one aspect of the invention. 2C Figure 11 illustrates a cross-sectional view of the semiconductor package 200 along the line 203 according to one aspect of the invention. 2D Figure 3 illustrates an isometric top view of the semiconductor package 200 according to one aspect. 2E Fig. 13 illustrates a package construction view of the semiconductor package 200 according to one aspect. 2F Figure 3 illustrates a bottom isometric view of the semiconductor package 200 according to one aspect. 2G Figure 13 illustrates an isometric top view of the semiconductor package 200 according to one aspect. 2H Figure 11 illustrates a cross-sectional view of the semiconductor package 200 according to one aspect. In some examples, the semiconductor package closes 200 a two-sided molded part and a four-sided housing formed by lines.

The semiconductor package 200 can reduce the resistance and inductance of the interconnectors for at least some of the components of the housing, and can provide a pathway for exhausting heat generated when the semiconductor housing 200 is activated. For example, the semiconductor package closes 200 a substrate 202 one that is configured to function as a heat sink by adding at least a portion of the substrate 202 through a molded part 212 exposed. In some examples, the dielectric material becomes a surface of the substrate 202 through the molding 212 exposed on the outside of the housing. In some examples, a redistribution layer (e.g., a metal track or copper metal track) is applied to the surface of the substrate 202 coupled, and at least a portion of the redistribution layer is through the molding 212 exposed on the outside of the case, as in 2G shown. In some examples, the redistribution layer is solder plated. For example, a solder plating can be deposited on the redistribution layer during the line completion process. In some examples, the surface of the substrate 202 by grinding along the molding 212 exposed to expose at least a portion of the surface or the redistribution layer. In some examples, a recess is made in the molded part 212 formed to expose at least a portion of the surface or the redistribution layer.

The semiconductor package 200 closes the substrate 202 , a first semiconductor chip 204 , a second semiconductor chip 206 and a third semiconductor chip 208 a. In some examples, the first are semiconductor chips 204 , the second semiconductor chip 206 and the third semiconductor chip 208 the active components within the semiconductor package 200 .

In some examples, the first semiconductor chip closes 204 a low-side semiconductor power device. In some examples, the first semiconductor chip closes 204 a transistor (e.g. bipolar transistor, field effect transistor, metal-oxide-semiconductor field effect transistor (MOSFET)). In some examples, the first semiconductor chip closes 204 one or more integrated circuits (ICs). In some examples, the first semiconductor chip closes 204 a field effect transistor (FET). In some examples, the first semiconductor chip closes 204 a gallium nitride lowside semiconductor chip (GaN lowside semiconductor chip).

In some examples, the second semiconductor chip closes 206 a high-side semiconductor power device. In some examples, the second semiconductor chip closes 206 a transistor (e.g. bipolar transistor, field effect transistor, metal-oxide-semiconductor field effect transistor (MOSFET)). In some examples, the second semiconductor chip closes 206 one or more ICs. In some examples, the second semiconductor chip closes 206 a field effect transistor (FET). In some examples, the second semiconductor chip closes 206 a gallium nitride lowside semiconductor chip (GaN lowside semiconductor chip). In some examples, the third semiconductor chip closes 208 a driver IC chip. In some examples, the third semiconductor chip closes 208 a transistor (e.g. bipolar transistor, field effect transistor, metal-oxide-semiconductor field effect transistor (MOSFET)). In some examples, the third semiconductor chip closes 208 one or more ICs. In some examples this takes Semiconductor package 200 the first semiconductor chip 204 and the second semiconductor chip 206 at an insulation gap that is compatible for 650V-800V or a higher nominal insulation voltage (e.g. greater than 800V).

The molding 212 encapsulates at least a large part of the components of the semiconductor package 200 a. In some examples, the molded part encapsulates 212 all components of the semiconductor package 200 except for a portion of the substrate 202 (and the lines that extend from the molding 212 from extend). In some examples the molding closes 212 an inorganic material. In some examples the molding closes 212 an organic material. In some examples the molding closes 212 a combination of one or more organic materials and / or one or more inorganic materials. In some examples the molding closes 212 an epoxy material formed from epoxy resins. In some examples the molding closes 212 a gel material (e.g., silicone gel).

The first semiconductor chip 204 , the second semiconductor chip 206 and the third semiconductor chip 208 are with the substrate 202 coupled. In some examples, the semiconductor package closes 200 one or more passive components 210 that with the substrate 202 are coupled, a. A passive component 210 can be any type of device that does not generate energy but can store or divert energy. In some examples the passive components close 210 Capacitors on. In some examples the passive components close 210 Resistors, inductors and / or transformers.

The semiconductor package 200 closes a leadframe that has multiple lines like a first line 230-1 , a second line 230-2 , a third line 230-3 , a fourth line 230-4 , a fifth line 230-5 , a sixth line 230-6 , a seventh line 230-7 , an eighth line 230-8 , a ninth line 230-9 , a tenth line 230-10 , an eleventh line 230-11 , a twelfth line 230-12 , and a thirteenth line 230 -13 defined, a. A section of the lines can be viewed as a leadframe section. In some examples, the semiconductor package closes 200 less than thirteen lines one. In some examples, the semiconductor package closes 200 more than thirteen lines one. The lines can be the external contacts, pins or inputs / outputs (I / O) for connecting the semiconductor package 200 Define with one or more external components. In some examples, the semiconductor package closes 200 Link bar components attached to the corner portions of the semiconductor package 200 are arranged as a first connecting rail 232-1 , a second connecting bar 232-2 , a third connecting bar 232-3 and a fourth connecting bar 232-4 , a. The connecting rails (e.g. 232-1 , 232-2 , 232-3 and 232-4 ) are between the corners of a die attach block 211 and attached to the leadframe, and may partially form dam rails that hold the leads spaced apart at desired intervals during the package molding process.

Each of the conduits can be any type of conduit that is used in a housing structure. In some examples, the conduits include one or more curved or bent portions extending from the molding 212 from extend, a. In some examples, the first line is 230-1 one line for input voltage (VIN). In some examples, the second line is 230-2 a line for the switch (SW). In some examples, the third line is 230-3 one line for high supply voltage (VDDH). In some examples, the fourth line is 230-4 a line for booting (BOOT). In some examples, the fifth line is 230-5 one line for the ground circuit breaker (PGND). In some examples it is the sixth line 230-6 one line for low supply voltage (VDDL). In some examples, this is the seventh line 230-7 one line for contactless contact (NC). In some examples, the eighth line is 230-8 one line for activation. In some examples, the ninth line is 230-9 one line for the lowside input (LIN). In some examples, the tenth line is 230-10 one line for the highside input (HIN). In some examples, the eleventh line is 230-11 a DT line. In some examples, the twelfth line is 230-12 one line for signal ground (SGND). In some examples, the thirteenth line is 230-13 one line for power supply (VDD).

The substrate 202 includes a dielectric material. In some examples, the substrate is 202 a ceramic substrate. The substrate 202 closes a first surface 205 and a second surface 207 that the first surface 205 opposite, a. In some examples this is the first surface 205 and the second surface 207 planar or substantially planar. In some examples, the first surface 205 considered a top surface. In some examples, the first is surface 205 the surface covered by the molding 212 is exposed. In some examples, the second surface 207 considered a lower surface. In some examples, the second surface is 207 the surface that adjoins the leadframe sections and / or the first semiconductor chip 204 , the second semiconductor chip 206 and the third semiconductor chip 208 is appropriate. The distance between the first surface 205 and the second surface 207 can be a thickness of the substrate 202 define. In some examples, the thickness of the substrate is 202 in a range of 15 to 100 mils. In some examples the thickness of the substrate is 202 at least 15 mils. In some examples, the thickness of the substrate is 202 under 15 mil.

As in 2 B and 2F shown are the first semiconductor chip 204 and the third semiconductor chip 208 with the second surface 207 of the substrate 202 coupled. Also, as in 2C , 2F and 2H shown the second semiconductor chip 206 and the passive components 210 with the second surface 207 of the substrate 202 coupled. In some examples, the first are semiconductor chips 204 , the second semiconductor chip 206 and the third semiconductor chip 208 with the second surface 207 of the substrate 202 coupled in a flip-chip configuration.

In some examples, there are three redistribution layers (e.g., metal traces) with the substrate 202 coupled (or formed thereon), which include a top redistribution layer that is connected to the first surface 205 of the substrate 202 coupled a first lower redistribution layer to the second surface 207 of the substrate 202 and a second lower redistribution layer coupled to the first lower redistribution layer. In some examples, there are two redistribution layers with the substrate 202 coupled (e.g. an upper redistribution layer is omitted). In some examples, a redistribution layer is with the substrate 202 coupled (e.g. the upper redistribution layer and the second lower redistribution layer are omitted). The first semiconductor chip 204 , the second semiconductor chip 206 , the third semiconductor chip 208 and the passive components 210 are each connected to the first lower redistribution layer and / or the second lower redistribution layer.

A first metal track is more precise 214 (e.g. the upper redistribution layer) with the first surface 205 of the substrate 202 coupled. In some examples, the first is metal track 214 directly with the first surface 205 of the substrate 202 coupled. In some examples, the first is metal track 214 a copper metal track. As in 2D shown, at least a portion of the first metal web 214 through the molding 212 be exposed. In some examples, an entire outside of the first metal sheet becomes 214 through the molding 212 exposed.

A second metal track 216 (e.g. the first lower redistribution layer) is with the second surface 207 of the substrate 202 coupled. In some examples, the second is metal track 216 directly to the second surface 207 of the substrate 202 coupled. In some examples, the second is metal track 216 a copper metal track. As in 2 B shown is the third semiconductor chip 208 with the second metal track 216 coupled. In some examples, the third is semiconductor chip 208 with the second metal track 216 soldered. In some examples, the third is semiconductor chip 208 via one or more conductive components (e.g. bumps, pillars, etc.) to the second metal track 216 connected. A third metal track 218 (e.g. the second lower redistribution layer) is associated with sections of the second metal web 216 coupled. In some examples, the third is metal track 218 directly with sections of the second metal track 216 coupled. In some examples, the third is metal track 218 a copper metal track. In some examples, the third metal track 218 as a spacer underneath the folded over chips (e.g. the first semiconductor chip 204 , of the second semiconductor chip 206 ) act as a suitable mold filling. In some examples, the third metal track 218 Provide the correct Z-height spacing to meet the isolation requirement and for the stack assembly when connected to the leadframe.

In some examples, the first is semiconductor chip 204 with the third metal track 218 connected. In some examples, the first is semiconductor chip 204 with the third metal track 218 soldered. In some examples, the first is semiconductor chip 204 via one or more conductive components (e.g. bumps, pillars, etc.) to the third metal track 218 connected. In some examples, the second is semiconductor chip 206 with the third metal track 218 connected. In some examples, the second is semiconductor chip 206 with the third metal track 218 soldered. In some examples, the second is semiconductor chip 206 via one or more conductive components (e.g. bumps, pillars, etc.) to the third metal track 218 connected.

As in 2 B shown is a leadframe section 220 with the third metal track 218 connected, and a leadframe section 222 is with the third metal track 218 connected. In some examples, the leadframe section is 220 a section of the first line 230-1 (e.g. VIN line), and the leadframe section 222 is a section of the twelfth line 230-12 (e.g. SGND line).

As in 2C shown are a leadframe section 224 , a passive component 210 , a leadframe section 226 and a leadframe section 228 with the substrate 202 over at least either the second metal track 216 or the third metal track 218 coupled. In some examples, the leadframe section is 224 with the third metal track 218 connected. For example, the second metal track 216 and the third metal track 218 between the leadframe section 226 and the substrate 202 arranged, and the leadframe section 224 is directly with the third metal track 218 connected. In other examples, the second is metal track 216 between the leadframe section 226 and the substrate 202 arranged (e.g. not the third metal track 218 ). In some Examples is the leadframe section 224 a section of the fifth line 230-5 (e.g. PGND line).

In some examples the component is passive 210 with the substrate 202 glued. In some examples the component is passive 210 is with the second metal track 216 connected. For example, the second is metal track 216 between the passive components 210 and the substrate 202 arranged. In some examples, the leadframe section is 226 with the third metal track 218 connected. In some examples, the second are metal tracks 216 and the third metal track 218 between the leadframe section 226 and the substrate 202 arranged. In some examples, the leadframe section is 226 a section of the sixth line 230-6 (e.g. VDDL line). In some examples, the leadframe section is 228 with the third metal track 218 connected. For example are the second metal track 216 and the third metal track 218 between the leadframe section 228 and the substrate 202 arranged. In some examples, the leadframe section is 228 a section of the seventh line 230-7 (e.g. NC line).

As in the 2C and 2F shown closes the substrate 202 a via 225 one that extends through the substrate 202 extends. In some examples the substrate closes 202 multiple vias 225 a. In some examples the via is 225 a hole with metal filling. In some examples the via is 225 a copper-filled via that allows the first metal track 214 is solder plated. In some examples the via is 225 with the leadframe section 228 coupled. The via 225 can the first metal track 214 with the leadframe section 228 connect, thereby enabling a current path during electrolytic solder plating. The via 225 can spread through the substrate 202 between the first metal track 214 and the second metal track 216 at a point near the leadframe section 228 extend out. In some examples, the leadframe section is 228 as discussed above, part of the NC line. In some examples it can be the via 225 allow the first metal track 214 is solder plated. For example, if there is space for an NC line, the NC line can be used as an interconnection with the first metal track 214 used by the via 225 passes through. Therefore, the solder plating onto the first metal track can be done during the wire completion process 214 to be deposited. In some examples, the NC line can optionally be soldered as a stub on a printed circuit board (PCB).

3A and 3B illustrate the semiconductor package 200 with top cooling options in accordance with one aspect. The semiconductor package 200 from 3A and 3B may include any of the features discussed with reference to the previous figures. For example, the first is metal track 214 with the first surface 205 of the substrate 202 coupled, and the leadframe section 224 , the second semiconductor chip 206 , the first semiconductor chip 204 , the leadframe section 220 are with the second surface 207 of the substrate 202 coupled (e.g. via the second metal track 216 and the third metal track 218 ).

In 3A is the top surface of the molding in some examples 212 to expose the first metal track 214 ground. In this example is the top surface of the molding 212 adjacent and substantially coplanar with the top surface of the first metal track 214 . In some examples, the entire top surface of the first metal track becomes 214 through the molding 212 exposed. In 3B is a recess in the molded part 212 formed to the first metal track 214 to expose. In some examples, a portion of the first metal sheet 214 through the molding 212 exposed, and a portion of the first metal sheet 214 through the molding 212 covered. In some examples, with reference to 3B , is the top surface of the first metal track 214 below the top surface of the molding 212 arranged.

4A and 4B illustrate a semiconductor package 400 that the semiconductor package 200 from 2A to 3B is similar except that a seventh line 430 - 7th (e.g. the NC cable) is cut off (e.g. hanging freely on the side of the housing). 4A Figure 13 illustrates a perspective view of the semiconductor package 400 according to one aspect. 4B Figure 11 illustrates a cross section of the semiconductor package 400 along the line 403 , according to one aspect. 4A and 4B illustrate an example of an isolated solderable heat sink. The semiconductor package 400 may include any of the features discussed with reference to the preceding figures.

For example, the semiconductor package closes 400 a substrate 402 , a first semiconductor chip 404 , a second semiconductor chip 406 , a third semiconductor chip 408 , passive components 410 , a first metal track 414 , a second metal track 416 , and a third metal track 418 a. The semiconductor package 400 includes a molding 412 one that includes all the components of the semiconductor package 400 encapsulated except for a portion of the substrate 402 and the portions of conduits extending from the molding 412 extend out. The semiconductor package 400 closes a leadframe that has multiple lines like a first line 430-1 , a second line 430-2 , a third line 430-3 , a fourth line 430-4 , a fifth line 430-5 , one sixth line 430-6 , a seventh line 430-7 , an eighth line 430-8 , a ninth line 430-9 , a tenth line 430-10 , an eleventh line 430-11 , a twelfth line 430-12 , and a thirteenth line 430-13 defined, a.

As in 4B shown are a leadframe section 424 , a passive component 410 , a leadframe section 426 and a leadframe section 428 with the substrate 402 over at least either the second metal track 416 or the third metal track 418 coupled. In some examples, the leadframe section is 424 a section of the fifth line 430-5 (e.g. the PGND line). In some examples, the leadframe section is 426 a section of the sixth line 430-6 (e.g. VDDL line). In some examples, the leadframe section is 428 a section of the seventh line 430-7 (e.g. NC line).

As in 4B shown closes the substrate 402 a via 425 one that extends through the substrate 402 extends. In some examples the via is 425 a copper-filled via that allows the first metal track 414 is solder plated. For example, if there is space for an NC line, the NC line can be used as an interconnection with the first metal track 414 used by the via 425 passes through. Therefore, solder plating on the first metal trace can occur during the lead completion process 414 to be deposited. In some examples, as in 4A shown is the seventh line 430-7 (e.g. NC cable) cut off (e.g. freely hanging on the housing side).

5A and 5B illustrate a semiconductor package 500 that the semiconductor package 200 from 2A to 3B is similar or the semiconductor package 400 from 4A and 4B with the exception that a neutral line (e.g. an eighth line 530-8 (e.g. EN line)) as an electrolytic conduction path to a first metal track 514 is used. In the example of 2A to 3B becomes the seventh line 230-7 (e.g. NC line) as the electrolytic conduction path to the first metal track 214 used. In the example of 4A and 4B becomes the seventh line 430-7 (e.g. the NC line) as the electrolytic conduction path to the first metal track 414 used, but the seventh line 430-7 is shorter than the seventh line 230-7 from 2A to 3B . In the example of 5A to 5B becomes the eighth line 530-8 (e.g. EN line) as the electrolytic conduction path to the first metal track 514 used.

5A Figure 13 illustrates a perspective view of the semiconductor package 500 according to one aspect. 5B Figure 11 illustrates a cross section of the semiconductor package 500 along the line 503 , according to one aspect. 5A and 5B illustrate an example of an isolated solderable heat sink. The semiconductor package 500 may include any of the features discussed with reference to the preceding figures.

For example, the semiconductor package closes 500 a substrate 502 , a first semiconductor chip 504 , a second semiconductor chip 506 , a third semiconductor chip 508 , passive components 510 , the first metal track 514 , a second metal track 516 , and a third metal track 518 a. The semiconductor package 500 includes a molding 512 one that covers most of the components of the semiconductor package 500 encapsulated except for a portion of the substrate 502 and the portions of conduits extending from the molding 512 extend out. The semiconductor package 500 closes a leadframe that has multiple lines like a first line 530-1 , a second line 530-2 , a third line 530-3 , a fourth line 530-4 , a fifth line 530-5 , a sixth line 530-6 , a seventh line 530-7 , the eighth line 530-8 , a ninth line 530-9 , a tenth line 530-10 , an eleventh line 530-11 , a twelfth line 530-12 and a thirteenth line 530-13 defined, a.

As in 5B shown are a leadframe section 524 , a passive component 510 and a leadframe section 527 with the substrate 502 over at least either the second metal track 516 or the third metal track 518 coupled. In some examples, the leadframe section is 524 a section of the fifth line 530-5 (e.g. PGND line). In some examples, the leadframe section is 527 a section of the eighth line 530-8 (e.g. EN line).

As in 5B shown closes the substrate 502 a via 525 that stretch through the substrate 502 extends, a. In some examples the via is 525 a copper-filled via that allows the first metal track 514 is solder plated. For example, if there is not enough space for a stub (or non-functional (NC) line), a neutral I / O line can be used as an electrolytic conduction path to the first metal track 514 (through the via 525 ) be used. In some examples, the EN line can be considered neutral with respect to the PGND line, the VIN line, and the SW line and therefore cannot have any creepage restrictions.

6A and 6B illustrate a semiconductor package 600 that the semiconductor package 200 from 2A to 3B is similar, the semiconductor package 400 from 4A and 4B , or the semiconductor package 500 from 5A and 5B with the exception that a connecting rail (e.g. a third connecting rail 632-3 ) as an electrolytic conduction path to a first metal track 614 is used. 6A Figure 13 illustrates a perspective view of the semiconductor package 600 according to one aspect. 6B Figure 11 illustrates a cross section of the semiconductor package 600 along the line 603 , according to one aspect. 6A and 6B illustrate an example of an isolated solderable heat sink. The semiconductor package 600 may include any of the features discussed with reference to the preceding figures.

For example, the semiconductor package closes 600 a substrate 602 , a first semiconductor chip 604 , a second semiconductor chip 606 , a third semiconductor chip 608 , passive components 610 , a first metal track 614 , a second metal track 616 , a third metal track 618 and a molding 612 a. The semiconductor package 600 closes a leadframe that has multiple lines like a first line 630-1 , a second line 630-2 , a third line 630-3 , a fourth line 630-4 , a fifth line 630-5 , a sixth line 630-6 , a seventh line 630-7 , an eighth line 630-8 , a ninth line 630-9 , a tenth line 630-10 , an eleventh line 630-11 , a twelfth line 630-12 and a thirteenth line 630-13 defined, a. In some examples, the semiconductor package closes 600 Link bar components attached to the corner portions of the semiconductor package 600 are arranged as a first connecting rail 632-1 , a second connecting bar 632-2 , the third connecting bar 632-3 and a fourth connecting bar 632-4 a.

As in 6B shown are a leadframe section 624 , a passive component 610 , a leadframe section 626 , a leadframe section 628 and a connecting rail section 629 with the substrate 602 over at least either the second metal track 616 or the third metal track 618 coupled. In some examples, the leadframe section is 624 a section of the fifth line 630-5 (e.g. PGND line). In some examples, the leadframe section is 626 a section of the sixth line 630-6 (e.g. VDDL line). In some examples, the leadframe section is 628 a section of the seventh line 630-7 (e.g. NC line). In some examples, the connecting rail section is 629 a portion of the third link rail 632-3 .

As in 6B shown closes the substrate 602 a via 625 that stretch through the substrate 602 extends, a. In some examples the via is 625 a copper-filled via that allows the first metal track 614 is solder plated. For example, if there is neither enough space for a stub line (non-functional line (NC line)) nor for a neutral I / O line, the corner isolation connecting bar (e.g. the third connecting bar 632-3 ) as an electrolytic conduction path to the first metal track 614 (through the via 625 ) to be used.

7A , 7B and 7C illustrate a semiconductor package 700 having an exposed substrate configured as a heat sink and flat leads extending from the housing. In some examples, the semiconductor package 700 useful when there is a Z-height restriction on board mounting. In some examples, the semiconductor package closes 700 a one-sided molded part with flat cables. Although the semiconductor package 700 the lines illustrated on four sides can be the semiconductor package 700 Include lines on only two sides. The semiconductor package 700 may include any of the features discussed with reference to the preceding figures.

7A Figure 13 illustrates a perspective view of the semiconductor package 700 according to one aspect. 7B Figure 11 illustrates a cross section of the semiconductor package 700 along the line 701 , according to one aspect. 7C Figure 11 illustrates a cross section of the semiconductor package 700 along the line 703 , according to one aspect.

The semiconductor package 700 includes a substrate 702 , a first semiconductor chip 704 , a second semiconductor chip 706 and a third semiconductor chip 708 a. In some examples, the first semiconductor chip closes 704 a low-side semiconductor power device. In some examples, the second semiconductor chip closes 706 a high-side semiconductor power device. The semiconductor package 700 includes a molding 712 that includes at least a majority of the components of the semiconductor package 700 encapsulated, a. In some examples, the molded part encapsulates 712 all components of the semiconductor package 700 except for a portion of the substrate 702 and the portions of conduits extending from the molding 712 extend out.

The first semiconductor chip 704 , the second semiconductor chip 706 and the third semiconductor chip 708 are with the substrate 702 coupled. In some examples, the semiconductor package closes 700 one or more passive components 710 that with the substrate 702 are coupled, a. In some examples the passive components close 710 Capacitors on. In some examples the passive components close 710 Resistors, inductors and / or transformers.

The semiconductor package 700 closes a leadframe that has multiple lines like a first line 730-1 , a second line 730-2 , a third line 730-3 , a fourth line 730-4, a fifth management 730-5 , a sixth line 730-6 , a seventh line 730-7 , an eighth line 730-8 , a ninth line 730-9 , a tenth line 730-10 , an eleventh line 730-11 , a twelfth line 730-12 and a thirteenth line 730-13 defined, a. A section of the lines can be viewed as a leadframe section. In some examples, the semiconductor package closes 700 less than thirteen lines one. In some examples, the semiconductor package closes 700 more than thirteen lines one. The lines can be the external contacts, pins or inputs / outputs (I / O) for connecting the semiconductor package 700 define with one or more external devices. In some examples, the semiconductor package closes 700 Link rail components as shown in the previous figures.

Each of the conduits can be any type of conduit that is used in a housing structure. In some examples, these are the sections of conduits that extend from the molding 712 extending, planar or flat (e.g. substantially free of curvature). In some examples, the first line is 730-1 the VIN line, the second line 730-2 the SW line, the third line 730-3 the VDDH line, the fourth line 730-4 the BOOT line, the fifth line 730-5 is the dimension of the PGND line, the sixth line 730-6 the VDDH line, the seventh line 730-7 the NC line, the eighth line 730-8 EN line, the ninth line 730-9 the LIN line, the tenth line 730-10 the HIV line, the eleventh line 730-11 the DT line, the twelfth line 730-12 the SGND line and the thirteenth line 730-13 the VDD line.

The substrate 702 includes a dielectric material. In some examples, the substrate is 702 a ceramic substrate. The substrate 702 closes a first surface 705 and a second surface 707 one that is the first surface 705 opposite. In some examples this is the first surface 705 and the second surface 707 planar or substantially planar. In some examples, the first surface 705 considered a top surface. In some examples, the first is surface 705 the surface covered by the molding 712 is exposed. In some examples, the second surface 707 considered a lower surface. In some examples, the second surface is 707 the surface on the leadframe sections and / or the first semiconductor chip 704 , the second semiconductor chip 706 and the third semiconductor chip 708 is appropriate. The distance between the first surface 705 and the second surface 707 can be a thickness of the substrate 702 define. In some examples, the thickness of the substrate is 702 in a range of 15 to 100 mils. In some examples the thickness of the substrate is 702 at least 15 mils. In some examples, the thickness of the substrate is 702 under 15 mil.

As in 7B shown are the first semiconductor chip 704 and the third semiconductor chip 708 with the second surface 707 of the substrate 702 coupled. Also, as in 7C shown the second semiconductor chip 706 and the passive components 710 with the second surface 707 of the substrate 702 coupled. In some examples, the first are semiconductor chips 704 , the second semiconductor chip 706 and the third semiconductor chip 708 with the second surface 707 of the substrate 702 coupled in a flip-chip configuration.

In some examples, there are three redistribution layers (e.g., metal traces) with the substrate 702 coupled (or formed thereon), which include a top redistribution layer that is connected to the first surface 705 of the substrate 702 coupled a first lower redistribution layer to the second surface 707 of the substrate 702 and a second lower redistribution layer coupled to the first lower redistribution layer. In some examples, there are two redistribution layers with the substrate 702 coupled (e.g. an upper redistribution layer omitted). In some examples, a redistribution layer is with the substrate 702 coupled (e.g. the upper redistribution layer and the second lower redistribution layer omitted). The first semiconductor chip 704 , the second semiconductor chip 706 , the third semiconductor chip 708 and the passive components 710 are each connected to the first lower redistribution layer and / or the second lower redistribution layer.

A first metal track is more precise 714 (e.g. the upper redistribution layer) with the first surface 705 of the substrate 702 coupled. In some examples, the first is metal track 714 directly with the first surface 705 of the substrate 702 coupled. In some examples, the first is metal track 714 a copper metal track. At least a portion of the first metal sheet 714 can through the molding 712 be exposed. In some examples, an entire outer surface of the first metal sheet becomes 714 through the molding 712 exposed.

A second metal track 716 (e.g. the first lower redistribution layer) is with the second surface 707 of the substrate 702 coupled. In some examples, the second is metal track 716 directly to the second surface 707 of the substrate 702 coupled. In some examples, the second is metal track 716 a copper metal track. As in 7B shown is the third semiconductor chip 708 with the second metal track 716 connected. In some examples, the third is semiconductor chip 708 with the second metal track 716 soldered. In some examples, the third semiconductor chip 708 via one or more conductive components (e.g. bumps, pillars, etc.) to the second metal track 716 connected. A third metal track 718 (e.g. the second lower redistribution layer) is associated with sections of the second metal web 716 coupled. In some examples, the third is metal track 718 directly with sections of the second metal track 716 coupled. In some examples, the third is metal track 718 a copper metal track. In some examples, the third metal track 718 as a spacer beneath the flip chip (e.g. the first semiconductor chip 704 , of the second semiconductor chip 706 ) serve as a suitable mold filling. In some examples, the third metal track 718 provide the correct Z-height spacing to meet the isolation requirement and for the stacked assembly to provide when connected to the leadframe.

In some examples, the first is semiconductor chip 704 with the third metal track 718 connected. In some examples, the first is semiconductor chip 704 with the third metal track 718 soldered. In some examples, the first is semiconductor chip 704 via one or more conductive components (e.g. bumps, pillars, etc.) to the third metal track 718 connected. In some examples, the second is semiconductor chip 706 with the third metal track 718 connected. In some examples, the second is semiconductor chip 706 with the third metal track 718 soldered. In some examples, the second is semiconductor chip 706 via one or more conductive components (e.g. bumps, pillars, etc.) to the third metal track 718 connected.

As in 7B shown is a leadframe section 720 with the third metal track 718 connected, and a leadframe section 722 is with the third metal track 718 connected. In some examples, the leadframe section is 720 a section of the first line 730 - 1 (e.g. VIN line), and the leadframe section 722 is a section of the twelfth line 730-12 (e.g. SGND line).

As in 7C shown are a leadframe section 740 , passive components 710 , the second semiconductor chip 706 , the first semiconductor chip 704 , and a leadframe section 742 to the substrate 702 over at least the second metal track 716 or the third metal track 718 coupled. In some examples, the leadframe section is 740 with the third metal track 718 connected. In some examples, the leadframe section is 740 a section of the fifth line 730-5 (e.g. the PGND line). In some examples the components are passive 710 with the second surface 707 of the substrate 702 connected. In some examples the components are passive 710 with the second metal track 716 connected. In some examples, the leadframe section is 742 with the third metal track 718 connected. In some examples, the leadframe section is 742 a section of the second line 730 - 2 (e.g. the software management).

8A and 8B illustrate a semiconductor package 800 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 800 can only include lines on two sides. The semiconductor package 800 may include any of the features discussed with reference to the preceding figures. The semiconductor package 800 may be similar to the semiconductor package discussed above, except that passive components 810 are coupled to the leadframe on one side, which is a substrate 802 opposite, and the leads on two sides of the semiconductor package 800 are included.

8A Figure 13 illustrates a perspective view of the semiconductor package 800 according to one aspect. 8B Figure 11 illustrates a cross section of the semiconductor package 800 along the line 801 , according to one aspect. The semiconductor package 800 closes the substrate 802 , a first semiconductor chip 804 , a second semiconductor chip 806 and a third semiconductor chip 808 a. In some examples, the first semiconductor chip closes 804 a low-side semiconductor power device. In some examples, the second semiconductor chip closes 806 a high-side semiconductor power device. The semiconductor package 800 includes a molding 812 that includes at least a majority of the components of the semiconductor package 800 encapsulated, a. In some examples, the molded part encapsulates 812 all components of the semiconductor package 800 except for a portion of the substrate 802 and the portions of conduits extending from the molding 812 extend out.

The semiconductor package 800 closes a leadframe that has multiple lines like a first line 830-1 (e.g. the VIN line), a second line 830-2 (e.g. SW line), a third line 830-3 (e.g. the VDDH line), a fourth line 830-4 (e.g. the BOOT line), a fifth line 830-5 (e.g. the PGND line), a sixth line 830-6 (e.g. the VDDL line), a seventh line 830-7 (e.g. the NC line), an eighth line 830-8 (e.g. EN line), a ninth line 830-9 (e.g. LIN line), a tenth line 830-10 (e.g. the HIV line), an eleventh line 830-11 (e.g. the DT line), a twelfth line 830-12 (e.g. the SGND line) and a thirteenth line 830-13 (e.g. the VDD line). A section of the lines can be viewed as a leadframe section. In some examples, the semiconductor package closes 800 less than thirteen lines one. In some examples, the semiconductor package closes 800 more than thirteen lines one. The lines can be the outer contacts, pins or inputs / outputs (I / O) for connecting the semiconductor housing 800 define with one or more external devices. In some examples, the semiconductor package closes 800 Link rail components as shown in the previous figures.

The substrate 802 includes a dielectric material. In some examples, the substrate is 802 a ceramic substrate. The substrate 802 closes a first surface 805 and a second surface 807 one that is the first surface 805 opposite. In some examples this is the first surface 805 and the second surface 807 planar or substantially planar. In some examples, the first surface 805 considered a top surface. In some examples, the first is surface 805 the surface covered by the molding 812 is exposed. In some examples, the second surface 807 considered a lower surface. In some examples, the second surface is 807 the surface on the leadframe sections and / or the first semiconductor chip 804 , the second semiconductor chip 806 and the third semiconductor chip 808 is appropriate. The distance between the first surface 805 and the second surface 807 can be a thickness of the substrate 802 define. In some examples, the thickness of the substrate is 802 in a range of 15 to 100 mils. In some examples the thickness of the substrate is 802 at least 15 mils. In some examples, the thickness of the substrate is 802 under 15 mil.

As in 8B shown are the first semiconductor chip 804 and the second semiconductor chip 806 with the second surface 807 of the substrate 802 coupled. The third semiconductor chip 808 is also with the second surface 807 of the substrate 802 coupled. In some examples, the first are semiconductor chips 804 , the second semiconductor chip 806 and the third semiconductor chip 808 with the second surface 807 of the substrate 802 coupled in a flip-chip configuration.

In some examples, there are three redistribution layers (e.g., metal traces) with the substrate 802 coupled (or formed thereon), which include a top redistribution layer that is connected to the first surface 805 of the substrate 802 coupled a first lower redistribution layer to the second surface 807 of the substrate 802 and a second lower redistribution layer coupled to the first lower redistribution layer. In some examples, there are two redistribution layers with the substrate 802 coupled (e.g. an upper redistribution layer is omitted, as in 8B shown). In some examples, a redistribution layer is with the substrate 802 coupled (e.g. the upper redistribution layer and the second lower redistribution layer are omitted). The first semiconductor chip 804 , the second semiconductor chip 806 and the third semiconductor chip 808 are each connected to the first lower redistribution layer and / or the second lower redistribution layer.

More specifically, a first metal track (e.g. the upper redistribution layer) (in 8B not shown) with the first surface 805 of the substrate 802 coupled. In some examples, the first metal track is directly with the first surface 805 of the substrate 802 coupled. In some examples, the first metal track is a copper metal track. At least a portion of the first metal web can pass through the molded part 812 be exposed. In some examples, an entire outer surface of the first metal sheet is covered by the molding 812 exposed.

A second metal track 816 (e.g. the first lower redistribution layer) is with the second surface 807 of the substrate 802 coupled. In some examples, the second is metal track 816 directly to the second surface 807 of the substrate 802 coupled. In some examples, the second is metal track 816 a copper metal track. In some examples, the third is semiconductor chip 808 with the second metal track 816 connected. A third metal track 818 (e.g. the second lower redistribution layer) is associated with sections of the second metal web 816 coupled. In some examples, the third is metal track 818 directly with sections of the second metal track 816 coupled. In some examples, the third is metal track 818 a copper metal track. In some examples, the first is semiconductor chip 804 with the third metal track 818 connected. In some examples, the second is semiconductor chip 806 with the third metal track 818 connected.

As in 8B shown is a leadframe section 820 with the third metal track 818 connected, and a leadframe section 822 is with the third metal track 818 connected. In some examples, the leadframe section is 820 a section of the sixth line 830 - 6th (e.g. VDDL line), and the leadframe section 822 is a section of the third line 830 - 3 (e.g. VDDH line). The passive components 810 are coupled to the leadframe (on a surface opposite the substrate 802 ). For example, a passive component 810 with the leadframe section 820 be coupled and another passive component 810 can with the leadframe section 822 be coupled.

9A and 9B illustrate a semiconductor package 900 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 900 can only include lines on two sides. The semiconductor package 900 may include any of the features discussed with reference to the preceding figures. The semiconductor package 900 can use the previously discussed semiconductor packages be similar except that passive components 910 are coupled to the leadframe, adjacent and on the same side as a substrate 902 .

9A Figure 13 illustrates a perspective view of the semiconductor package 900 according to one aspect. 9B Figure 11 illustrates a cross section of the semiconductor package 900 along the line 901 , according to one aspect. The semiconductor package 900 closes the substrate 902 , a first semiconductor chip 904 , a second semiconductor chip 906 and a third semiconductor chip 908 a. In some examples, the first semiconductor chip closes 904 a low-side semiconductor power device. In some examples, the second semiconductor chip closes 906 a high-side semiconductor power device. The semiconductor package 900 includes a molding 912 that includes at least a majority of the components of the semiconductor package 900 encapsulated, a. In some examples, the molded part encapsulates 912 all components of the semiconductor package 900 except for a portion of the substrate 902 and the portions of conduits extending from the molding 912 extend out.

The semiconductor package 900 closes a leadframe that has multiple lines like a first line 930-1 (e.g. the VIN line), a second line 930-2 (e.g. SW line), a third line 930-3 (e.g. the VDDH line), a fourth line 930-4 (e.g. the BOOT line), a fifth line 930-5 (e.g. the PGND line), a sixth line 930-6 (e.g. the VDDL line), a seventh line 930-7 (e.g. the NC line), an eighth line 930-8 (e.g. EN line), a ninth line 930-9 (e.g. LIN line), a tenth line 930-10 (e.g. the HIV line), an eleventh line 930-11 (e.g. the DT line), a twelfth line 930-12 (e.g. the SGND line) and a thirteenth line 930-13 (e.g. the VDD line). A section of the lines can be viewed as a leadframe section. In some examples, the semiconductor package closes 900 less than thirteen lines one. In some examples, the semiconductor package closes 900 more than thirteen lines one. The lines can be the external contacts, pins or inputs / outputs (I / O) for connecting the semiconductor package 900 define with one or more external devices. In some examples, the semiconductor package closes 900 Connecting rail components as shown in the previous figures.

The substrate 902 includes a dielectric material. In some examples, the substrate is 902 a ceramic substrate. The substrate 902 closes a first surface 905 and a second surface 907 one that is the first surface 905 opposite. In some examples this is the first surface 905 and the second surface 907 planar or substantially planar. In some examples, the first surface 905 considered a top surface. In some examples, the first is surface 905 the surface covered by the molding 912 is exposed. In some examples, the second surface 907 considered a lower surface. In some examples, the second surface is 907 the surface on the leadframe sections and / or the first semiconductor chip 904 , the second semiconductor chip 906 and the third semiconductor chip 908 is appropriate. The distance between the first surface 905 and the second surface 907 can be a thickness of the substrate 902 define. In some examples, the thickness of the substrate is 902 in a range of 15 to 100 mils. In some examples the thickness of the substrate is 902 at least 15 mils. In some examples, the thickness of the substrate is 902 under 15 mil.

As in 9B shown are the first semiconductor chip 904 and the second semiconductor chip 906 with the second surface 907 of the substrate 902 coupled. The third semiconductor chip 908 is also with the second surface 907 of the substrate 902 coupled. In some examples, the first are semiconductor chips 904 , the second semiconductor chip 906 and the third semiconductor chip 908 with the second surface 907 of the substrate 902 coupled in a flip-chip configuration.

In some examples, there are three redistribution layers (e.g., metal traces) with the substrate 902 coupled (or formed thereon), which include a top redistribution layer that is connected to the first surface 905 of the substrate 902 coupled a first lower redistribution layer to the second surface 907 of the substrate 902 and a second lower redistribution layer coupled to the first lower redistribution layer. In some examples, there are two redistribution layers with the substrate 902 coupled (e.g. an upper redistribution layer is omitted, as in 9B shown). In some examples, a redistribution layer is with the substrate 902 coupled (e.g. the upper redistribution layer and the second lower redistribution layer are omitted). The first semiconductor chip 904 , the second semiconductor chip 906 and the third semiconductor chip 908 are each connected to the first lower redistribution layer and / or the second lower redistribution layer.

More specifically, a first metal track (e.g. the upper redistribution layer) (in 9B not shown) with the first surface 905 of the substrate 902 coupled. In some examples, the first metal track is directly with the first surface 905 of the substrate 902 coupled. In some examples, the first metal track is a copper metal track. At least a portion of the first metal web can through the Molding 912 be exposed. In some examples, an entire exterior of the first metal sheet is passed through the molding 912 exposed.

A second metal track 916 (e.g. the first lower redistribution layer) is with the second surface 907 of the substrate 902 coupled. In some examples, the second is metal track 916 directly to the second surface 907 of the substrate 902 coupled. In some examples, the second is metal track 916 a copper metal track. In some examples, the third is semiconductor chip 908 with the second metal track 916 connected. A third metal track 918 (e.g. the second lower redistribution layer) is associated with sections of the second metal web 916 coupled. In some examples, the third is metal track 918 directly with sections of the second metal track 916 coupled. In some examples, the third is metal track 918 a copper metal track. In some examples, the first is semiconductor chip 904 with the third metal track 918 connected. In some examples, the second is semiconductor chip 906 with the third metal track 918 connected.

As in 9B shown is a leadframe section 920 with the third metal track 918 connected, and a leadframe section 922 is with the third metal track 918 connected. In some examples, the leadframe section is 920 a section of the sixth line 930-6 (e.g. VDDL line) and the lead frame section 922 is a section of the third line 930-3 (e.g. VDDH line). The passive components 910 are adjacent to the leadframe (e.g. on the top of the leadframe and on the same side as the substrate 902 coupled. For example, a passive component 910 with the leadframe section 920 be coupled, and another passive component 910 can with the leadframe section 922 be coupled.

10A and 10B illustrate a semiconductor package 1000 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1000 can only include lines on two sides. The semiconductor package 1000 may include any of the features discussed with reference to the preceding figures. The semiconductor package 1000 can the semiconductor package 800 of the 8A and 8B be similar except that bond wires 1060 used to make one or more sections of a third semiconductor chip 1008 to connect with one or more leadframe sections. For example, instead of redirecting the redistribution layer to the other side of the substrate 1002 the semiconductor package 100 one or more bond wires 1060 use to address potential I / O conflicts.

10A Figure 13 illustrates a perspective view of the semiconductor package 1000 according to one aspect. 10B Figure 11 illustrates a cross section of the semiconductor package 1000 along the line 1001 , according to one aspect. 10C Figure 11 illustrates a cross section of the semiconductor package 100 along the line 1003 , according to one aspect.

The semiconductor package 1000 closes the substrate 1002 , a first semiconductor chip 1004 , a second semiconductor chip 1006 and the third semiconductor chip 1008 a. In some examples, the first semiconductor chip closes 1004 a low-side semiconductor power device. In some examples, the second semiconductor chip closes 1006 a high-side semiconductor power device. The semiconductor package 1000 includes a molding 1012 that includes at least a majority of the components of the semiconductor package 1000 encapsulated, a. In some examples, the molded part encapsulates 1012 all components of the semiconductor package 1000 except for a portion of the substrate 1002 and the portions of conduits extending from the molding 1012 extend out.

The semiconductor package 1000 closes a leadframe that has multiple lines like a first line 1030-1 (e.g. the VIN line), a second line 1030-2 (e.g. SW line), a third line 1030-3 (e.g. the VDDH line), a fourth line 1030-4 (e.g. the BOOT line), a fifth line 1030-5 (e.g. the PGND line), a sixth line 1030-6 (e.g. the VDDL line), a seventh line 1030-7 (e.g. the NC line), an eighth line 1030-8 (e.g. EN line), a ninth line 1030-9 (e.g. LIN line), a tenth line 1030-10 (e.g. the HIV line), an eleventh line 1030-11 (e.g. the DT line), a twelfth line 1030-12 (e.g. the SGND line) and a thirteenth line 1030-13 (e.g. the VDD line). A section of the lines can be viewed as a leadframe section. In some examples, the semiconductor package closes 1000 less than thirteen lines one. In some examples, the semiconductor package closes 1000 more than thirteen lines one. The lines can be the external contacts, pins or inputs / outputs (I / O) for connecting the semiconductor package 1000 define with one or more external devices. In some examples, the semiconductor package closes 1000 Link rail components as shown in the previous figures.

The substrate 1002 includes a dielectric material. In some examples, the substrate is 1002 a ceramic substrate. The substrate 1002 closes a first surface 1005 and a second surface 1007 one that is the first surface 1005 opposite. In some examples this is the first surface 1005 and the second surface 1007 planar or substantially planar. In some examples, the first surface 1005 considered a top surface. In some examples, the first is surface 1005 the surface covered by the molding 1012 is exposed. In some examples, the second surface 1007 considered a lower surface. In some examples, the second surface is 1007 the surface on the leadframe sections and / or the first semiconductor chip 1004 , the second semiconductor chip 1006 and the third semiconductor chip 1008 is appropriate. The distance between the first surface 1005 and the second surface 1007 can be a thickness of the substrate 1002 define. In some examples, the thickness of the substrate is 1002 in a range of 15 to 100 mils. In some examples the thickness of the substrate is 1002 at least 15 mils. In some examples, the thickness of the substrate is 1002 under 15 mil.

As in 10B shown are the first semiconductor chip 1004 and the second semiconductor chip 1006 with the second surface 1007 of the substrate 1002 coupled. The third semiconductor chip 1008 , as in 10C shown is also with the second surface 1007 of the substrate 1002 coupled. In some examples, the first are semiconductor chips 1004 , the second semiconductor chip 1006 and the third semiconductor chip 1008 with the second surface 1007 of the substrate 1002 coupled in a flip-chip configuration.

As in 10B shown is a leadframe section 1020 with the substrate 1002 connected, and a leadframe section 1022 is with the substrate 1002 connected. In some examples, the leadframe section is 1020 a section of the sixth line 1030 - 6th (e.g. VDDL line), and the leadframe section 1022 is a section of the third line 1030 - 3 (e.g. VDDH line). The passive components 1010 are coupled to the leadframe (on a surface opposite the substrate 1002 ). For example, a passive component 1010 with the leadframe section 1020 be coupled, and another passive component 1010 can with the leadframe section 1022 be coupled. As in 10C shown are a leadframe section 1040 and a leadframe section 1042 coupled to the substrate, and a bond wire 1060 is with the leadframe section 1042 and the substrate 1002 connected.

In some examples, there are three redistribution layers (e.g., metal traces) with the substrate 1002 coupled (or formed thereon), which include a top redistribution layer that is connected to the first surface 1005 of the substrate 1002 coupled a first lower redistribution layer to the second surface 1007 of the substrate 1002 and a second lower redistribution layer coupled to the first lower redistribution layer. In some examples, there are two redistribution layers with the substrate 1002 coupled (e.g. an upper redistribution layer is omitted, as in 10B shown). In some examples, a redistribution layer is with the substrate 1002 coupled (e.g. the upper redistribution layer and the second lower redistribution layer are omitted). The first semiconductor chip 1004 , the second semiconductor chip 1006 and the third semiconductor chip 1008 are each connected to the first lower redistribution layer and / or the second lower redistribution layer.

11 to 18th illustrate dual cooling techniques for each of the semiconductor packages discussed above, in accordance with one aspect. The semiconductor package of the 11 to 18th may include any of the features discussed with reference to the preceding figures.

11 Fig. 11 illustrates a semiconductor package 1100 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1100 includes a substrate 1102 with a first surface 1105 and a second surface 1107 a. The semiconductor package 1100 includes a molding 1112 one that is configured to house all of the components of the semiconductor package 1100 except for a portion of the substrate 1102 (e.g. the top surface of the substrate 1102 ) and the sections of ducts that extend from the molding 1112 from extend to encapsulate. With reference to 11 becomes the top surface of the molding 1112 sanded to the first surface 1105 of the substrate 1102 (e.g. the bare ceramic). In some examples, the entire top surface of the substrate is used 1102 through the molding 1112 exposed.

The semiconductor package 1100 includes a first semiconductor chip 1104 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1106 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1100 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1100 passive components 1110 (e.g. capacitors). The first semiconductor chip 1104 and the second semiconductor chip 1106 are connected to the substrate via one or more redistribution layers 1102 coupled. In some examples, the first surface has 1105 of the substrate 1102 no redistribution layer (e.g. the bare ceramic is exposed).

With reference to 11 can be a leadframe section 1140 , the first semiconductor chip 1104 , the second semiconductor chip 1106 and a leadframe section 1142 with the second surface 1107 of the substrate 1102 be coupled. Of the Leadframe section 1140 and the leadframe section 1142 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1110 can be coupled to the leadframe on one side that is the substrate 1102 opposite. For example, in the passive component 1110 with the leadframe section 1140 (on one of the substrate 1102 opposite position) and another passive element 1110 can with the leadframe section 1142 (on one of the substrate 1102 opposite position).

12 Fig. 11 illustrates a semiconductor package 1200 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1200 includes a substrate 1202 with a first surface 1205 and a second surface 1207 a.

The semiconductor package 1200 closes a metal track 1214 (e.g. an upper redistribution layer) that is connected to the first surface 1205 is coupled, a. The semiconductor package 1200 includes a molding 1212 one that is configured to house all of the components of the semiconductor package 1200 except for a portion of the substrate 1202 (e.g. the top surface of the substrate 1202 ) and the sections of ducts that extend from the molding 1212 from extend to encapsulate. With reference to 12 becomes the top surface of the molding 1212 sanded to the metal track 1214 of the substrate 1202 to expose. In some examples, the entire metal track 1214 through the molding 1212 exposed. In some examples, the metal track 1214 solder-plated.

The semiconductor package 1200 includes a first semiconductor chip 1204 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1206 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1200 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1200 passive components 1210 (e.g. capacitors). The first semiconductor chip 1204 and the second semiconductor chip 1206 are connected to the substrate via one or more redistribution layers 1202 coupled.

With reference to 12 can be a leadframe section 1240 , the first semiconductor chip 1204 , the second semiconductor chip 1206 and a leadframe section 1242 with the second surface 1207 of the substrate 1202 be coupled. The leadframe section 1240 and the leadframe section 1242 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1210 can be coupled to the leadframe on one side that is the substrate 1202 opposite. For example, a passive component 1210 with the leadframe section 1240 (on one of the substrate 1202 opposite position) and another passive element 1210 can with the leadframe section 1242 (on one of the substrate 1202 opposite position).

13 Fig. 11 illustrates a semiconductor package 1300 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1300 includes a substrate 1302 with a first surface 1305 and a second surface 1307 a. The semiconductor package 1300 includes a molding 1312 one that is configured to house all of the components of the semiconductor package 1300 except for a portion of the substrate 1302 (e.g. the top surface of the substrate 1302 ) and the sections of ducts that extend from the molding 1312 from extend to encapsulate. With reference to 13 becomes the top surface of the molding 1312 sanded to the first surface 1305 of the substrate 1302 to expose. In some examples, the entire top surface of the substrate is used 1302 through the molding 1312 exposed.

The semiconductor package 1300 includes a first semiconductor chip 1304 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1306 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1300 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1300 passive components 1310 (e.g. capacitors). The passive components 1310 can with the leadframe on the same side as the substrate 1302 be coupled. The first semiconductor chip 1304 and the second semiconductor chip 1306 are connected to the substrate via one or more redistribution layers 1302 coupled. In some examples, the first surface has 1305 of the substrate 1302 no redistribution layer (e.g. the bare ceramic is exposed).

With reference to 13 can be a leadframe section 1340 , the first semiconductor chip 1304 , the second semiconductor chip 1306 and a leadframe section 1342 with the second surface 1307 of the substrate 1302 be coupled. The leadframe section 1340 and the leadframe section 1342 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1310 can with the leadframe frame on the same side as the substrate 1302 be coupled. For example, a passive component 1310 with the Leadframe section 1340 (at a position on the same side as the substrate 1302 ) be coupled and another passive element 1310 can with the leadframe section 1342 (at a position on the same side as the substrate 1302 ) be coupled.

14th Fig. 11 illustrates a semiconductor package 1400 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1400 includes a substrate 1402 with a first surface 1405 and a second surface 1407 a. The semiconductor package 1400 closes a metal track 1414 (e.g. an upper redistribution layer) that is connected to the first surface 1405 is coupled, a. In addition, the semiconductor housing closes 1400 a metal spacer 1415 , the one with the metal track 1414 is coupled, a. In some examples, the spacer is metal 1415 a metal heat sink. The semiconductor package 1400 includes a molding 1412 one that is configured to house all of the components of the semiconductor package 1400 except for a portion of the substrate 1402 (e.g. the top surface of the substrate 1402 ) and the sections of ducts that extend from the molding 1412 from extend to encapsulate. With reference to 14th becomes the top portion of the molding 1412 sanded to the metal spacers 1415 of the substrate 1402 to expose. The metal spacer 1415 helps prevent the top surfaces of the passive components 1410 (or other larger components in the case) are accidentally abraded

The semiconductor package 1400 includes a first semiconductor chip 1404 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1406 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1400 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1400 the passive components 1410 a. The first semiconductor chip 1404 and the second semiconductor chip 1406 are connected to the substrate via one or more redistribution layers 1402 coupled.

With reference to 14th can be a leadframe section 1440 , the first semiconductor chip 1404 , the second semiconductor chip 1406 and a leadframe section 1442 with the second surface 1407 of the substrate 1402 be coupled. The leadframe section 1440 and the leadframe section 1442 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1410 can with the leadframe frame on the same side as the substrate 1402 be coupled. For example, a passive component 1410 with the leadframe section 1440 (at a position on the same side as the substrate 1402 ) be coupled and another passive element 1410 can with the leadframe section 1442 (at a position on the same side as the substrate).

15th Fig. 11 illustrates a semiconductor package 1500 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1500 includes a substrate 1502 with a first surface 1505 and a second surface 1507 a. The semiconductor package 1500 includes a molding 1512 one that is configured to house all of the components of the semiconductor package 1500 except for a portion of the substrate 1502 (e.g. the top surface of the substrate 1502 ) encapsulate. In 15th is a recess in the molded part 1512 formed to the first surface 1505 to expose. In some examples, a portion of the first surface 1505 through the molding 1512 exposed, and a portion of the first surface 1505 through the molding 1512 covered. In some examples, the first is surface 1505 below the top surface of the molding 1512 arranged.

The semiconductor package 1500 includes a first semiconductor chip 1504 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1506 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1500 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1500 passive components 1510 a. The first semiconductor chip 1504 and the second semiconductor chip 1506 may have one or more redistribution layers with the substrate 1502 be coupled. In some examples, the first surface has 1505 of the substrate 1502 no redistribution layer (e.g. the bare ceramic is exposed).

With reference to 15th can be a leadframe section 1540 , the first semiconductor chip 1504 , the second semiconductor chip 1506 and a leadframe section 1542 with the second surface 1507 of the substrate 1502 be coupled. The leadframe section 1540 and the leadframe section 1542 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1510 can with the leadframe opposite the substrate 1502 be coupled. For example, a passive component 1510 with the leadframe section 1540 (on one of the substrate 1502 opposite position) and another passive element 1510 can with the leadframe section 1542 (on one of the substrate 1502 opposite position).

16 Fig. 11 illustrates a semiconductor package 1600 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1600 includes a substrate 1602 with a first surface 1605 and a second surface 1607 a. The semiconductor package 1600 closes a metal track 1614 (e.g. an upper redistribution layer) that is connected to the first surface 1605 is coupled, a. In some examples, the metal track is 1614 solder-plated. The semiconductor package 1600 includes a molding 1612 one that is configured to house all of the components of the semiconductor package 1600 except for a portion of the substrate 1602 (e.g. the top surface of the substrate 1602 ) encapsulate. In 16 is a recess in the molded part 1612 trained to the metal track 1614 to expose. In some examples, a portion of the metal web 1614 through the molding 1612 exposed, and a section of the metal track 1614 through the molding 1612 covered. In some examples, the metal track is 1614 below the top surface of the molding 1612 arranged.

The semiconductor package 1600 includes a first semiconductor chip 1604 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1606 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1600 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1600 passive components 1610 a. The first semiconductor chip 1604 and the second semiconductor chip 1606 are connected to the substrate via one or more redistribution layers 1602 coupled.

With reference to 16 can be a leadframe section 1640 , the first semiconductor chip 1604 , the second semiconductor chip 1606 and a leadframe section 1642 with the second surface 1607 of the substrate 1602 be coupled. The leadframe section 1640 and the leadframe section 1642 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1610 can with the leadframe opposite the substrate 1602 be coupled. For example, a passive component 1610 with the leadframe section 1640 (on one of the substrate 1602 opposite position) and another passive element 1610 can with the leadframe section 1642 (on one of the substrate 1602 opposite position).

17th Fig. 11 illustrates a semiconductor package 1700 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1700 includes a substrate 1702 with a first surface 1705 and a second surface 1707 a. The semiconductor package 1700 includes a molding 1712 one that is configured to house all of the components of the semiconductor package 1700 except for a portion of the substrate 1702 (e.g. the top surface of the substrate 1702 ) encapsulate. In 17th is a recess in the molded part 1712 formed to the first surface 1705 to expose. In some examples, a portion of the first surface 1705 through the molding 1712 exposed, and a portion of the first surface 1705 through the molding 1712 covered. In some examples, the first is surface 1705 below the top surface of the molding 1712 arranged.

The semiconductor package 1700 includes a first semiconductor chip 1704 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1706 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1700 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1700 passive components 1710 a. The passive components 1710 can with the leadframe on the same side as the substrate 1702 be coupled. The first semiconductor chip 1704 and the second semiconductor chip 1706 are connected to the substrate via one or more redistribution layers 1702 coupled. In some examples, the first surface has 1705 of the substrate 1702 no redistribution layer (e.g. the bare ceramic is exposed).

With reference to 17th can be a leadframe section 1740 , the first semiconductor chip 1704 , the second semiconductor chip 1706 and a leadframe section 1742 with the second surface 1707 of the substrate 1702 be coupled. The leadframe section 1740 and the leadframe section 1742 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1710 can with the leadframe frame on the same side as the substrate 1702 be coupled. For example, a passive component 1710 with the leadframe section 1740 (at a position on the same side as the substrate 1702 ) be coupled and another passive element 1710 can with the leadframe section 1742 (at a position on the same side as the substrate 1702 ) be coupled.

18th Fig. 11 illustrates a semiconductor package 1800 having an exposed substrate configured as a heat sink according to the aspect. The semiconductor package 1800 includes a substrate 1802 with a first surface 1805 and a second surface 1807 a. The semiconductor package 1800 closes a metal track 1814 (e.g. an upper redistribution layer) that coincides with the first surface 1805 is coupled. In some examples, the metal track is 1814 solder-plated. The semiconductor package 1800 includes a molding 1812 one that is configured to house all of the components of the semiconductor package 1800 except for a portion of the substrate 1802 (e.g. the top surface of the substrate 1802 ) encapsulate. In 18th is a recess in the molded part 1812 trained to the metal track 1814 to expose. In some examples, a portion of the metal web 1814 through the molding 1812 exposed, and a section of the metal track 1814 through the molding 1812 covered. In some examples, the metal track is 1814 below the top surface of the molding 1812 arranged.

The semiconductor package 1800 includes a first semiconductor chip 1804 (e.g. a lowside semiconductor power chip) and a second semiconductor chip 1806 (e.g. a high-side semiconductor power chip). In addition, the semiconductor package 1800 include a third semiconductor chip (e.g., a driver IC chip) as discussed with reference to the previous figures. In addition, the semiconductor housing closes 1800 passive components 1810 a. The first semiconductor chip 1804 and the second semiconductor chip 1806 may have one or more redistribution layers with the substrate 1802 be coupled.

With reference to 18th can be a leadframe section 1840 , the first semiconductor chip 1804 , the second semiconductor chip 1806 and a leadframe section 1842 with the second surface 1807 of the substrate 1802 be coupled. The leadframe section 1840 and the leadframe section 1842 can be any portions of the conduits discussed with reference to the previous figures. The passive components 1810 can with the leadframe frame on the same side as the substrate 1802 be coupled. For example, a passive component 1810 with the leadframe section 1840 (at a position on the same side as the substrate 1802 ) be coupled and another passive element 1810 can with the leadframe section 1842 (at a position on the same side as the substrate 1802 ) be coupled.

It will be understood that in the foregoing description, when an element is referred to as connected, electrically connected, coupled to, or electrically coupled to another element, it may be disposed, connected or coupled directly on the other element, or one or more intervening therebetween Elements may be present. Conversely, when an element is said to be directly connected or directly connected to another element, there are no intervening elements. Although the terms directly connected or directly coupled may not be used in the detailed description, elements shown as directly connected or directly coupled may be referred to as such. The claims of the application may be modified as necessary to identify exemplary relationships described in the specification or shown in the figures. Implementations of the various techniques described herein can be implemented in digital electronic circuitry or in computer hardware, firmware, software, or combinations thereof. Process steps can also be performed by a dedicated logic circuit, e.g. B. an FPGA (Field Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit) and a device can be implemented in this form.

Some implementations can be implemented using various semiconductor processing or packaging techniques. Some embodiments may be implemented using various types of semiconductor processing techniques in conjunction with semiconductor substrates including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like, for example.

While certain features of the implementations described have been illustrated as described in this document, numerous modifications, substitutions, changes, and equivalents will now become apparent to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of the embodiments. It is to be understood that they have been presented in the form of examples only, without being limiting, and various changes in form and detail can be made. Each section of the apparatus and / or method described in this document can be combined in any combination, except for mutually exclusive combinations. The claims described in this document may contain various combinations and / or sub-combinations of the functions, components and / or features of the various described embodiments.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 62811147 [0001]
• US 16506405 [0001]

Claims (10)

A semiconductor package comprising: a substrate having a first surface and a second surface opposite the first surface; a semiconductor chip coupled to the second surface of the substrate; a molded part that encapsulates the semiconductor chip and a large part of the substrate, wherein at least a portion of the first surface is exposed through the molding such that the substrate is configured to function as a heat sink. Semiconductor package according to Claim 1 , wherein the substrate includes a via extending between the first surface and the second surface, the semiconductor package further comprising: a metal trace coupled to the first surface of the substrate and at least a portion of the metal trace extending through the Molding is exposed. Semiconductor package according to Claim 1 wherein the semiconductor chip is a first semiconductor chip, the semiconductor package further comprising: a second semiconductor chip coupled to the second surface of the substrate; and a third semiconductor chip coupled to the second surface of the substrate; Semiconductor package according to Claim 1 further comprising: a first metal trace coupled to the second surface of the substrate; and a second metal line coupled to the first metal line, wherein the semiconductor chip is coupled to the second metal line. Semiconductor package according to Claim 1 , further comprising: a leadframe section coupled to the substrate; and a passive component coupled to the leadframe section. A semiconductor package comprising: a substrate having a first surface and a second surface opposite the first surface; a leadframe section coupled to the substrate; a first metal trace coupled to the first surface of the substrate; at least one second metal trace coupled to the second surface of the substrate; a semiconductor chip coupled to the at least one second metal line; and a molded part that encapsulates the semiconductor chip and a large part of the substrate, wherein at least a portion of the first metal sheet is exposed through the molding such that the substrate is configured to function as a heat sink. Semiconductor package according to Claim 6 wherein the substrate includes a via connecting the leadframe portion to the first metal trace, the at least one second metal trace including two stacked metal traces, the semiconductor package further comprising; a capacitor coupled to the leadframe section or the substrate. Semiconductor package according to Claim 6 wherein the semiconductor chip is a first semiconductor chip, wherein the semiconductor package further comprises a second semiconductor chip coupled to the at least one second metal track; and a third semiconductor chip coupled to the at least one second metal line; wherein the first semiconductor chip is a low-side semiconductor chip, the second semiconductor chip is a high-side semiconductor chip and the third semiconductor chip is a chip for integrated driver circuits (IC). A semiconductor package comprising: a substrate having a first surface and a second surface opposite the first surface, the substrate having a via extending between the first surface and the second surface, a lead frame portion coupled to the second surface of the substrate; a metal trace coupled to the first surface of the substrate, the via connecting the metal trace to the leadframe portion; a high-side semiconductor chip coupled to the second surface of the substrate; a low-side semiconductor chip coupled to the second surface of the substrate; a molded part that encapsulates the semiconductor chip and a large part of the substrate, wherein at least a portion of the metal web is exposed through the molding such that the substrate is configured to function as a heat sink. Semiconductor package according to Claim 9 , further comprising: a first passive device coupled to the substrate; a second passive component coupled to the substrate; an integrated driver circuit (IC) chip coupled to the second surface of the substrate, wherein the high-side semiconductor chip and the low-side semiconductor chip are coupled to the second surface of the substrate via a second metal line and a third metal line, and the driver IC chip is coupled to the second surface of the substrate via the second metal line but not the third metal line is.

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