DE102019124738A1 - Method for the energy-saving operation of a computer system and the associated computer system and computer program product - Google Patents

Abstract

For the purpose of energy saving and thus extended operation of a computer system (6) which has a DRAM memory (1) consisting of several memory banks (2), the memory contents of which can be refreshed individually by means of a DRAM refresh cycle (7) , It is proposed that by reading out the DRAM memory (1) first of all data (9) are recorded which are to be obtained so that these data (9) are then written back in compressed form to the DRAM memory (1), in particular where less of the memory banks (2) are written with data to be received (9) than a number of memory banks (2) which contained such data to be received (9) before reading out, and that ultimately only those of the memory banks (2) by means of the DRAM refresh cycle (7) are periodically refreshed, which sin when writing the compressed data (28) in the DRAM memory (1) with compressed data (9, 28) to be obtained d

Description

The invention relates to a method for the energy-saving operation of a computer system, which can in particular be designed as an “in-vehicle infotainment” (IVI) system. The invention also relates to such a computer system and an associated computer program product.

Said computer system has a DRAM memory based on a Dynamic Random Access Memory (DRAM), which in turn has several individually addressable memory banks. The respective memory contents of the memory banks can be refreshed electronically by means of a DRAM refresh cycle. The computer system also includes a host controller for reading and writing to the DRAM memory. Finally, the computer system can be switched from a normal operating state to a standby mode, in which the total energy consumption of the computer system is reduced compared to the normal operating state.

Such computer systems are already in use, in particular as so-called "in-vehicle infotainment" (IVI) systems, which are used for electronic entertainment and information (information and entertainment, i.e. "infotainment") for passengers in vehicles. In order to save energy during operation, such systems typically have the aforementioned standby mode, i.e. an energy-saving function through which individual system components are put into a respective energy-saving mode in which the respective electrical power consumption of the system component is reduced and thus the overall energy requirement of the system is reduced.

A chipset and a data storage system of the computer system typically make a major contribution to energy consumption. Nowadays, the latter is typically designed as a DRAM (Dynamic Random Access Memory). Since the storage capacity of DRAM memories is currently increasing from chip generation to chip generation, it is becoming more and more important to lower the energy requirement of the DRAM in order to limit the overall energy requirement of the computer system. This problem will be exacerbated in the future as the DRAM storage capacity continues to grow.

For this reason, four generations of low-power variants of DRAM have already been developed, which are known under the industry standards LPDDR1, LPDDR2, LPDDR3 and LPDDR4 (published in 2014 by JEDEC). More precisely, this is Low-Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR-SDRAM), often abbreviated as low-power DDR SDRAM and hereinafter referred to as LPDDRx for the sake of simplicity. In February 2019, a fifth generation of the standard under the abbreviation LPDDR5 was published by JEDEC. All of these DRAM types, which are specifically designed for use in mobile end devices, share the property of low energy consumption, which is achieved in particular by continuously lowering the supply voltage to 0.5 V in LPDDR5.

Furthermore, these memory types have very low “self-refresh currents” in the range of a few mA, that is typically an order of magnitude less than, for example, conventional Double Data Rate Synchronous Dynamic Random Access Memory (DDR-SDRAM), which reduces energy consumption in “standby mode”. reduced to a few mW.

With so-called "Suspend-to-RAM" as part of the standby mode, the current system configuration is typically written to the DRAM memory and most of the system components are switched off in order to consume less electrical energy. Only the DRAM is still supplied with power, otherwise the stored data would be lost. This already results in enormous savings in electrical energy compared to normal operating conditions.

Despite these precautions and the use of energy-saving DRAM memories of the LPDDRx type, the time in which today's computer systems can be operated in the standby mode is limited.

Proceeding from this, the invention is based on the object of further reducing the energy requirement of computer systems as described at the outset - at least in the standby mode.

To achieve this object, the features of claim 1 are provided according to the invention in a method for energy-saving operation of a computer system. In particular, according to the invention, in order to achieve the object in a method of the type described at the outset, in the standby mode, in an identification step, those of the memory banks of the DRAM memory that contain no data or currently no longer required are identified as memory banks to be excluded. It is also proposed that, in a refresh step, all of the remaining memory banks of the DRAM memory which contain data to be received are refreshed by means of the DRAM refresh cycle, while those to be excluded Memory banks are excluded from the DRAM refresh cycle.

In other words, it is accordingly proposed not to refresh the entire DRAM memory, but rather only selected memory banks of the DRAM memory. The selection of which of the memory banks of the DRAM memory are refreshed by means of the DRAM refresh cycle can be made on the basis of the memory content of the memory banks, as will be explained in more detail below.

The individual memory cells of individual memory banks of the DRAM memory, which are used to store a respective data bit, typically each consist of a tiny capacitance and an associated transistor for applying an electrical charge to the capacitance. Because of leakage currents, the memory cell must be periodically recharged electrically in order to maintain the memory state and thus avoid data loss, which is referred to as “refresh”. So-called self-refresh modes, with which the memory contents of the memory cells can be refreshed, are used to recharge the capacities of individual memory cells in order to compensate for their leakage currents.

A “refresh” or refreshing of the DRAM memory can thus be understood here in particular as a process in which data is periodically read out from memory cells of the DRAM memory and these read data are immediately written back to the respective memory cells of the DRAM memory without modification with the purpose of thereby obtaining the data stored in the memory cells or the information encoded by the data. Such DRAM refresh cycles are therefore a necessary background process for the operation of DRAM in order to avoid data loss.

• Im Bereitschaftsbetriebszustand können stets nur diejenigen Speicherbänke elektronisch wiederaufgefrischt werden, die tatsächlich Daten enthalten, die zu einem späteren Zeitpunkt, insbesondere nach einem Übergang in den Normalbetriebszustand, von dem Computersystem benötigt werden. Dadurch kann ein Refresh-Strom, der zum Wiederauffrischen der Speicherbänke des DRAM-Speichers im Bereitschaftsbetriebszustand eingesetzt werden muss, stark reduziert werden, was den Energieverbrauch des Computersystems im Bereitschaftsbetriebszustand senkt.

The advantages of the procedure described above are as follows:

• In the standby operating state, only those memory banks can be electronically refreshed which actually contain data that are required by the computer system at a later point in time, in particular after a transition to the normal operating state. As a result, a refresh current that has to be used to refresh the memory banks of the DRAM memory in the standby mode can be greatly reduced, which lowers the energy consumption of the computer system in the standby mode.

The possible energy savings are considerable: For example, from technology generation to technology generation, typically 12-15% energy savings are achieved with LPDDR memory modules. In contrast, significantly higher energy savings can be achieved with the proposed method according to the invention.

Another advantage is that, after the identification step, the host controller knows all storage locations and thus all memory banks of the DRAM memory in which data to be received is currently stored and which must therefore be refreshed using the DRAM refresh cycle to prevent data loss to avoid. This knowledge goes hand in hand with the knowledge of all those memory locations and thus memory banks of the DRAM memory which currently, in particular after the identification step, contain no data or currently no longer required data; they therefore do not have to be refreshed, since no relevant data loss can occur in these memory banks to be excluded from the DRAM refresh cycle. By avoiding refreshing memory banks that do not have to be refreshed, power consumption and thus electrical energy can be saved.

Due to the reduced energy consumption in the standby mode, it is also achieved that a possible “suspend-to-RAM” time in which the computer system is operated in the standby mode is maximized.

According to the invention, the object can also be achieved by further advantageous embodiments according to the subclaims.

For example, it can be provided that the identification step comprises a modification, preferably a rearrangement, of the data to be obtained on the memory banks and / or a, preferably lossless, data compression of the data to be obtained.

(Data) compression can be understood here in particular as a process in which a quantity of, preferably digital, original data is compressed into compressed data, so that a storage space required for the quantity is reduced. Such a compression reduces the storage space required and the transmission time of the data is shortened. The data compression can be based on the approach of removing redundant information in the data.

Lossless compression can be understood here as a compression, as a result of which all original data are restored from compressed data can be obtained without any loss of information.

The modification and / or the data compression can take place in a variety of ways.

The identification step is preferably carried out in such a way that a number of memory banks that are excluded from the DRAM refresh cycle in the refresh step is increased compared to a number of memory banks that did not contain any data or data that were no longer required before the identification step.

Alternatively or additionally, the memory banks to be excluded can also be identified in such a way that a number of memory banks that are refreshed in the refresh step by means of the DRAM refresh cycle is reduced compared to a number of memory banks that contained data to be obtained before the identification step.

Finally, the identification step can additionally or alternatively be carried out in such a way that, after the identification step, the respective memory banks, in particular individual memory locations, in particular memory cells in which the data to be obtained are currently stored in the DRAM memory, are known.

1. A. der gesamte Speicherinhalt des DRAM-Speichers wird ausgelesen;
2. B. der ausgelesene gesamte Speicherinhalt wird, vorzugsweise mit einer maximal verfügbaren Kompressionsrate und/oder verlustfrei, in ein komprimiertes Speicherabbild komprimiert;
3. C. das komprimierte Speicherabbild wird in den DRAM-Speicher geschrieben.

According to a preferred embodiment, the identification step comprises the following steps AC:

1. A. the entire memory content of the DRAM memory is read out;
2. B. the entire memory content that has been read is compressed into a compressed memory image, preferably with a maximum available compression rate and / or loss-free;
3. C. The compressed memory map is written to the DRAM memory.

It is preferred here if the compression is designed such that all of the original data of the DRAM memory can be recovered in the form of the original memory content by decompressing the compressed memory image.

Furthermore, those of the memory banks of the DRAM memory which are not written to in step C can be identified as memory banks to be excluded in the identification step.

Alternatively or additionally, however, those of the memory banks which have been written to with the compressed memory image in step C can be refreshed in the refresh step.

In particular, if the data to be saved has been compressed in the identification step, fewer of the memory banks can be written to in step C than a number of memory banks which contained data to be obtained before step C.

Furthermore, in step C, individual memory banks that contained data to be received can be overwritten with the compressed memory image and / or, in the refresh step, individual memory banks that contained data to be received prior to step C can be excluded from the DRAM refresh cycle.

For a particularly energy-saving operation of the computer system, it is also advantageous if the identification step is only repeated as soon as new data has been written to the DRAM memory or older data has been deleted from the DRAM memory. Only in these cases do more memory banks have to be refreshed (if new data were added) or even fewer memory banks can be refreshed with an even lower refresh current (namely when some of the originally retained data has been deleted).

In this case, the refreshing step can be repeated at regular intervals even if no new data has been written into the DRAM memory and no older data has been deleted in the DRAM memory. Because this precisely ensures that the data to be received is retained even without a new identification step.

After the identification step, the refresh step can thus be repeated periodically.

In order to enable the computer system to operate smoothly as usual, as soon as a user switches the computer system from the standby mode to the normal mode, which can also be done automatically in response to certain commands or sensor signals, the modification, in particular the rearrangement, of the data and / or the Data compression can be reversed when the computer system is brought from the standby mode to the normal mode.

• D. das komprimierte Speicherabbild wird aus dem DRAM-Speicher ausgelesen;
• E. das ausgelesene komprimierte Speicherabbild wird in einen dekomprimierten Speicherinhalt dekomprimiert;
• F. der dekomprimierte Speicherinhalt wird in den DRAM-Speicher geschrieben.

In particular, a wake-up process can be carried out for this purpose, which comprises the following steps DF:

• D. the compressed memory map is read from the DRAM memory;
• E. The read-out compressed memory image is decompressed into a decompressed memory content;
• F. the decompressed memory content is written to the DRAM memory.

The wake-up process can preferably take place in such a way that, in the normal state, after a latency period, the computer system can fully access an original memory content of the DRAM memory before the identification step is carried out. This original memory content can in particular correspond to the previously explained decompressed memory content.

A particularly preferred variant of the method provides that, in the identification step, the entire memory content read is divided into critical data and non-critical data, and that the critical data is written as compressed data in a first partition of the DRAM memory, while the non-critical data is written in a second partition of the DRAM memory can be written as compressed data. It is preferred here if the first partition and the second partition do not have any overlap in memory banks of the DRAM memory.

The subdivision of the memory contents into critical data and non-critical data has the advantage that the transition to the normal operating state can be proceeded in stages in order to shorten the latency period after which the memory contents of the DRAM memory can be accessed as usual.

For this purpose, when the computer system is switched from the standby operating state to the normal operating state and / or during the wake-up process explained above, only the first partition can initially be read out. Data read out from the first partition can then be decompressed and then written back to the DRAM memory as decompressed critical data.

It can thus be achieved that a latency period after which access to the decompressed critical data is possible is shortened compared to a latency period which would be required for access to the entire original memory content of the DRAM memory.

It is also preferable here if, after reading out the first partition, the second partition is read out, in particular by means of a background process. Subsequently, data read out from the second partition can be decompressed and then written back to the DRAM memory as decompressed, non-critical data.

It is very particularly preferred in this two-stage wake-up process if the first partition is designed to be smaller than the second partition, because this leads to a further shortening of said latency period. It is also preferable if the first partition and the second partition do not have a common memory bank, since this means that no data is unnecessarily read out in the first step, which would cost further latency.

To achieve the stated object, the features of the independent device claim, directed to a computer system, are also provided according to the invention. In particular, it is therefore proposed according to the invention to achieve the object in a computer system of the type described above that the host controller of the computer system is set up to carry out a method according to one of the preceding claims in conjunction with the DRAM memory.

For this purpose, the computer system, in particular the host controller, can have a chipset for compressing the entire memory content of the DRAM memory in order to carry out the previously described rearrangement and compression of the memory content of the DRAM memory.

The computer system preferably also has an intermediate memory for temporarily storing a compressed memory image of the DRAM memory and / or compressed data.

It is also preferred if the computer system itself has a chipset for decompressing the compressed memory image of the DRAM memory and / or compressed data.

According to an embodiment of the computer system that is particularly preferred because it is easy to implement, it is provided that the DRAM memory is made up of several LPDDRx memory modules (cf. the explanations at the beginning), each of which has several individually addressable memory banks, the respective memory contents of which are electronically by means of a DRAM refresh cycle can be refreshed.

It is preferred here if the host controller is set up to identify individual memory banks in each of the LPDDR4 memories as memory banks to be excluded in the identification step.

The host controller can also be set up to refresh those To refresh memory banks of the DRAM memory which contain data to be retained by means of a Partial Array Self Refresh (PASR).

The host controller of the computer system according to the invention can therefore in particular be set up in the standby mode in an identification step to identify those memory banks as excluded memory banks that contain no data or data that is no longer required and / or, in a refresh step, all the remaining memory banks that contain the data to be received contain to refresh by means of the DRAM refresh cycle and to exclude the identified memory banks from the DRAM refresh cycle.

Furthermore, the host controller can be set up in such a way that in the identification step it identifies as memory banks to be excluded those of the memory banks of the DRAM memory that are not written in step C and / or in the refresh step refreshes those of the memory banks that were compressed in step C with the Memory dump were written.

The DRAM memory can preferably be implemented in the following architecture, especially when the computer system is configured as an IVI system: The DRAM memory has a 128-bit wide data bus line with which four different LPDDRx memory modules of the DRAM memory can be written. The four LPDDRx memory modules are addressed in parallel and each have a bit width of 32 bits. When using such a DRAM memory, the method for energy-saving operation of the computer system can provide that a respective memory bank runs over all four LPDDRx memory modules of the DRAM memory. Accordingly, if one of the memory banks is recognized as a “memory bank to be excluded” in the identification step and excluded from the DRAM refresh cycle in the refresh step, then none of those memory cells in the four LPDDRx memory modules of the DRAM memory that belong to the excluded memory bank are removed refreshed. This approach can be described simply as “dropping a bank across all LPDDRx memory devices”, with “dropping” denoting an exclusion from the DRAM refresh cycle.

1. A. der host controller liest den gesamten Speicherinhalt des DRAM-Speichers aus;
2. B. der host controller komprimiert den gesamten ausgelesenen Speicherinhalt, vorzugsweise mit einer maximal verfügbaren Kompressionsrate, in ein komprimiertes Speicherabbild;
3. C. der host controller schreibt das komprimierte Speicherabbild in den DRAM-Speicher.

Furthermore, in a computer system according to the invention, the identification step can include the following steps AC:

1. A. the host controller reads out the entire memory content of the DRAM memory;
2. B. the host controller compresses the entire read memory content, preferably with a maximum available compression rate, into a compressed memory map;
3. C. the host controller writes the compressed memory image to the DRAM memory.

Finally, the invention also proposes a computer program product, in particular in the form of a software application, in order to achieve the object described at the outset. This computer program product can be loaded into a memory of a computer system, wherein the computer system can in particular be configured as described above. To achieve the object, the computer program product comprises a software code with the aid of which a method according to the invention as described above and / or according to one of the claims directed to a method is implemented as soon as the software code is executed by the computer system.

The invention will now be described in more detail with reference to exemplary embodiments, but is not limited to these exemplary embodiments.

Further exemplary embodiments result from the combination of the features of individual or several protection claims with one another and / or with individual or several features of the respective exemplary embodiment. In particular, embodiments of the invention can thus be obtained from the following description of a preferred exemplary embodiment in conjunction with the general description, the claims and the drawings.

• 1 ein erfindungsgemäßes Computersystem,
• 2 eine Illustration von zwei grundlegenden Ansätzen für DRAM-Refresh-Zyklen,
• 3 eine Illustration der Anwendung eines erfindungsgemäßen Verfahrens auf einen DRAM-Speicher eines erfindungsgemäßen Computersystems beim Übergang von einem Normalbetriebszustand in einen Bereitschaftsbetriebszustand,
• 4 eine Illustration des Wiederauffrischungsschritts des erfindungsgemäßen Verfahrens,
• 5 eine Illustration der Anwendung eines erfindungsgemäßen Verfahrens auf einen DRAM-Speicher eines erfindungsgemäßen Computersystems beim Übergang von einem Bereitschaftsbetriebszustand in einen Normalbetriebszustand,
• 5 eine Illustration der Anwendung eines erfindungsgemäßen Verfahrens auf einen DRAM-Speicher eines erfindungsgemäßen Computersystems beim Übergang von einem Bereitschaftsbetriebszustand in einen Normalbetriebszustand,
• 6 den Betrieb des Computersystems in einem Wechsel zwischen Normalbetriebszustand und Bereitschaftsbetriebszustand,
• 7 eine mögliche Ausgestaltung des DRAM-Speichers des Computersystems aus 1,
• 8 Details des DRAM-Speichers gemäß 7,
• 9 eine bevorzugte, stufenweise Ausgestaltung des erfindungsgemäßen Verfahrens, wobei der DRAM-Speicher hierzu in zwei Partitionen unterteilt wird.

It shows:

• 1 a computer system according to the invention,
• 2 an illustration of two basic approaches to DRAM refresh cycles,
• 3 an illustration of the application of a method according to the invention to a DRAM memory of a computer system according to the invention during the transition from a normal operating state to a standby operating state,
• 4th an illustration of the refresh step of the method according to the invention,
• 5 an illustration of the application of a method according to the invention to a DRAM memory of a computer system according to the invention during the transition from a standby operating state to a normal operating state,
• 5 an illustration of the application of a method according to the invention to a DRAM memory of a computer system according to the invention during the transition from a standby operating state to a normal operating state,
• 6th the operation of the computer system in a change between normal operating mode and standby mode,
• 7th a possible configuration of the DRAM memory of the computer system 1 ,
• 8th Details of the DRAM memory according to 7th ,
• 9 a preferred, step-by-step embodiment of the method according to the invention, the DRAM memory being divided into two partitions for this purpose.

The 1 shows a whole with a number 6th Designated computer system, which is designed as an in-vehicle-infotainment (IVI) system and a DRAM memory 1 on the basis of a dynamic random access memory (DRAM), which is controlled by a host controller 4 of the computer system 6th can be read out and written to. The DRAM memory 1 has a total of 4 LPDRAM memory modules 3 on. Together these form a total of four individually addressable memory banks 2 off (in the 1 referred to as “bank 0”, “bank 1”, “bank 2” and “bank 3” and highlighted with dashed boxes), their respective memory contents electronically by means of a DRAM refresh cycle 7th can be refreshed. The DRAM refresh cycle 7th rewrites individual memory cells with identical memory contents, as a result of which a respective charge on a capacity of the memory cell is brought to the desired value, which corresponds to the bit to be stored in each case by the memory cell.

For this purpose, the host controller 4 uses a data bus 5 on the DRAM memory 1 to. Software applications 8th running on the computer system 6th run, mediated by the host controller 4, on the DRAM memory 1 access.

• Die 2 erläutert zunächst zwei grundlegende vorbekannte Verfahren, mit Hilfe derer Speicherinhalte eines DRAM-Speichers 1 vor Datenverlust geschützt werden können: Bei dem sogenannten „all bank refresh“-Verfahren, links dargestellt in 2, werden alle Speicherbänke 2 eines DRAM-Speichers 1, gemeinsam wiederaufgefrischt, d.h. in periodischen Zeitabständen mit identischen Daten neu beschrieben, um die eingangs beschriebenen Datenverluste aufgrund von Leckströmen in den Kapazitäten der einzelnen Speicherzellen der Speicherbänke 2 zu vermeiden.

As the 6th illustrated, the computer system can 6th between a normal operating condition 14th and a standby mode 15th toggling back and forth, taking the total power consumption of the computer system 6th in standby mode 15th is reduced compared to the normal operating state 14th . To now the total energy consumption of the computer system 6th in standby mode 15th To lower it further, the host controller 4 is set up to use a method according to the invention in interaction with the DRAM memory 1 to be carried out, which is explained in more detail below:

• The 2 first explains two basic previously known methods with the aid of which the memory contents of a DRAM memory 1 can be protected against data loss: With the so-called “all bank refresh” procedure, shown on the left in 2 , become all memory banks 2 of a DRAM memory 1 , refreshed together, ie rewritten at periodic time intervals with identical data, in order to avoid the initially described data losses due to leakage currents in the capacities of the individual memory cells of the memory banks 2 to avoid.

The in 2 On the other hand, the “partial array self refresh” method shown on the right - depending on requirements - only some of the memory banks are used 2 of the DRAM memory 1 Refreshed: As in right in 2 can be seen with this method, for example, only two memory banks 2 ("2 banks refresh") or just one of the memory banks 2 ("1 bank refresh"). The remaining memory banks 2 from the refresh cycle 7th are excluded, are therefore not rewritten, so that the data that are stored in their memory cells are exposed to expiry and are lost after a short time.

These previously known procedures can be used in order to save electrical power and thus electrical energy that is required when rewriting the memory cells during the refresh cycle 7th must be spent. Excluding memory banks 2 from the refresh cycle 7th ("Dropping the banks") is not critical as long as the refresh cycle 7th excluded memory banks 12th ("Dropped banks") no data to be received 9 contain.

Like in the 3 can be seen at the top, lie - after a certain operating time of the DRAM memory 1 in normal operating condition 14th - such data to be obtained 9 however, typically distributed randomly in several of the memory banks 2 of the DRAM memory 1 in front. In other words, it is typically an original memory content 22nd that after a transition of the computer system 6th from the standby mode 15th in the normal operating state 14th Must be made accessible again in order for the computer system to operate properly 6th to ensure over the entire DRAM memory 1 distributed. Therefore, it is not easy to say at first which of the memory banks 2 of the DRAM memory 1 relevant data to be obtained 9 included and which of the memory banks 2 no data or data that cannot be obtained 10 included, so they are not would have to be refreshed. It should be noted that the computer system 6th the DRAM memory in the normal operating state 1 constantly dynamically reads and rewrites, depending on the requirements of the software applications currently running, so that the data to be retained 9 after a short time randomly via the DRAM memory 1 distributed.

To now an energy-saving operation of the computer system 6th in standby mode 15th to enable, the inventive method proposes that in an identification step 17th first those of the memory banks 2 of the DRAM memory 1 as memory banks to be excluded 12th identify which no data or data that is currently no longer required 10 contain. In a second subsequent refresh step 18th can then all the rest of the memory banks 2 , the data to be obtained 9 included, by means of the DRAM refresh cycle 7th are refreshed while the memory banks to be excluded 12th from the DRAM refresh cycle 7th can just be excluded.

To identify the memory banks to be excluded 12th To enable, a preferred embodiment of the method suggests that initially the entire memory content 22nd of the DRAM memory 1 is read out, then the entire memory content that has been read out 22nd with a maximum available compression rate lossless into a compressed memory image 19th is compressed and finally the compressed memory dump 19th , after being temporarily stored in a buffer 11 , again in the DRAM memory 1 is written back. This procedure is in the 3 shown. As can be seen, this method thus comprises the three steps A), B) and C) (compare claim 3).

By compressing the data to be preserved 9 originally across all memory banks 2 of the DRAM memory 1 were distributed, the storage requirements for this data 9 greatly reduced, so all data to be preserved 9 in the in 3 illustrated example only in the first memory bank 2 "Bank 0" can be stored. All that remains is the first memory bank 2 “Bank 0” is refreshed as “memory bank 12 to be refreshed”, while the other memory banks 2 “Bank 1, 2, 3” from the DRAM refresh cycle 7th can be excluded as "memory banks 12 to be excluded". This results in a lower necessary refresh current and thus energy savings.

In the example according to 3 , especially with the memory allocation as at the top of the DRAM memory 1 apparent, should normally be in standby mode 15th all four memory banks 2 refreshed one at a time. After compressing and rearranging the data to be preserved 9 are these relevant data 9 but all in the first memory bank 2 "Bank 0" arranged as in the figure below of the DRAM memory 1 in 3 can be seen. Therefore, after rewriting the DRAM memory 1 with the compressed memory image 19th only the first of the four memory banks 2 "Bank 0" can be refreshed while the remaining three memory banks 2 "Bank 1 - 3" as memory banks to be excluded 12th have been identified that have no data or data that is currently no longer required 10 contain. These memory banks 2 "Bank 1 - bank 3" are thus in the refresh step 18th from the DRAM refresh cycle 7th excluded ("banks 1-3 can be dropped").

As by comparing DRAM memory 1 before and after the identification step 17th it can be seen that the data to be obtained were 9 thus on the memory banks 2 of the DRAM memory 1 rearranged and modified. The original memory contents became more precise 22nd lossless to a compressed memory image 19th compressed and then back into the DRAM memory 1 written. During this write back, both data to be preserved 9 of the original memory contents 22nd overwritten and partially abandoned to expiry. Because, for example, “bank 1” is the data originally to be received 9 after the identification step 17th in the refresh step 18th no longer refreshed.

Since the original memory contents 22nd initially across all four memory banks 2 of the DRAM memory 1 was distributed, had to be in normal operating condition 14th initially all of these four memory banks 2 be refreshed. Compared to the situation before the identification step 17th The number of memory banks has therefore increased due to the modification of the data 2 that gave it refresh step from the DRAM refresh cycle 7th excluded (in the example the 3 if these are the memory banks "bank 1, bank 2, bank 3"), increased compared to the number of memory banks 2 (in this example the 3 "Zero" memory banks 2 ) before the identification step 17th no data or data that is no longer required 10 contained.

From a different point of view, the number of memory banks has also increased 2 that are in the refresh step 18th refreshed, namely only the "bank 0" is reduced compared to a number of memory banks 2 that before the identification step 17th data to be obtained 9 contained (originally these were all memory banks 2 "Bank 0-3") and had to be refreshed accordingly.

As the 4th shows, “bank 0” can be refreshed by means of a “bank refresh across all LPDRAM devices”, ie by refreshing the first memory bank 2 over all 4 LPDRAM memory modules 3 away.

By rewriting the DRAM memory 1 with the compressed memory image 19th (Step C in 3 ) is the computer system 6th thus after the identification step 17th known in which memory cells and thus also in which memory banks 2 of the DRAM memory 1 current data to be received 9 are stored. This allows the computer system 6th after the identification step 17th autonomously decide which of the memory banks 2 from the DRAM refresh cycle 7th can be excluded without data loss.

This is particularly easy if the computer system 6th in the identification step 17th those of the memory banks 2 of the DRAM memory 1 as memory banks to be excluded 12th identified which just in step C (compare 3 ) have not been written to (i.e. the memory banks "bank 1 - 3"). In other words, it is precisely those of the memory banks that can be used in the refresh step 2 refreshed in step C with the compressed memory image 19th have been described.

The advantage of the method described is that in step C fewer of the memory banks 2 must be described as a number of memory banks containing the data to be obtained before step C. 9 contained. Because in the present example the 3 in step C only the "bank 0" is described, but not the "banks 1-3", which are before the identification step 17th data to be obtained 9 contained.

It is also noticeable that in step C the "bank 0" with the compressed memory image 19th was overwritten, although this memory bank 2 data originally to be received 9 contained. On the other hand, however, are also in the refresh step 18th the memory banks “banks 1 - 3” just excluded from the DRAM refresh cycle 7, although these memory banks 2 data to be obtained before step C. 9 contained.

According to the invention, the identification step 17th will only be repeated when new data is in the DRAM memory 1 written or older of the data to be retained 9 in the DRAM memory 1 have been deleted, which can happen, for example, if the computer system 6th meanwhile in the normal operating state 14th had changed. The refresh step 18th can, however, be repeated at regular intervals even if there is no new data in the DRAM memory 1 written and no older data in the DRAM memory 1 have been deleted. As the 6th illustrated, can also after the identification step 17th the refresh step 18th be repeated at periodic intervals.

• Im Schritt D liest der host controller 4 zunächst den DRAM-Speicher 1 aus und extrahiert dadurch das komprimierte Speicherabbild 19, welches zuvor im Bereitschaftsbetriebszustand 15 während des Identifikationsschritt 17 erzeugt wurde. Anschließend dekomprimiert der host controller 4 im Schritt E mit Hilfe eines dafür eingerichteten Chipsets 16 das komprimierte Speicherabbild 19 in einen dekomprimiert Speicherinhalt 21 und legt diesen im Zwischenspeicher 11 ab.

To now ensure the smooth operation of the computer system 6th after relocating the computer system 6th from the standby mode 15th in the normal operating state 14th a procedure as in 5 illustrated proposed: So that the computer system 6th to the original memory contents 22nd after transition to normal operating status 14th can access again, the modification of the data, ie in particular the data compression, must first be undone. For this purpose, a so-called wake-up process 20 is carried out, which comprises three steps D to F, such as 5 shows:

• In step D, the host controller 4 first reads the DRAM memory 1 and extracts the compressed memory image 19th , which was previously in standby mode 15th during the identification step 17th was generated. The host controller 4 then decompresses in step E with the aid of a chipset set up for this purpose 16 the compressed memory image 19th into a decompressed memory content 21 and stores it in the buffer 11 from.

The host controller 4 then again writes to the DRAM memory in step F 1 with the decompressed memory content 21 which has just returned to the original memory contents 22nd corresponds to. This just becomes the memory state of the DRAM memory 1 restored to the one before the computer system entered 6th in the standby mode 15th prevailed, as based on a comparison of the 5 at the bottom with the 3 can be seen at the very top. Thus, the DRAM memory has just become the original state 1 before the transition of the computer system 6th in the standby mode 15th restored.

As a result, the computer system can 6th after a certain latency, which is required for the steps DF described above, to the original memory content 22nd of the DRAM memory 1 access to the full.

The latency time can be shortened with a further refinement of the method, as follows using the 9 The following is explained: For this purpose, the entire read-out memory content 22nd of the DRAM memory 1 in for the operation of the computer system 6th critical data 23 and non-critical data 24 divided. In other words, there is a classification in the DRAM memory 1 stored data based on the question, whether the respective data at the transition of the computer system 6th from the standby mode 15th in the normal operating state 14th may or may not be needed initially.

After the data has been subdivided, it is displayed as in the example of 3 compressed, with the critical data 23 into a first partition 25th of the DRAM memory 1 are written while the non-critical data 24 into a second partition 26th of the DRAM memory 1 to be written. As at the top in 9 recognizable is the first partition 25th straight through the first two memory banks 2 , ie “bank 0” and “bank 1”, are formed while the second partition 26th through the memory banks 2 "Bank 2" and "Bank 3" are formed.

When transitioning from the standby mode 15th in the normal operating state 14th the host controller 4 then does not read the entire compressed memory image 19th from the DRAM memory 1 off, just the first partition 25th , that is, the compressed critical data 23 , 28 from the memory banks 2 "Bank 0" and "bank 1". After this data has been decompressed, the host controller 4 then writes a decompressed memory image of this critical data 23 in the first partition 25th back, so that the critical data now comes from software applications 8th mediated via the host controller 4 from the DRAM memory 1 can be read out (compare 1 ). This enables rudimentary operation of the computer system after a very short latency period 6th guaranteed.

After reading out the first partition 25th can then also use a background process to create the second partition 26th read out in an analogous manner, decompressed and then as decompressed non-critical data 24 , 28 again from the host controller 4 into the DRAM memory 1 back what is written in 9 is shown below the dashed horizontal line.

After a second latency period, the original memory content is available 22nd fully available again for reading. However, it must be taken into account here that, for example, the critical data 23 originally typically across the entire DRAM memory 1 were randomly distributed and by rearranging the data during the identification step 17th after the transition from the standby mode 15th in the normal operating state 14th in the first partition 25th of the DRAM memory 1 have been concentrated.

Since the computer system 6th However, this rearrangement of the data has done itself, it is ensured that the computer system 6th on all relevant data 9 of the original memory contents 22nd after completing the wake-up process 20th can access again. For this approach it is of great advantage if the two partitions 25th and 26th just have no overlap, so critical data 23 of uncritical data 24 are securely separable. It is also used for a particularly fast transition from the standby mode 15th in the normal operating state 14th advantageous if the first partition 25th is designed to be as small as possible, i.e. with sufficient storage capacity to store all of the critical data that is typically required 23 to be able to record in decompressed form.

All of the procedures described above are carried out in the computer system 6th implemented in that a computer program product according to the invention is stored in an internal memory of the computer system 6th is loaded, this computer program product comprising a software code generated by the computer system 6th is carried out in order to implement the method according to the invention.

The 7th and 8th finally show a preferred embodiment of a DRAM memory 1 of a computer system according to the invention 6th . As can be seen, the DRAM memory 1 formed by four LPDDRx memory modules 3 arranged in parallel, which provide a total of 8 memory banks ("bank 0 ... bank 7"). Here, each of the four LPDDRx memory chips 3 is organized with a bit data width of 32, so that a data bus 5 is formed with a bit width of 128, as in 7th and 8th illustrated please do not wait for me to eat. As the 8th shows by way of example, there are just four of the memory banks 2 from the DRAM refresh cycle 7th locked out.

In summary, for the purpose of energy saving and thus prolonged operation of a computer system 6th , which is a DRAM memory 1 has consisting of several memory banks 2 whose memory contents are each individually by means of a DRAM refresh cycle 7th Can be refreshed, suggested that by reading out the DRAM memory 1 Data 9 are recorded, which are to be obtained that subsequently this data 9 in compressed form in the DRAM memory 1 are written back, in particular with fewer memory banks 2 with data to be obtained 9 can be described as a number of the memory banks 2 , the data to be preserved before reading out 9 contained, and that ultimately only those of the memory banks 2 by means of the DRAM refresh cycle 7th periodically refreshed when the compressed data is written 28 into DRAM memory 1 with compressed data to be preserved 9 , 28 have been rewritten.

List of reference symbols

1

DRAM memory

2

Memory bank (of 1)

3

Memory chip

4th

host controller

5

Data bus

6th

Computer system

7th

DRAM refresh cycle

8th

Software application

9

data to be obtained

10

no data / data not to be obtained

11

Cache

12th

memory bank (s) excluded from refreshing

13th

memory bank (s) to be refreshed

14th

Normal operating condition

15th

Stand-by mode

16

Chipset

17th

Identification step

18th

Refresh step

19th

compressed memory image (of 1)

20th

Wake up process

21

decompressed memory content

22nd

original memory content

23

critical data

24

non-critical data

25th

first partition

26th

second partition

27

decompressed data

28

compressed data

Claims (13)

A method for the energy-saving operation of a computer system (6), in particular an in-vehicle infotainment (IVI) system, with - a DRAM memory (1) based on a dynamic random access memory (DRAM), which has several individually addressable memory banks (2 ), the memory contents of which can be refreshed electronically by means of a DRAM refresh cycle (7) and - a host controller (4) for reading and writing to the DRAM memory (1), - the computer system (6) from a normal operating state ( 14) can be put into a standby mode (15), in which the total energy consumption of the computer system (6) is reduced compared to the normal operating mode (14), characterized in that in the standby mode (15) - in an identification step (17) those of the memory banks (2) to be identified as memory banks (12) to be excluded that contain no data or currently no longer required data (10) and that - in a In the refreshing step (18), all remaining memory banks (13) containing data (9) to be received are refreshed by means of the DRAM refresh cycle (7), while the memory banks (12) to be excluded are excluded from the DRAM refresh cycle become. Procedure according to Claim 1 - wherein the identification step (17) comprises a modification, preferably a rearrangement, of the data (9) to be received on the memory banks (2), and / or - preferably lossless, data compression of the data (9) to be received, - preferably in such a way that a number of memory banks (2) which are excluded from the DRAM refresh cycle (7) in the refresh step (18) is increased compared to a number of memory banks (2) which were excluded before the identification step (17) contained no data or data (10) no longer required and / or such that a number of memory banks (2) that are refreshed in the refresh step (18) by means of the DRAM refresh cycle (7) is reduced compared to one Number of memory banks (2) which contained data (9) to be obtained before the identification step (17) and / or such that - after the identification step (17), respective memory banks (2), in particular individual memory locations, are stored in which the data (9) to be obtained are currently stored in the DRAM memory (1) are known. Procedure according to Claim 1 or 2 , wherein the identification step (17) comprises the following steps AC: A. the entire memory content of the DRAM memory (1) is read out; B. the entire memory content read out is compressed into a compressed memory image (19), preferably with a maximum available compression rate and / or loss-free; C. the compressed memory map (19) is written into the DRAM memory (1). Procedure according to Claim 3 - wherein in the identification step (17), those of the memory banks (2) of the DRAM memory (1) are identified as memory banks (12) to be excluded which are not written to in step C and / or - wherein in the refreshing step (18) those of the memory banks (2) are refreshed which have been written with the compressed memory image (19) in step C. Method according to one of the Claims 3 to 4th , wherein - in step C fewer of the memory banks (2) are written than a number of the memory banks (2) that contained data (9) to be obtained before step C and / or - wherein in step C individual memory banks (2) that contain to be received data (9) are overwritten with the compressed memory image (19) and / or - in the refresh step (18) individual of the memory banks (2) are excluded from the DRAM refresh cycle (7) that were prior to step C contained data to be obtained (9). Method according to one of the preceding claims, - The identification step (17) is only repeated when new data has been written to the DRAM memory (1) or older data has been deleted in the DRAM memory (1), - In particular, the refreshing step (18) being repeated at regular intervals even if no new data has been written to the DRAM memory (1) and no older data has been deleted in the DRAM memory (1) and / or where - after the identification step (17), the refreshing step (18) is repeated periodically. Method according to one of the Claims 3 to 6th , whereby when the computer system (6) is moved from the standby operating state (15) to the normal operating state (14) - the modification, in particular the rearrangement, of the data and / or the data compression is reversed and / or - a wake-up process ( 20), which comprises the following steps DF: D. the compressed memory map (19) is read from the DRAM memory; E. the read-out compressed memory image (19) is decompressed into a decompressed memory content (21); F. the decompressed memory content (21) is written into the DRAM memory (1), - preferably so that the computer system (6) in the normal operating state (14) after a latency period on an original memory content (22) of the DRAM memory (1), in particular which corresponds to the decompressed memory content (21), can access the full extent before the identification step (17) is carried out. Method according to one of the preceding Claims 3 to 7th , wherein in the identification step (17) - the read out entire memory content (22) is divided into critical data (23) and non-critical data (24), and - the critical data (23) in a first partition (25) of the DRAM memory ( 1) are written as compressed data, while the non-critical data (24) are written as compressed data in a second partition (26) of the DRAM memory (1). Procedure according to Claim 8 , wherein when the computer system (6) is moved from the standby operating state (15) to the normal operating state (14) and / or during the wake-up process (20) - initially only the first partition (25) is read out, decompressed and then as decompressed critical data (24, 27) is written into the DRAM memory (1) - in particular in such a way that a latency period after which access to the decompressed critical data (23, 27) is possible is shortened compared to a Latency time that would be required for access to the entire original memory content (22) of the DRAM memory (1), - preferably with the second partition (26) after reading out the first partition (25), in particular by means of a background process, read out, decompressed and then written as decompressed non-critical data (24, 27) in the DRAM memory (1) - particularly preferred, the first partition (25) being designed to be smaller than the second part tion (26) and / or wherein the first partition (25) and the second partition (26) do not have a common memory bank (2). Computer system (6), in particular designed as an in-vehicle infotainment (IVI) system, with - a DRAM memory (1) based on a dynamic random access memory (DRAM), which has several individually addressable memory banks (2), the memory contents of which can be refreshed electronically by means of a DRAM refresh cycle (7) and - a host controller (4) for reading and writing to the DRAM memory (1), - the computer system (6) being able to be put into a standby mode (15) is, in which the total energy consumption of the computer system (6) is reduced compared to a normal operating state (14), characterized in that the host controller (4) is set up to implement a method according to one of the preceding claims in interaction with the DRAM Execute memory (1). Computer system (6) according to Claim 10 , wherein the computer system (6), in particular the host controller (4), has a chipset (16) for compressing an entire memory content (22) of the DRAM memory (1), - preferably and a buffer (11) for buffering a compressed Memory images (19) and / or compressed data (28), - particularly preferred, and a chipset (16) for decompressing the compressed memory image (19) and / or compressed data (28). Computer system (6) according to Claim 10 or 11 , the DRAM memory (1) being constructed from several LPDDRx memory modules (3) each having several individually addressable memory banks (2), the respective memory contents of which can be refreshed electronically by means of a DRAM refresh cycle (7), preferably wherein the host controller (4) is set up to identify individual memory banks (2) as excluded memory banks (12) in the identification step (17) in each of the LPDDR4 memory modules (3), in particular where the host controller (4) does this is set up in the refreshing step (18) to refresh those memory banks (2) of the DRAM memory (1) which contain data (9) to be obtained by means of a partial array self refresh (PASR). Computer program product which is stored in a memory of a computer system (6), in particular according to Claim 10 or 11 , can be loaded and comprises a software code with the aid of which a method according to one of the Claims 1 to 9 is implemented when the software code is executed by the computer system (6).

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