DE102019121417B4 - Semiconductor device and high voltage device having a transistor device diode-connected between two HEMT devices and method of forming the same - Google Patents

Abstract

A semiconductor device comprising:a first HEMT device (104, 302) disposed within a semiconductor structure (212) and having a first source (S1), a first drain (D1) and a first gate (G1);a second HEMT Device (108, 304, 502) arranged within the semiconductor structure (212) in series with the first HEMT device (104, 302) and a second source (S2) connected to the first drain (D1), a second drain (D2) and a second gate (G2); anda diode-connected transistor device (110,306) disposed within the semiconductor structure (212) and connected between the first HEMT device (104,302) and the second HEMT device (108,304,502), and a third source (S3), a third gate (G3) and a third drain (D3) connected to the second gate (G2).

Description

BACKGROUND

Today's integrated chips have millions or billions of semiconductor devices formed on a semiconductor (e.g., silicon) substrate. Integrated chips (ICs) may employ many different types of transistor devices depending on an IC's application. In recent years, the growing market for cellular and RF (radio frequency) devices has resulted in a significant increase in the use of high voltage transistor devices. For example, high voltage transistor devices are often used in power amplifiers in RF transmit/receive chains because of their ability to handle high breakdown voltages (e.g., greater than about 50V) and high frequencies.

the U.S. 8,541,815 B2 describes a transistor circuit having a first HEMT and a second HEMT, the second HEMT limiting the voltage between the source and gate of the first HEMT. Further prior art is known from: U.S. 2017/0 271327 A1 , US 2012 / 0 098 037 A1 , U.S. 2013/0 271 208 A1 , U.S. 2013/0 020 614 A1 and U.S. 9,882,020 B2 . The invention provides a semiconductor device according to claim 1, a high voltage device according to claim 15 and a method according to claim 19. Refinements are given in the dependent claims.

character list

• 1 stellt eine schematische grafische Darstellung dar, die einige Ausführungsformen einer Hochspannungsvorrichtung zeigt, die eine Kaskodenstruktur mit mehreren Vorrichtungen mit Transistoren von einer hohen Elektronenbeweglichkeit (HEMT) aufweist.
• 2 zeigt eine Querschnittsansicht einer Hochspannungsvorrichtung, die eine Kaskodenstruktur mit mehreren HEMT-Vorrichtungen aufweist.
• Die 3A-5B zeigen einige zusätzliche Ausführungsformen von Hochspannungsvorrichtungen, die eine Kaskodenstruktur mit mehreren HEMT-Vorrichtungen aufweisen.
• Die 6A-8 zeigen Querschnittsansichten einiger Ausführungsformen einer gepackten Hochspannungsvorrichtung, die eine Kaskodenstruktur mit mehreren HEMT-Vorrichtungen aufweist.
• Die 9-15 zeigen Querschnittsansichten einiger Ausführungsformen eines Verfahrens zum Ausbilden einer Hochspannungsvorrichtung, die eine Kaskodenstruktur mit mehreren HEMT-Vorrichtungen aufweist.
• Die 16-25 zeigen Querschnittsansichten einiger alternativer Ausführungsformen eines Verfahrens zum Ausbilden einer Hochspannungsvorrichtung, die eine Kaskodenstruktur mit mehreren HEMT-Vorrichtungen aufweist.
• 26 stellt ein Ablaufdiagramm einiger Ausführungsformen eines Verfahrens zum Ausbilden einer Hochspannungsvorrichtung dar, die eine Kaskodenstruktur mit mehreren HEMT-Vorrichtungen aufweist.

Embodiments of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of presentation.

• 1 FIG. 12 is a schematic diagram showing some embodiments of a high voltage device having a cascode structure with multiple devices with high electron mobility transistors (HEMT).
• 2 FIG. 12 shows a cross-sectional view of a high voltage device having a cascode structure with multiple HEMT devices.
• the 3A-5B show some additional embodiments of high voltage devices having a cascode structure with multiple HEMT devices.
• the 6A-8 12 show cross-sectional views of some embodiments of a high voltage packaged device having a cascode structure with multiple HEMT devices.
• the 9-15 12 show cross-sectional views of some embodiments of a method for forming a high voltage device having a cascode structure with multiple HEMT devices.
• the 16-25 12 show cross-sectional views of some alternative embodiments of a method for forming a high voltage device having a cascode structure with multiple HEMT devices.
• 26 FIG. 12 illustrates a flow chart of some embodiments of a method for forming a high voltage device having a cascode structure with multiple HEMT devices.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first member over or on a second member in the following description may include embodiments where the first and second members are formed in direct contact, and may also include embodiments where additional members are between the first and the second element can be formed such that the first and second elements cannot be in direct contact. Also, in the present disclosure, reference numerals and/or letters may be repeated among various examples. This repetition is for the purpose of simplicity and clarity and does not in itself imply a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatial relational terms, such as "below", "below", "lower", "above", "upper" and the like, may be used herein for ease of description to indicate the relationship of one element or feature to another element or Describe feature (other elements or features) as shown in the figures. The spatial relation terms are intended to represent different orientations of the orientation in use or operation in addition to the orientation depicted in the figures. The device may be oriented (rotated 90 degrees or in other directions) in other ways, and the spatial notation used herein interpreted accordingly as well.

For the past four decades, silicon-based semiconductor transistors have been a standard in the semiconductor industry. Silicon is an inexpensive semiconductor material that provides good electrical properties. However, as semiconductor devices continue to scale (i.e. shrink) in size, it has become increasingly difficult to fabricate transistors on silicon substrates. As silicon devices become more difficult to scale, semiconductor devices based on alternative materials are receiving increasing attention. Gallium nitride (GaN) devices are a popular alternative to silicon devices. The GaN devices exhibit high mobility and a wide band gap, which is advantageous for high-voltage and/or high-power applications. The higher carrier mobility allows a GaN device to have a smaller physical size for a given on-resistance and/or breakdown voltage than a silicon device.

A common type of GaN device are the high electron mobility transistor (HEMT) devices. HEMT devices typically have a stacked structure with a GaN layer and an overlying electron donating material (e.g., AlGaN). A heterojunction between the GaN layer and the overlying electron donating material acts as a channel of the HEMT (instead of a doped region used in a MOSFET). In order to reduce the device cost, the GaN layer can be formed on a silicon substrate. GaN HEMT devices formed on a silicon substrate often suffer from lateral leakage between devices and vertical leakage between a device and the silicon substrate. At high voltages (e.g., greater than about 500 V), vertical conduction loss predominates, so a maximum breakdown voltage of a GaN device is proportional to a thickness of the GaN layer.

For example, to form a device with a maximum breakdown voltage of 650 V and an acceptable level of vertical conduction loss, a thickness of a GaN layer must be greater than about 5 µm (microns). In order to form a device with a maximum breakdown voltage of 1000 V and an acceptable level of vertical conduction loss, a GaN layer may have a thickness equal to approximately 10 µm. However, it is difficult to grow thick GaN layers (e.g. over 5 µm) on a silicon substrate because of lattice mismatch and deposition problems. Because it is difficult to grow thick GaN layers on a silicon substrate, forming a GaN HEMT device that has a high breakdown voltage (e.g., greater than about 1000 V) is a challenge.

The present disclosure relates, in some embodiments, to a high voltage device that includes a first HEMT device connected in series with a second HEMT device. A gate of the second HEMT device is connected to the first HEMT device via a diode-connected transistor. By having the first HEMT device connected in series with the second HEMT device, the two devices are able to operate together as an equivalent to a single high voltage transistor device that has a relatively high breakdown voltage (i.e., a breakdown voltage that is greater than the breakdown voltages of either the first HEMT or the second HEMT device). Therefore, the two HEMT devices with relatively thin GaN layers (e.g. 5 µm or less or less than 10 µm) can achieve a similar breakdown voltage as a high voltage device with a thicker GaN layer (e.g. greater than 5 µm).

1 FIG. 12 illustrates a schematic diagram of some embodiments of a high voltage device 100 including multiple high electron mobility transistor (HEMT) devices connected in series.

The high voltage device 100 has a cascode structure with a common source level 102 and a common gate level 106 . The common source stage 102 includes a first high electron mobility transistor (HEMT) device 104 having a first source S ₁ , a first drain D ₁ , and a first gate G ₁ . The common gate stage 106 includes a second HEMT device 108 having a second source S ₂ connected to the first drain D ₁ , a second drain D ₂ , and a second gate G ₂ . A diode-connected transistor 110 is connected between the first HEMT device 104 and the second HEMT device 108 and is configured to protect the first HEMT device 104 from high voltages (eg, in the second HEMT device 108) that could damage the first HEMT device 104. The diode-connected transistor 110 has a third gate G ₃ , a third source S ₃ connected to either the first gate G ₁ or the first source S ₁ of the first HEMT device 104, and a third drain D ₃ , connected to the second gate G ₂ of the second HEMT device 108 .

The first HEMT device 104 , the second HEMT device 108 and the diode connected transistor 110 are arranged within a package component 101 . In some embodiments, the first HEMT device 104 may be an enhancement mode device (i.e., a normally off device). In various embodiments, the second HEMT device 108 may be an enhancement mode device (i.e., a normally off device) or a depletion mode device (i.e., a normally on device). In some embodiments, diode connected transistor 110 may be an enhancement mode HEMT device.

By having the first HEMT device 104 in series with the second HEMT device 108, the high voltage device 100 is able to operate in a manner equivalent to a single high voltage transistor device. For example, the first HEMT device 104 and the second HEMT device 108 are configured to jointly define a common source Sc, a common drain DC and a common gate _{Gc of} the high voltage device 100 . The high voltage device 100 has a breakdown voltage that is greater than the breakdown voltages of either the first HEMT device 104 or the second HEMT device 108 . For example, in some embodiments, the first HEMT device 104 and the second HEMT device 108 may each have breakdown voltages of approximately 650V, while the high voltage device 100 may have a breakdown voltage of approximately 1200V. By using the first HEMT device 104 and the second HEMT device 108 to operate as a single high voltage device, the high voltage device 100 is able to achieve a high breakdown voltage while using inexpensive HEMT devices (where eg HEMT devices can be used with a GaN layer having a thickness of less than 10 µm).

In addition, the high voltage device 100 achieves a capacitance in excess of prior art switching devices (e.g., single HEMT devices, silicon carbide MOSFETS, etc.) and therefore the disclosed high voltage device 100 has good switching performance. For example, connecting the first HEMT device 104 and the second HEMT device 108 in series results in a high voltage device 100 having a total capacitance that is less than both the first HEMT device 104 and the second HEMT device 108 (thereby (e.g., it turns out that the disclosed high voltage device 100 has a capacitance that is one to two orders of magnitude smaller than prior art switching devices). This leads to improved figures of merit describing the switching characteristics of the device. For example, Qoss*Ron (where Qoss: MOSFET output capacitance charge and Ron: on-resistance), a figure of merit describing the process of high-speed switching of devices (describing e.g. resonant source-drain transition time), can be more than twice as good as conventional ones silicon carbide MOSFET devices.

2 FIG. 2 shows a cross-sectional view of a high voltage device 200 having a cascode structure with multiple HEMT devices. It will be clear that the here (e.g. in the 2 , 3B , 4B etc.) cross-sectional views illustrated are schematic views and may not be representative of sizes and/or shapes of some components in the device.

The high voltage device 200 includes a first HEMT device 104, a second HEMT device 108, and a diode connected transistor 110 disposed within a semiconductor structure 212. FIG. The semiconductor structure 212 includes a substrate 202 , a channel structure 204 over the substrate 202 , and an active structure 206 over the channel structure 204 . The substrate 202 includes a first semiconductor material, the channel structure 204 includes a second semiconductor material, and the active structure 206 includes a third semiconductor material. The second semiconductor material and the third semiconductor material have band gaps that form a heterojunction between the channel structure 204 and the active structure 206 . The heterojunction confines the electrons to a quantum well that forms a two-dimensional electron gas (2DEG) 205 along an interface between the channel structure 204 and the active structure 206 .

In some embodiments, the first semiconductor material may be silicon, the second semiconductor material may be gallium nitride, and the third semiconductor material may be aluminum gallium nitride be rid In other embodiments, the second semiconductor material and the third semiconductor material may include different III-V semiconductors (eg, GaAs, GaSb, or the like). In some embodiments (not shown), a buffer layer may be arranged between the first semiconductor material and the second semiconductor material. The buffer layer is configured to reduce a lattice mismatch between the first semiconductor material and the second semiconductor material. In some embodiments, the buffer layer may include aluminum nitride, for example.

In the semiconductor structure 212, a plurality of first isolation regions 208 may be disposed between two or more of the first HEMT device 104, the second HEMT device 108, and the diode-connected transistor 110. FIG. The plurality of first isolation regions 208 are configured to provide electrical isolation between the first HEMT device 104 , the second HEMT device 108 and/or the diode connected transistor 110 . In some embodiments, the plurality of first isolation regions 208 are arranged within the channel structure 204 and the active structure 206 . In some embodiments, the plurality of first isolation regions 208 may include regions doped (e.g., with fluorine dopants, oxygen dopants, or the like). In other embodiments, the plurality of first isolation regions 208 may include a dielectric material (e.g., a shallow trench isolation structure).

A second isolation region 210 is also disposed between the first HEMT device 104 and the second HEMT device 108 . The second isolation region 210 is configured to provide electrical isolation between the first HEMT device 104 and the second HEMT device 108 . In some embodiments, the second isolation region 210 may include a doped isolation region. In other embodiments, the second isolation region 210 may be a region that is free of semiconductor material. For example, in some such embodiments, the semiconductor structure 212 may include a first region (e.g., a first die) and a second region (e.g., a second die) that have outermost sidewalls that are laterally separated by a non-zero distance. In some embodiments, the first HEMT device 104 and the diode connected transistor 110 may be located within the first region and the second HEMT device 108 may be located within the second region.

The first HEMT device 104, the second HEMT device 108 and the diode connected transistor 110 each have a gate structure 214 disposed over the active structure 206 between a source contact 216s and a drain contact 216d. The gate structure 214, source contact 216s, and drain contact 216d define: a first gate G ₁ , a first source S ₁ , and a first drain D ₁ of the first HEMT device 104; a second gate G ₂ , a second source S ₂ and a second drain D ₂ of the second HEMT device 108; and a third gate G ₃ , third source S ₃ , and third drain D ₃ of diode connected transistor 110. In some embodiments, the distance from a gate to a drain for the first HEMT device 104, the second HEMT device 108 and/or the diode connected transistor 110 are in a range between about 15 microns (µm) and about 20 µm. For example, the distance from a gate (eg, the first gate G ₁ ) to a drain (eg, the first drain D ₁ ) may be approximately 18 μm.

Gate structure 214 includes a bottom gate portion 214a and a gate electrode 214b disposed over bottom gate portion 214a. In some embodiments, the bottom gate portion 214a may include a dielectric material (e.g., an oxide, a nitride, or the like). In other embodiments, the lower gate portion 214a may comprise a semiconductor material (e.g., p-doped gallium nitride). In some embodiments, the gate electrode 214b may include a metal (e.g., aluminum, titanium, copper, tungsten, tantalum, or the like) or doped polysilicon. In some embodiments, the bottom gate portions 214a of the first HEMT device 104, the second HEMT device 108, and/or the diode connected transistor 110 may comprise different materials. For example, in some embodiments, the bottom gate portion 214a of the first HEMT device 104 and the diode connected transistor 110 may comprise a dielectric material, while the bottom gate portion 214a of the second HEMT device 108 may comprise p-doped GaN. In other embodiments, the bottom gate portions 214a of the first HEMT device 104, the second HEMT device 108, and the diode connected transistor 110 may comprise a same material (e.g., a dielectric material).

In order to provide a large breakdown voltage (eg, a breakdown voltage greater than about 1200 V) for the high-voltage device 200, the effective widths of the first gate G ₁ , the second gate G ₂ , and the third gate G ₃ may have a relatively large dimension. In some embodiments, the effective width of the first gate G ₁ , the second gate G ₂ and the third gate G ₃ collectively range from about 200 millimeters (mm) to about 300 mm. In some such embodiments, the first gate G ₁ and/or the second gate G ₂ may each have effective widths in a range between about 100 mm and about 150 mm, while the effective width of the third gate G ₃ is in a range between about 5 mm and 15 mm. For example, the effective width of the first gate G ₁ and/or the second gate G ₂ may be approximately 120 mm, while the effective width of the third gate G ₃ may be approximately 11.2 mm. In some embodiments, the first gate G ₁ , the second gate G ₂ , and the third gate G ₃ may have effective widths that extend along multiple different directions (eg, along a first direction and a second direction perpendicular to the first direction). . By extending the effective widths of the first gate G ₁ , the second gate G ₂ and the third gate G ₃ along several different directions, the gates can be arranged in an arrangement that is accommodated in an area smaller than the effective ones widths (e.g. in an area of 10 mm ² ).

A dielectric structure 218 is disposed over the active structure 206 . Dielectric structure 218 surrounds gate structure 214, source contact 216s and drain contact 216d. Gate structure 214, source contact 216s, and drain contact 216d are electrically connected by one or more conductive layers (not shown) (such as in FIG 1 is shown). In some embodiments, the one or more conductive layers may include interconnect layers disposed within dielectric structure 218 . In some additional embodiments, the one or more conductive layers may be redistribution layers, conductive layers in an intermediate carrier substrate, conductive traces on a printed circuit board, or the like.

the 3A-3B illustrate some additional embodiments of a high voltage device having a cascode structure with multiple high electron mobility transistor devices.

As shown in a schematic diagram 300 of FIG 3A As shown, the high voltage device includes a first HEMT device 302, a second HEMT device 304, and a diode connected HEMT device 306. FIG. The first HEMT device 302 and the diode connected HEMT device 306 are arranged in a first die 308a, while the second HEMT device 304 is arranged in a second die 308b. The first HEMT device 302 has a first source S ₁ , a first drain D ₁ and a first gate G ₁ . The second HEMT device 304 has a second source S ₂ connected to the first drain D ₁ , a second drain D ₂ and a second gate G ₂ . The diode-connected HEMT device 306 has a third source S ₃ connected to the first gate G ₁ , a third drain D ₃ connected to the second gate G ₂ , and a third gate G ₃ connected to the is connected to the third source S ₃ . The first HEMT device 302, the second HEMT device 304, and the diode connected HEMT device 306 are enhancement mode devices (ie, normally off devices) that are in an off state when zero bias is applied to their gates.

The first HEMT device 302 and the second HEMT device 304 provide the high voltage device with a common source S _C , a common drain D _C and a common gate G _C . During operation, the common source SC may be _maintained at V _SS (eg, ground) and the common drain _DC may be maintained at V _DD (eg, 1000V). A bias applied to a common gate terminal Gc turns on both the first HEMT device 302 and the second HEMT device 304 . By connecting the first gate G ₁ to the second gate G ₂ using the diode-connected HEMT device 306, the first gate G ₁ is not inadvertently driven by a gate-drain voltage (V _GD ) of the second HEMT device 304 and also protects the first gate G ₁ from a possible high gate-source voltage (V _GS ) of the second HEMT device 304 .

As shown in cross-sectional view 310 of FIG 3B As shown, the first HEMT device 302 and the diode connected HEMT device 306 are located within the first die 308a, and the second HEMT device 304 is located within the second die 308b, which is different from the first die 308a. The first die 308a and the second die 308b have outermost sidewalls separated by a non-zero distance S . The non-zero distance separates the first die 308a from the second die 308b to avoid leakage between the first HEMT device 302 and the second HEMT device 304 .

In some embodiments, the first die 308a includes a first substrate 312a comprising a first semiconductor material, a first channel layer 314a overlying the first substrate 312a and comprising a second semiconductor material, and a first active layer 316a positioned over the first channel layer 314a and comprising a third semiconductor material different from the second semiconductor material. In some embodiments, the second die 308b includes a second substrate 312b comprising the first semiconductor material, a second channel layer 314b positioned over the second substrate 312b and comprising the second semiconductor material, and a second active layer 316b overlying the second channel layer 314b and comprises the third semiconductor material. In some embodiments, the first semiconductor material may include or be silicon, the second semiconductor material may include or be gallium nitride, and the third semiconductor material may include or be aluminum gallium nitride.

In some embodiments, the first channel layer 314a and the second channel layer 314b may comprise GaN with thicknesses less than or equal to about 5 microns because GaN at such thicknesses can be reliably formed on silicon with relatively little effort. In some other embodiments, the first channel layer 314a and the second channel layer 314b may comprise GaN having thicknesses less than or equal to about 10 microns because GaN at such thicknesses can be reliably formed on silicon with relatively little effort. In still other embodiments, the first channel layer 314a and the second channel layer 314b may comprise GaN with thicknesses greater than 5 microns. For example, the first channel layer 314a and the second channel layer 314b may comprise GaN with thicknesses ranging from about 5 microns to about 10 microns.

A plurality of first isolation regions 208 are disposed within the first die 308a between the first HEMT device 302 and the diode connected HEMT device 306 . The plurality of first isolation regions 208 may include doped regions dividing (ie, interrupting) a 2DEG lying between the first channel layer 314a and the first active layer 316a. In some embodiments, the plurality of first isolation regions 208 may include oxygen dopants, fluorine dopants, or the like. The plurality of first isolation regions 208 may extend continuously around the first HEMT device 302 , the second HEMT device 304 , and the diode connected HEMT device 306 . In some embodiments, the plurality of first isolation regions 208 have a first width w ₁ along the outer edges of the first die 308a and a second width w ₂ immediately between the first HEMT device 302 and the diode connected HEMT device 306 . In some embodiments, the second width w2 is greater than the first width w1 because of a dicing operation used to singulate the first die 308a.

The first HEMT device 302, the diode connected HEMT device 306 and the second HEMT device 304 each have a source contact 216s, a drain contact 216d and a gate structure 318 formed within a first dielectric structure 324a and a second dielectric structure 324b disposed over the first active layer 316a and the second active layer 316b. One or more conductive layers 326 are connected to the source contact 216s, the drain contact 216d and the gate structure 318 of the first HEMT device 302, the diode connected HEMT device 306 and the second HEMT device 304. The one or more conductive layers 326 are configured to electrically connect the first HEMT device 302, the diode connected HEMT device 306 and the second HEMT device 304, as shown in FIG 3A is shown. In some embodiments, the one or more conductive layers 326 may include interconnect layers (eg, interconnect wires and/or vias), bond wires, or the like.

Source contact 216s and drain contact 216d comprise a conductive material such as a metal such as aluminum, tungsten, copper, gold, titanium, tantalum, or the like. Since the first HEMT device 302, the second HEMT device 304, and the diode connected HEMT device 306 are enhancement mode devices in some embodiments, the gate structure 318 may include a doped layer of semiconductor material 320 and a gate electrode 322 , which is arranged over the doped layer of semiconductor material 320. FIG. In some embodiments, the doped layer of semiconductor material 320 may include a GaN layer with p-type dopants. In some embodiments, gate electrode 322 may include a metal such as aluminum, tungsten, copper, gold, titanium, tantalum, or the like.

the 4A-4B illustrate some additional embodiments of a high voltage device comprising a cascode with multiple HEMT devices.

As shown in a schematic diagram 400 of FIG 4A As shown, the high voltage device includes a first HEMT device 302, a second HEMT device 304, and a diode connected HEMT device 306. FIG. The first HEMT device 302, the second HEMT device 304 and diode connected HEMT device 306 are disposed within die 402 . The first HEMT device 302, the second HEMT device 304, and the diode connected HEMT device 306 are enhancement mode devices (ie, normally off devices) that are in an off state when zero bias is applied to their gates.

As shown in cross-sectional view 404 of FIG 4B As shown, the first HEMT device 302, the second HEMT device 304, and the diode connected HEMT device 306 are disposed within the die 402, which includes a substrate 406 having a first doping type, an epitaxial buffer layer 408 over the substrate 406, a channel layer 410 over the epitaxial buffer layer 408 and an active layer 412 over the channel layer 410 . In some embodiments, the substrate 406 and the epitaxial buffer layer 408 may include or be silicon with the first doping type (eg, p-type), the channel layer 410 may include or be gallium nitride, and the active layer 412 may include or be aluminum gallium nitride. In some embodiments, channel layer 410 may be gallium nitride having a thickness less than or equal to about 10 microns. In some embodiments, channel layer 410 may be gallium nitride having a thickness less than or equal to about 5 microns.

An isolation structure 414 is arranged within the die 402 . The isolation structure 414 has a second doping type (e.g. n-type) that differs from the first doping type. Isolation structure 414 includes a horizontally extending isolation region 414a laterally disposed between the sidewalls of one or more vertically extending isolation regions 414b. In some embodiments, the epitaxial buffer layer 408 is interposed between the isolation structure 414 and the channel layer 410 . A lattice defect may occur on the substrate 406 during the formation of the horizontally extending isolation region 414a. The epitaxial buffer layer 408 provides a consistent lattice to grow the channel layer 410 such that propagation of a lattice defect in the substrate 406 is avoided.

Conductive contacts 416 extend through channel layer 410 and active layer 412 to contact one or more vertically extending isolation regions 414b. Conductive contacts 416 are further connected to conductive contacts 418 disposed within dielectric structure 324 over active layer 412 . In some embodiments, conductive contacts 416 physically touch isolation structure 414 along a horizontal plane that extends along a top surface of epitaxial buffer layer 408 .

The conductive contacts 416 are configured to bias the isolation structure 414 to form a junction that electrically isolates the substrate 406 from the channel layer 410 of the second HEMT device 304 . By electrically isolating the substrate 406 from the channel layer 410 of the second HEMT device 304, leakage between the devices through the substrate 406 is mitigated. In some embodiments, an insulating layer 417 comprising one or more dielectric materials may be disposed along the sidewalls of the conductive contacts 416. In some such embodiments, isolation layer 417 may include a first dielectric material contacting epitaxial buffer layer 408 , a second dielectric material contacting channel layer 410 , and a third dielectric material contacting active layer 412 . In other embodiments, conductive contacts 416 may touch channel layer 410 directly.

In some embodiments, a plurality of first isolation regions 208 may extend continuously around first HEMT device 302 and diode-connected HEMT device 306 . In some embodiments, the conductive contacts 416 and underlying isolation structure 414 may extend continuously around the second HEMT device 304 . In other embodiments, the isolation structure 414 may extend continuously around the second HEMT device 304 while the conductive contacts 416 may have separate portions disposed over a portion of the isolation structure 414 .

the 5A-5B illustrate some additional embodiments of a high voltage device comprising a cascode with multiple HEMT devices.

As shown in a schematic diagram 500 of FIG 5A As shown, the high voltage device includes a first HEMT device 302, a second HEMT device 502, and a diode connected HEMT device 306. FIG. The first HEMT device 302 and the diode connected HEMT device 306 are arranged within a first die 308a, while the second HEMT device 502 is arranged within a second die 308b. The first HEMT device 302 and the diode connected HEMT device 306 are enhancement mode devices (i.e. normally off devices) that are in an off state when zero bias is applied to their gates. The second HEMT device 502 is a depletion-mode device (ie, normally-on devices) that is in an on-state when zero bias is applied to its gate.

The first HEMT device 302 has a first source S ₁ , a first drain D ₁ and a first gate G ₁ . The second HEMT device 502 has a second source S ₂ connected to the first drain D ₁ , a second drain D ₂ and a second gate G ₂ . The diode-connected HEMT device 306 has a third source region S ₃ connected to the first source S ₁ and a third drain D ₃ connected to the second gate G ₂ . By connecting the first source S ₁ to the second gate G ₂ using the diode connected HEMT device 306, the first HEMT device 302 is not inadvertently driven by a gate-drain (VGD) voltage of the second HEMT device 304 affected.

As shown in cross-sectional view 504 of FIG 5B As shown, the first HEMT device 302 and the diode connected HEMT device 306 are disposed within the first die 308a and the second HEMT device 502 is disposed within the second die 308b. The first die 308a and the second die 308b have outermost sidewalls separated by a non-zero distance S .

The first HEMT device 302, the diode connected HEMT device 306 and the second HEMT device 502 each have a source contact 216s and a drain contact 216d. Since the first HEMT device 302 and the diode connected HEMT device 306 are enhancement mode devices, the first HEMT device 302 and the diode connected HEMT device 306 have a gate structure 318 with a doped layer of semiconductor material 320 and a gate electrode 322 over the doped layer of semiconductor material 320 . Since the second HEMT device 502 is a depletion mode device, the second HEMT device 502 has a gate structure 506 with a dielectric layer 508 and a gate electrode 322 over the dielectric layer 508 .

the 6A-6B show some embodiments of a high voltage packaged device having a cascode structure with multiple HEMT devices. 6A FIG. 6 shows a cross-sectional view 600 of the packaged high voltage device. 6B 620 illustrates a top view of the packaged high voltage device.

The high voltage packaged device includes a die pad 602 over which a first die 308a and a second die 308b are bonded. In some embodiments, the first die 308a and the second die 308b are bonded to the die pad 602 via an adhesive layer 604 . In various embodiments, the adhesive layer 604 may include an adhesive, an epoxy, or the like. The first die 308a and the second die 308b are typically separated by a non-zero distance S . In some embodiments, the non-zero distance S may range from about 1 micron to about 1 mm to ensure electrical isolation between the first die 308a and the second die 308b.

Surrounding the die pad 602 is a molding compound 612 that extends continuously over the first die 308a and the second die 308b. Extending from the interior of the molding compound 612 to the outside of the molding compound 612 are a plurality of leadframes 614. In some embodiments, the molding compound 612 may include epoxy, silicon, silica filler, and/or other types of polymers. One or more bond wires 616 are configured to connect the first die 308a and the second die 308b. The one or more bond wires 616 further connect the first die 308a and the second die 308b to the plurality of leadframes 614.

As illustrated in cross-sectional view 600, first die 308a includes a first dielectric structure 324a surrounding a plurality of first conductive interconnect layers 606a. The plurality of first conductive interconnect layers 606a electrically connect the first HEMT device 302 and the diode connected HEMT device 306 to the bond pads 608 over the first dielectric structure 324a. In some embodiments, a passivation layer 610 may overly the bond pads 608 . The second die 308b includes a second dielectric structure 324b surrounding a plurality of second conductive interconnect layers 606b. The second plurality of conductive interconnect layers 606b electrically connects the second HEMT device to the bond pads 608 over the second dielectric structure 324b. In some embodiments, the first dielectric structure includes 324a and/or the second dielectric structure 324b stacked ILD layers each comprising silicon dioxide, doped silicon dioxide (e.g., silicon dioxide doped with carbon), silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), fluorinated silicate glass (FSG), or the like exhibit.

In some embodiments (not shown), the first conductive interconnect layers 606a are configured to electrically connect a first gate G ₁ of the first HEMT device 302 to a third source S ₃ and a third gate G ₃ of the diode-connected HEMT device 306 . The one or more bond wires 616 are configured to connect a first drain D ₁ of the first HEMT device 302 to a second source S ₂ of the second HEMT device 304 and also the second gate G ₂ of the second HEMT device 304 to a third drain D ₃ of diode connected HEMT device 306 .

In other embodiments (not shown), the plurality of first conductive interconnect layers 606a are configured to electrically connect a first source S ₁ of the first HEMT device 302 to a third source S ₃ and a third gate G ₃ of the diode-connected HEMT device 306 . The one or more bond wires 616 are configured to electrically connect a first drain D ₁ of the first HEMT device 302 to a second source S ₂ of the second HEMT device 304 and also the second gate G ₂ of the second HEMT device 304 to to a third drain D ₃ of the diode connected HEMT device 306 .

7 FIG. 7 shows a cross-sectional view of some additional embodiments of a high voltage packaged device 700 having a cascode structure with multiple HEMT devices.

The high voltage packaged device 700 includes a die 402 disposed over a support substrate 702 (e.g., an interposer substrate). The die 402 includes a first HEMT device 302, a second HEMT device 304, and a diode connected HEMT device 306. FIG. A molding compound 704 is also disposed over the support substrate 702 and encapsulates the die 402.

Die 402 includes a dielectric structure 324 surrounding multiple conductive interconnect layers 706 . In some embodiments (not shown), the plurality of conductive interconnect layers 706 are configured to electrically connect a first gate G ₁ of the first HEMT device 302 to a third source S ₃ and a third gate G ₃ of the diode-connected HEMT device 306. electrically connect a first drain D ₁ of the first HEMT device 302 to a second source S ₂ of the second HEMT device 304 and also electrically connect the second gate G ₂ of the second HEMT device 304 to the third drain D ₃ of the diode connected HEMT - Device 306 to connect.

The die 402 is electrically connected to the support substrate 702 by means of a plurality of micro bumps 708 . A plurality of substrate vias (TSV) 710 extend through the support substrate 702 and electrically connect the plurality of micro bumps 708 to a plurality of solder bumps 714. In some embodiments, the one or more redistribution layers 712a and/or 712b may be along the top and/or bottom surfaces of the support substrate 702 to provide lateral routing between the TSV 710 and the plurality of microbumps 708 and/or the plurality of solder bumps 714.

8th 8 shows a cross-sectional view of some additional embodiments of a high voltage packaged device 800 having a cascode structure with multiple HEMT devices.

The high voltage packaged device 800 has a die pad 602 over which a die 402 is bonded. In some embodiments, die 402 is bonded to die pad 602 with adhesive layer 604 . The die pad 602 is encapsulated by a molding compound 612 that extends over the die 402 . A plurality of lead frames 614 extend from the interior of the molding compound 612 to the exterior of the molding compound 612 . One or more bonding wires 616 are configured to connect the die 402 to the plurality of lead frames 614 . In some embodiments, the one or more bond wires 616 are connected to the bond pads 608 and the lead frames 614 via solder bumps 618 .

Die 402 includes a dielectric structure 324 surrounding multiple conductive interconnect layers 706 . In some embodiments, the plurality of conductive interconnect layers 706 are configured to electrically connect a first gate G ₁ of the first HEMT device 302 to a third source S ₃ and a third gate G ₃ of the diode-connected HEMT device 306, a first drain D ₁ of the first HEMT device 302 to a second source S ₂ of the second HEMT device 304 and also the second gate G ₂ of the second HEMT device 304 to the third drain D ₃ of the as a diode connected HEMT device 306 .

the 9-15 9 show cross-sectional views 900-1500 of some embodiments of a method for forming a high voltage device having a cascode structure with multiple HEMT devices. Although the cross-sectional views 900-1500 shown in Figs 9-15 , will be described with reference to a method for forming a cascode structure with multiple HEMT devices, it will be appreciated that the methods illustrated in FIGS 9-15 illustrated methods are not limited to the manufacturing method but may be self-contained separately from the method.

As shown in cross-sectional view 900 of FIG 9 As shown, a substrate 312 is provided. The substrate 312 includes a semiconductor material having a first doping type (eg, a p-type dopant). In various embodiments, the substrate 312 may be any type of semiconductor body (eg, silicon, SiGe, SOI, etc.) as well as any other type of semiconductor associated with epitaxial, dielectric, or metal layers. The substrate 312 has a first HEMT device region 902 , a second HEMT device region 904 , and a diode connected HEMT device region 906 .

As in the cross-sectional view 1000 of 10 As shown, a channel layer 314 is formed over substrate 312 and an active layer 316 is formed over channel layer 314 . The channel layer 314 comprises a first material different from a second material of the active layer 316 . For example, in some embodiments, the channel layer 314 may include gallium nitride (GaN) and the active layer 316 may include aluminum gallium nitride (AlGaN). In various embodiments, the channel layer 314 and/or the active layer 316 may be deposited using deposition processes (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.) on the substrate 312 are formed. In some embodiments, channel layer 314 may be formed to a thickness less than or equal to about 5 microns to provide a high quality channel layer with relatively little effort.

As shown in cross-sectional view 1100 of FIG 11 As shown, a plurality of first isolation regions 208 are formed within the active layer 316 . The plurality of first isolation regions 208 may include doped regions extending into the interior of the channel layer 314 from a top surface of the active layer 316 . The plurality of first isolation regions 208 are positioned laterally between the first HEMT device region 902 , the second HEMT device region 904 , and the diode connected HEMT device region 906 .

In some embodiments, the plurality of first isolation regions 208 are formed by forming a first patterned mask layer 1102 over the active layer 316 and then implanting one or more dopants 1104 into the active layer 316 according to the first patterned mask layer 1102 . In some embodiments, the dopants 1104 may be implanted with an energy sufficient to infuse the dopants 1104 into the channel layer 314 . In some embodiments, a post-implant penetration anneal may be performed to diffuse the dopants. In some embodiments, the dopants 1104 may include oxygen dopants, fluorine dopants, or the like. In some embodiments, the first patterned mask layer 1102 may include a photoresist, for example.

The cross-sectional view 1200 of FIG 12A and cross-sectional view 1202 of FIG 12B 12 show alternative embodiments for forming a gate structure 214, a source contact 216s, and a drain contact 216d over the substrate 312 and within the first HEMT device region (902 of 11 ), the second HEMT device area (904 of 11 ), and the region of the diode-connected HEMT device (906 of 11 ). Gate structure 214, source contact 216s, and drain contact 216d define: a first gate G ₁ , a first source S ₁ , and a first drain D ₁ of a first HEMT device 104; a second gate G ₂ , a second source S ₂ and a second drain D ₂ of a second HEMT device 108; and a third gate G ₃ , a third source S ₃ and a third drain D ₃ of a diode-connected transistor 110.

In some embodiments shown in cross-sectional view 1200 of FIG 12A 1, the gate structure 214 in the first HEMT device 104, the second HEMT device 108, and the diode connected transistor 110 may be formed by depositing a bottom gate layer over the active layer 316. FIG. In some embodiments, the bottom gate layer may include a dielectric material (eg, an oxide, a nitride, or the like) or a semiconductor material (eg, p-doped GaN). the lower one Gate layer is patterned to define a lower gate portion 214a of gate structure 214 . A conductive layer is formed over the lower gate portion 214a and the active layer 316 . The conductive layer is patterned to define a gate electrode 214b, source contacts 216s and drain contacts 216d. In some embodiments, the bottom gate layer and the conductive layer may be patterned by forming photoresist layers over the bottom gate layer and the conductive layer, and then forming the bottom gate layer and the conductive layer in the areas not covered by the photoresist layers are covered, are etched. In such embodiments, the gate structure 214 may have a first height h1 that is greater than a second height h2 of the source contact 216s and the drain contact 216d. In some such embodiments, the bottom gate portion 214a may extend laterally beyond the outermost sidewalls of the gate electrode 214b.

In other embodiments shown in cross-sectional view 1202 of FIG 12B , the gate structure 214 in the first HEMT device 104, the second HEMT device 108 and the diode connected transistor 110 can be formed by placing a bottom gate layer over the active layer 316 and a conductive layer over the lower gate layer are deposited. The bottom gate layer and the conductive layer are then patterned using a similar masking layer (eg, photoresist layer) to define a gate structure 214 having a bottom gate portion 214a and a gate electrode 214b. A dielectric material 1204 is then deposited over the active layer 316 and the gate structure 214 . The dielectric material 1204 is selectively patterned to define openings in the dielectric material 1204. FIG. The openings are then filled with a conductive material, followed by a planarization process that defines source contact 216s and drain contact 216d. In such embodiments, the gate structure 214 may have a first height h ₁ that is less than a second height h ₂ of the source contact 216s and the drain contact 216d. In some such embodiments, the sidewalls of the lower gate portion 214a and the gate electrode 214b may be substantially aligned.

As shown in cross-sectional view 1300 of FIG 13 1, one or more conductive interconnect layers 606 are formed within a dielectric structure 324 that has been formed over active layer 316. FIG. In some embodiments (not shown), the one or more conductive interconnect layers 606 are configured to connect the first gate G ₁ of the first HEMT device 104 to the third source S ₃ and third gate G ₃ of the diode connected transistor 110 . In other embodiments, the one or more conductive interconnection layers 606 are configured to connect the first source S ₁ of the first HEMT device 104 to the third source S3 and the third gate G3 of the diode connected transistor 110 .

In some embodiments, the dielectric structure 324 may include multiple stacked ILD layers separated by multiple etch stop layers. In some embodiments, the plurality of conductive interconnect layers 706 may include alternating layers of interconnect wires and interconnect vias. In some embodiments, the plurality of conductive interconnect layers 706 may each be formed using a damascene process. In such embodiments, an ILD layer is formed over active layer 412 . The ILD layer is then etched to form a via hole and/or a trench that is filled with a conductive material (e.g., tungsten, copper, and/or aluminum). A chemical mechanical planarization (CMP) process is then performed to eliminate excess conductive material over the ILD layer.

In some embodiments, bond pads 608 may be formed on the one or more conductive interconnect layers 606 and/or the dielectric structure 324 . A passivation layer 610 may then be formed over the bond pads 608 . The bond pads 608 may be formed by depositing a conductive layer over the one or more conductive interconnect layers 606 and the dielectric structure 324 and then patterning the conductive layer to define the bond pads 608 . The passivation layer 610 can be formed by a deposition process followed by a patterning process.

As shown in cross-sectional view 1400 of FIG 14 As shown, the substrate 312 is diced along one or more scribe lines 1402 to form a first die 308a and a second die 308b. The first die 308a includes the first HEMT device 104 and the diode connected transistor 110 . The second die 308b includes the second HEMT device 108 . Although the first Die 308a and the second Die 308b as one same 1, it will be appreciated that in alternative embodiments, the first die 308a and the second die 308b may be formed in different substrates. For example, in some embodiments, the first die 308a is formed in a first wafer and the second die is formed in a second wafer that is different than the first wafer.

As shown in cross-sectional view 1500 of 15 As shown, the first die 308a and the second die 308b are housed within one package. In some embodiments, the first die 308a and the second die 308b may be bonded to a die pad 602 via an adhesive layer 604 . The first die 308a is then wire bonded to the second die 308b and a plurality of lead frames 614 using one or more bond wires 616 . Then, a molding compound is created around the first die 308a, the second die 308b, the die pad 602, and the plurality of leadframes 614. FIG.

In some embodiments (not shown), the one or more bonding wires 616 are configured to electrically connect a first drain D ₁ of the first HEMT device 104 to a second source S ₂ of the second HEMT device 108 and also the second gate G ₂ of the second HEMT device 108 to a third drain D ₃ of the diode connected transistor 110 . The electrical connections from the one or more conductive interconnect layers 606 and the one or more bond wires 616 cause the first HEMT device 104, the second HEMT device 108, and the diode-connected transistor 110 to operate as a single high-voltage device that has a common source, a common drain and a common gate (in 2 shown). The high voltage device has a breakdown voltage that is greater than that of either the first HEMT device 104 or the second HEMT device 108 .

the 16-23 16 show cross-sectional views 1600-2300 of some alternative embodiments of a method for forming a high voltage device having a cascode structure with multiple HEMT devices. Although the cross-sectional views 1600-2300 shown in Figs 16-23 are described with reference to a method for forming a cascode structure with multiple HEMT devices, it will be appreciated that the structures shown in FIGS 16-23 are not limited to the manufacturing process but may be self-contained separate from the process.

As shown in cross-sectional view 1600 of FIG 16 As shown, a substrate 406 is provided. The substrate 406 includes a semiconductor material having a first doping type (eg, a p-type dopant). In various embodiments, the substrate 406 may be any type of semiconductor body (eg, silicon, SiGe, SOI, etc.) as well as any other type of semiconductor associated with epitaxial, dielectric, or metal layers. The substrate 406 includes a first HEMT device region 902 , a second HEMT device region 904 , and a diode connected HEMT device region 906 .

As shown in cross-sectional view 1700 of 17 1, a horizontally extending isolation region 414a is formed within the substrate 406. As shown in FIG. The horizontally extending isolation region 414a has a doped region with a second doping type that differs from the first doping type of the substrate 406 . In some embodiments, the horizontally extending isolation region 414a may be formed by forming a first masking layer 1702 over the substrate 406 and then implanting one or more first dopants 1704 into the substrate 406 according to the first patterned masking layer 1702 . In some embodiments, the first masking layer 1702 may include a photoresist, for example.

As in the cross-sectional view 1800 of 18 As shown, an epitaxial buffer layer 408 is formed over the substrate 406 and the horizontally extending isolation region 414a. The epitaxial buffer layer 408 is configured to provide a consistent crystal lattice that prevents propagation of a crystal defect of the horizontally extending isolation region 414a into overlying layers. In some embodiments, the epitaxial buffer layer 408 may include a semiconductor material such as silicon. In some embodiments, the epitaxial buffer layer 408 may be of the same material as the underlying substrate 406 .

A channel layer 410 is formed over the epitaxial buffer layer 408 and an active layer 412 is formed over the channel layer 410 . The channel layer 410 has a different material than the active layer 412 . For example, in some embodiments, the channel layer 410 may include gallium nitride (GaN) and the active layer 412 may include aluminum gallium nitride (AlGaN). In various embodiments, the channel Layer 410 and/or active layer 412 may be formed using deposition processes (eg, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc.). In some embodiments, channel layer 410 may be formed to a thickness less than or equal to about 5 microns to provide a high quality channel layer with relatively little effort. In other embodiments, the channel layer 410 may be formed to a thickness that is less than or equal to about 10 microns. In still other embodiments, channel layer 410 may be formed to a thickness ranging from about 5 microns to about 10 microns.

As in the 1900 cross-sectional view of 19 As shown, a plurality of first isolation regions 208 are formed within active layer 316 . The plurality of first isolation regions 208 may include doped regions that extend vertically from a top surface of the active layer 316 into an interior of the channel layer 314 . The plurality of first isolation regions 208 are positioned laterally between the first HEMT device region 902 , the second HEMT device region 904 , and the diode connected HEMT device region 906 .

In some embodiments, the plurality of first isolation regions 208 are formed by forming a first patterned mask layer 1102 over the active layer 316 and then implanting one or more dopants 1104 into the active layer 316 according to the first patterned mask layer 1102 . In some embodiments, the dopants 1104 may be implanted with an energy sufficient to infuse the dopants 1104 into the channel layer 314 . In some embodiments, a penetration anneal may be performed to diffuse the dopants after implantation.

As in the 2000 cross-sectional view of 20 As shown, channel layer 410 and active layer 412 are selectively etched to define trenches 2002 that extend through channel layer 410 and active layer 412 . Trenches 2002 extend vertically from a top of active layer 412 to epitaxial buffer layer 408. In some embodiments, trenches 2002 may extend into epitaxial buffer layer 408 such that sidewalls of trenches 2002 respectively penetrate epitaxial buffer layer 408, channel layer 410 and the active layer 412 are defined. In some embodiments, channel layer 410 and active layer 412 may be selectively etched by forming a second patterned mask layer 2004 over active layer 412 and then exposing channel layer 410 and active layer 412 to one or more etchants 2006 in the areas which are not covered by the second patterned mask layer 2004.

As shown in cross-sectional view 2100 of FIG 21 1, the one or more vertically extending isolation regions 414b are formed within the epitaxial buffer layer 408 over the horizontally extending isolation region 414a. The one or more vertically extending isolation regions 414b have doped regions with the second doping type. The horizontally extending isolation region 414a and the one or more vertically extending isolation regions 414b together define an isolation structure 414 that is configured to separate the second HEMT device region 904 from the first HEMT device region 902 and the diode-connected HEMT device region 906 electrically isolate.

In some embodiments, the one or more vertically extending isolation regions 414b may be formed by selectively implanting one or more second dopants 2104 into the epitaxial buffer layer 408 according to a third patterned mask layer 2102 . In some embodiments, the one or more second dopants 2104 may be the same as the one or more first dopants (1704 of 17 ) used to form the horizontally extending isolation region 414a. In some embodiments, the third patterned mask layer 2102 may include the second patterned mask layer 2004 that was used to define the trenches 2002. FIG. In some embodiments, the one or more vertically extending isolation regions 414b may extend laterally beyond an exterior of the horizontally extending isolation region 414a. In some additional embodiments, the one or more vertically extending isolation regions 414b may extend vertically under a top surface of the horizontally extending isolation region 414a. In such embodiments, the one or more vertically extending isolation regions 414b may touch the horizontally extending isolation region 414a along a first direction and along a second direction perpendicular to the first direction.

As shown in cross-sectional view 2200 of FIG 22 1, a conductive material is formed within trenches 2002 to define conductive contacts 416. FIG. Conductive contacts 416 extend vertically through channel layer 410 and active layer 412 to contact isolation structure 414 . In some embodiments, an isolation layer 417 comprising one or more dielectric materials may be formed along sidewalls of the trenches 2002 before the conductive material is formed. In some embodiments, the isolation layer 417 may be formed by performing a thermal oxidation process, wherein the third patterned mask layer (2102 of 21 ) already exists. The thermal oxidation process forms an insulating layer (eg, an oxide) on the exposed surfaces of the epitaxial buffer layer 408, the channel layer 410, and/or the active layer 412. FIG. An etch process may then be performed to remove the insulating layer from a top surface of the epitaxial buffer layer 408 . In some such embodiments, isolation layer 417 may include a first dielectric material contacting epitaxial buffer layer 408 , a second dielectric material contacting channel layer 410 , and a third dielectric material contacting active layer 412 .

As shown in cross-sectional view 2300 of FIG 23 As shown, a gate structure 318, a source contact 216s, and a drain contact 216d are formed over the active layer 412 within the first HEMT device region (902 of 21 ), a second HEMT device region (904 of 21 ) and a portion of the diode-connected HEMT device (906 of 21 ) educated. Gate structure 318, source contact 216s, and drain contact 216d define: a first gate G ₁ , a first source S ₁ , and a first drain D ₁ of a first HEMT device 302; a second gate G ₂ , a second source S ₂ and a second drain D2 of a second HEMT device 304; and a third gate G3, a third source S3, and a third drain D3 of a diode-connected HEMT device 306. In some embodiments, the gate structure 318 may include a doped semiconductor material layer 320 and a gate electrode 322 overlying the doped semiconductor material layer 320 is arranged.

As shown in cross-sectional view 2400 of FIG 24 As shown, a plurality of conductive interconnect layers 706 are formed within a dielectric structure 324 formed over active layer 412. FIG. In some embodiments, the dielectric structure 324 may include multiple stacked ILD layers separated by multiple etch stop layers. In some embodiments, the plurality of conductive interconnect layers 706 may include alternating layers of interconnect wires and interconnect vias.

In some embodiments (not shown), the plurality of conductive interconnection layers 706 are configured to electrically connect the first gate G ₁ of the first HEMT device 302 to the third source S ₃ and the third gate G ₃ of the diode-connected HEMT device 306. to connect the first drain D ₁ of the first HEMT device 302 to the second source S ₂ of the second HEMT device 304 and also to connect the second gate G ₂ of the second HEMT device 304 to the third drain D ₃ of the diode connected HEMT- device 306 to connect. The electrical connections from the plurality of conductive interconnect layers 706 cause the first HEMT device 302, the second HEMT device 304, and the diode connected HEMT device 306 to operate as a single high voltage device having a common source, common drain terminal and a common gate terminal (in 2 shown). The high voltage device has a breakdown voltage that is greater than that of either the first HEMT device 302 or the second HEMT device 304 .

As in the cross-sectional view 2500 of 25 As shown, the die 402 is housed within a package. In some embodiments, the die 402 may be bonded to a support substrate 702 via one or more micro bumps 708 . A molding compound 704 is then formed over the support substrate 702 and the die 402 .

26 FIG. 26 illustrates a flow chart of some embodiments of a method 2600 for forming a high voltage device having a cascode structure with multiple HEMT devices.

Although method 2600 is illustrated and described herein as a sequence of operations or acts, it will be appreciated that the illustrated order of such operations or acts is not to be construed as a limitation. For example, some operations may occur in different orders and/or concurrently with other operations or operations than those illustrated and/or described herein. In addition, not all of the work steps shown need to be necessary in order to implement one or more configurations or embodiments of the description here. Besides that one or more of the operations presented herein may be performed in one or more separate operations and/or phases.

In 2602, a substrate is provided having a first HEMT device region, a second HEMT device region, and a diode-connected HEMT device region. the 9 and 16 9 show cross-sectional views 900 and 1600 of some embodiments according to operation 2602.

In 2604, in some embodiments, an epitaxial buffer layer may be formed over the substrate. 18 Figure 18 shows cross-sectional view 1800 of some embodiments according to operation 2604.

At 2606, a channel layer is formed over the substrate. the 10 and 18 1000 and 1800 show cross-sectional views of some embodiments according to operation 2606.

At 2608, an active layer is formed over the substrate. the 10 and 18 1000 and 1800 show cross-sectional views of some embodiments according to operation 2608.

In 2610, isolation regions are formed within the active layer and the channel layer between the first HEMT device region, the second HEMT device region, and the diode-connected HEMT device region. the 11 and 19 1000 and 1700 show cross-sectional views of some embodiments according to operation 2610.

At 2612, the first HEMT device area and the diode connected HEMT device area are electrically isolated from the second HEMT device area. the 14 and 17 and 20-22 Figure 12 shows the cross-sectional views of some embodiments according to operation 2612.

At 2614, a first gate structure, a first source contact, and a first drain contact are formed within the first HEMT device region to define a first HEMT device. the 12A , 12B and 23 12 show cross-sectional views 1200, 1202, and 2300 of some embodiments according to operation 2614.

At 2616, a second gate structure, a second source contact, and a second drain contact are formed within the second HEMT device region to define a second HEMT device. the 12A , 12B , and 23 12 show cross-sectional views 1200, 1202, and 2300 of some embodiments according to operation 2616.

At 2618, a third gate structure, a third source contact, and a third drain contact are formed within the area of the diode connected HEMT device to define a diode connected HEMT device. the 12A , 12B and 23 12 show cross-sectional views 1200, 1202, and 2300 of some embodiments according to operation 2618.

At 2620, one or more conductive layers are formed to connect the first HEMT device and the second HEMT device in a series circuit that defines a high voltage device that includes the diode-connected HEMT device. The high voltage device has a breakdown voltage that is greater than the breakdown voltages of the first HEMT device or the second HEMT device. the 13 and 15 and the 24-25 Figure 12 shows the cross-sectional views of some embodiments corresponding to operation 2620.

Accordingly, the present disclosure relates to a high voltage device including a first HEMT device connected in series with a second HEMT device so as to function together as an equivalent to a single high voltage transistor device having a relatively large breakdown voltage (i.e., a breakdown voltage, which is greater than the breakdown voltages of either the first HEMT device or the second HEMT device).

Claims (20)

A semiconductor device comprising: a first HEMT device (104, 302) disposed within a semiconductor structure (212) and having a first source (S1), a first drain (D1) and a first gate (G1); a second HEMT device (108, 304, 502) arranged within the semiconductor structure (212) in series with the first HEMT device (104, 302) and a second source (S2) connected to the first drain (D1 ) is connected, has a second drain (D2) and a second gate (G2); and a diode connected transistor device (110, 306) disposed within the semiconductor structure (212) and connected between the first HEMT device (104, 302) and the second HEMT device (108, 304, 502) and a third Source (S3), a third gate (G3) and a third drain (D3) connected to the second gate (G2). semiconductor device claim 1 , wherein the first HEMT device (104, 302) is a first enhancement mode HEMT device. semiconductor device claim 1 or 2 wherein the second HEMT device (108, 304, 502) is a second enhancement mode HEMT device; and wherein the third source (S3) is connected to the first gate (G1) and the third drain (D3) is connected to the second gate (G2). semiconductor device claim 1 or 2 wherein the second HEMT device (108, 304, 502) is a depletion mode HEMT device; and wherein the third source (S3) is connected to the first source (S1) and the third drain (D3) is connected to the second gate (G2). Semiconductor device according to one of the preceding claims, wherein the first HEMT device (104, 302) and the diode connected transistor device (110, 306) are disposed within a first die (308a); and wherein the second HEMT device (108, 304, 502) is disposed within a second die (308b) having an outermost sidewall separated from an outermost sidewall of the first die (308a) by a non-zero distance is separated. semiconductor device claim 5 , wherein the first die (308a) and the second die (308b) each comprise: a substrate (202, 312,406) comprising a first semiconductor material, a channel layer (314,410) disposed over the substrate (202, 312,406) and comprising a second semiconductor material, and an active layer (316,412) disposed over the channel layer (314,410) and comprising a third semiconductor material. semiconductor device claim 5 or 6 wherein the first die (308a) and the second die (308b) each comprise: a gallium nitride layer disposed over a silicon substrate and an aluminum gallium nitride layer disposed on the gallium nitride layer. semiconductor device claim 7 , wherein the gallium nitride layer has a thickness that is less than or equal to about 10 microns. A semiconductor device as claimed in any preceding claim, wherein the first HEMT device (104, 302), the diode connected transistor device (110, 306) and the second HEMT device (108, 304, 502) are within a die (308a, 308b, 402) are arranged. semiconductor device claim 9 , wherein the die (308a, 308b, 402) comprises: a substrate (202, 312, 406) comprising silicon with a first doping type, a gallium nitride layer disposed over the substrate (202, 312, 406), and an aluminum Gallium nitride layer touching a top surface of the gallium nitride layer. semiconductor device claim 9 , wherein the die (308a, 308b, 402) comprises: a substrate (202, 312, 406) comprising a first semiconductor material having a first doping type, an epitaxial buffer layer (408) disposed over the substrate (202, 312, 406) and the first semiconductor material having the first doping type comprises a channel layer (314,410) arranged over the epitaxial buffer layer (408) and comprising a second semiconductor material, and an active layer (316,412) arranged over the channel layer (314,410) and a third semiconductor material. semiconductor device claim 10 or 11 , further comprising: an isolation structure (414) having a doped region having a second doping type different from the first doping type, the doped region having a horizontally extending portion disposed within the substrate (202, 312, 406). has and vertically extending portions protruding outward from a top of the horizontally extending portion. semiconductor device claim 12 , further comprising: one or more conductive contacts extending through the channel layer (314, 410) and the active layer (316, 412) to contact the isolation structure (414). semiconductor device Claim 13 wherein the one or more conductive contacts physically touch the isolation structure (414) at an interface disposed along a horizontal plane that extends along a top surface of the epitaxial buffer layer (408). A high voltage device comprising: a semiconductor structure (212) including a substrate (202, 312,406), a channel layer (314,410) over the substrate (202,312,406) and an active layer (316,412) over the channel layer (314,410), a first HEMT device (104,302) having a first source (S1 ), a first drain (D1) and first gate (G1) disposed over the active layer (316, 412), a second HEMT device (108, 304, 502) having a second source (S2), a second drain (D2) and a second gate (G2) disposed over the active layer (316,412) in series with the first HEMT device (104,302), a diode connected transistor device (110,306), connected between the first HEMT device (104, 302) and the second HEMT device (108, 304, 502) and having a third source (S3), a third drain (D3) and a third gate (G3), disposed over the active layer (316, 412), and one or more conductive layers disposed over the semiconductor structure (212) and are arranged to electrically connect the first drain (D1) to the second source (S2) and the third drain (D3) to the second gate (G2). high voltage device claim 15 wherein the first HEMT device (104, 302) and the diode connected transistor device (110, 306) are disposed within a first die (308a); and wherein the second HEMT device (108, 304, 502) is disposed within a second die (308b) separated by a non-zero distance from the first die (308a). high voltage device claim 15 or 16 wherein the substrate (202, 312, 406) extends continuously beneath the first HEMT device (104, 302), the diode-connected transistor device (110, 306) and the second HEMT device (108, 304, 502). High-voltage device according to any one of Claims 15 until 17 , further comprising: an isolation structure (414) having a doped region disposed within said substrate (202,312,406) and having a different doping type than said substrate (202,312,406), said doped region having a horizontally extending portion laterally therebetween a first vertically extending portion protruding outwardly from a top of the horizontally extending portion, and a second vertically extending portion protruding outwardly from a top of the horizontally extending portion. A method of forming a high voltage device, comprising: forming a channel layer (314,410) comprising a second semiconductor material over a substrate (202,312,406) comprising a first semiconductor material, forming an active layer (316,412) comprising a third semiconductor material over the channel layer (314,410), forming a first gate structure (G1), a first source contact (S1), and a first drain contact (D1) over the active layer (316, 412) to define a first HEMT device (104, 302). , forming a second gate structure (G2), a second source contact (S2), and a second drain contact (D2) over the active layer (316, 412) to form a second HEMT device (108, 304, 502) define, Forming a diode connected transistor device (110, 306) connected between the first HEMT device (104, 302) and the second HEMT device (108, 304, 502) and a third source contact (S3), a a third drain contact (D3) and a third gate structure (G3) over the active layer (316, 412), and forming one or more conductive layers over the active layer (316,412) to electrically connect the first HEMT device (104,302) and the second HEMT device (108,304,502) in a series circuit and the third drain contact (D3) to electrically connect the second gate structure (G2) defining a high voltage device having a breakdown voltage greater than breakdown voltages of the first HEMT device (104, 302) or the second HEMT device (108, 304, 502 ) is. procedure after claim 19 , further comprising: selectively implanting a first dopant into the substrate (202, 312,406) to form a horizontally extending isolation region within the substrate (202, 312, 406), forming an epitaxial buffer layer (408) on the substrate (202, 312,406 ) after implanting the first dopant and before forming the channel layer (314, 410), selectively patterning the active layer (316, 412) and the channel layer (314, 410) to define trenches extending through the active layer (316, 412 ) and the channel layer (314, 410) extending through to the epitaxial buffer layer (408), and implanting the epitaxial buffer layer (408) to form one or more vertically extending isolation regions contacting the horizontally extending isolation region, the one or the plurality of vertically extending isolation regions on opposite sides ten of the second HEMT device (108, 304, 502) are arranged.

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