DE102019119044A1 - SEMICONDUCTOR COMPONENT AND METHOD - Google Patents
SEMICONDUCTOR COMPONENT AND METHOD Download PDFInfo
- Publication number
- DE102019119044A1 DE102019119044A1 DE102019119044.4A DE102019119044A DE102019119044A1 DE 102019119044 A1 DE102019119044 A1 DE 102019119044A1 DE 102019119044 A DE102019119044 A DE 102019119044A DE 102019119044 A1 DE102019119044 A1 DE 102019119044A1
- Authority
- DE
- Germany
- Prior art keywords
- nanowires
- epitaxial
- material stack
- epitaxial material
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 135
- 239000004065 semiconductor Substances 0.000 title claims abstract description 96
- 239000000463 material Substances 0.000 claims abstract description 227
- 239000002070 nanowire Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 39
- 239000002019 doping agent Substances 0.000 claims description 32
- 125000006850 spacer group Chemical group 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 16
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000000151 deposition Methods 0.000 claims description 11
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 188
- 239000002243 precursor Substances 0.000 description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- 239000003989 dielectric material Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 239000011810 insulating material Substances 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- 239000012774 insulation material Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 239000012686 silicon precursor Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000005368 silicate glass Substances 0.000 description 3
- -1 silicon oxide nitride Chemical class 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 229910021478 group 5 element Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910015890 BF2 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000347 anisotropic wet etching Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011417 postcuring Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Nanotechnology (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Bei einer Ausführungsform weist ein Verfahren die folgenden Schritte auf: Erzeugen einer ersten Aussparung und einer zweiten Aussparung in einem Substrat; Aufwachsen eines ersten epitaxialen Materialstapels in der ersten Aussparung, wobei der erste epitaxiale Materialstapel wechselnde Schichten aus einem ersten Halbleitermaterial und einem zweiten Halbleitermaterial umfasst, wobei die Schichten des ersten epitaxialen Materialstapels undotiert sind; Aufwachsen eines zweiten epitaxialen Materialstapels in der zweiten Aussparung, wobei der zweite epitaxiale Materialstapel wechselnde Schichten aus dem ersten Halbleitermaterial und dem zweiten Halbleitermaterial umfasst, wobei eine erste Teilmenge des zweiten epitaxialen Materialstapels undotiert ist und eine zweite Teilmenge des zweiten epitaxialen Materialstapels dotiert ist; Strukturieren des ersten epitaxialen Materialstapels und des zweiten epitaxialen Materialstapels, um erste Nanodrähte bzw. zweite Nanodrähte herzustellen; und Herstellen einer ersten Gatestruktur um die ersten Nanodrähte und einer zweiten Gatestruktur um die zweiten Nanodrähte.In one embodiment, a method includes the steps of: creating a first recess and a second recess in a substrate; Growing a first epitaxial material stack in the first recess, the first epitaxial material stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; Growing a second epitaxial material stack in the second recess, the second epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped and a second subset of the second epitaxial material stack being doped; Patterning the first epitaxial material stack and the second epitaxial material stack to produce first nanowires and second nanowires, respectively; and fabricating a first gate structure around the first nanowires and a second gate structure around the second nanowires.
Description
Prioritätsanspruch und QuerverweisPriority claim and cross-reference
Die vorliegende Anmeldung beansprucht die Priorität der am 30. November 2018 eingereichten vorläufigen US-Patentanmeldung mit dem Aktenzeichen 62/773.346, die durch Bezugnahme aufgenommen ist.This application claims priority from U.S. Provisional Application No. 62 / 773,346, filed November 30, 2018, which is incorporated by reference.
Hintergrundbackground
Halbleiter-Bauelemente kommen in verschiedenen elektronischen Anwendungsgebieten zum Einsatz, wie etwa Personal Computern, Mobiltelefonen, digitalen Kameras und anderen elektronischen Geräten. Halbleiter-Bauelemente werden normalerweise dadurch hergestellt, dass isolierende oder dielektrische Schichten, leitfähige Schichten und Halbleiterschichten nacheinander über einem Halbleitersubstrat abgeschieden werden und die verschiedenen Materialschichten durch Lithografie strukturiert werden, um Schaltkreiskomponenten und -elemente auf dem Substrat herzustellen.Semiconductor devices are used in various electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers and semiconductor layers over a semiconductor substrate and structuring the various material layers by lithography to produce circuit components and elements on the substrate.
Die Halbleiterindustrie verbessert die Integrationsdichte verschiedener elektronischer Komponenten (z. B. Transistoren, Dioden, Widerstände, Kondensatoren usw.) immer weiter, indem sie die kleinste Strukturbreite ständig reduziert, sodass mehr Komponenten auf einer gegebenen Fläche integriert werden können. Wenn die kleinste Strukturbreite reduziert wird, entstehen jedoch weitere Probleme, die angegangen werden sollten.The semiconductor industry continues to improve the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by constantly reducing the smallest structure width so that more components can be integrated in a given area. If the smallest structure width is reduced, however, further problems arise which should be addressed.
FigurenlisteFigure list
Aspekte der vorliegenden Erfindung lassen sich am besten anhand der nachstehenden detaillierten Beschreibung in Verbindung mit den beigefügten Zeichnungen verstehen. Es ist zu beachten, dass entsprechend der üblichen Praxis in der Branche verschiedene Elemente nicht maßstabsgetreu gezeichnet sind. Vielmehr können der Übersichtlichkeit der Erörterung halber die Abmessungen der verschiedenen Elemente beliebig vergrößert oder verkleinert sein.
- Die
1 bis24 sind verschiedene Darstellungen von Zwischenstufen bei der Herstellung von Gate-all-around-Feldeffekttransistoren (GAA-FETs) gemäß einigen Ausführungsformen. - Die
25A bis25C sind verschiedene Darstellungen von Zwischenstufen bei der Herstellung von GAA-FETs gemäß weiteren Ausführungsformen.
- The
1 to24th 14 are various representations of intermediate stages in the manufacture of gate all around field effect transistors (GAA-FETs) in accordance with some embodiments. - The
25A to25C are different representations of intermediate stages in the manufacture of GAA-FETs according to further embodiments.
Detaillierte BeschreibungDetailed description
Die nachstehende Beschreibung liefert viele verschiedene Ausführungsformen oder Beispiele zum Implementieren verschiedener Merkmale der Erfindung. Nachstehend werden spezielle Beispiele für Komponenten und Anordnungen beschrieben, um die vorliegende Erfindung zu vereinfachen. Diese sind natürlich lediglich Beispiele und sollen nicht beschränkend sein. Zum Beispiel kann die Herstellung eines ersten Elements über oder auf einem zweiten Element in der nachstehenden Beschreibung Ausführungsformen umfassen, bei denen das erste und das zweite Element in direktem Kontakt hergestellt werden, und sie kann auch Ausführungsformen umfassen, bei denen zusätzliche Elemente zwischen dem ersten und dem zweiten Element so hergestellt werden können, dass das erste und das zweite Element nicht in direktem Kontakt sind. Darüber hinaus können in der vorliegenden Erfindung Bezugszahlen und/oder -buchstaben in den verschiedenen Beispielen wiederholt werden. Diese Wiederholung dient der Einfachheit und Übersichtlichkeit und schreibt an sich keine Beziehung zwischen den verschiedenen erörterten Ausführungsformen und/oder Konfigurationen vor.The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are of course only examples and are not intended to be limiting. For example, the manufacture of a first element above or on a second element in the description below may include embodiments in which the first and second elements are made in direct contact, and may also include embodiments in which additional elements are between the first and the second element can be made so that the first and second elements are not in direct contact. In addition, reference numbers and / or letters can be repeated in the various examples in the present invention. This repetition is for simplicity and clarity, and by itself does not dictate a relationship between the various embodiments and / or configurations discussed.
Darüber hinaus können hier räumlich relative Begriffe, wie etwa „darunter befindlich“, „unter“, „untere(r)“/„unteres“, „darüber befindlich“, „obere(r)“/„oberes“ und dergleichen, zur einfachen Beschreibung der Beziehung eines Elements oder einer Struktur zu einem oder mehreren anderen Elementen oder Strukturen verwendet werden, die in den Figuren dargestellt sind. Die räumlich relativen Begriffe sollen zusätzlich zu der in den Figuren dargestellten Orientierung andere Orientierungen der in Gebrauch oder in Betrieb befindlichen Vorrichtung umfassen. Die Vorrichtung kann anders ausgerichtet werden (um 90 Grad gedreht oder in einer anderen Orientierung), und die räumlich relativen Deskriptoren, die hier verwendet werden, können ebenso entsprechend interpretiert werden.In addition, spatially relative terms, such as "below", "below", "lower (r)" / "lower", "above", "upper" / "upper" and the like, can be used easily Description of the relationship of an element or structure to one or more other elements or structures used in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include other orientations of the device in use or in operation. The device can be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used here can also be interpreted accordingly.
Gemäß einigen Ausführungsformen wird eine Mehrzahl von epitaxialen Materialstapeln in einem Substrat hergestellt. Die epitaxialen Materialstapel werden während des Aufwachsens dotiert und haben unterschiedliche mittlere Dotierungskonzentrationen. Die epitaxialen Materialstapel werden dann zu Nanodrähten für Gate-all-around-Feldeffekttransistoren (GAA-FETs) strukturiert. Die mittlere Dotierungskonzentration der Nanodrähte für jeden GAA-FET bestimmt die Schwellenspannung für den GAA-FET. Somit können Bauelemente mit mehreren Schwellenspannungen auf dem gleichen Substrat hergestellt werden.According to some embodiments, a plurality of epitaxial material stacks are made in a substrate. The epitaxial material stacks are doped during growth and have different mean doping concentrations. The epitaxial material stacks are then structured into nanowires for gate all-around field effect transistors (GAA-FETs). The average doping concentration of the nanowires for each GAA-FET determines the threshold voltage for the GAA-FET. Components with multiple threshold voltages can thus be produced on the same substrate.
Die
In
Das Substrat
Die GAA-FETs, die in den Bereichen
Außerdem können geeignete Wannen (nicht dargestellt) in dem Substrat
Bei den Ausführungsformen mit unterschiedlichen Wannentypen können unterschiedliche Implantationsprozesse für die NMOS- und die PMOS-Bereiche unter Verwendung eines Fotoresists oder anderer Masken (nicht dargestellt) realisiert werden. Zum Beispiel kann über dem Substrat
Nach dem Implantieren der PMOS-Bereiche wird ein Fotoresist über dem Substrat
Nach den Implantationen der NMOS- und PMOS-Bereiche des Substrats
In
In
Die epitaxialen Materialstapel
Die epitaxialen Materialstapel
In
In
In den
Die epitaxialen Materialstapel
Die erste Teilmenge
Die zweite Teilmenge
Die ersten Halbleiterschichten
In
In
In den
Die epitaxialen Materialstapel
Die erste Teilmenge
Die zweite Teilmenge
In
Die
In
Die GAA-Strukturen
Bei einigen Ausführungsformen werden die verbliebenen Abstandshalter zum Strukturieren einer Maske
In
In
In
Nach der Herstellung der Gate-Abstandshalterschicht
In
Weiterhin werden Source-/Drain-Aussparungen
In
Die Source-/Drain-Epitaxiebereiche
Die Source-/Drain-Epitaxiebereiche
Durch die Epitaxieprozesse, die zum Herstellen der Source-/Drain-Epitaxiebereiche
In
Außerdem kann ein Planarisierungsprozess, wie etwa eine CMP, durchgeführt werden, um die Oberseiten des ersten ILD
In
Nach dem Entfernen der Dummy-Gates
In
Die Gate-Elektroden
Bei einigen Ausführungsformen sind die Austrittsarbeitsschichten für n- und p-Bauelemente unterschiedlich. Wenn p-FETs hergestellt werden (siehe
In
Außerdem werden bei einigen Ausführungsformen Gatekontakte
Die
Ausführungsformen können einige Vorzüge erzielen. Durch Herstellen mehrerer epitaxialer Materialstapel mit dotierten und undotierten Bereichen können GAA-FETs mit unterschiedlichen Schwellenspannungen auf dem gleichen Substrat entstehen. Durch Verwenden von unterschiedlichen Austrittsarbeitsmaterialien für n- und p-Bauelemente kann außerdem die Anzahl von möglichen unterschiedlichen Schwellenspannungen erhöht werden.Embodiments can achieve some merits. By manufacturing multiple epitaxial material stacks with doped and undoped areas, GAA-FETs with different threshold voltages can be created on the same substrate. By using different work function materials for n and p components, the number of possible different threshold voltages can also be increased.
Bei einer Ausführungsform weist ein Verfahren die folgenden Schritte auf: Erzeugen einer ersten Aussparung und einer zweiten Aussparung in einem Substrat; Aufwachsen eines ersten epitaxialen Materialstapels in der ersten Aussparung, wobei der erste epitaxiale Materialstapel wechselnde Schichten aus einem ersten Halbleitermaterial und einem zweiten Halbleitermaterial umfasst, wobei die Schichten des ersten epitaxialen Materialstapels undotiert sind; Aufwachsen eines zweiten epitaxialen Materialstapels in der zweiten Aussparung, wobei der zweite epitaxiale Materialstapel wechselnde Schichten aus dem ersten Halbleitermaterial und dem zweiten Halbleitermaterial umfasst, wobei eine erste Teilmenge des zweiten epitaxialen Materialstapels undotiert ist und eine zweite Teilmenge des zweiten epitaxialen Materialstapels dotiert ist; Strukturieren des ersten epitaxialen Materialstapels und des zweiten epitaxialen Materialstapels, um erste Nanodrähte bzw. zweite Nanodrähte herzustellen; und Herstellen einer ersten Gatestruktur um die ersten Nanodrähte und einer zweiten Gatestruktur um die zweiten Nanodrähte.In one embodiment, a method includes the steps of: creating a first recess and a second recess in a substrate; Growing a first epitaxial material stack in the first recess, the first epitaxial material stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; Growing a second epitaxial material stack in the second recess, the second epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped and a second subset of the second epitaxial material stack being doped; Patterning the first epitaxial material stack and the second epitaxial material stack to produce first nanowires and second nanowires, respectively; and fabricating a first gate structure around the first nanowires and a second gate structure around the second nanowires.
Bei einigen Ausführungsformen des Verfahrens ist das erste Halbleitermaterial Siliziumgermanium und das zweite Halbleitermaterial ist Silizium, wobei Schichten aus Siliziumgermanium in der zweiten Teilmenge des zweiten epitaxialen Materialstapels mit einem Element der Gruppe V dotiert werden und Schichten aus Silizium in der zweiten Teilmenge des zweiten epitaxialen Materialstapels mit einem Element der Gruppe III dotiert werden. Bei einigen Ausführungsformen des Verfahrens umfasst das Herstellen der ersten Gatestruktur ein Abscheiden eines ersten Metalls um die ersten Nanodrähte, und das Herstellen der zweiten Gatestruktur umfasst ein Abscheiden eines zweiten Metalls um die zweiten Nanodrähte, wobei das zweite Metall von dem ersten Metall verschieden ist. Bei einigen Ausführungsformen umfasst das Verfahren weiterhin Folgendes: Erzeugen einer dritten Aussparung in dem Substrat; Aufwachsen eines dritten epitaxialen Materialstapels in der dritten Aussparung, wobei der dritte epitaxiale Materialstapel wechselnde Schichten aus dem ersten Halbleitermaterial und dem zweiten Halbleitermaterial umfasst, wobei eine erste Teilmenge des dritten epitaxialen Materialstapels undotiert ist und eine zweite Teilmenge des dritten epitaxialen Materialstapels dotiert ist, wobei die zweite Teilmenge des dritten epitaxialen Materialstapels mehr Schichten als die zweite Teilmenge des zweiten epitaxialen Materialstapels umfasst; Strukturieren des dritten epitaxialen Materialstapels, um dritte Nanodrähte herzustellen; und Herstellen einer dritten Gatestruktur um die dritten Nanodrähte. Bei einigen Ausführungsformen des Verfahrens umfasst das Aufwachsen des ersten epitaxialen Materialstapels ein Aufwachsen des ersten epitaxialen Materialstapels mit einem ersten epitaxialen Aufwachsprozess. Bei einigen Ausführungsformen des Verfahrens umfasst das Aufwachsen des zweiten epitaxialen Materialstapels Folgendes: Aufwachsen der ersten Teilmenge des zweiten epitaxialen Materialstapels mit dem ersten epitaxialen Aufwachsprozess; und Aufwachsen der zweiten Teilmenge des zweiten epitaxialen Materialstapels mit einem zweiten epitaxialen Aufwachsprozess, wobei der zweite epitaxiale Aufwachsprozess von dem ersten epitaxialen Aufwachsprozess verschieden ist. Bei einigen Ausführungsformen des Verfahrens umfasst das Aufwachsen des dritten epitaxialen Materialstapels Folgendes: Aufwachsen der ersten Teilmenge des dritten epitaxialen Materialstapels mit dem ersten epitaxialen Aufwachsprozess; und Aufwachsen der zweiten Teilmenge des dritten epitaxialen Materialstapels mit dem zweiten epitaxialen Aufwachsprozess. Bei einigen Ausführungsformen des Verfahrens umfasst das Strukturieren des ersten epitaxialen Materialstapels Folgendes: Ätzen von Gräben in dem ersten epitaxialen Materialstapel, um eine erste Gate-all-around(GAA)-Struktur mit wechselnden Schichten aus dem ersten Halbleitermaterial und dem zweiten Halbleitermaterial herzustellen; Herstellen von ersten Gate-Abstandshaltern über der ersten GAA-Struktur; und Ätzen von Teilen der ersten GAA-Struktur zwischen den ersten Gate-Abstandshaltern, wobei durch das Ätzen die Schichten aus dem ersten Halbleitermaterial selektiv entfernt werden und verbliebene Schichten aus dem zweiten Halbleitermaterial die ersten Nanodrähte bilden. Bei einigen Ausführungsformen umfasst das Verfahren weiterhin ein Planarisieren des Substrats, sodass Oberseiten des zweiten epitaxialen Materialstapels, des ersten epitaxialen Materialstapels und des Substrats auf gleicher Höhe sind. In some embodiments of the method, the first semiconductor material is silicon germanium and the second semiconductor material is silicon, layers of silicon germanium in the second subset of the second epitaxial material stack being doped with a Group V element and layers of silicon in the second subset of the second epitaxial material stack a Group III element. In some embodiments of the method, fabricating the first gate structure includes depositing a first metal around the first nanowires, and fabricating the second gate structure includes depositing a second metal around the second nanowires, the second metal being different from the first metal. In some embodiments, the method further includes: creating a third recess in the substrate; Growing a third epitaxial material stack in the third recess, the third epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the third epitaxial material stack being undoped and a second subset of the third epitaxial material stack being doped, the second subset of the third epitaxial material stack comprises more layers than the second subset of the second epitaxial material stack; Patterning the third epitaxial material stack to produce third nanowires; and fabricating a third gate structure around the third nanowires. In some embodiments of the method, growing the first epitaxial material stack comprises growing the first epitaxial material stack with a first epitaxial growth process. In some embodiments of the method, growing the second epitaxial material stack comprises: growing the first subset of the second epitaxial material stack with the first epitaxial growth process; and growing the second subset of the second epitaxial material stack with a second epitaxial growth process, the second epitaxial growth process being different from the first epitaxial growth process. In some embodiments of the method, growing the third epitaxial material stack comprises: growing the first subset of the third epitaxial material stack with the first epitaxial growth process; and growing the second subset of the third epitaxial material stack with the second epitaxial growth process. In some embodiments of the method, patterning the first epitaxial material stack comprises: etching trenches in the first epitaxial material stack to produce a first gate all-around (GAA) structure with alternating layers of the first semiconductor material and the second semiconductor material; Making first gate spacers over the first ATM structure; and etching parts of the first GAA structure between the first gate spacers, the etching selectively removing the layers of the first semiconductor material and remaining layers of the second semiconductor material forming the first nanowires. In some embodiments, the method further includes planarizing the substrate so that tops of the second epitaxial material stack, the first epitaxial material stack, and the substrate are level.
Bei einer Ausführungsform weist ein Verfahren die folgenden Schritte auf: Aufwachsen eines ersten epitaxialen Materialstapels in einem Substrat, wobei der erste epitaxiale Materialstapel eine erste mittlere Dotierungskonzentration hat; Aufwachsen eines zweiten epitaxialen Materialstapels in dem Substrat, wobei der zweite epitaxiale Materialstapel eine zweite mittlere Dotierungskonzentration hat; Aufwachsen eines dritten epitaxialen Materialstapels in dem Substrat, wobei der dritte epitaxiale Materialstapel eine dritte mittlere Dotierungskonzentration hat, wobei die erste mittlere Dotierungskonzentration, die zweite mittlere Dotierungskonzentration und die dritte mittlere Dotierungskonzentration verschieden sind; Planarisieren des Substrats, sodass Oberseiten des ersten epitaxialen Materialstapels, des zweiten epitaxialen Materialstapels und des dritten epitaxialen Materialstapels auf gleicher Höhe sind; Strukturieren des ersten epitaxialen Materialstapels, des zweiten epitaxialen Materialstapels und des dritten epitaxialen Materialstapels, um erste Nanodrähte, zweite Nanodrähte bzw. dritte Nanodrähte herzustellen; und Herstellen einer ersten Gatestruktur um die ersten Nanodrähte, einer zweiten Gatestruktur um die zweiten Nanodrähte und einer dritten Gatestruktur um die dritten Nanodrähte.In one embodiment, a method has the following steps: growing a first epitaxial material stack in a substrate, the first epitaxial material stack having a first average doping concentration; Growing a second epitaxial material stack in the substrate, the second epitaxial material stack having a second average doping concentration; Growing a third epitaxial material stack in the substrate, the third epitaxial material stack having a third average doping concentration, the first average doping concentration, the second average doping concentration and the third average doping concentration being different; Planarizing the substrate so that tops of the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack are at the same level; Structuring the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack to produce first nanowires, second nanowires and third nanowires, respectively; and fabricating a first gate structure around the first nanowires, a second gate structure around the second nanowires, and a third gate structure around the third nanowires.
Bei einigen Ausführungsformen des Verfahrens haben der erste epitaxiale Materialstapel, der zweite epitaxiale Materialstapel und der dritte epitaxiale Materialstapel die gleiche Anzahl von Schichten. Bei einigen Ausführungsformen des Verfahrens haben der erste epitaxiale Materialstapel und der dritte epitaxiale Materialstapel eine erste Anzahl von Schichten, und der zweite epitaxiale Materialstapel hat eine zweite Anzahl von Schichten, wobei die zweite Anzahl von der ersten Anzahl verschieden ist.In some embodiments of the method, the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack have the same number of layers. In some embodiments of the method, the first epitaxial material stack and the third epitaxial material stack have a first number of layers, and the second epitaxial material stack has a second number of layers, the second number being different from the first number.
Bei einer Ausführungsform weist eine Vorrichtung Folgendes auf: einen ersten Transistor mit ersten Nanodrähten und einer ersten Gatestruktur um die ersten Nanodrähte, wobei die ersten Nanodrähte eine erste mittlere Dotierungskonzentration haben und die erste Gatestruktur eine erste Gruppe von Austrittsarbeits-Einstellschichten umfasst; einen zweiten Transistor mit zweiten Nanodrähten und einer zweiten Gatestruktur um die zweiten Nanodrähte, wobei die zweiten Nanodrähte eine zweite mittlere Dotierungskonzentration haben, wobei die zweite mittlere Dotierungskonzentration von der ersten mittleren Dotierungskonzentration verschieden ist, und die zweite Gatestruktur die erste Gruppe von Austrittsarbeits-Einstellschichten umfasst; einen dritten Transistor mit dritten Nanodrähten und einer dritten Gatestruktur um die dritten Nanodrähte, wobei die dritten Nanodrähte die erste mittlere Dotierungskonzentration haben und die dritte Gatestruktur eine zweite Gruppe von Austrittsarbeits-Einstellschichten umfasst; und einen vierten Transistor mit vierten Nanodrähten und einer vierten Gatestruktur um die vierten Nanodrähte, wobei die vierten Nanodrähte die zweite mittlere Dotierungskonzentration haben und die vierte Gatestruktur die zweite Gruppe von Austrittsarbeits-Einstellschichten umfasst, wobei die zweite Gruppe von Austrittsarbeits-Einstellschichten von der ersten Gruppe von Austrittsarbeits-Einstellschichten verschieden ist.In one embodiment, an apparatus includes: a first transistor having first nanowires and a first gate structure around the first nanowires, the first nanowires having a first average doping concentration and the first gate structure comprising a first group of work function adjustment layers; a second transistor having second nanowires and a second gate structure around the second nanowires, the second nanowires having a second average doping concentration, the second average doping concentration different from the first average doping concentration, and the second gate structure comprising the first group of work function adjustment layers ; a third transistor having third nanowires and a third gate structure around the third nanowires, the third nanowires having the first average doping concentration and the third gate structure comprising a second group of work function adjustment layers; and a fourth transistor having fourth nanowires and a fourth gate structure around the fourth nanowires, the fourth nanowires having the second mean doping concentration and the fourth gate structure comprising the second group of work function adjustment layers, the second group of work function adjustment layers from the first group is different from work function adjustment layers.
Bei einigen Ausführungsformen der Vorrichtung haben der erste Transistor, der zweite Transistor, der dritte Transistor und der vierte Transistor jeweils die gleiche Anzahl von Nanodrähten. Bei einigen Ausführungsformen der Vorrichtung haben der erste Transistor und der dritte Transistor eine erste Anzahl von Nanodrähten, und der zweite Transistor und der vierte Transistor haben eine zweite Anzahl von Nanodrähten, wobei die zweite Anzahl von der ersten Anzahl verschieden ist. Bei einigen Ausführungsformen der Vorrichtung sind der erste Transistor und der zweite Transistor p-Gate-all-around-Feldeffekttransistoren (p-GAA-FETs), und der dritte Transistor und der vierte Transistor sind n-GAA-FETs. Bei einigen Ausführungsformen der Vorrichtung weisen die ersten Nanodrähte undotiertes Siliziumgermanium auf, eine erste Teilmenge der zweiten Nanodrähte weist undotiertes Siliziumgermanium auf, und eine zweite Teilmenge der zweiten Nanodrähte weist Siliziumgermanium auf, das mit einem Dotierungsstoff der Gruppe V dotiert ist. Bei einigen Ausführungsformen der Vorrichtung weist die erste Gruppe von Austrittsarbeits-Einstellschichten TiN, TaN oder Mo auf. Bei einigen Ausführungsformen der Vorrichtung weisen die dritten Nanodrähte undotiertes Silizium auf, eine erste Teilmenge der vierten Nanodrähte weist undotiertes Silizium auf, und eine zweite Teilmenge der vierten Nanodrähte weist Silizium auf, das mit einem Dotierungsstoff der Gruppe III dotiert ist. Bei einigen Ausführungsformen der Vorrichtung weist die zweite Gruppe von Austrittsarbeits-Einstellschichten WN, Ta oder Ti auf.In some embodiments of the device, the first transistor, the second transistor, the third transistor and the fourth transistor each have the same number of nanowires. In some embodiments of the device, the first transistor and the third transistor have a first number of nanowires, and the second transistor and the fourth transistor have a second number of nanowires, the second number being different from the first number. In some embodiments of the device, the first transistor and the second transistor are p-gate all around field effect transistors (p-GAA-FETs) and the third transistor and the fourth transistor are n-GAA-FETs. In some embodiments of the device, the first nanowires comprise undoped silicon germanium, a first subset of the second nanowires comprises undoped silicon germanium, and a second subset of the second nanowires comprises silicon germanium doped with a group V dopant. In some embodiments of the device, the first group of work function adjustment layers comprises TiN, TaN or Mo. In some embodiments of the device, the third nanowires comprise undoped silicon, a first subset of the fourth nanowires comprises undoped silicon, and a second subset of the fourth nanowires comprises silicon doped with a group III dopant. In some embodiments of the device, the second group of work function adjustment layers comprises WN, Ta or Ti.
Vorstehend sind Merkmale verschiedener Ausführungsformen beschrieben worden, sodass Fachleute die Aspekte der vorliegenden Erfindung besser verstehen können. Fachleuten dürfte klar sein, dass sie die vorliegende Erfindung ohne Weiteres als eine Grundlage zum Gestalten oder Modifizieren anderer Verfahren und Strukturen zum Erreichen der gleichen Ziele und/oder zum Erzielen der gleichen Vorzüge wie bei den hier vorgestellten Ausführungsformen verwenden können. Fachleute dürften ebenfalls erkennen, dass solche äquivalenten Auslegungen nicht von dem Grundgedanken und Schutzumfang der vorliegenden Erfindung abweichen und dass sie hier verschiedene Änderungen, Ersetzungen und Abwandlungen vornehmen können, ohne von dem Grundgedanken und Schutzumfang der vorliegenden Erfindung abzuweichen.Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It will be apparent to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same goals and / or to achieve the same benefits as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent interpretations do not depart from the spirit and scope of the present invention and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present invention.
Claims (20)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201862773346P | 2018-11-30 | 2018-11-30 | |
US62/773,346 | 2018-11-30 | ||
US16/504,786 US11031298B2 (en) | 2018-11-30 | 2019-07-08 | Semiconductor device and method |
US16/504,786 | 2019-07-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102019119044A1 true DE102019119044A1 (en) | 2020-06-04 |
Family
ID=70680924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102019119044.4A Pending DE102019119044A1 (en) | 2018-11-30 | 2019-07-15 | SEMICONDUCTOR COMPONENT AND METHOD |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102019119044A1 (en) |
-
2019
- 2019-07-15 DE DE102019119044.4A patent/DE102019119044A1/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102016100022B4 (en) | Nanowire biased CMOS device and manufacturing process | |
DE102017114427B4 (en) | Process for the production of separating elements for semiconductor structures | |
DE102020115120A1 (en) | NANOSHEET FIELD EFFECT TRANSISTOR DEVICE AND METHOD OF MANUFACTURING IT | |
DE102017103419A1 (en) | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH SEPARATED FUSED STRUCTURE | |
DE102019117011B4 (en) | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD | |
DE102019111297B4 (en) | Semiconductor device and method | |
DE102019116036B4 (en) | SEMICONDUCTOR DEVICE AND METHOD | |
DE102019109857A1 (en) | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD | |
DE102017117793A1 (en) | Method of fabricating multi-gate transistors and resulting structures | |
DE102020109608A1 (en) | DUMMY FINS AND METHOD OF MANUFACTURING THEREOF | |
DE102020110754A1 (en) | SEMICONDUCTOR DEVICE AND METHOD | |
DE102019113052A1 (en) | SEMICONDUCTOR COMPONENT AND METHOD | |
DE102021100720A1 (en) | CONTACTS FOR SEMICONDUCTOR DEVICES AND METHOD FOR THEIR MANUFACTURE | |
DE102021105733A1 (en) | CONTACT PLUG STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME | |
DE102018119795A1 (en) | Voltage modulation for dielectric layers | |
DE102020114314A1 (en) | SEMICONDUCTOR DEVICE AND METHOD | |
DE102019122443A1 (en) | Transistors with semiconductor stack layers as channels | |
DE102020120658A1 (en) | Transistor gates and processes for their manufacture | |
DE102020115408A1 (en) | SEMICONDUCTOR DEVICE AND METHOD | |
DE102020104379A1 (en) | SEMICONDUCTOR COMPONENT AND PROCESS | |
DE102019101165A1 (en) | GATE SPACER STRUCTURE AND METHOD FOR PRODUCING THE SAME | |
DE102021116786B4 (en) | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE | |
DE102022107309A1 (en) | METAL GATE FIN ELECTRODE STRUCTURE AND PROCESS | |
DE102022100092A1 (en) | GATE STRUCTURES IN TRANSISTOR DEVICES AND PROCESSES FOR THEIR MANUFACTURE | |
DE102020104370B4 (en) | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R012 | Request for examination validly filed | ||
R016 | Response to examination communication |