DE102019119044A1 - SEMICONDUCTOR COMPONENT AND METHOD - Google Patents

Abstract

In one embodiment, a method includes the steps of: creating a first recess and a second recess in a substrate; Growing a first epitaxial material stack in the first recess, the first epitaxial material stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; Growing a second epitaxial material stack in the second recess, the second epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped and a second subset of the second epitaxial material stack being doped; Patterning the first epitaxial material stack and the second epitaxial material stack to produce first nanowires and second nanowires, respectively; and fabricating a first gate structure around the first nanowires and a second gate structure around the second nanowires.

Description

Priority claim and cross-reference

This application claims priority from U.S. Provisional Application No. 62 / 773,346, filed November 30, 2018, which is incorporated by reference.

background

Semiconductor devices are used in various electronic applications, such as personal computers, cell phones, digital cameras and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric layers, conductive layers and semiconductor layers over a semiconductor substrate and structuring the various material layers by lithography to produce circuit components and elements on the substrate.

The semiconductor industry continues to improve the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, etc.) by constantly reducing the smallest structure width so that more components can be integrated in a given area. If the smallest structure width is reduced, however, further problems arise which should be addressed.

Figure list

• Die 1 bis 24 sind verschiedene Darstellungen von Zwischenstufen bei der Herstellung von Gate-all-around-Feldeffekttransistoren (GAA-FETs) gemäß einigen Ausführungsformen.
• Die 25A bis 25C sind verschiedene Darstellungen von Zwischenstufen bei der Herstellung von GAA-FETs gemäß weiteren Ausführungsformen.

Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with normal industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of the discussion, the dimensions of the various elements can be enlarged or reduced as desired.

• The 1 to 24th 14 are various representations of intermediate stages in the manufacture of gate all around field effect transistors (GAA-FETs) in accordance with some embodiments.
• The 25A to 25C are different representations of intermediate stages in the manufacture of GAA-FETs according to further embodiments.

Detailed description

The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are of course only examples and are not intended to be limiting. For example, the manufacture of a first element above or on a second element in the description below may include embodiments in which the first and second elements are made in direct contact, and may also include embodiments in which additional elements are between the first and the second element can be made so that the first and second elements are not in direct contact. In addition, reference numbers and / or letters can be repeated in the various examples in the present invention. This repetition is for simplicity and clarity, and by itself does not dictate a relationship between the various embodiments and / or configurations discussed.

In addition, spatially relative terms, such as "below", "below", "lower (r)" / "lower", "above", "upper" / "upper" and the like, can be used easily Description of the relationship of an element or structure to one or more other elements or structures used in the figures. In addition to the orientation shown in the figures, the spatially relative terms are intended to include other orientations of the device in use or in operation. The device can be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used here can also be interpreted accordingly.

According to some embodiments, a plurality of epitaxial material stacks are made in a substrate. The epitaxial material stacks are doped during growth and have different mean doping concentrations. The epitaxial material stacks are then structured into nanowires for gate all-around field effect transistors (GAA-FETs). The average doping concentration of the nanowires for each GAA-FET determines the threshold voltage for the GAA-FET. Components with multiple threshold voltages can thus be produced on the same substrate.

The 1 to 12 are sectional views of intermediate stages in the manufacture of ATMs FETs according to some embodiments. GAA-FETs that have different threshold voltages are manufactured in different areas of the same device. The threshold voltage of an FET is the minimum gate-source voltage required to establish a conductor path between a source and a drain connection of the FET.

In 1 becomes a substrate 50 provided. The substrate 50 may be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of a semiconductor material that is produced on an insulating layer. The insulating layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer or the like. The insulating layer is made on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 Include: silicon; Germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

The substrate 50 has areas 50A , 50B and 50C . The areas 50A , 50B and 50C can be used to manufacture n-type devices such as NMOS transistors, e.g. B. n-GAA-FETs, or for the manufacture of p-type devices, such as PMOS transistors, for. B. p-GAA-FETs can be used. The areas 50A , 50B and 50C can be physically separate, and between areas 50A , 50B and 50C can be arranged any number of component structures (z. B. other active components, doped regions, isolation structures, etc.). As will be explained in more detail later, epitaxial material stacks in the areas 50A , 50B and 50C produced. The epitaxial material stacks become GAA-FETs in the areas 50A , 50B and 50C structured. Although only one epitaxial stack of material is shown in each area, it should be understood that the areas 50A , 50B and 50C can have several epitaxial material stacks.

The GAA-FETs in the fields 50A , 508 and 50C have different threshold voltages. In particular, GAA-FETs have a first threshold voltage V ₁ have in the area 50A manufactured GAA-FETs that have a higher second threshold voltage V ₂ have in the area 50B manufactured, and GAA-FETs, which have an even higher third threshold voltage V ₃ have in the area 50C produced. You can also use n-GAA FETs or p-GAA FETs in the fields 50A , 50B and 50C getting produced. The n-GAA FETs and the p-GAA-FETs are made using different work materials in their gate electrodes. This allows GAA-FETs with six possible threshold voltages (e.g. three for the n-GAA-FETs and three for the p-GAA-FETs) on the substrate 50 getting produced.

In addition, suitable wells (not shown) can be placed in the substrate 50 getting produced. In some embodiments, p-wells are made in areas where n-GAA FETs are made (e.g., NMOS areas) and n-wells are made in areas where p-GAA FETs are made ( e.g. in PMOS areas). Different implantation processes can be used to manufacture n-wells and p-wells.

In the embodiments with different tub types, different implantation processes for the NMOS and PMOS areas can be implemented using a photoresist or other masks (not shown). For example, over the substrate 50 a photoresist can be produced, which is then patterned around the PMOS regions of the substrate 50 to expose. The photoresist can be produced by spin coating and can then be structured using suitable photolithographic processes. After the photoresist has been patterned, n-type dopants are implanted in the PMOS regions and the photoresist can act as a mask to largely avoid n-type dopants being implanted in the NMOS region. The n-type dopants can be phosphorus, arsenic, antimony or the like, and they are in the range with a concentration equal to or less than 10 ¹⁸ cm ^-3 , e.g. B. about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 , implanted. After the implantation, for example, the photoresist can be removed using a suitable detachment process.

After the PMOS areas have been implanted, a photoresist is placed over the substrate 50 which is then patterned around the NMOS regions of the substrate 50 to expose. The photoresist can be produced by spin coating and can be structured using suitable photolithographic processes. After the photoresist has been patterned, p-type dopants are implanted in the NMOS regions, and the photoresist can act as a mask to largely prevent p-type dopants from being implanted in the PMOS regions will. The p-type dopants can be boron, BF2, indium or the like, and they are in the range with a concentration equal to or less than 10 ¹⁸ cm ^-3 , e.g. B. about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 , implanted. After the implantation, for example, the photoresist can be removed using a suitable detachment process.

After the implantation of the NMOS and PMOS areas of the substrate 50 an annealing process can be performed to activate the p- and / or n-dopants that have been implanted. In some embodiments, the substrate 50 grown epitaxially and doped in situ during growth so that the implantations can be omitted, but in situ doping and implantation doping can also be used together.

In 2nd become recesses 52 in that area 50A of the substrate 50 generated. The cutouts 52 can be produced using suitable photolithographic and etching processes. For example, a mask layer 54 over the substrate 50 getting produced. The mask layer 54 can be made of a non-metallic material such as silicon nitride, silicon oxide, silicon carbonitride, silicon oxide carbonitride, silicon oxide carbide or the like with a deposition method such as CVD or the like. The mask layer 54 can also be made from a metallic material such as titanium nitride, titanium, tantalum nitride, tantalum or the like by PVD, high frequency PVD (RFPVD), atomic layer deposition (ALD) or the like. After its manufacture, the mask layer 54 with openings that structure the recesses 52 in that area 50A correspond. The structuring can be realized as follows: production of a photoresist (not shown) over the mask layer 54 ; Expose and develop the photoresist to the structure of the recesses 52 to obtain; and transferring the structure of the photoresist to the mask layer 54 . The structured mask layer 54 can be used as an etching mask for etching the recesses 52 in that area 50A of the substrate 50 be used. The etching can be done using any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etch can be anisotropic.

In 3rd become epitaxial material stacks 56 in the recesses 52 produced. The epitaxial stacks of materials 56 have changing first semiconductor layers 58A and second semiconductor layers 58B on. The first semiconductor layers 58A are made of a first semiconductor material, and the second semiconductor layers 58B are made from a different, second semiconductor material. The first semiconductor material is a material that is suitable for producing channel regions of p-FETs, such as silicon germanium (Si _x Ge _1-x , where x can be 0 to 1). The second semiconductor material is a material that is suitable for producing channel regions of n-FETs, such as silicon. The epitaxial stacks of materials 56 can have a plurality of layers. In embodiments where GAA-FETs have six possible threshold voltages on the substrate 50 A total of eight layers (e.g. four of each semiconductor material) can be produced.

The epitaxial stacks of materials 56 are structured to channel areas of the GAA-FETs in the area 50A to manufacture. In particular, the epitaxial material stacks 56 patterned to produce horizontal nanowires, the channel regions of the resulting GAA-FETs having multiple horizontal nanowires. The GAA-FETs that come from the epitaxial material stacks 56 be produced (e.g. in the area 50A of the substrate 50 ) have a first threshold voltage V ₁ . The first threshold voltage V ₁ is low. In some embodiments, the first threshold voltage is V ₁ about -0.13 V to about -0.07 V for p-type devices and about 0.13 V to about 0.07 V for n-type devices.

The epitaxial stacks of materials 56 can with a first epitaxial growth process 60 be produced, which can be carried out in a growth chamber. During the first epitaxial growth process 60 becomes a first group of precursors for selectively growing the first semiconductor layers 58A in the recesses 52 cyclically introduced into the growth chamber, and then a second group of precursors for selectively growing the second semiconductor layers 58B in the recesses 52 initiated. The first group of precursors includes precursors for the first semiconductor material (e.g. silicon germanium), and the second group of precursors includes precursors for the second semiconductor material (e.g. silicon). The epitaxial stacks of materials 56 are not endowed. Therefore, include the precursors to the first epitaxial recovery process 60 no precursors for dopants. In some embodiments, the first group of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., Monogerman), and the second group of precursors includes the silicon precursor but not the germanium precursor. The first epitaxial growth process 60 may thus include: continuously introducing the silicon precursor into the growth chamber; and then cyclically (1) introducing the germanium precursor into the growth chamber when a first semiconductor layer 58A and (2) non-introducing the germanium precursor into the growth chamber when a second semiconductor layer 58B is grown up. The cyclical Treatment can be repeated until a desired number of layers have been produced.

In 4th a planarization process is performed around the top of the substrate 50 with tops of the epitaxial material stacks 56 bring it to the same level. The planarization process also makes the mask layer 54 and parts of the epitaxial material stack 56 removed that is outside of the recesses 52 are located. The planarization process can be a chemical mechanical polishing (CMP), an etch back process, a combination thereof, or the like. After the planarization process are the tops of the substrate 50 and the epitaxial stack of materials 56 at the same height.

In 5 become recesses 62 in that area 50B of the substrate 50 generated. The cutouts 62 can be done with a similar procedure as the procedure for creating the recesses 52 , e.g. B. using a structured mask layer 54 as an etching mask during a suitable etching process. Alternatively, the cutouts 62 be generated with another method.

In the 6 and 7 become epitaxial material stacks 66 in the recesses 62 produced. The epitaxial stacks of materials 66 have changing semiconductor layers. A first subset 66A of the layers comprises undoped semiconductor layers. A second subset 66B of the layers comprises doped semiconductor layers. The epitaxial stacks of materials 66 have the same number of layers as the epitaxial material stacks 56 .

The epitaxial stacks of materials 66 also become channel areas of GAA-FETs in the area 50B structured. The GAA-FETs that come from the epitaxial material stacks 66 (e.g. in the area 50B of the substrate 50 ) have a second threshold voltage V2 . The threshold voltage of a GAA-FET is influenced by the concentration of dopants in the channel region of the GAA-FET, a higher concentration of dopants leading to a higher threshold voltage. The concentration of dopants in a channel region of an FET relates to an average doping concentration for the nanowires that form the channel region of the FET. Because the epitaxial material stack 66 have doped layers, is the second threshold voltage V2 lower than the first threshold voltage V ₁ . In some embodiments, the second threshold voltage is V2 about -0.23 V to about -0.17 V for p-type devices, and is about 0.23 V to about 0.17 V for n-type devices.

The first subset 66A of the layers (see 6 ) includes changing first semiconductor layers 58A and second semiconductor layers 58B . The first subset 66A of the layers is accomplished by performing several cycles of the first epitaxial growth process 60 produced. In embodiments where GAA FETs with six possible threshold voltages are desired, the first subset comprises 66A the epitaxial stack of materials 66 half of all layers of the stack.

The second subset 66B of the layers (see 7 ) includes changing first semiconductor layers 70A and second semiconductor layers 70B . The first semiconductor layers 70A are made from the same basic semiconductor materials as the first semiconductor layers 58A (e.g. silicon germanium) and are additionally doped with Group V elements (e.g. phosphorus, arsenic, etc.). The second semiconductor layers 70B are made from the same semiconductor base materials as the second semiconductor layers 58B (e.g. silicon) and are additionally doped with elements of group III (e.g. boron). The second subset 66B the layers can be treated with a second epitaxial growth process 72 be produced in the same growth chamber as the first epitaxial growth process 60 can be carried out. During the second epitaxial growth process 72 become the same groups of precursors as in the first epitaxial recovery process 60 cyclically introduced into the growth chamber, and suitable dopant precursors are additionally introduced. During the second epitaxial growth process 72 For example, the first group of precursors may also include, for example, a precursor to the Group V dopant, and the second group of precursors may also include a precursor to the Group III dopant. The second epitaxial growth process 72 may thus include: continuously introducing the silicon precursor into the growth chamber; and then cyclically (1) introducing the germanium and group V precursors into the growth chamber when the first semiconductor layers 70A and (2) not introducing the germanium precursor and introducing the group III precursor into the growth chamber when the second semiconductor layers 70B grow up. The cyclic treatment can be repeated until a desired number of layers have been produced. If one takes up the example above, the second subset can 66B the epitaxial stack of materials 66 comprise half of all layers of the stack.

The first semiconductor layers 70A and the second semiconductor layers 70B can be doped to any doping concentration. As stated above, higher ones increase Doping concentrations the threshold voltages of the resulting GAA-FETs in the range 50B . The first semiconductor layers 70A and the second semiconductor layers 70B can be doped to the same concentration or to different concentrations. In some embodiments, the first semiconductor layers 70A doped with arsenic to a concentration of about 10 ¹⁷ cm ^-3 to about 10 ¹⁹ cm ^-3 (e.g. about 10 ¹⁹ cm ^-3 ), and the second semiconductor layers 70B are also doped with boron to a concentration of about 10 ¹⁷ cm ^-3 to about 10 ¹⁹ cm ^-3 (e.g. about 10 ¹⁹ cm ^-3 ).

In 8th a planarization process is performed around the top of the substrate 50 with tops of the epitaxial material stacks 66 bring it to the same level. Through the planarization process also the mask layer 64 and parts of the epitaxial material stack 66 removed that is outside of the recesses 62 are located. The planarization process can be a chemical mechanical polishing (CMP), an etch back process, a combination thereof, or the like. After the planarization process are the tops of the substrate 50 and the epitaxial stack of materials 56 and 66 at the same height.

In 9 become recesses 74 in that area 50C of the substrate 50 generated. The cutouts 74 can be done with a similar procedure as the procedure for creating the recesses 52 , e.g. B. using a structured mask layer 76 as an etching mask during a suitable etching process. Alternatively, the cutouts 74 be generated with another method.

In the 10th and 11 become epitaxial material stacks 78 in the recesses 74 produced. The epitaxial stacks of materials 78 have changing semiconductor layers. A first subset 78A of the layers comprises undoped semiconductor layers. A second subset 78B of the layers comprises doped semiconductor layers. The epitaxial stacks of materials 78 have the same number of layers as the epitaxial material stacks 56 and 66 .

The epitaxial stacks of materials 78 also become channel areas of GAA-FETs in the area 50C structured. The GAA-FETs that come from the epitaxial material stacks 78 (e.g. in the area 50C of the substrate 50 ) have a third threshold voltage V ₃ . As stated above, the threshold voltage of a GAA-FET is affected by the concentration of dopants in the channel region of the GAA-FET, and the concentration of dopants in a channel region relates to an average doping concentration for the nanowires that form the channel region. In the illustrated embodiments, similar layers have the epitaxial material stacks 66 and 78 the same doping concentration, and the number of doped semiconductor layers in the epitaxial material stacks 78 is higher than the number of doped semiconductor layers in the epitaxial material stacks 66 . In other embodiments (not shown), the layers have the epitaxial material stacks 66 and 78 different doping concentrations, and the number of doped semiconductor layers in the epitaxial material stacks 78 is equal to the number of doped semiconductor layers in the epitaxial material stacks 66 . The mean doping concentration in the epitaxial material stacks 78 is therefore higher than in the epitaxial material stacks 66 . Because the epitaxial material stack 78 more doped layers than the epitaxial material stacks 66 is the third threshold voltage V ₃ higher than the second threshold voltage V2 and the first threshold voltage V ₁ . In some embodiments, the third threshold voltage is V ₃ about -0.33 V to about -0.27 V for p-type devices, and is about 0.33 V to about 0.27 V for n-type devices.

The first subset 78A of the layers (see 10th ) includes changing first semiconductor layers 58A and second semiconductor layers 58B . The first subset 78A of the layers is accomplished by performing several cycles of the first epitaxial growth process 60 produced. In embodiments where GAA FETs with six possible threshold voltages are desired, the first subset comprises 78A the epitaxial stack of materials 78 a quarter of all layers of the stack.

The second subset 78B of the layers (see 11 ) includes changing first semiconductor layers 70A and second semiconductor layers 70B . The second subset 78B of the layers can be accomplished by performing multiple cycles of the second epitaxial growth process 72 getting produced. In embodiments where GAA FETs with six possible threshold voltages are desired, the second subset comprises 78B the epitaxial stack of materials 78 three quarters of all layers of the stack.

In 12 a planarization process is performed around the top of the substrate 50 with tops of the epitaxial material stacks 78 bring it to the same level. The planarization process also makes the mask layer 76 and parts of the epitaxial material stack 78 removed that is outside of the recesses 74 are located. The planarization process can be a chemical mechanical polishing (CMP), an etch back process, a combination thereof, or the like. After the planarization process, the tops of the Substrate 50 and the epitaxial stack of materials 56 , 66 and 78 at the same height.

The 13 to 20th and 22 14 are perspective views of further intermediate stages in the manufacture of GAA FETs in accordance with some embodiments. The 21A and 21B are sectional views taken along a reference cross section A / B - A / B of 22 are shown. It is just one of the areas 50A / 50B / 50C of the substrate 50 shown. It should be understood that a similar editing in all areas 50A / 50B / 50C of the substrate 50 can be carried out. And although only one gate structure and only one pair of source / drain regions are shown, it should be understood that multiple gate structures and multiple source / drain regions can be fabricated.

In 13 become Finns 90 and ATM structures 92 in the substrate 50 produced. Finns 90 are semiconductor layers, and the GAA structures 92 are on the fins 90 arranged. In some embodiments, the fins 90 and the ATM structures 92 each by etching trenches in the substrate 50 and the epitaxial material stacks 56 , 66 and 78 getting produced.

The ATM structures 92 can be structured using any suitable method. For example, the structures can be structured using one or more lithographic processes, such as double structuring or multiple structuring processes. In general, double structuring or multiple structuring processes combine photolithographic and self-aligned processes that can be used to produce structures that have, for example, grid spacings that are smaller than those that can otherwise be achieved with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is made over a substrate, which is then patterned using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to structure the ATM structures 92 be used.

In some embodiments, the remaining spacers are used to pattern a mask 94 then used to structure the ATM structures 92 and the Finns 90 is used. The mask 94 can be a single-layer mask or a multi-layer mask, such as a multi-layer mask that includes a first mask layer 94A and a second mask layer 94B having. The first mask layer 94A and the second mask layer 94B can each be made from a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using suitable methods. The first mask layer 94A and the second mask layer 94B have different materials that have a high etching selectivity. For example, the first mask layer 94A Have silicon oxide, and the second mask layer 94B can have silicon nitride. The mask 94 can be structured using a suitable etching process. The mask 94 can then be used as an etching mask to etch the substrate 50 and the epitaxial stack of materials 56 , 66 and 78 be used. The etching can be done by any suitable etching method such as reactive ion etching (RIE), neutral beam etching (NBE) or the like or a combination thereof. The etch can be anisotropic.

In 14 become STI areas 96 (STI: shallow trench isolation) over the substrate 50 and between neighboring Finns 90 produced. As an example of making the STI areas 96 can be an insulating material over the substrate 50 be deposited. The insulating material may be an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be flowable CVD (FCVD) (e.g., material deposition) through chemical vapor deposition (HDP-CVD) CVD base in a remote plasma system and post-curing to convert the material to another material (such as an oxide) or the like, or a combination thereof. Other insulating materials made by a suitable method can also be used. In the illustrated embodiment, the insulating material is silicon oxide, which is deposited using an FCVD process. After the insulation material has been deposited, an annealing process can be carried out. In one embodiment, the insulation material is deposited so that excess insulation material fins 90 and the ATM structures 92 covered. In some embodiments, a topping is first used 96A along surfaces of the substrate 50 and the Finns 90 manufactured, and over the topping 96A becomes a filler 96B deposited, such as that discussed above. In some embodiments, the topping 96A omitted. Then a removal process for the insulation material is used to remove excess insulation material over the fins 90 and the ATM structures 92 to remove. In some embodiments, a planarization process, such as a CMP, an etch back process, a combination thereof, or the like, may be used. Through the planarization process, the ATM structures 92 exposed, leaving tops of the ATM structures 92 and the insulating material after the The planarization process has ended at the same level. Then the insulation material is cut out around the STI areas 96 to manufacture. The insulating material is cut out so that the ATM structures 92 between neighboring STI areas 96 stick out. You can also use the top of the STI areas 96 have a flat surface as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The tops of the STI areas 96 can be made flat, convex and / or concave by suitable etching. The STI areas 96 can be done using a suitable etching process, such as one that is selective for the insulating material (e.g., the insulating material at a higher speed than the material of the fins 90 and the ATM structures 92 etched). For example, chemical oxide removal using a suitable etching process e.g. B. using dilute hydrofluoric acid (dHF acid).

In 15 become dummy dielectrics 100 on the ATM structures 92 manufactured, and on the dummy dielectrics 100 become dummy gates 102 produced. As an example of manufacturing the dummy dielectrics 100 and the dummy gates 102 can have a dummy dielectric layer on the GAA structures 92 and the STI areas 96 getting produced. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof or the like and can be deposited or thermally grown using suitable methods. A dummy gate layer can then be formed over the dummy dielectric layer. The dummy gate layer can be deposited over the dummy dielectric layer and then planarized, for example with a CMP. The dummy gate layer can be a conductive material that can be selected from the group of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides and metals. The dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or by other methods known and used in the conductive material deposition art. The dummy gate layer can also be produced from other materials which have a high etching selectivity due to the etching of insulation regions. Then masks 104 made over the dummy gate layer. The masks 104 can be made from silicon nitride, silicon oxide nitride, combinations thereof, or the like, and can be patterned using suitable photolithographic and etching methods. The structure of the masks 104 can then be transferred to the dummy gate layer using a suitable etching process to form the dummy gates 102 and it can then be transferred to the dummy dielectric layer using a suitable etching process to remove the dummy dielectrics 100 to manufacture. The dummy gates 102 cover respective channel areas of the ATM structures 92 . The structure of the masks 104 can be used to physically separate each of the dummy gates 102 used by neighboring dummy gates. The dummy gates 102 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the fins 90 is.

In 18th becomes a gate spacer layer 106 by conformally depositing an insulating material over the ATM structures 92 , the STI areas 96 and the dummy gates 102 produced. The insulating material may be silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer 106 comprise several sub-layers. For example, a first sub-layer (sometimes referred to as a gate seal spacer layer) can be formed by thermal oxidation or deposition, and a second sub-layer (sometimes referred to as a main gate spacer layer) can conform to the first sub-layer be deposited.

After making the gate spacer layer 106 can be performed for lightly doped source / drain areas (LDD areas; not shown). Suitable dopants (e.g. p- or n-dopants) can be found in the exposed GAA structures 92 and / or Finns 90 be implanted. The n-type dopants can all be the n-type dopants mentioned above and the p-type dopants can all be the p-type dopants mentioned above. The lightly doped source / drain regions can have a doping concentration of approximately 10 ¹⁵ cm ^-3 to approximately 10 ¹⁶ cm ^-3 . The implanted dopants can be activated with a tempering process.

In 17th become gate spacers 108 by anisotropically etching the gate spacer layer 106 produced. The anisotropic etching allows horizontal parts of the gate spacer layer 106 (e.g. above the STI areas 96 and the dummy gates 102 ) are removed, leaving remaining vertical portions of the gate spacer layer 106 (e.g. along sides of the dummy gates 102 and the ATM structures 92 ) the gate spacers 108 form.

Furthermore, source / drain recesses 110 in the ATM structures 92 generated. The source / drain recesses 110 can look through the ATM structures 92 stretch and into the fins 90 reach into it. The source / drain recesses 110 can be made using suitable etching techniques using the dummy gates 102 as an etching mask.

In 18th become source / drain epitaxial regions 112 in the source / drain recesses 110 manufactured to provide mechanical tension in respective channel areas of the ATM structures 92 should be entered so that the performance is improved. The source / drain epitaxial regions 112 are in the ATM structures 92 made so that each dummy gate 102 between respective adjacent pairs of the source / drain epitaxial regions 112 is arranged. In some embodiments, the source / drain epitaxial regions 112 in the Finns 90 reach into it and penetrate it. In some embodiments, the gate spacers 108 used to cover the source / drain epitaxial regions 112 with a suitable lateral distance from the dummy gates 102 separate so that the source / drain epitaxial areas 112 Do not short-circuit gates of the resulting GAA-FETs produced later.

The source / drain epitaxial regions 112 become epitaxial in the source / drain recesses 110 grew up. The source / drain epitaxial regions 112 can be a suitable material, such as a material suitable for n- or p-GAA FETs. For example, when fabricating n-GAA FETs, the source / drain epitaxial regions can 112 Have materials that apply tensile stress to the channel regions, such as silicon, SiC, SiCP, SiP or the like. Likewise, when p-GAA FETs are fabricated, the source / drain epitaxial regions can 112 Have materials that apply compressive stress to the channel areas, such as SiGe, SiGeB, Ge, GeSn or the like. The source / drain epitaxial regions 112 can have surfaces that face respective fin surfaces 90 are elevated and they can have bevels.

The source / drain epitaxial regions 112 and / or the Finns 90 can be implanted with dopants to produce source / drain regions similar to the process discussed above for fabricating lightly doped source / drain regions, followed by an annealing process. The source / drain regions can have a doping concentration of approximately 10 ¹⁹ cm ^-3 to approximately 10 ²¹ cm ^-3 . The n and / or p dopants for the source / drain regions can all be the dopants mentioned above. In some embodiments, the source / drain epitaxial regions 112 be doped in situ while growing up.

Through the epitaxial processes used to create the source / drain epitaxial regions 112 used have tops of the source / drain epitaxial regions 112 Bevels that extend laterally outwards over the side walls of the fins 90 stretch out. In the illustrated embodiment, these bevels cause adjacent source / drain epitaxial regions to merge 112 one and the same GAA FET as shown. In other embodiments (not shown), adjacent source / drain epitaxial regions remain 112 separated after the end of the epitaxial process.

In 19th becomes a first interlayer dielectric (ILD) 114 deposited over the intermediate structure shown. The first ILD 114 can be made from a dielectric material and can be deposited using a suitable method such as CVD, plasma enhanced chemical vapor deposition (PECVD) or FCVD. Dielectric materials can be phosphorus silicate glass (PSG), borosilicate glass (BSG), boron phosphorus silicate glass (BPSG), undoped silicate glass (USG) or the like. Other insulating materials that are deposited using a suitable method can also be used. In some embodiments, a contact etch stop layer (CESL) 116 between the first ILD 114 and the source / drain epitaxial regions 112 , the gate spacers 108 and the STI areas 96 deposited. The CESL 116 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, that has a different etch rate than the material of the first ILD overlying it 114 Has.

A planarization process, such as a CMP, can also be performed around the tops of the first ILD 114 and the CESL 116 level with the top of the dummy gates 102 and the gate spacer 108 bring to. The masks can also be created through the planarization process 104 on the dummy gates 102 and parts of the gate spacers 108 along side walls of the masks 104 be removed. After the planarization process, the tops are the dummy gates 102 , the gate spacer 108 and the first ILD 114 at the same height. Accordingly, the tops of the dummy gates 102 through the first ILD 114 exposed.

In 20th become the dummy gates 102 removed in one or more etching steps, leaving recesses 118 arise. Parts of the dummy dielectric 100 in the recesses 118 can also be removed. In some embodiments, the dummy dielectric 100 from recesses 118 removed in a first area of a die (e.g., a core logic area) and it remains in recesses 118 in a second area of the dies (e.g. an input / output area) consist. In some embodiments, the dummy gates 102 removed with an anisotropic dry etching process. For example, the etching process may be a dry etching process using one or more reaction gases that selectively select the dummy gates 102 etch without the first ILD 114 or the gate spacers 108 to etch. Every recess 118 defines a channel area of a respective ATM structure 92 free. Each channel region is between adjacent pairs of the source / drain epitaxial regions 112 arranged. During the removal, the dummy dielectric can 100 can be used as an etch stop layer when the dummy gates 102 be etched. The dummy dielectric 100 can after removing the dummy gates 102 optionally removed.

After removing the dummy gates 102 and the dummy dielectric 100 become corresponding parts of the ATM stack 92 away. When producing p-FETs (see 21A) , the second semiconductor layers 58B from the GAA stacks 92 removed so that the first semiconductor layers 58A than the channel regions of the p-FETs remain. When producing n-FETs (see 21B) , become the first semiconductor layers 58A from the GAA stacks 92 removed so the second semiconductor layers 58B than the channel regions of the n-FETs remain. The removal can be done with a suitable etching process, such as an anisotropic wet etching, which is selective for the desired material (e.g. silicon germanium if the first semiconductor layers 58A removed, or silicon if the second semiconductor layers 58B be removed). The GAA stack 92 can be in a process other than the process of creating the recesses 118 can be etched, or they can be etched in the same process.

In 22 become dielectric gate layers 120 and gate electrodes 122 made for replacement gates. The dielectric gate layers 120 are compliant in the recesses 118 deposited, such as on the tops and sidewalls of the Finns 90 and on the side walls of the gate spacers 108 . The dielectric gate layers 120 can also be on top of the first ILD 114 getting produced. It should be noted that the gate dielectric layers 120 the remaining vertical nanowires of the ATM stacks 92 enclose. When producing p-FETs (see 23A) , enclose the dielectric gate layers 120 the remaining first semiconductor layers 58A and 70A (e.g. the nanowires of the p-GAA FETs). When producing n-FETs (see 23B) , enclose the dielectric gate layers 120 the remaining second semiconductor layers 58B and 70B (e.g. the nanowires of the n-GAA FETs). In some embodiments, the gate dielectric layers have 120 Silicon oxide, silicon nitride or multilayers thereof. In some embodiments, the gate dielectric layers have 120 a high-k dielectric material, and in these embodiments, the gate dielectric layers 120 have a k value greater than about 7.0 and can include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb and combinations thereof. As a manufacturing process for the dielectric gate layers 120 molecular beam deposition (MBD), ALD, PECVD and the like can be used. In embodiments where parts of the dummy dielectrics 100 in the recesses 118 remain, the dielectric gate layers have 120 a material of dummy dielectrics 100 (e.g. SiO ₂ ).

The gate electrodes 122 are over and around the dielectric gate layers 120 deposited and fill the remaining parts of the recesses 118 . The gate electrodes 122 may include a metal-containing material, such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, or combinations thereof or multilayers thereof. Although a single layer gate electrode 122 is shown, the gate electrode 122 have any number of facings, any number of work function adjustment layers (to be discussed later) and a filler. After filling the gate electrodes 122 A planarization process, such as a CMP, can be performed to cover the top of the first ILD 114 excess parts of the dielectric gate layers 120 and the material of the gate electrodes 122 to remove. The remaining parts of the material of the gate electrodes 122 and the gate dielectric layers 120 thus form replacement gates of the resulting GAA-FETs. A single gate electrode 122 and corresponding gate dielectric layers 120 can be collectively called a "gate stack". Each gate stack runs around the nanowires by structuring the GAA structures 92 getting produced.

In some embodiments, the work function layers are different for n and p devices. When producing p-FETs (see 23A) , becomes a first group of work function adjustment layers 124A around each gate dielectric layer 120 produced. When producing n-FETs (see 23B) , becomes a second group of work function adjustment layers 124B around each gate dielectric layer 120 produced. The first group of work function adjustment layers 124A has work function metals other than the second group of work function adjustment layers 124B on. For example, the first group of work function adjustment layers 124A Have TiN, TaN or Mo, and the second group of work function adjustment layers 124B can WN, Ta or Ti have. The materials chosen for the work function adjustment layers modify the threshold voltages of the resulting GAA-FETs. Because the ATM structures 92 three initial threshold voltages ( V ₁ , V ₂ and V ₃ ) and there are two groups of selectable work function adjustment layer materials (n and p materials), the resulting GAA-FETs can have one of six possible threshold voltages.

In 24th becomes a second ILD 126 above the first ILD 114 deposited. In some embodiments, the second is ILD 126 a flowable layer made by flowable CVD. In some embodiments, the second ILD 126 made of a dielectric material such as PSG, BSG, BPSG, USG or the like and can be deposited by any suitable method such as CVD and PECVD. In some embodiments, a gate mask (not shown) is formed over the gate stacks before the second ILD 126 will be produced.

In addition, in some embodiments, gate contacts 128 and source / drain contacts 130 through the second ILD 126 and the first ILD 114 produced. Through the first ILD 114 and the second ILD 126 become openings for the source / drain contacts 130 generated, and by the second ILD 126 (and optionally the gate mask) are openings for the gate contact 128 generated. The openings can be created using suitable photolithographic and etching processes. A covering, such as a diffusion barrier layer, an adhesive layer or the like, is produced in the openings. The coating can have titanium, titanium nitride, tantalum, tantalum nitride or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel or the like. A planarization process, such as a CMP, can be performed to remove excess material from a top of the second ILD 126 to remove. The remaining covering and the remaining conductive material form the source / drain contacts 130 and the gate contacts 128 in the openings. An annealing process can be performed to remove a silicide at the interface between the source / drain epitaxial regions 112 and the source / drain contacts 130 to create. The source / drain contacts 130 are physical and electrical with the source / drain epitaxial regions 112 connected, and the gate contacts 128 are physical and electrical with the gate electrodes 122 connected. The source / drain contacts 130 and the gate contacts 128 can be made in different processes or they can be made in the same process. Although it is shown that the source / drain contacts 130 and the gate contacts 128 are manufactured with the same cross-sections, it should be understood that they can be manufactured with different cross-sections, which prevents the contacts from being short-circuited.

The 25A to 25C 14 are sectional views showing intermediate stages in the manufacture of GAA-FETs according to further embodiments. As stated above, the doping concentration in a channel region relates to an average doping concentration. 25A shows an embodiment in which some epitaxial material stacks, such as the epitaxial material stacks 66 , include half as many layers as other stacks, but have layers twice the thickness of layers from other stacks. The epitaxial stacks of materials 66 from 25A thus have the same mean doping concentration as the epitaxial material stacks 66 from 12 . The ATM structures in the area 508 can therefore be manufactured with fewer epitaxial steps, which can lower the manufacturing costs. The 25B and 25C show sectional views of resulting GAA-FETs in the area 50B . The p-components (see 25B) and the n components (see 25C ) both have larger nanowires in their channel areas, which can absorb higher channel currents.

Embodiments can achieve some merits. By manufacturing multiple epitaxial material stacks with doped and undoped areas, GAA-FETs with different threshold voltages can be created on the same substrate. By using different work function materials for n and p components, the number of possible different threshold voltages can also be increased.

In one embodiment, a method includes the steps of: creating a first recess and a second recess in a substrate; Growing a first epitaxial material stack in the first recess, the first epitaxial material stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; Growing a second epitaxial material stack in the second recess, the second epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped and a second subset of the second epitaxial material stack being doped; Patterning the first epitaxial material stack and the second epitaxial material stack to produce first nanowires and second nanowires, respectively; and fabricating a first gate structure around the first nanowires and a second gate structure around the second nanowires.

In some embodiments of the method, the first semiconductor material is silicon germanium and the second semiconductor material is silicon, layers of silicon germanium in the second subset of the second epitaxial material stack being doped with a Group V element and layers of silicon in the second subset of the second epitaxial material stack a Group III element. In some embodiments of the method, fabricating the first gate structure includes depositing a first metal around the first nanowires, and fabricating the second gate structure includes depositing a second metal around the second nanowires, the second metal being different from the first metal. In some embodiments, the method further includes: creating a third recess in the substrate; Growing a third epitaxial material stack in the third recess, the third epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the third epitaxial material stack being undoped and a second subset of the third epitaxial material stack being doped, the second subset of the third epitaxial material stack comprises more layers than the second subset of the second epitaxial material stack; Patterning the third epitaxial material stack to produce third nanowires; and fabricating a third gate structure around the third nanowires. In some embodiments of the method, growing the first epitaxial material stack comprises growing the first epitaxial material stack with a first epitaxial growth process. In some embodiments of the method, growing the second epitaxial material stack comprises: growing the first subset of the second epitaxial material stack with the first epitaxial growth process; and growing the second subset of the second epitaxial material stack with a second epitaxial growth process, the second epitaxial growth process being different from the first epitaxial growth process. In some embodiments of the method, growing the third epitaxial material stack comprises: growing the first subset of the third epitaxial material stack with the first epitaxial growth process; and growing the second subset of the third epitaxial material stack with the second epitaxial growth process. In some embodiments of the method, patterning the first epitaxial material stack comprises: etching trenches in the first epitaxial material stack to produce a first gate all-around (GAA) structure with alternating layers of the first semiconductor material and the second semiconductor material; Making first gate spacers over the first ATM structure; and etching parts of the first GAA structure between the first gate spacers, the etching selectively removing the layers of the first semiconductor material and remaining layers of the second semiconductor material forming the first nanowires. In some embodiments, the method further includes planarizing the substrate so that tops of the second epitaxial material stack, the first epitaxial material stack, and the substrate are level.

In one embodiment, a method has the following steps: growing a first epitaxial material stack in a substrate, the first epitaxial material stack having a first average doping concentration; Growing a second epitaxial material stack in the substrate, the second epitaxial material stack having a second average doping concentration; Growing a third epitaxial material stack in the substrate, the third epitaxial material stack having a third average doping concentration, the first average doping concentration, the second average doping concentration and the third average doping concentration being different; Planarizing the substrate so that tops of the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack are at the same level; Structuring the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack to produce first nanowires, second nanowires and third nanowires, respectively; and fabricating a first gate structure around the first nanowires, a second gate structure around the second nanowires, and a third gate structure around the third nanowires.

In some embodiments of the method, the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack have the same number of layers. In some embodiments of the method, the first epitaxial material stack and the third epitaxial material stack have a first number of layers, and the second epitaxial material stack has a second number of layers, the second number being different from the first number.

In one embodiment, an apparatus includes: a first transistor having first nanowires and a first gate structure around the first nanowires, the first nanowires having a first average doping concentration and the first gate structure comprising a first group of work function adjustment layers; a second transistor having second nanowires and a second gate structure around the second nanowires, the second nanowires having a second average doping concentration, the second average doping concentration different from the first average doping concentration, and the second gate structure comprising the first group of work function adjustment layers ; a third transistor having third nanowires and a third gate structure around the third nanowires, the third nanowires having the first average doping concentration and the third gate structure comprising a second group of work function adjustment layers; and a fourth transistor having fourth nanowires and a fourth gate structure around the fourth nanowires, the fourth nanowires having the second mean doping concentration and the fourth gate structure comprising the second group of work function adjustment layers, the second group of work function adjustment layers from the first group is different from work function adjustment layers.

In some embodiments of the device, the first transistor, the second transistor, the third transistor and the fourth transistor each have the same number of nanowires. In some embodiments of the device, the first transistor and the third transistor have a first number of nanowires, and the second transistor and the fourth transistor have a second number of nanowires, the second number being different from the first number. In some embodiments of the device, the first transistor and the second transistor are p-gate all around field effect transistors (p-GAA-FETs) and the third transistor and the fourth transistor are n-GAA-FETs. In some embodiments of the device, the first nanowires comprise undoped silicon germanium, a first subset of the second nanowires comprises undoped silicon germanium, and a second subset of the second nanowires comprises silicon germanium doped with a group V dopant. In some embodiments of the device, the first group of work function adjustment layers comprises TiN, TaN or Mo. In some embodiments of the device, the third nanowires comprise undoped silicon, a first subset of the fourth nanowires comprises undoped silicon, and a second subset of the fourth nanowires comprises silicon doped with a group III dopant. In some embodiments of the device, the second group of work function adjustment layers comprises WN, Ta or Ti.

Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It will be apparent to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same goals and / or to achieve the same benefits as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent interpretations do not depart from the spirit and scope of the present invention and that they can make various changes, substitutions and modifications here without departing from the spirit and scope of the present invention.

Claims (20)

Procedure with the following steps: Creating a first recess and a second recess in a substrate; Growing a first epitaxial material stack in the first recess, the first epitaxial material stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; Growing a second epitaxial material stack in the second recess, the second epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped and a second subset of the second epitaxial material stack being doped; Patterning the first epitaxial material stack and the second epitaxial material stack to produce first nanowires and second nanowires, respectively; and Fabricating a first gate structure around the first nanowires and a second gate structure around the second nanowires. Procedure according to Claim 1 , wherein the first semiconductor material is silicon germanium and the second semiconductor material is silicon, layers of silicon germanium in the second subset of the second epitaxial material stack being doped with an element from group V and layers of silicon in the second subset of the second epitaxial material stack with an element of Group III will be endowed. Procedure according to Claim 1 or 2nd wherein fabricating the first gate structure includes depositing a first metal around the first nanowires, and fabricating the second gate structure includes depositing a second metal around the second nanowires, the second metal different from the first metal. The method of any preceding claim, further comprising: creating a third recess in the substrate; Growing a third epitaxial material stack in the third recess, the third epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the third epitaxial material stack being undoped and a second subset of the third epitaxial material stack being doped, the second subset of the third epitaxial material stack comprises more layers than the second subset of the second epitaxial material stack; Patterning the third epitaxial material stack to produce third nanowires; and fabricating a third gate structure around the third nanowires. Procedure according to Claim 4 , wherein the growing up of the first epitaxial material stack comprises growing up the first epitaxial material stack with a first epitaxial growth process. Procedure according to Claim 5 wherein growing the second epitaxial stack of materials comprises: growing the first subset of the second epitaxial stack of materials with the first epitaxial growth process; and growing the second subset of the second epitaxial material stack with a second epitaxial growth process, the second epitaxial growth process being different from the first epitaxial growth process. Procedure according to Claim 6 wherein growing the third epitaxial stack of materials comprises: growing the first subset of the third epitaxial stack of materials with the first epitaxial growth process; and growing the second subset of the third epitaxial material stack with the second epitaxial growth process. The method of any preceding claim, wherein structuring the first epitaxial stack of materials comprises: Etching trenches in the first epitaxial material stack to produce a first gate all-around (GAA) structure with alternating layers of the first semiconductor material and the second semiconductor material; Making first gate spacers over the first ATM structure; and Etching parts of the first GAA structure between the first gate spacers, the etching selectively removing the layers of the first semiconductor material and remaining layers of the second semiconductor material forming the first nanowires. The method of any preceding claim, further comprising planarizing the substrate so that tops of the second epitaxial material stack, the first epitaxial material stack, and the substrate are level. Procedure with the following steps: Growing a first epitaxial material stack in a substrate, the first epitaxial material stack having a first average doping concentration; Growing a second epitaxial material stack in the substrate, the second epitaxial material stack having a second average doping concentration; Growing a third epitaxial material stack in the substrate, the third epitaxial material stack having a third average doping concentration, the first average doping concentration, the second average doping concentration and the third average doping concentration being different; Planarizing the substrate so that tops of the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack are at the same level; Structuring the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack to produce first nanowires, second nanowires and third nanowires, respectively; and Manufacture of a first gate structure around the first nanowires, a second gate structure around the second nanowires and a third gate structure around the third nanowires. Procedure according to Claim 10 , wherein the first epitaxial material stack, the second epitaxial material stack and the third epitaxial material stack comprise the same number of. Procedure according to Claim 10 , wherein the first epitaxial material stack and the third epitaxial material stack comprise a first number of layers and the second epitaxial material stack comprises a second number of layers, the second number being different from the first number. An apparatus comprising: a first transistor having first nanowires and a first gate structure around the first nanowires, the first nanowires having a first average doping concentration and the first gate structure comprising a first group of work function adjustment layers; a second transistor with second nanowires and a second gate structure around the second nanowires, the second nanowires having a second average doping concentration, the second average doping concentration being different from that the first average dopant concentration is different and the second gate structure comprises the first group of work function adjustment layers; a third transistor having third nanowires and a third gate structure around the third nanowires, the third nanowires having the first average doping concentration and the third gate structure comprising a second group of work function adjustment layers; and a fourth transistor with fourth nanowires and a fourth gate structure around the fourth nanowires, the fourth nanowires having the second average doping concentration and the fourth gate structure comprising the second group of work function adjustment layers, the second group of work function adjustment layers from the first group is different from work function adjustment layers. Device after Claim 13 , wherein the first transistor, the second transistor, the third transistor and the fourth transistor each comprise the same number of nanowires. Device after Claim 13 , wherein the first transistor and the third transistor comprise a first number of nanowires and the second transistor and the fourth transistor comprise a second number of nanowires, the second number being different from the first number. Device according to one of the Claims 13 to 15 , wherein the first transistor and the second transistor are p-gate all-around field effect transistors (p-GAA-FETs) and the third transistor and the fourth transistor are n-GAA-FETs. Device according to one of the Claims 13 to 16 , wherein the first nanowires have undoped silicon germanium, a first subset of the second nanowires undoped silicon germanium and a second subset of the second nanowires silicon germanium doped with a Group V dopant. Device according to one of the Claims 13 to 17th wherein the first group of work function adjustment layers comprises TiN, TaN or Mo. Device according to one of the Claims 13 to 16 , wherein the third nanowires comprise undoped silicon, a first subset of the fourth nanowires undoped silicon and a second subset of the fourth nanowires silicon which is doped with a dopant of group III. Device according to one of the Claims 13 to 19th wherein the second group of work function adjustment layers comprises WN, Ta or Ti.

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