DE102019112801A1 - Backwards compatible bus system with low bus resistance with the ability to assign the bus node addresses using AMR or GMR measuring equipment - Google Patents

Abstract

The invention relates to a bus node (BK) for a single-wire data bus (bus) with the ability to take part in an auto-addressing method and corresponding further variants and methods that the bus node and the data bus system carry out. The bus node (BK) is intended to be inserted into the single-wire data bus (bus). It has a bus node controller (BS) and at least one coupling device with a preferred internal resistance of less than 0.5 Ω, which preferably has a magnetic field-generating sub-device (L) in combination with a measuring system (HL), in particular an AMR measuring device or a GMR Measuring device for detecting the generated magnetic flux density (B). The coupling device (L, HL, D1, R2) is intended to be flowed through by a bus current (I) of the single-wire data bus (bus) at least temporarily in the addressing phase in the direction of a bus master (BM). In the event of such a flow through the bus current (I), the coupling device (L, HL, D1, R2) generates a measured value of the bus current (I) which depends on the bus current (I). The address assignment by the bus node controller (BS) then takes place as a function of this measured value of the bus current (I), which is detected by the coupling device (HL, L, D1, R2).

Description

preamble

The invention relates to a bus node for a single-wire data bus capable of participating in an auto-addressing method, the bus node recognizing the auto-addressing current by means of a magnetic field, and an associated method.

General introduction

Various methods for address assignment in LIN bus systems are known from the prior art. Here is an example of the scriptures DE 10 2010 026 431 B1 . DE 10 147 512 B4 . EP 1490 772 B1 and US 9 331 866 B2 directed.

All of these documents have in common that the amount of bus nodes which can be addressed by the bus master is limited, since a bus shunt resistor must be provided for each bus node, which is typically 1 to 2 ohms in the prior art. As a result, the bus resistance increases overall, which leads to deterioration in the electromagnetic compatibility and other disadvantages. Therefore, there was a need on the market for a technical solution that a) is compatible with the previous solutions and b) may require a lower bus shunt resistance.

Object of the invention

The object of the proposal is therefore to create a solution which does not have the above disadvantages of the prior art and has further advantages.

This object is achieved by a device according to claim ... and a method according to claim ....

Solution of the task according to the invention

For better orientation, the following directions are first agreed on the data bus: The viewing direction from a bus node is such that everything that is in the data bus between the bus node and bus master is located BEFORE the bus node and everything that is between the bus node and the end of the data bus is located AFTER the bus node. These definitions apply throughout the following document.

The following describes the procedure for automatic address assignment based on a standard-compliant LIN bus system, in which a node with a bridged bus shunt resistor is inserted as an extreme case. In contrast to the methods and devices of DE 10 147 512 B4 . EP 1 490 772 B1 and US 9 331 866 B2 the resistance value of the bus shunt resistor is reduced to the exemplary extreme value of 0 ohms. The Local Interconnect Network (LIN), also called LIN bus, is a serial communication system for the networking of sensors and actuators, a field bus. LIN is used where the bandwidth and versatility of CAN is not required. Typical applications are networking within the door or seat of a motor vehicle. The relevant standard is the ISO standard 17987-1, "Road vehicles - Local interconnect network (LIN) - Part 1-7".

When assigning the bus node addresses according to the prior art, the bus master signals to the bus participants that it wants to assign a bus node address. The bus nodes that do not yet have a valid bus node address then feed a defined addressing stream into the bus line, which flows to the bus master. This addressing stream of a bus node can be detected by all other bus nodes upstream of the feeding bus node and can be recognized from this that they are not the last bus nodes in the direction of the end of the data bus. The last bus node without a valid bus node address does not record an addressing current of a bus node lying behind it without a valid bus node address, since there is no such one and can then take over the new bus node address offered by the bus master. Various variants are known for this, which can be combined with the method described here or the device described here.

The basic idea of the following method and the device described below is now to detect the electrical addressing current through the data bus in the addressing phase instead of the electrical resistance of a bus shunt resistor using a current measuring device which does not record the voltage drop but the magnetic field, that this generates electrical current as it flows through the data bus.

For this purpose, it is useful, for example, to provide a GMR or AMR measuring device which is combined with a device which, depending on the current flow through the data bus, generates a magnetic field which penetrates the GMR or AMR measuring device.

A mixed installation capability is imperative in the market. Therefore, the conventional award method cannot be dispensed with. Therefore, it makes sense if an integrated circuit to support the method proposed here and at the same time should be compatible with the prior art, has a first data bus input and a data bus output which is connected by an internal bus shunt resistor of a conventional type. A conventional sub-device within the integrated circuit evaluates the voltage drop across the bus shunt resistor in the addressing phase, as is known from the prior art, so that the proposed device is fully compatible with the prior art.

However, going beyond the prior art, it is now proposed that at least one of the two connections be connected to a third connection with a very low resistance via a magnetic field-generating sub-device. Such a magnetic field generating device can be, for example, a flat coil integrated in the integrated circuit, which is located above the GMR resistance of a GMR measuring device or above the AMR resistance of an AMR measuring device. The bus node modified in this way is then preferably connected in such a way that it is inserted into the data bus with its first connection and the third connection.

The internal bus shunt resistor is preferably short-circuited externally by connecting the second bus connection to the first bus connection. In the case of a bus current, the bus node controller of a bus node according to the invention then recognizes that the GMR or AMR measuring device reports a bus current, while the bus shunt measuring system does not detect any voltage drop across the bus shunt and thus does not detect any bus current.

As a result, the bus node controller recognizes that the auto-addressing is not to be carried out by means of the bus shunt resistor, but rather by means of the measured value of the GMR or AMR measuring device.

From the as yet unpublished German patent application DE 10 2017 122 365.7 , which is a complete part of this disclosure, it is known that addressing can preferably be carried out with the maximum possible addressing current, in which case the measured current value of the voltage drop across the bus shunt resistor is used as a control parameter for feeding in the own addressing current. If the bus current is now detected by means of the GMR or AMR measuring device, the bus node controller switches this addressing current control, if present, in such a way that the measured value which is detected by the GMR or AMR measuring device is used as a control parameter instead of the Measured value from the current measurement using bus shunt resistor is used.

Various methods are known from the prior art which can be combined with the idea according to the invention.

A bus node (SL1, SL2, SL3) for a single-wire data bus (bus) with the ability to participate in an auto-addressing method is proposed here. In particular, the technical teachings of the following writings are considered as basic technologies as the auto-addressing method: EP 1490 772 B1 . DE 10 2010 026 431 B4 . EP 1 603 282 B1 . EP 1 364 288 B1 as well as the as yet unpublished German patent applications DE 10 2017 122 364.9 . DE 10 2017 122 365.7 ; DE 10 2017 012 179.6 ; DE 10 2017 128 489.3 ; DE 10 2017 128 923.2 ; DE 10 2018 104 488.7 . DE 10 2018 104 489.5 whose technical teaching is a full part of this disclosure.

The bus node ( SL1 . SL2 . SL3 ) intended to be inserted into the single-wire data bus (bus). The bus node ( SL1 . SL2 . SL3 ) is preferably provided with a bus node controller (BS) that controls the internal processes within the bus node ( SL1 . SL2 . SL3 ) controls. What is new compared to the prior art is the use of a magnetic field generating sub-device ( L ), which is preferably a flat coil connected to the integrated circuit of the bus node ( SL1 . SL2 . SL3 ) is preferably integrated monolithically. This coil has a low resistance and the bus current flows through it. According to the invention, it has now been recognized that it makes sense to use a measuring system ( HL ) for detecting the from the coil ( L ) generated magnetic flux density ( B ) in the integrated circuit of the bus node ( SL1 . SL2 . SL3 ) and to solve the problem of excessive bus resistance. Since the through the coil ( L ) generated magnetic flux density ( B ) proportional to the bus current ( i1 . i2 . i3 ) is, when this flux density is recorded by a measuring system ( HL ) for this flux density ( B ) the determined measured value as a measured value for the bus current ( i1 . i2 . i3 ) to be used. Such a measuring device is particularly preferred ( HL ) for this flux density ( B ) a GMR measuring device with a GMR measuring resistor or an AMR measuring device with an AMR resistor. The magnetic field generating device ( L ) is preferably provided by a bus stream ( i1 . i2 . i3 ) of the single-wire data bus (bus) at least temporarily in the addressing phase towards a bus master ( ECU ) to be flowed through. The magnetic field generating device ( L ) generated in the event of such a flow through the bus current ( i1 . i2 . i3 ) a magnetic flux ( B ), which is at least partially the measuring system ( HL ) flows through. Stray fields can emerge. The bus node preferably ( SL1 . SL2 . SL3 ) a magnetic shield for the measuring system ( HL ) for this flux density ( B ) on. According to the invention, it is now preferably that the address assignment by the bus node controller (BS) depending on the detected value of the magnetic flux density ( B ) is carried out by the measuring system ( HL ) for the magnetic flux density ( B ) is recorded. The main advantage over the prior art is that no internal bus shunt resistor ( R2 ) and also no external bus shunt resistor ( R _s ) are needed more or that they have a very low value of less than 1 Ω, for example less than 0.5 Ω or better less than 0.2Ω or even better less than 0.1 Ω. As a result, the total bus resistance is considerably reduced and the electromagnetic robustness against Irradiation is significantly improved.

The measuring system ( HL ) for the magnetic flux density ( B ) as a GMR measuring device with a GMR measuring resistor ( HP ) or as a GMR-AMR measuring device with an AMR measuring resistor, since this can be carried out particularly well with an integrated circuit using CMOS technology. Of course, microsystems are also conceivable that use other principles (eg Hall).

For the generation of the magnetic flux ( B ), which in the measuring system ( HL ) is to be coupled in, a flat coil is preferably used as the magnetic field-generating sub-device ( L ) used, which is preferably immediately above the GMR measuring resistor ( HP ) or above the AMR resistance ( HP ) is arranged. This minimizes the stray fields that are not used.

In order to solve the problem of backward compatibility, it makes sense if the bus node ( SL1 . SL2 . SL3 ) also via a conventional device for assigning a bus address using a bus shunt resistor ( R2 . R _s ) has. The bus node ( SL1 . SL2 . SL3 ) via a first connection and via a second connection and via a third connection. The bus node ( SL1 . SL2 . SL3 ) then preferably has a first measuring device (HL) for measuring a first measured value of the bus current ( i1 . i2 . i3 ), which has an internal resistance less than 400mOhm. This is preferably the partial device (L) generating the magnetic field in combination with the measuring system ( HL ) for the partial device (L) generating the magnetic field as a function of the bus current ( i1 . i2 . i3 ) generated magnetic flux density (B). Furthermore, the bus node ( SL1 . SL2 . SI3 ) via a second measuring device for measuring a second measured value of the bus current ( i1 . i2 . i3 ), which has an internal resistance greater than 400mOhm or is designed to be used together with other components, in particular a bus shunt resistor ( R2 . R _S ) as a further component to have an internal resistance of more than 400mOhm. This is preferably a device part, as is known from the named prior art. The bus node ( SL1 . SI2 . SI3 ) is preferably designed to address these two values of the bus current in an addressing phase of the bus system ( i1 . i2 . i3 ) capture. The bus node controller (BS) of the bus node ( SL1 . SL2 . SL3 ) compares the amount of the recorded first measured value with a first threshold value and compares the amount of the recorded second measured value with a second threshold value. This bus node controller ( BS ) causes the bus node ( SL1 . SL2 . SI3 ) in the addressing phase of the bus system only to adopt or generate a bus address if the magnitude of the first measured value is below the first threshold and if the magnitude of the second measured value is also below the second threshold, neither the magnetic field-controlled measuring system ( HL ) the measuring system based on the bus shunt resistance ( R2 . R _s ) determine a sufficiently large bus stream.

The inventive idea of using such a microsystem bus current measurement for auto addressing can also be understood in such a way that an addressing bus node as a bus node ( SL1 . SL2 . SL3 ) for a serial data bus system as a single-wire data bus system with a bus master connected to a bus line (bus) ( ECU ) and with several bus nodes connected consecutively to the bus line (bus) ( SL1 . SL2 . SL3 ), some of which are addressing bus nodes ( SL1 . SL2 . SL3 ) and other than standard bus nodes ( CS1 . CS2 ) can be implemented with an already defined address, whereby the addressing bus node ( SL1 . SL2 . SL3 ) is provided for the assignment of its address by the bus node. The addressing bus node according to the invention has a first current measuring means ( R2 ) based on the measurement of a voltage drop across a shunt resistor to acquire a first measured value and a second current measuring means ( HL ) based on the measurement of a magnetic flux density ( B ) to acquire a second measured value. Furthermore, the addressing bus node in question has an addressing current source for feeding an addressing current into the bus line (bus) and through this bus line (bus) to the bus master (ECU). In this configuration, the addressing current is fed in such a way that it is also detected by the first and / or second current measuring means of the bus node. In contrast, it is conceivable to choose the configuration in such a way that the addressing current which is only fed in by the bus node is only detected by the bus node preceding in the direction of the bus master (ECU). In this case, the control described immediately no longer works and the design of the bus node must be selected so that it switches off its addressing current when the bus current stops Threshold value exceeded. The bus node typically has a quiescent current source for feeding a quiescent current into the bus line and through it to the bus master (ECU), the quiescent current source being able to be identical to the addressing current source. In the case of a regulated addressing current, the bus node normally comprises a control unit for increasing the addressing current supplied by the addressing current source, which takes place with a variable rate of increase, if necessary, until a predeterminable maximum current is exceeded by the first measured value and / or the second measured value and for - with a possibly also variable reduction rate, in particular down to zero - reduction in the addressing current supplied by the addressing current source when the maximum measured value is exceeded once by the first measured value and / or the second measured value. The regulation of the bus current leaving the bus node in the direction of the bus master (ECU) ( i1 . i2 . i3 ) takes place in such a way that the maximum of the first or second measured value is decisive. So the magnetic field controlled measuring system (HL) measures a bus current ( i1 . i2 . i3 ), this controls the regulation of the addressing current in the case of a regulated addressing current. Does the voltage-controlled, bus shunt-based measuring system measure a bus current ( i1 . i2 . i3 ) and the other not, this controls the regulation of the addressing current in the case of a regulated addressing current. For example, an internal bus shunt ( R2 ) are short-circuited by a wire bridge and the control takes place automatically via the GMR or AMR measuring device ( HL ).

In the case of an unregulated addressing bus current that does not flow through the measuring means of the bus node of the associated addressing current source, a method for assigning addresses in a serial data bus system described below results. As before, the data bus system has a bus line (bus), a bus master (ECU) and bus node ( SL1 . SL2 . SL3 ) on. On the one hand the bus master (ECU) is connected to the bus line (bus) and on the other hand the bus nodes ( SL1 . SL2 . SL3 ) successively connected to the bus line (bus) or better described: inserted. At least some of the bus nodes feed a current flowing to the bus master (ECU) into the bus line (bus). One of the bus nodes is the first bus node connected to the bus master (ECU). The other bus nodes are connected to the bus line upstream of the first bus node. One of the bus nodes is the most distant last bus node connected to the bus line from the bus master (ECU). The other bus nodes are connected to the bus line between this bus node and the bus master (ECU) downstream of this last bus node. At least two of the bus nodes are addressing bus nodes ( SL1 . SL2 . SL3 , SLx), to which an address is assigned by the bus master (ECU) in an addressing phase. Other bus nodes can be standard bus nodes ( CS1 . CS2 ) with an address specified before the addressing phase is carried out. In the method, the bus nodes feed a quiescent current into the bus line or potentially a quiescent current into the bus line or - alternatively - some of the standard bus nodes ( CS1 . CS2 ) and / or some of the addressing bus nodes ( SL1 . SL2 . SL3 , SLx) feed a quiescent current into the bus line and others of the standard bus nodes ( CS1 . CS2 ) and / or the addressing bus node ( SL1 . SL2 , 30 SL3 , SLx) do not feed any quiescent current into the bus line. Any addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 , SLx) typically feeds an addressing stream into the bus line (bus) at the beginning of an address assignment phase. Any addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ) now detects using a first current measuring device ( R2 ), e.g. using the bus shunt method, the bus current flowing through it as the sum of the quiescent currents of all upstream bus nodes and its own addressing current and the addressing currents of all upstream, not yet addressed addressing bus nodes ( SL1 . SL2 . SL3 . SLx ) as the first measured value and / or with the aid of a second current measuring device ( HL ), e.g. a flat coil and a GMR sensor system or AMR sensor system, the bus current flowing through it as the sum of the quiescent currents of all upstream bus nodes and its own addressing current and the addressing currents of all upstream, not yet addressed addressing bus nodes ( SL1 . SL2 . SL3 . SLx ) as the second measured value.

A maximum permissible maximum addressing current is determined during the addressing phase, which together with the sum of all fed-in quiescent currents results in a maximum permissible maximum bus current, which is smaller than the bus current flowing into the bus master (ECU), at which in the bus master (ECU ) an error is detected. In the addressing phase, several addressing cycles, each lasting for a predefinable period of time, are identified to identify an addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ), whereby an addressing bus node (identified in an addressing cycle SL1 . SL2 . SL3 . SLx ) no longer participates in the subsequent addressing process, for example by acting like a standard bus node ( CS1 . CS2 ) behaves.

At the beginning of each addressing cycle, each addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ) an addressing stream into the Bus line (bus) on. In the addressing phase of each addressing cycle, each addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ) the bus current flowing through it as the first measured value using the first current measuring means and the second measured value using the second current measuring means. In this addressing phase of each addressing cycle, each addressing bus node that has not yet been addressed compares ( SL1 . SL2 . SL3 . SLx ) compares the first measured value with the maximum bus current and the second measured value with the maximum bus current. If the maximum bus current is exceeded by the first measured value or the second measured value, the relevant addressing bus node ( SL1 . SL2 . SL3 . SLx ) its addressing current fed into the bus line at a rate of reduction. Alternatively, each address bus node that has not yet been addressed ( SL1 . SL2 . SL3 , SLx) its addressing current fed into the bus line and compares this with the maximum addressing current. If the maximum addressing current is exceeded, it then reduces its addressing current fed into the bus line at a rate of reduction. At the end of the addressing cycle, a single addressing bus node that has not yet been addressed typically remains ( SL1 . SL2 . SL3 . SLx ), the maximum Addressing current feeds into the bus line and is thus identified. This identified addressing bus node ( SL1 . SL2 . SL3 . SLx ) an address is then assigned.

Instead of the method described above with an addressing current regulated to a maximum value, the idea according to the invention can also be used in other auto addressing systems: For this case, a method for assigning addresses in a serial data bus system is proposed. The proposed data bus system includes a bus line, a bus master and bus node. On the one hand the bus master is connected to the bus line and on the other hand the bus nodes are connected to the bus line in succession. At least some of the bus nodes each feed a current flowing to the bus master into the bus line. One of the bus nodes is the first bus node connected to the bus line closest to the bus master (ECU) and the other bus nodes are connected to the bus line upstream of the first bus node. One of the bus nodes is the most distant last bus node connected to the bus line from the bus master (ECU) and the other bus nodes are connected to the bus line downstream of this last bus node between this bus node and the bus master (ECU). At least two of the bus nodes are addressing bus nodes ( SL1 . SL2 . SL3 , SLx), to which an address is assigned by the bus master (ECU) in an addressing phase. Other bus nodes can be standard bus nodes ( CS1 . CS2 ) with an address specified before the addressing phase is carried out. In the method, the bus nodes feed a quiescent current into the bus line or potentially a quiescent current into the bus line or - alternatively - some of the standard bus nodes ( CS1 . CS2 ) and / or some of the addressing bus nodes ( SL1 . SL2 . SL3 , SLx) feed a quiescent current into the bus line and others of the standard bus nodes ( CS1 . CS2 ) and / or the addressing bus node ( SL1 . SL2 . 30 SL3 . SLx ) do not feed any quiescent current into the bus line. Any addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ) feeds an addressing current into the bus line. Any addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ) recorded using a current measuring device ( HL ) the bus stream flowing through it as the sum of the quiescent currents of all upstream bus nodes and its own addressing stream and the addressing streams of all upstream, not yet addressed addressing bus nodes ( SL1 . SL2 . SL3 . SLx ) as a measured value. A maximum permissible maximum addressing current is determined during the addressing phase, which together with the sum of all fed-in quiescent currents results in a maximum permissible maximum bus current, which is smaller than the bus current flowing into the bus master (ECU) at which the bus master (ECU) an error case is recognized. In the addressing phase, several addressing cycles, each lasting for a predefinable period of time, are identified to identify an addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ), whereby an addressing bus node (identified in an addressing cycle SL1 . SL2 . SL3 . SLx ) to the 15 the subsequent addressing process no longer takes part, for example, as a standard bus node ( CS1 . CS2 ) behaves. Each addressing bus node that has not yet been addressed feeds per addressing cycle and at the beginning of an addressing cycle ( SL1 . SL2 . SL3 . SLx ) an addressing current that increases with a rate of increase into the bus line. During the addressing phase, each addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 , SLx) the bus current flowing through it as a measured value and compares this measured value with the maximum bus current. If the measured value exceeds the maximum bus current, the addressing bus node reduces its addressing current fed into the bus line at a rate of reduction. Alternatively, each address bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ) its addressing current fed into the bus line and compares this measured value of the addressing current with the maximum addressing current. If the maximum addressing current is exceeded, the addressing bus node in question reduces its addressing current fed into the bus line at a rate of reduction. At the end of the addressing cycle, there remains a single addressing bus node that has not yet been addressed ( SL1 . SL2 . SL3 . SLx ), which feeds the maximum addressing current into the bus line and is thus identified. This identified addressing bus node ( SL1 . SL2 . SL3 . SLx ) an address is then finally assigned. The method is characterized in that at least one addressing bus node (not yet addressed) ( SL1 . SL2 . SL3 . SLx ) a magnetic flux (B) as a function of the bus current flowing through it as the sum of the quiescent currents of all upstream bus nodes and its own addressing current and the addressing currents of all upstream, yet unaddressed addressing bus nodes ( SL1 . SL2 . SL3 , SLx) and this magnetic flux ( B ) with the help of a flow measuring device ( HL ) recorded and used as a measured value for the bus current flowing through it.

Another application of the idea according to the invention relates to a further method for addressing the subscribers of a bus system. The bus system includes, among other things, a control unit, a bus originating from the control unit and several addressable participants that are connected to the bus. In the method, each unaddressed subscriber feeds an identification stream into the bus for identification. All identification currents flow through the bus towards the control unit. Each participant that has not yet been addressed detects the current flowing through the bus. Only the participant who has not yet been addressed and who does not detect any current or only a current which is less than a predeterminable first threshold value is identified as an as yet unaddressed participant. An address is assigned to the subscriber identified in this way for addressing. The above-mentioned steps are carried out without the last addressed subscriber in each case until all the subscribers not yet addressed are addressed. According to the invention, the method is then characterized in that the current flowing through the bus flows through at least one first measuring device of at least one unaddressed subscriber or flows through a second measuring device of the unaddressed subscriber or flows through the first and second measuring device of the unaddressed subscriber and that the latter at least one not yet addressed subscriber detects the current flowing through the first measuring device as the first measured value and that this at least one not yet addressed subscriber detects the current flowing through the second measuring device as the second measured value. This at least one as yet unaddressed subscriber is then identified as the as yet unaddressed subscriber who does not detect any current or only a current which is less than a predefinable first threshold value, and thus identified as an as yet unaddressed subscriber if his first measured value is less than the first threshold value and if at the same time its second measured value is smaller than the first threshold value.

The first measuring device preferably has an internal resistance greater than 200mOhm and the second measuring device has an internal resistance less than 200mOhm.

Another method variant results as a further method for addressing the participants in a bus system. Here too, the bus system comprises a control unit, a bus originating from the control unit and a plurality of addressable subscribers which are connected to the bus. As before, each unaddressed subscriber feeds an identification stream into the bus in this further method for identification. All identification currents flow through the bus towards the control unit. Each participant that has not yet been addressed detects the current flowing through the bus. Only the participant who has not yet been addressed and who does not detect any current or only a current which is less than a predeterminable first threshold value is identified as an as yet unaddressed participant. The subscriber identified in this way is then assigned an address again for the purpose of addressing, the aforementioned steps being carried out without the subscriber last addressed in each case until all the subscribers which have not yet been addressed are addressed. The proposed method is then characterized in that the current flowing through the bus causes a magnetic flux (B) in the area of at least one not yet addressed subscriber and that this at least one, as yet unaddressed subscriber, this magnetic flux as the first measured value as a measured value for the bus flowing current detected. This at least one, as yet unaddressed subscriber is then identified as the as yet unaddressed subscriber who does not detect any current or only a current which is less than a predeterminable first threshold value and is identified as an as yet unaddressed subscriber when this measured value is less than the first threshold.

In summary, it is a bus node for a bus system with a bus master, which is suitable for performing an auto-addressing procedure for assigning bus addresses using an addressing stream as a component of a bus stream in the direction of the bus master in an addressing phase. The bus node is characterized in that the bus node has a first means for generating a magnetic field with a flux density as a function of the bus current in the area of the bus node, and in that the bus node has second means for determining a measurement value as a function of the magnetic flux density in this area of the Bus node and that the bus addresses are assigned depending on the flux density in this area of the bus node.

According to the invention, a bus node ( BK ) for a single-wire data bus (bus) with the ability to participate in an auto-addressing method, which, in contrast to the prior art, can have a lower or no bus shunt resistance. In the prior art, the bus shunt resistance cannot fall below a value of approx. 500mΩ without there being negative voltage values in the event of a ground offset along the bus system between the ground connection of the bus master and the ground connection of the respective bus node comes below the ground potential of the bus node in question at the connections of this respective bus shunt resistor. This limitation is exceeded by the proposed procedure. Bus chains with more than approx. 15 Bus participants can access this addressing procedure. The bus node ( BK ) is therefore intended to be inserted into the single-wire data bus (bus). It includes a bus node controller ( BS ), a coupling device with an internal resistance less than 0.5 Ω, here in particular a magnetic field-generating sub-device ( L ) in combination with a measuring system ( HL ) to detect the magnetic flux density (B) that this sub-device ( L ) generated. The coupling device ( L . HL ) is preferably provided by a bus stream ( I _BUS ) of the single-wire data bus (bus) at least temporarily in the addressing phase towards a bus master ( BM ) to be flowed through. The coupling device ( L . HL ) generated in the event of such a flow through the bus current ( I _BUS ) a measured value or a measured value signal from which the bus current ( I _BUS ) depends. The address assignment by the bus node controller ( BS ) then takes place depending on this measured value, which is determined by the measuring system ( HL ) is recorded.

Instead of the magnetic coupling, other possibilities are also conceivable for the coupling element ( D1 . R2 ) to realize. These options can also be used in combination (see e.g. 4 ). The invention then again relates to a bus node ( BK ) for a single-wire data bus (bus) with the ability to participate in an auto-addressing procedure. The bus node ( BK ) is supplied with electrical energy by a positive supply voltage line and a negative supply voltage line. The bus node ( BK ) is now again intended to be inserted into the single-wire data bus. It again includes a bus node controller ( BS ) and a coupling device ( D1 . R2 ) with an internal resistance less than 0.5 Ω and / or less than 0.3 Ω and / or less than 0.2 Ω and / or less than 0.1 Ω and / or less than 0.05 Ω. However, the coupling device ( D1 . R2 ) via a bus shunt resistor ( R2 ) with a first connection and a second connection, which is intended to be connected by the bus current ( I _BUS ) of the single-wire data bus (bus) at least temporarily in the addressing phase towards a bus master ( BM ) to be flowed through. The magnetic field generating device ( L ) and the measuring device ( HL ) are therefore not absolutely necessary. The coupling device ( R2 . D1 ) is again provided by a bus stream ( I _BUS ) of the single-wire data bus (bus) to be flowed through at least temporarily in the addressing phase in the direction of a bus master (BM). The coupling device ( R2 . D1 ) generated in the event of such a flow through the bus current ( I _BUS ) a measured value of the bus current ( I _BUS ) from which the bus stream ( I _BUS ) depends. In the specific case, a differential amplifier ( D1 ) of the bus node (BK), the part of this coupling device ( R2 . D1 ), with its negative input to the first connection of the bus shunt resistor ( R2 ) connected and with its positive input to the second connection of the bus shunt resistor ( R2 ) connected. The voltage or current signal at the output of the differential amplifier ( D1 ) is preferred as the measured value signal of the measured value of the coupling device ( D1 . R2 ) used. The differential amplifier ( D1 ) is preferably designed to measure this differential voltage at the connections of the bus shunt resistor ( R2 ) even if the most negative potential of the first connection of the bus shunt resistor ( R2 ) and / or the second connection of the bus shunt resistor ( R2 ) is more than 0.5V and / or 1.0V and / or 1.5V and / or 2.0V and / or 2.5V below the potential of the negative supply voltage line (ground) of the bus node (BK). The output signal of the differential amplifier ( D1 ) can be used as the measured value of the coupling device ( R2 . D1 ) for the bus stream ( I _BUS ) be used. The address is again assigned by the bus node controller (BS) depending on this measured value of the bus current ( I _BUS ) by the coupling device ( R2 . D1 ) is recorded. In this case, the address is preferably assigned as a function of the output signal of the operational amplifier ( D1 ). To ensure that the differential amplifier ( D1 ) also works with an unfavorable mass offset, it is proposed that at least the differential amplifier ( D1 ), but preferably the rest of the circuit with monolithic integration in SOI technology is isolated from the semiconductor substrate. This enables the differential amplifier to be offset ( D1 ) to potentials below the substrate potential. In this case, the energy supply to the differential amplifier ( D1 ) by a charge pump (charge pump), which the differential amplifier ( D1 ) with a negative operating voltage potential lower or the same depth as the lowest potential to be measured. The differential amplifier ( D1 ) can also on one separate dice or in a separate component separate from the rest of the bus node circuit.

Different implementations for the coupling device ( L . HL . D1 . R2 ) possible. A bus node ( BK ), such as in 4 and 5 shown, also several different types of coupling devices ( L . HL . R2 . D1 ) include.

Advantage of the invention

The main advantage of the invention is that the bus resistance drops and therefore no longer differs from the bus resistors without bus shunt resistors. As a result, the robustness against electromagnetic radiation is massively reduced. It is also essential that the proposed bus nodes can still be used in mixed installation with bus nodes in which the auto-addressing takes place by means of a bus shunt resistor. The advantages are not limited to this.

glossary

AMR AMR is the abbreviation for the anisotropic magnetoresistive effect, or AMR effect for short. With AMR resistors, the resistance depends on the magnetic flux density that penetrates the AMR resistor. The AMR effect is based on anisotropic (depending on the spatial direction) scatter in ferromagnetic metals. This means that it occurs in materials that have their own magnetization. In this disclosure, AMR resistors generally stand for resistors that change their electrical resistance depending on the magnetic flux density and / or the electrical field strength.

GMR The GMR effect (giant magnetoresistance) or giant magnetoresistance is based on a magnetoresistive effect and is observed in structures that consist of alternating magnetic and non-magnetic thin layers with a thickness of a few nanometers. The effect causes the electrical resistance of the structure to depend on the mutual orientation of the magnetization of the magnetic layers, namely that it is significantly higher when magnetized in opposite directions than when magnetized in the same direction. GMR resistors are the corresponding components. In this disclosure, GMR resistors generally stand for resistors that change their electrical resistance depending on the magnetic flux density and / or the electrical field strength.

LIST OF REFERENCE NUMBERS

B

magnetic flux density which is generated by the magnetic field generating sub-device (L) when flowing through with electric current;

BK

bus node

BS

Busknotensteuerung;

bus

Bus line, also known as a single-wire data bus;

ECU

Bus master;

HL

Measuring system (HL) for detecting the magnetic flux density (B) generated by the coil (L). Such a measuring device (HL) for this flux density (B) is particularly preferred a GMR measuring device with a GMR resistor (HP) or an AMR measuring device with an AMR resistor (HP). In connection with this disclosure, this measuring system is also referred to as a second current measuring means;

HP

GMR measuring device with a GMR resistor (HP) or AMR measuring device with an AMR resistor (HP);

i1

Bus current at the output of the first bus node ( SL1 );

i2

Bus current at the output of the second bus node ( SL2 );

i3

Bus current at the output of the third bus node ( SL3 );

L

magnetic field generating device (L). The magnetic field generating device (L) is, as a rule or preferably, a flat coil;

R2

internal bus shunt resistor;

R2 '

additional external bus shunt resistor;

R _S

external bus shunt resistor:

SL1

first bus node;

SL2

second bus node;

SL3

third bus node;

SLx

x-th bus node;

List of cited documents / registrations

• DE 10 147 512 B4 .
• DE 10 2010 026 431 B1 .
• DE 10 2017 012 179.6 .
• DE 10 2017 122 364.9 .
• DE 10 2017 122 365.7 .
• DE 10 2017 128 489.3 .
• DE 10 2017 128 923.2 .
• DE 10 2018 104 488.7 .
• DE 10 2018 104 489.5 .
• EP 1364 288 B1 .
• EP 1490 772 B1 .
• EP 1603 282 B1 .
• US 9 331 866 B2 ,

QUOTES INCLUDE IN THE DESCRIPTION

This list of documents listed by the applicant has been generated automatically and is only included for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• DE 102010026431 B1 [0002, 0036]
• DE 10147512 B4 [0002, 0007, 0036]
• EP 1490772 B1 [0002, 0007, 0017, 0036]
• US 9331866 B2 [0002, 0007, 0036]
• DE 102017122365 [0015, 0017, 0036]
• DE 102010026431 B4 [0017]
• EP 1603282 B1 [0017, 0036]
• EP 1364288 B1 [0017, 0036]
• DE 102017122364 [0017, 0036]
• DE 102017012179 [0017, 0036]
• DE 102017128489 [0017, 0036]
• DE 102017128923 [0017, 0036]
• DE 102018104488 [0017, 0036]
• DE 102018104489 [0017, 0036]

Claims (16)

Bus node (BK) for a single-wire data bus (bus) with the ability to participate in an auto-addressing process, - the bus node (BK) being intended to be inserted into the single-wire data bus (bus), - with a bus node controller (BS) and - with a magnetic field generating device (L) and - with a measuring system (HL) for detecting a magnetic flux density (B) and - wherein the magnetic field generating device (L) is provided, by a bus current (I _BUS ) of the single-wire data bus (bus) at least temporarily during the addressing phase in the direction of a bus master (BM) and - the partial field device (L) which generates the magnetic field generates such a magnetic flux (B) in the event of such a flow through the bus current (I _BUS ) which at least partially the measuring system ( HL) flows through - and the address assignment by the bus node controller (BS) is dependent on the value of the magnetic flux density (B), the dur ch the measuring system (HL) is recorded. Bus node after Claim 1 - The measuring system is an AMR measuring device with an AMR resistor (HP) or a GMR measuring device is a GMR resistor (HP) and - wherein the magnetic field generating device (L) is a flat coil and - wherein the flat coil is above the AMR Measuring device or GMR measuring device is arranged. Bus node (BK) for a single-wire data bus (bus) with the ability to participate in an auto-addressing process, - the bus node having a first connection and a second connection and a third connection, and - the bus node having a first measuring device for measuring a first measured value of the bus current, which has an internal resistance less than 400mOhm, and - wherein the bus node has a second measuring device for measuring a second measured value of the bus current, which has an internal resistance greater than 400mOhm or is designed to be used together with other components in the application , in particular a bus shunt resistor (R _S ) as a further component, having an internal resistance of more than 400mOhm, and - the bus node being designed to detect these two values of the bus current in an addressing phase of the bus system, and - whereby one Bus node control (BS) of the bus node Compares the amount of the recorded first measured value with a first threshold value and - wherein the bus node controller of the bus node compares the amount of the recorded second measured value with a second threshold value and - the bus node only takes over or generates a bus address in the addressing phase of the bus system if the amount of the first measured value is below the first threshold value and if at the same time the magnitude of the second measured value is below the second threshold value. Addressing bus node for a serial data bus system with a bus master (ECU) connected to a bus line and with several bus nodes connected in succession to the bus line, some of which are addressing bus nodes and others as standard bus nodes (CS1, CS2) with an already defined address can be, wherein the addressing bus node is provided for assigning its address by the bus node and has A first current measuring means (R2) based on the measurement of a voltage drop across a shunt resistor for acquiring a first measured value, A second current measuring means (HL) based on the measurement of a magnetic flux density for recording a second measured value, An addressing current source for feeding an addressing current into the bus line and through it to the bus master (ECU), specifically when detected by the first and / or second current measuring means and A quiescent current source for feeding a quiescent current into the bus line and through this to the bus master (ECU), the quiescent current source being identical to the addressing current source, and A control unit for increasing the addressing current supplied by the addressing current source with a possibly increasing rate of rise until a predetermined maximum current can possibly be exceeded by the first measured value and / or the second measured value and for a possibly decreasing rate of reduction, in particular up to zero reduction in the addressing current supplied by the addressing current source when the maximum measured value is exceeded once by the first measured value and / or the second measured value. Method for assigning addresses in a serial data bus system, which - has a bus line, a bus master and bus node, - on the one hand the bus master is connected to the bus line and on the other hand the bus nodes are connected successively to the bus line, at least some of the bus nodes feed a current flowing to the bus master into the bus line and - one of the bus nodes is the first bus node connected to the bus master (ECU) and the other bus nodes are connected to the bus line upstream of the first bus node and - one of the bus nodes furthest away from the bus master (ECU) is the last bus node connected to the bus line and the other bus nodes downstream of this last bus node are connected to the bus line between this bus node and the bus master (ECU) and - At least two of the bus nodes are addressing bus nodes (SL1, SL2, SL3, SLx), each of which is assigned an address by the bus master (ECU) in an addressing phase, and further bus nodes are standard bus nodes (CS1, CS2), each of which is already implemented the addressing phase can be a fixed address, with the method - the bus nodes feed a quiescent current into the bus line or potentially feed a quiescent current into the bus line or - alternatively - some of the standard bus nodes (CS1, CS2) and / or some of the addressing bus nodes (SL1, SL2, SL3, SLx) feed a quiescent current into the bus line and others of the standard bus nodes (CS1, CS2) and / or the addressing bus nodes (SL1, SL2, 30 SL3, SLx) do not feed quiescent current into the bus line, - each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed feeds an addressing stream into the bus line, - each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed • using a first S drum measuring means (R2) detects the bus current flowing through it as the sum of the quiescent currents of all upstream bus nodes and its own addressing current and the addressing currents of all upstream, yet unaddressed addressing bus nodes (SL1, SL2, SL3, SLx) and / or • with the help of a second current measuring means (HL), the bus current flowing through it is detected as the second measured value as the sum of the quiescent currents of all bus nodes arranged upstream and its own addressing current and the addressing currents of all addressing bus nodes (SL1, SL2, SL3, SLx) arranged upstream and not yet addressed , - A maximum permissible maximum addressing current is determined during the addressing phase, which together with the sum - results in a maximum permissible maximum bus current from all fed-in quiescent currents, which is smaller than the bus current flowing into the bus master (ECU), at which in the bus aster (ECU) an error case is detected, - in the addressing phase several addressing cycles each lasting for a predefinable period of time are carried out for the identification of one addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed, with an addressing identified in an addressing cycle -Bus node (SL1, SL2, SL3, SLx) no longer participates in the subsequent addressing process, for example, it behaves like a standard bus node (CS1, CS2), - per addressing cycle • At the beginning, each addressing bus node that has not yet been addressed ( SL1, SL2, SL3, SLx) feeds an addressing current into the bus line that increases with an increase rate, • during the addressing phase, each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed measures the bus current flowing through it as the first and second measured value , as well as comparing the first measured value with the maximum bus current and comparing the second measured value with the maximum bus current and when exceeded s of the maximum bus current is reduced by the first measured value or the second measured value its addressing current fed into the bus line with a reduction rate or each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed measures its addressing current fed into the bus line and measures it with the Compares the maximum addressing current and, when the maximum addressing current is exceeded, reduces its addressing current fed into the bus line at a rate of reduction, and • at the end of the addressing cycle, a single addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed and remains the maximum Feeds the addressing current into the bus line and is thus identified, and an address is assigned to this identified addressing bus node (SL1, SL2, SL3, SLx). Method for assigning addresses in a serial data bus system, the has a bus line, a bus master and bus node, on the one hand the bus master is connected to the bus line and on the other hand the bus nodes are connected successively to the bus line, - At least some of the bus nodes feed a current flowing to the bus master into the bus line and one of the bus nodes which is the first bus node connected to the bus master (ECU) and the other bus nodes are connected to the bus line upstream of the first bus node and one of the bus nodes furthest from the bus master (ECU) is the last bus node connected to the bus line and the other bus nodes downstream of this last bus node are connected to the bus line between this bus node and the bus master (ECU) and - At least two of the bus nodes are addressing bus nodes (SL1, SL2, SL3, SLx), each of which is assigned an address by the bus master (ECU) in an addressing phase, and further bus nodes are standard bus nodes (CS1, CS2), each with an address before Implementation of the addressing phase can be a fixed address, with the method - the bus nodes feed a quiescent current into the bus line or potentially feed a quiescent current into the bus line or - alternatively - some of the standard bus nodes (CS1, CS2) and / or some of the addressing bus nodes (SL1, SL2, SL3, SLx) a quiescent current feed into the bus line and others of the standard bus nodes (CS1, CS2) and / or the addressing bus nodes (SL1, SL2, 30 SL3, SLx) do not feed any quiescent current into the bus line, each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed feeds an addressing stream into the bus line, - any addressing bus node that has not yet been addressed (SL1, SL2, SL3, SLx) With the aid of a current measuring means (HL) the bus current flowing through it as the sum of the quiescent currents of all upstream bus nodes and its own addressing current and the addressing currents of all upstream, not yet addressed addressing bus nodes (SL1, SL2, SL3, SLx) as a measured value, - A maximum permissible maximum addressing current is determined during the addressing phase, which together with the sum - from all the fed-in quiescent currents results in a maximum permissible maximum bus current, which is smaller than the bus current flowing into the bus master (ECU), in which an error is detected in the bus master (ECU), - In the addressing phase, several addressing cycles each lasting for a predeterminable period of time are carried out in order to identify one addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed, an addressing bus node (SL1, SL2, SL3, identified in an addressing cycle) being carried out. SLx) no longer participates in the subsequent 15 addressing process, for example by behaves like a standard bus node (CS1, CS2), - - per addressing cycle At the beginning, each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed feeds an addressing current into the bus line that increases with an increase rate, • During the addressing phase, each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed measures the bus current flowing through it as a measured value, and compares the measured value with the maximum bus current and, if the maximum bus current is exceeded by the measured value, into the Addressing current fed into the bus line is reduced at a rate of reduction or each addressing bus node (SL1, SL2, SL3, SLx) that has not yet been addressed measures its addressing current fed into the bus line and compares it with the maximum addressing current and, if the maximum addressing current is exceeded, its fed into the bus line Addressing current decreased at a decrease rate, and • At the end of the addressing cycle, a single addressing bus node (SL1, SL2, SL3, SLx) not yet addressed remains, which feeds the maximum addressing current into the bus line and is thus identified, and - - This identified addressing bus node (SL1, SL2, SL3, SLx) is assigned an address, characterized in that - that at least one not yet addressed addressing bus node (SL1, SL2, SL3, SLx) • generates a magnetic flux (B) as a function of the bus current flowing through it as the sum of the quiescent currents of all upstream bus nodes and its own addressing current and the addressing currents of all upstream, yet unaddressed addressing bus nodes (SL1, SL2, SL3, SLx) • This magnetic flux (B) is recorded using a flux measuring device (HL) as a measured value for the bus current flowing through it. Method for addressing the subscribers of a bus system - with a control unit, - a bus originating from the control unit and - with several addressable subscribers, • which are connected to the bus, - in the method, each unaddressed subscriber for identification uses an identification stream in the Bus feeds in, - with all identification currents flowing through the bus in the direction of the control unit, - each participant not yet addressed detects the current flowing through the bus, and - only the participant who has not yet been addressed, • who does not detect any current or only one current, which is smaller than a predeterminable first threshold value, • is identified as a not yet addressed subscriber, and - whereby the subscriber identified in this way is assigned an address for addressing purposes and - the aforementioned steps are carried out without the last addressed subscriber until all Liche not yet addressed addresses are characterized in that the current flowing through the bus flows through at least one first measuring device of at least one not yet addressed address or flows through a second measuring device of the not yet addressed address or flows through the first and second measuring device of the not yet addressed address and - that this at least one not yet addressed subscriber detects the current flowing through the first measuring device as the first measured value and - that this at least one not yet addressed subscriber detects the current flowing through the second measuring device as the second measured value and - whereby this at least one, still unaddressed subscriber as the as yet unaddressed subscriber who does not detect any current or only a current which is less than a predeterminable first threshold value and is identified as an as yet unaddressed subscriber, • if his first measured value is less than the first threshold value and • if its second measured value is less than the first threshold. Method according to the preceding claim, characterized in that - the first measuring device has an internal resistance greater than 200mOhm Method according to the two preceding claims, characterized in that the second measuring device has an internal resistance less than 200mOhm Method for addressing the subscribers of a bus system - with a control unit, - a bus originating from the control unit and - with several addressable subscribers, • which are connected to the bus, - in the method, each unaddressed subscriber for identification uses an identification stream in the Bus feeds in, - with all identification currents flowing through the bus in the direction of the control unit, - each participant not yet addressed detects the current flowing through the bus, and - only the participant who has not yet been addressed, • who does not detect any current or only one current, which is smaller than a predeterminable first threshold value, • is identified as a not yet addressed subscriber, and - whereby the subscriber identified in this way is assigned an address for addressing purposes and - the aforementioned steps are carried out without the last addressed subscriber until all Unaddressed participants are characterized in that - the current flowing through the bus causes a magnetic flux (B) in the area of at least one unaddressed participant - that this at least one unaddressed participant uses this magnetic flux as the first measured value as a measured value for the current flowing through the bus is detected and - wherein this identifies at least one, as yet unaddressed, participant as the as yet unaddressed participant who does not detect any current or only a current that is smaller than a predeterminable first threshold value and as an as yet unaddressed participant if • this measured value is less than the first threshold value. Bus node for a bus system with a bus master, which is suitable for performing an auto-addressing procedure for assigning bus addresses by means of an addressing stream as a current component of a bus stream in the direction of the bus master in an addressing phase, characterized in that - the bus node is connected via a first means for generating a magnetic field with a flux density as a function of the bus current in the area of the bus node and - that the bus node has second means for determining a measured value as a function of the magnetic flux density in this area of the bus node and - that the bus addresses are assigned as a function of the flux density occurs in this area of the bus node. Bus node (BK) for a single-wire data bus (bus) with the ability to participate in an auto-addressing process, - the bus node (BK) being intended to be inserted into the single-wire data bus (bus), - with a bus node controller (BS) and - with a coupling device with an internal resistance of less than 0.5 Ω and / or less than 0.3 Ω and / or less than 0.2 Ω and / or less than 0.1 Ω and / or less than 0.05 Ω, where the coupling device (L, HL, R2, D1) is intended to be flowed through at least temporarily in the addressing phase towards a bus master (BM) by a bus current (I _BUS ) of the single-wire data bus (bus), and - whereby the coupling device (L, HL, R2, D1) in the case of such a flow generated by the bus current (I _BUS) a measured value of the bus current (I _BUS) to that of which depends the bus current (I _BUS), and - wherein the address assignment by the Busknotensteuerung (BS) depending on this measured value of the bus current (I _BUS ), which is detected by the coupling device (L, HL, R2, D1). Bus node (BK) according to the preceding claim, - The coupling device (L, HL) comprises a magnetic field generating device (L) in combination with a measuring system (HL) for detecting the magnetic flux density (B) generated by this device (L). Bus node (BK) to Claim 12 , - the bus node (BK) being supplied with electrical energy by a positive supply voltage line and a negative supply voltage line, and - the coupling device comprising a bus shunt resistor (R2) with a first connection and a second connection, which is provided for this purpose, to be flowed through by the bus current (I _BUS ) of the single-wire data bus (bus) at least temporarily in the addressing phase in the direction of a bus master (BM) and - whereby a differential amplifier (D1) of the bus node (BK) with its negative input with the first Connection of the bus shunt resistor (R2) is connected and - whereby a differential amplifier (D1) of the bus node (BK) is connected with its positive input to the second connection of the bus shunt resistor (R2) and - whereby the differential amplifier is designed to detect this differential voltage when the most negative potential of the first connection of the bus shunt resistor (R2) or the second Ansc Connection of the bus shunt resistor (R2) more than 0.5V and / or 1.0V and / or 1.5V and / or 2.0V and / or 2.5V below the potential of the negative supply voltage line (ground) of the bus node (BK) lies. Bus node according to the preceding claim, characterized in that - the differential amplifier (D1) is isolated from the semiconductor substrate using SOI technology or as a separate component. Bus node according to one or more of the two preceding claims - That the differential amplifier (D1) is supplied with energy by a charge pump of the bus node (BK).

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