DE102019112036B4 - Scalable ESD protection structure with adjustable breakdown voltage - Google Patents

Abstract

ESD protection structure for protecting a first signal connection (A) and a second signal connection (B) with a first node (K) and with a first reference potential (GND) and with a first bipolar transistor (T1) and with a second bipolar transistor (T2) and with a third bipolar transistor (T3) and with a fourth bipolar transistor (T4), wherein the first bipolar transistor (T1) is a bipolar transistor of a transistor type and wherein the second bipolar transistor (T2) is a bipolar transistor of the same transistor type and wherein the third bipolar transistor (T3) is a bipolar transistor of the same transistor type is andwherein the fourth bipolar transistor (T4) is a bipolar transistor of the same transistor type andwherein the transistor type is a PNP bipolar transistor or an NPN bipolar transistor and wherein the collector of the first bipolar transistor (T1) is connected to the first signal terminal (A) andwherein the base of the first bipolar transistor (T1) is connected to the first node (K) and wherein the emitter of the first bipolar transistor (T1) is connected to the first node (K) and wherein the collector of the second bipolar transistor (T2) is connected to the reference potential (GND) and wherein the base of the second bipolar transistor (T2) is connected to the first node (K), and the emitter of the second bipolar transistor (T2) is connected to the first node (K), and the collector of the third bipolar transistor (T3) is connected to the first signal terminal (A ) is connected and wherein the base of the third bipolar transistor (T3) is connected to the first node (K) and wherein the emitter of the third bipolar transistor (T3) is connected to the second signal terminal (B) and wherein the collector of the fourth bipolar transistor (T4) is connected to the second signal terminal (B) is connected and wherein the base of the fourth bipolar transistor (T4) is connected to the first node (K) and wherein the emitter of the fourth bipolar transistor (T4) is connected to the first node (K).

Description

Generic term

The invention is directed to an ESD protection structure for protecting a first signal connection (A) and a second signal connection (B), to which both positive and negative voltages can be present. The ESD protective structure is therefore suitable for use in automotive buses.

General introduction

In automotive applications, every external connection of an integrated circuit must be protected against electrostatic discharge (ESD). Normally, the supply voltage of an integrated circuit, as well as the voltage range of the connections, is positive. Simple ESD protection could therefore be implemented using a PN diode leading to a negative reference potential. However, for automotive buses, e.g. CAN bus or LIN bus, it is necessary that negative voltages of up to approximately -35 V can also be applied to the external connection terminals. ESD protection structures are also known for this application, such as the “back-to-back” bipolar diode.

State of the art

Different implementations based on PNP or NPN bipolar transistors are known for ESD protection structures in BCD processes. PNP bipolar transistors with breakdown voltages that can be adjusted over distances are often used. The base is firmly connected to a positive connection terminal, as in 1 shown. Such structures can be purchased in commercially available circuits on the market. The 1 comes from a development by the applicant based on such a component. The use of such components below the substrate voltage, in the negative voltage range, is usually not intended.

In automotive buses, positive and negative terminal voltages are applied. A known solution for use below the substrate voltage is to connect the PNP transistors to the base in such a way that ESD protection for positive and negative terminal voltages is possible, as in 2 shown.

For differential or multiple input terminals, according to the applicant's findings, the in 2 ESD protection structures shown can be combined, as in 3 shown.

From the publication US 2012 / 0 205 714 A1 and in particular its 1 and 6 An ESD protection circuit is known which protects two signal connections to ground using bipolar transistors.

From the publication US 2014 / 0 339 601 A1 and in particular its 3 An ESD protection circuit is also known which protects two signal connections to ground using bipolar transistors.

From the publication US 2013 / 0 279 051 A1 and in particular its 2 and 3 and the associated description there is also known an ESD protection circuit made of npn bipolar transistors, which protects two IO pins against ground using a common dissipating npn stack.

From the publication US 2012 / 0 049 326 A1 and in particular its 1 and the associated description there is another ESD protection circuit known, which protects two pins against ground.

Here too, the use of such components below the substrate voltage, in the negative voltage range, is usually not intended.

Task

The proposal is based on the task of implementing an area-effective, adaptable and easy-to-connect ESD protection structure for two input terminals, in a working range below and above the substrate voltage (e.g. -35V to +45V), as required in automotive buses. The ESD protection structure should meet the requirements in BCD processes up to system level requirements.

This object is achieved by a device according to claim 1 and claim 2 and by a method according to claim 3 or claim 4.

Solution to the task

In an ESD protection structure for a first signal connection (A) and a second signal connection (B) of the type described above, the problem is solved according to the proposal in that the adjustable bipolar transistors used are of a transistor type in a common base well, a third well (D3), to get integrated. The transistor type can be a PNP bipolar transistor or an NPN bipolar transistor.

The invention is explained using the exemplary figures.

By connecting the first bipolar transistor (T1) connected to the first signal connection (A) and the fourth bipolar transistor (T4) connected to the second signal connection (B) together at a first node (K) with a second bipolar transistor (T2), in a Base well, the third well (D3), a third bipolar transistor (T3) is created between the first signal connection (A) and the second signal connection (B). The second bipolar transistor (T2) is connected to a third signal connection (C). A first reference potential (GND) is present at the third signal connection (C). The connection is in 4 shown. The cross section is in 5 shown. 6 shows the same cross section as 5 . Additionally is in 6 the location of a first area (G1) and the location of a second area (G2) and the location of a third area (G3) and the location of a fourth area (G4) and the location of a fifth area (G5) and the location of a sixth area (G6) shown.

A highly doped, buried first buried layer (BL) is incorporated into a first substrate (SUB). Above this there are a first trough (D1), a second trough (D2), a third trough (D3), a sixth trough (D6) and a seventh trough (D7). Their endowments will be discussed later. These troughs are shielded from the surface by means of a first insulation layer (I). Openings for contacts are inserted into the first insulation layer (I).

An eighth well (D8), which extends to the surface of the first substrate (SUB), is incorporated into the first well (D1) at such a contact opening in the first insulation layer (I). A first contact doping (KD1) is incorporated into the eighth well (D8).

A ninth well (D9), which extends to the surface of the first substrate (SUB), is incorporated into the second well (D2) at such a contact opening in the first insulation layer (I). A second contact doping (KD2) is incorporated into the ninth well (D9).

In the third well (D3), a tenth well (D10) is incorporated at such a contact opening in the first insulation layer (I), which extends to the surface of the first substrate (SUB). A third contact doping (KD3) is incorporated into the tenth well (D10).

A thirteenth well (D13), which extends to the surface of the first substrate (SUB), is incorporated into the third well (D3) at such a contact opening in the first insulation layer (I). A sixth contact doping (KD6) is incorporated into the thirteenth well (D13).

A fourth tub (D4) is embedded in the third tub (D3).

An eleventh well (D11), which extends to the surface of the first substrate (SUB), is incorporated into the fourth well (D4) at such a contact opening in the first insulation layer (I). A fourth contact doping (KD4) is incorporated into the eleventh well (D11).

A fifth tub (D5) is embedded in the third tub (D3).

A twelfth well (D12), which extends to the surface of the first substrate (SUB), is incorporated into the fifth well (D5) at such a contact opening in the first insulation layer (I). A fifth contact doping (KD5) is incorporated into the twelfth well (D12).

A fourteenth well (D14), which extends to the surface of the first substrate (SUB), is incorporated into the sixth well (D6) at such a contact opening in the first insulation layer (I). A seventh contact doping (KD7) is incorporated into the fourteenth well (D14).

In the seventh well (D7), a fifteenth well (D15) is incorporated at such a contact opening in the first insulation layer (I), which extends to the surface of the first substrate (SUB). An eighth contact doping (KD8) is incorporated into the fifteenth well (D15).

The second trough (D2) is preferably connected to the sixth trough (D6) and preferably includes the third trough (D3).

The third trough (D3) preferably comprises the fourth trough (D4) and the fifth trough (D5).

Preferably, the first trough (D1) is connected to the seventh trough (D7) and preferably comprises the second trough (D2) and the sixth trough (D6), as well as the third trough (D3) encompassed by these, as well as the fourth trough encompassed by this Tub (D4) and fifth tub (D5).

Preferably, the first well (D1) and the second well (D2) and the third well (D3) and the sixth well (D6) and the seventh well (D7) extend from the first insulation layer (I) to the surface of the first substrate (SUB) to the first buried layer (BL) inside the first substrate (SUB).

The fourth well (D4) and the fifth well (D5) preferably extend from the first insulation layer (I) on the surface of the first substrate (SUB) into the third well (D3), but not to the first buried layer (BL ) inside the first substrate (SUB).

The first signal connection (A) is connected to the fourth contact doping (KD4).

The second signal connection (B) is connected to the fifth contact doping (KD5).

The third signal connection (C) is connected to the second contact doping (KD2) and to the seventh contact doping (KD7).

The first contact doping (KD1) and the third contact doping (KD3) and the sixth contact doping (KD6) and the eighth contact doping (KD8) are connected to the first node (K).

The first well (D1) and the third well (D3) and the seventh well (D7) and the eighth well (D8) and the fifteenth well (D15) are weakly n-doped when using PNP bipolar transistors.

The first well (D1) and the third well (D3) and the seventh well (D7) and the eighth well (D8) and the fifteenth well (D15) are weakly p-doped when using NPN bipolar transistors.

The second well (D2) and the sixth well (D6) and the ninth well (D9) and the fourteenth well (D14) are weakly p-doped when using PNP bipolar transistors.

The second well (D2) and the sixth well (D6) and the ninth well (D9) and the fourteenth well (D14) are weakly n-doped when using NPN bipolar transistors.

The fourth well (D4) and the fifth well (D5) and the tenth well (D10) and the eleventh well (D11) and the twelfth well (D12) and the thirteenth well (D13) are p- when using PNP bipolar transistors. endowed.

The fourth well (D4) and the fifth well (D5) and the tenth well (D10) and the eleventh well (D11) and the twelfth well (D12) and the thirteenth well (D13) are n- endowed.

The first contact doping (KD1) and the eighth contact doping (KD8) are heavily n-doped when using PNP bipolar transistors.

The first contact doping (KD1) and the eighth contact doping (KD8) are heavily p-doped when using NPN bipolar transistors.

The third contact doping (KD3) and the fourth contact doping (KD4) and the fifth contact doping (KD5) and the sixth contact doping (KD6) are heavily p-doped when using PNP bipolar transistors.

The third contact doping (KD3) and the fourth contact doping (KD4) and the fifth contact doping (KD5) and the sixth contact doping (KD6) are heavily n-doped when using NPN bipolar transistors.

The second contact doping (KD2) and the seventh contact doping (KD7) are p-doped when using PNP bipolar transistors.

The second contact doping (KD2) and the seventh contact doping (KD7) are n-doped when using NPN bipolar transistors.

The first buried layer (BL) is heavily n-doped when using PNP bipolar transistors.

The first buried layer (BL) is heavily p-doped when using NPN bipolar transistors.

The first substrate (SUB) is weakly p-doped when using PNP bipolar transistors.

The first substrate (SUB) is weakly n-doped when using NPN bipolar transistors.

The first region (G1) includes the second well (D2) and the ninth well (D9) and the second contact doping (KD2).

The second region (G2) includes the tenth well (D10) and the third contact doping (KD3).

The third region (G3) includes the fourth well (D4) and the eleventh well (D11) and the fourth contact doping (KD4).

The fourth region (G4) includes the fifth well (D5) and the twelfth well (D12) and the fifth contact doping (KD5).

The fifth region (G5) includes the thirteenth well (D13) and the sixth contact doping (KD6).

The sixth region (G6) includes the sixth well (D6) and the fourteenth well (D14) and the seventh contact doping (KD7).

The collector of the first bipolar transistor (T1) is realized by the third region (G3).

The emitter of the first bipolar transistor (T1) is realized by the second region (G2).

The collector of the second bipolar transistor (T2) is realized by the first region (G1) and by the sixth region (G6).

The emitter of the second bipolar transistor (T2) is realized by the second region (G2) and by the fifth region (G5).

The collector of the third bipolar transistor (T3) is realized by the third region (G3).

The emitter of the third bipolar transistor (T3) is realized by the fourth region (G4).

The collector of the fourth bipolar transistor (T4) is realized by the fourth region (G4).

The emitter of the fourth bipolar transistor (T4) is realized by the fifth region (G5).

The third well (D3) is the common base well of the first bipolar transistor (T1), the second bipolar transistor (T2), the third bipolar transistor (T3) and the fourth bipolar transistor (T4).

The breakdown voltage of the third bipolar transistor (T3) can be varied via a first distance (d) between the fourth well (D4) and the fifth well (D5). Here, the breakdown voltage is increased by increasing the first distance (d) between the fourth well (D4) and the fifth well (D5).

The breakdown voltage of the third bipolar transistor (T3) can be varied via the doping profile between the fourth well (D4) and the fifth well (D5). The breakdown voltage increases as the doping concentration decreases at the edges of the doping region between the fourth well (D4) and the fifth well (D5).

The structure of the ESD protective structure according to the invention is in 7 and in 8th shown, where in 8th the position of the first bipolar transistor (T1), the second bipolar transistor (T2), the third bipolar transistor (T3) and the fourth bipolar transistor (T4) is shown.

Due to the integration into a common base well, the third well (D3), and the above-described implementation of the third bipolar transistor (T3) between the first signal connection (A) and the second signal connection (B), the ESD protection structure is more variable

Breakdown voltage area efficient. In comparison to an ESD protection structure implemented with discrete bipolar transistors, the required area of the ESD protection structure according to the invention is 15% smaller, as in 9 shown. The ESD strength is retained despite the reduction in area. Scalability and thermal conductivity are improved.

Features of the invention

The invention relates to an ESD protection structure for protecting the first signal connection (A) and the second signal connection (B).

It includes the first node (K), the first reference potential (GND), the first bipolar transistor (T1), the second bipolar transistor (T2), the third bipolar transistor (T3) and the fourth bipolar transistor (T4).

The first bipolar transistor (T1), the second bipolar transistor (T2), the third bipolar transistor (T3) and the fourth bipolar transistor (T4) are bipolar transistors of a transistor type.

The transistor type is PNP bipolar transistor or NPN bipolar transistor.

The collector of the first bipolar transistor (T1) is connected to the first signal terminal (A). The base of the first bipolar transistor (T1) is connected to the first node (K). The emitter of the first bipolar transistor (T1) is connected to the first node (K).

The collector of the second bipolar transistor (T2) is connected to a third signal terminal (C). The first reference potential (GND) is present at the third signal connection (C). The base of the second bipolar transistor (T2) is connected to the first node (K). The emitter of the second bipolar transistor (T2) is connected to the first node (K).

The collector of the third bipolar transistor (T3) is connected to the first signal terminal (A). The base of the third bipolar transistor (T3) is connected to the first node (K). The emitter of the third bipolar transistor (T3) is connected to the second signal terminal (B).

The collector of the fourth bipolar transistor (T4) is connected to the second signal terminal (B). The base of the fourth bipolar transistor (T4) is connected to the first node (K). The emitter of the fourth bipolar transistor (T4) is connected to the first node (K).

The ESD protection structure for protecting the first signal connection (A) and the second signal connection (B) is preferably located in a common base well, the third well (D3).

The first buried layer (BL) is incorporated into the first substrate (SUB). Above this are the first tub (D1), the second tub (D2), third tub (D3), the sixth tub (D6) and the seventh tub (D7). These troughs are shielded from the surface by means of the first insulation layer (I). Openings for contacts are inserted into the first insulation layer (I).

The eighth well (D8), which extends to the surface of the first substrate (SUB), is incorporated into the first well (D1) at such a contact opening in the first insulation layer (I). The first contact doping (KD1) is incorporated into the eighth well (D8).

The ninth well (D9), which extends to the surface of the first substrate (SUB), is incorporated into the second well (D2) at such a contact opening in the first insulation layer (I). The second contact doping (KD2) is incorporated into the ninth well (D9).

The tenth well (D10), which extends to the surface of the first substrate (SUB), is incorporated into the third well (D3) at such a contact opening in the first insulation layer (I). The third contact doping (KD3) is incorporated into the tenth well (D10).

The thirteenth well (D13), which extends to the surface of the first substrate (SUB), is incorporated into the third well (D3) at such a contact opening in the first insulation layer (I). The sixth contact doping (KD6) is incorporated into the thirteenth well (D13).

The fourth tub (D4) is embedded in the third tub (D3).

The eleventh well (D11), which extends to the surface of the first substrate (SUB), is incorporated into the fourth well (D4) at such a contact opening in the first insulation layer (I). The fourth contact doping (KD4) is incorporated into the eleventh well (D11).

The fifth tub (D5) is embedded in the third tub (D3).

In the fifth well (D5), the twelfth well (D12), which extends to the surface of the first substrate (SUB), is incorporated at such a contact opening in the first insulation layer (I). The fifth contact doping (KD5) is incorporated into the twelfth well (D12).

In the sixth well (D6), the fourteenth well (D14), which extends to the surface of the first substrate (SUB), is incorporated at such a contact opening in the first insulation layer (I). The seventh contact doping (KD7) is incorporated into the fourteenth well (D14).

In the seventh well (D7), the fifteenth well (D15), which extends to the surface of the first substrate (SUB), is incorporated at such a contact opening in the first insulation layer (I). The eighth contact doping (KD8) is incorporated into the fifteenth well (D15).

The second trough (D2) is preferably connected to the sixth trough (D6) and preferably includes the third trough (D3).

The third trough (D3) preferably comprises the fourth trough (D4) and the fifth trough (D5).

Preferably, the first trough (D1) is connected to the seventh trough (D7) and preferably comprises the second trough (D2) and the sixth trough (D6), as well as the third trough (D3) encompassed by these, as well as the fourth trough encompassed by this Tub (D4) and fifth tub (D5).

Preferably, the first well (D1) and the second well (D2) and the third well (D3) and the sixth well (D6) and the seventh well (D7) extend from the first insulation layer (I) to the surface of the first substrate (SUB) to the first buried layer (BL) inside the first substrate (SUB).

The fourth well (D4) and the fifth well (D5) preferably extend from the first insulation layer (I) on the surface of the first substrate (SUB) into the third well (D3), but not to the first buried layer (BL ) inside the first substrate (SUB).

The first well (D1) and the third well (D3) and the seventh well (D7) and the eighth well (D8) and the fifteenth well (D15) are weakly n-doped when using PNP bipolar transistors.

The first well (D1) and the third well (D3) and the seventh well (D7) and the eighth well (D8) and the fifteenth well (D15) are weakly p-doped when using NPN bipolar transistors.

The second tub (D2) and the sixth tub (D6) and the ninth tub (D9) and the four Tenth well (D14) are weakly p-doped when using PNP bipolar transistors.

The second well (D2) and the sixth well (D6) and the ninth well (D9) and the fourteenth well (D14) are weakly n-doped when using NPN bipolar transistors.

The fourth well (D4) and the fifth well (D5) and the tenth well (D10) and the eleventh well (D11) and the twelfth well (D12) and the thirteenth well (D13) are p- when using PNP bipolar transistors. endowed.

The fourth well (D4) and the fifth well (D5) and the tenth well (D10) and the eleventh well (D11) and the twelfth well (D12) and the thirteenth well (D13) are n- endowed.

The first contact doping (KD1) and the eighth contact doping (KD8) are heavily n-doped when using PNP bipolar transistors.

The first contact doping (KD1) and the eighth contact doping (KD8) are heavily p-doped when using NPN bipolar transistors.

The third contact doping (KD3) and the fourth contact doping (KD4) and the fifth contact doping (KD5) and the sixth contact doping (KD6) are heavily p-doped when using PNP bipolar transistors.

The third contact doping (KD3) and the fourth contact doping (KD4) and the fifth contact doping (KD5) and the sixth contact doping (KD6) are heavily n-doped when using NPN bipolar transistors.

The second contact doping (KD2) and the seventh contact doping (KD7) are p-doped when using PNP bipolar transistors.

The second contact doping (KD2) and the seventh contact doping (KD7) are n-doped when using NPN bipolar transistors.

The first buried layer (BL) is heavily n-doped when using PNP bipolar transistors.

The first buried layer (BL) is heavily p-doped when using NPN bipolar transistors.

The first substrate (SUB) is weakly p-doped when using PNP bipolar transistors.

The first substrate (SUB) is weakly n-doped when using NPN bipolar transistors.

The first region (G1) includes the second well (D2) and the ninth well (D9) and the second contact doping (KD2).

The second region (G2) includes the tenth well (D10) and the third contact doping (KD3).

The third region (G3) includes the fourth well (D4) and the eleventh well (D11) and the fourth contact doping (KD4).

The fourth region (G4) includes the fifth well (D5) and the twelfth well (D12) and the fifth contact doping (KD5).

The fifth region (G5) includes the thirteenth well (D13) and the sixth contact doping (KD6).

The sixth region (G6) includes the sixth well (D6) and the fourteenth well (D14) and the seventh contact doping (KD7).

The collector of the first bipolar transistor (T1) is realized by the third region (G3).

The emitter of the first bipolar transistor (T1) is realized by the second region (G2).

The collector of the second bipolar transistor (T2) is realized by the first region (G1) and by the sixth region (G6).

The emitter of the second bipolar transistor (T2) is realized by the second region (G2) and by the fifth region (G5).

The collector of the third bipolar transistor (T3) is realized by the third region (G3).

The emitter of the third bipolar transistor (T3) is realized by the fourth region (G4).

The collector of the fourth bipolar transistor (T4) is realized by the fourth region (G4).

The emitter of the fourth bipolar transistor (T4) is realized by the fifth region (G5).

The third well (D3) is the common base well of the first bipolar transistor (T1), the second bipolar transistor (T2), the third bipolar transistor (T3) and the fourth bipolar transistor (T4).

The invention further relates to a method for adjusting the breakdown voltage of the third bipolar transistor (T3) of the ESD protection structure.

The breakdown voltage of the third bipolar transistor (T3) can be varied via the first distance (d) between the fourth well (D4) and the fifth well (D5). Here, the breakdown voltage is increased by increasing the first distance (d) between the fourth well (D4) and the fifth well (D5).

The breakdown voltage of the third bipolar transistor (T3) can be varied via the doping profile between the fourth well (D4) and the fifth well (D5). The breakdown voltage increases as the doping concentration decreases at the edges of the doping region between the fourth well (D4) and the fifth well (D5).

Advantage

Through the in 5 , 6 , 7 and 8th shown integration of the first bipolar transistor (T1), the second bipolar transistor (T2) and the fourth bipolar transistor (T4) into the common base well, the third well (D3), the adjustable third bipolar transistor (T3) is between the first signal connection (A) and the second signal connection (B).

One emitter connection is saved compared to a discrete structure. This reduces the area occupied by the ESD protective structure by approximately 15%, as in 9 shown. The simplified wiring results in improved heat distribution. This results in very good scalability.

The breakdown voltage of the third bipolar transistor (T3) can be determined via two parameters, the first distance (d) between the fourth well (D4) and the fifth well (D5) and the doping profile between the fourth well (D4) and the fifth well (D5). , can be set.

List of characters

• 1 shows an ESD protection structure that is common in BCD processes and can be adjusted via distances and implemented with bipolar transistors, which is not intended for negative terminal voltages and corresponds to the state of the art (SdT).
• 2 shows a possible solution for an ESD protection structure for negative terminal voltages, which corresponds to the state of the art (SdT).
• 3 shows a frequently used solution for an ESD protection structure for two (differential) connection terminals, which corresponds to the state of the art (SdT).
• 4 shows an example of a circuit diagram of the ESD protection structure according to the invention with PNP bipolar transistors.
• 5 shows a simplified representation of a cross section of the ESD protection structure according to the invention with bipolar transistors in the common base well, the third well (D3).
• 6 Shows the same simplified cross section as 5 . In addition, the location of the first area (G1), the second area (G2), the third area (G3), the fourth area (G4), the fifth area (G5) and the sixth area (G6) are shown.
• 7 shows a cross section of the structure of the ESD protection structure according to the invention with bipolar transistors in the common base well, the third well (D3).
• 8th 7 shows the same cross section of the structure of the ESD protection structure according to the invention with bipolar transistors as 6 . In addition, the position of the first bipolar transistor (T1), the second bipolar transistor (T2), the third bipolar transistor (T3) and the fourth bipolar transistor (T4) is shown.
• 9 shows the difference in area between the active areas of a common prior art ESD protection structure (SdT) made of discrete bipolar transistors and the ESD protection structure according to the invention.

Description of the characters

Figure 1

1 shows the cross section of an ESD protection structure that is common in BCD processes in the prior art (SdT) and implemented with bipolar transistors of the same transistor type. The type of transistor used here can be either a PNP bipolar transistor or an NPN bipolar transistor.

A highly doped second buried layer (BL2) is incorporated into a second substrate (SUB2). Directly connected to the second substrate (SUB2) are a twenty-third well (D23) and a twenty-ninth well (D29). The second buried layer (BL2) is enclosed by the twenty-third well (D23) and by the twenty-ninth well (D29). Above the second buried layer (BL2) are a twenty-fourth well (D24), a twenty-fifth well (D25), a twenty-sixth well (D26), a twenty-seventh well (D27), and a twenty-eighth well (D28). These troughs, as well as the twenty-ninth trough (D29) and the twenty-third trough (D23), are protected from the surface by means of a second insulation layer (12). shielded. Openings for contacts are inserted into the second insulation layer (12).

In the twenty-third well (D23), a sixteenth well (D16) is incorporated at such a contact opening in the second insulation layer (12), which extends to the surface of the second substrate (SUB2). A ninth contact doping (KD9) is incorporated into the sixteenth well (D16).

In the twenty-fourth well (D24), a seventeenth well (D17) is incorporated at such a contact opening in the second insulation layer (12), which extends to the surface of the second substrate (SUB2). A tenth contact doping (KD10) is incorporated into the seventeenth well (D17).

In the twenty-fifth well (D25), an eighteenth well (D18) is incorporated at such a contact opening in the second insulation layer (12), which extends to the surface of the second substrate (SUB2). An eleventh contact doping (KD11) is incorporated into the eighteenth well (D18).

In the twenty-sixth well (D26), a nineteenth well (D19) is incorporated at such a contact opening in the second insulation layer (12), which extends to the surface of the second substrate (SUB2). A twelfth contact doping (KD12) is incorporated into the nineteenth well (D19).

In the twenty-seventh well (D27), a twentieth well (D20) is incorporated at such a contact opening in the second insulation layer (12), which extends to the surface of the second substrate (SUB2). A thirteenth contact doping (KD13) is incorporated into the twentieth well (D20).

In the twenty-eighth well (D28), a twenty-first well (D21) is incorporated at such a contact opening in the second insulation layer (12), which extends to the surface of the second substrate (SUB2). A fourteenth contact doping (KD14) is incorporated into the twenty-first well (D21).

In the twenty-ninth well (D29), a twenty-second well (D22) is incorporated at such a contact opening in the second insulation layer (12), which extends to the surface of the second substrate (SUB2). A fifteenth contact doping (KD15) is incorporated into the twenty-second well (D22).

The twenty-third tub (D23), the twenty-fifth tub (D25), the twenty-seventh tub (D27), the twenty-ninth tub (D29), the thirtieth tub (D30), the thirty-second tub (D32), the thirty-fourth tub (D34) and the Thirty-sixth well (D36) are p-doped when using PNP bipolar transistors.

The twenty-third tub (D23), the twenty-fifth tub (D25), the twenty-seventh tub (D27), the twenty-ninth tub (D29), the thirtieth tub (D30), the thirty-second tub (D32), the thirty-fourth tub (D34) and the Thirty-sixth well (D36) are n-doped when using NPN bipolar transistors.

The twenty-fourth well (D24), the twenty-sixth well (D26), the twenty-eighth well (D28), the thirty-first well (D31), the thirty-third well (D33), and the thirty-fifth well (D35) are n- endowed.

The twenty-fourth well (D24), the twenty-sixth well (D26), the twenty-eighth well (D28), the thirty-first well (D31), the thirty-third well (D33), and the thirty-fifth well (D35) are p- when using NPN bipolar transistors. endowed.

The ninth contact doping (KD9), the eleventh contact doping (KD11), the thirteenth contact doping (KD13) and the fifteenth contact doping (KD15) are heavily p-doped when using PNP bipolar transistors.

The ninth contact doping (KD9), the eleventh contact doping (KD11), the thirteenth contact doping (KD13) and the fifteenth contact doping (KD15) are heavily n-doped when using NPN bipolar transistors.

The tenth contact doping (KD10), the twelfth contact doping (KD12) and the fourteenth contact doping (KD14) are heavily n-doped when using PNP bipolar transistors.

The tenth contact doping (KD10), the twelfth contact doping (KD12) and the fourteenth contact doping (KD14) are heavily p-doped when using NPN bipolar transistors.

The second buried layer (BL2) is heavily n-doped when using PNP bipolar transistors.

The second buried layer (BL2) is heavily p-doped when using NPN bipolar transistors.

The second substrate (SUB2) is weakly p-doped when using PNP bipolar transistors.

The second substrate (SUB2) is weakly n-doped when using NPN bipolar transistors.

A first voltage (S) can be adjusted by changing the distance between the twenty-fifth well (D25) and the twenty-sixth well (D26).

A fifth signal connection (PLUS) is connected to the tenth contact doping (KD10), to the twelfth contact doping (KD12) and to the fourteenth contact doping (KD14). When using PNP bipolar transistors, there is a positive potential at the fifth signal connection (PLUS). When using NPN bipolar transistors, there is a negative potential at the fifth signal connection (PLUS).

The eleventh contact doping (KD11) is connected to the thirteenth contact doping (KD13) and to the fourth signal connection (MIN). When using PNP bipolar transistors, there is a negative potential at the fourth signal connection (MIN). When using NPN bipolar transistors, there is a positive potential at the fourth signal connection (MIN).

A substrate connection (PSUB) is connected to the ninth contact doping (KD9). A substrate voltage is present at the substrate connection (PSUB).

It is not intended to use the ESD protection structure for terminal voltages lower than the substrate voltage present at the substrate connection (PSUB).

Figure 2

A possible solution according to the state of the art (SdT) for an ESD protection structure for terminal voltages, which can also be lower than the substrate voltage, as is common in automotive buses, is to connect several PNP structures together at the base. The use of NPN structures is also possible. For example, this ESD protection structure can also be implemented with discrete PN diodes. The corresponding circuit diagram is in 2 shown.

The cathodes of a first discrete PN diode (PN1), a second discrete PN diode (PN2) and a third discrete PN diode (PN3) are connected to each other at a second node (K2). The anode of the first discrete PN diode (PN1) is connected to a sixth signal terminal (A1). A second reference potential (GND2) is present at the anode of the second discrete PN diode (PN2). A second substrate voltage (SUB2) is present at the anode of the third discrete PN diode (PN3).

Figure 3

3 shows a solution often used in the prior art (SdT) for an ESD protection structure for two (differential) connection terminals, to which negative voltages can also be present. The ESD protection structure is exemplified as in 2 shown with discrete PN diodes, two as in 2 ESD protection structures shown are interconnected at the base.

The ESD protection for the sixth signal connection (A1) is as in 2 shown realized.

The cathodes of the first discrete PN diode (PN1), the second discrete PN diode (PN2) and the third discrete PN diode (PN3) are connected to each other at the second node (K2). The anode of the first discrete PN diode (PN1) is connected to the sixth signal terminal (A1). The second reference potential (GND2) is present at the anode of the second discrete PN diode (PN2). The second substrate voltage (SUB2) is present at the anode of the third discrete PN diode (PN3).

The cathodes of a fourth discrete PN diode (PN4), a fifth discrete PN diode (PN5) and a sixth discrete PN diode (PN6) are connected to each other at a third node (K3). The anode of the fourth discrete PN diode (PN4) is connected to a seventh signal terminal (B1). The second reference potential (GND2) is present at the anode of the fifth discrete PN diode (PN5). The second substrate voltage (SUB2) is present at the anode of the sixth discrete PN diode (PN6).

A common ESD protection structure for the sixth signal connection (A1) and the seventh signal connection (B1) is implemented as described below. The cathodes of a seventh discrete PN diode (PN7), an eighth discrete PN diode (PN8), a ninth discrete PN diode (PN9) and a tenth discrete PN diode (PN10) are connected to each other at a fourth node (K4). tied together. The anode of the seventh discrete PN diode (PN7) is connected to the sixth signal terminal (A1). The anode of the eighth discrete PN Diode (PN8) is connected to the seventh signal terminal (B1). The second reference potential (GND2) is present at the anode of the ninth discrete PN diode (PN9). The second substrate voltage (SUB2) is present at the anode of the tenth discrete PN diode (PN10).

Figure 4

4 shows an example of a circuit diagram of the ESD protection structure according to the invention with PNP bipolar transistors. The first signal connection (A) is connected to the collector of the first bipolar transistor (T1) and to the collector of the third bipolar transistor (T3). The second signal connection (B) is connected to the emitter of the third bipolar transistor (T3) and to the collector of the fourth bipolar transistor (T4). The base of the first bipolar transistor (T1) and the emitter of the first bipolar transistor (T1) and the base of the second bipolar transistor (T2) and the emitter of the second bipolar transistor (T2) and the base of the third bipolar transistor (T3) and the base of the fourth bipolar transistor (T4) and the emitter of the fourth bipolar transistor (T4) are connected to each other at the first node (K). The collector of the second bipolar transistor (T2) is connected to the first reference potential (GND). The ESD protection structure can also be realized with NPN bipolar transistors.

Figure 5

5 shows a simplified representation of a cross section of the ESD protective structure according to the invention.

The highly doped, buried first buried layer (BL) is incorporated into the first substrate (SUB). Above this are the first tub (D1), the second tub (D2), the third tub (D3), the sixth tub (D6) and the seventh tub (D7). These troughs are shielded from the surface by means of the first insulation layer (I). Openings for contacts are inserted into the first insulation layer (I).

The eighth well (D8), which extends to the surface of the first substrate (SUB), is incorporated into the first well (D1) at such a contact opening in the first insulation layer (I). The first contact doping (KD1) is incorporated into the eighth well (D8).

The ninth well (D9), which extends to the surface of the first substrate (SUB), is incorporated into the second well (D2) at such a contact opening in the first insulation layer (I). The second contact doping (KD2) is incorporated into the ninth well (D9).

The tenth well (D10), which extends to the surface of the first substrate (SUB), is incorporated into the third well (D3) at such a contact opening in the first insulation layer (I). The third contact doping (KD3) is incorporated into the tenth well (D10).

The thirteenth well (D13), which extends to the surface of the first substrate (SUB), is incorporated into the third well (D3) at such a contact opening in the first insulation layer (I). The sixth contact doping (KD6) is incorporated into the thirteenth well (D13).

The fourth tub (D4) is embedded in the third tub (D3).

The eleventh well (D11), which extends to the surface of the first substrate (SUB), is incorporated into the fourth well (D4) at such a contact opening in the first insulation layer (I). The fourth contact doping (KD4) is incorporated into the eleventh well (D11).

The fifth tub (D5) is embedded in the third tub (D3).

In the fifth well (D5), the twelfth well (D12), which extends to the surface of the first substrate (SUB), is incorporated at such a contact opening in the first insulation layer (I). The fifth contact doping (KD5) is incorporated into the twelfth well (D12). In the sixth well (D6), the fourteenth well (D14), which extends to the surface of the first substrate (SUB), is incorporated at such a contact opening in the first insulation layer (I). The seventh contact doping (KD7) is incorporated into the fourteenth well (D14).

In the seventh well (D7), the fifteenth well (D15), which extends to the surface of the first substrate (SUB), is incorporated at such a contact opening in the first insulation layer (I). The eighth contact doping (KD8) is incorporated into the fifteenth well (D15).

The second trough (D2) is connected to the sixth trough (D6) and includes the third trough (D3).

The third well (D3) includes the fourth well (D4) and the fifth well (D5).

The first trough (D1) is connected to the seventh trough (D7) and includes the second trough (D2) and the sixth trough (D6), as well as the third trough (D3) encompassed by these, as well as the fourth trough (D3) encompassed by this. D4) and fifth tub (D5).

The first well (D1) and the second well (D2) and the third well (D3) and the sixth well (D6) and the seventh well (D7) extend from the first insulation layer (I) to the surface of the first substrate ( SUB) to the first buried layer (BL) inside the first substrate (SUB). The fourth well (D4) and the fifth well (D5) extend from the first insulation layer (I) on the surface of the first substrate (SUB) into the third well (D3), but not to the first buried layer (BL) inside the first substrate (SUB).

The first signal connection (A) is connected to the fourth contact doping (KD4).

The second signal connection (B) is connected to the fifth contact doping (KD5).

The third signal connection (C) is connected to the second contact doping (KD2) and to the seventh contact doping (KD7).

The first contact doping (KD1) and the third contact doping (KD3) and the sixth contact doping (KD6) and the eighth contact doping (KD8) are connected to the first node (K).

Figure 6

6 shows the same cross section as described above 5 . Additionally is in 6 the location of the first area (G1) and the location of the second area (G2) and the location of the third area (G3) and the location of the fourth area (G4) and the location of the fifth area (G5) and the location of the sixth area (G6) shown.

The first region (G1) includes the second well (D2) and the ninth well (D9) and the second contact doping (KD2).

The second region (G2) includes the tenth well (D10) and the third contact doping (KD3).

The third region (G3) includes the fourth well (D4) and the eleventh well (D11) and the fourth contact doping (KD4).

The fourth region (G4) includes the fifth well (D5) and the twelfth well (D12) and the fifth contact doping (KD5).

The fifth region (G5) includes the thirteenth well (D13) and the sixth contact doping (KD6).

The sixth region (G6) includes the sixth well (D6) and the fourteenth well (D14) and the seventh contact doping (KD7).

Figure 7

7 shows the same cross section of the exemplary structure of the ESD protective structure according to the invention as 5 and 6 as a perspective drawing. In addition, the realization of the connections using conductor tracks and vias is shown.

The first signal connection (A) is connected to a sixth conductor track (L6).

The second signal connection (B) is connected to an eighth conductor track (L8).

The third signal connection (C) is connected to a fourth conductor track (L4).

The first contact doping (KD1) is connected to a first conductor track (L1).

The second contact doping (KD2) is connected to a third conductor track (L3).

The third contact doping (KD3) is connected to a fifth conductor track (L5).

The fourth contact doping (KD4) is connected to a seventh conductor track (L7).

The fifth contact doping (KD5) is connected to a ninth conductor track (L9).

The sixth contact doping (KD6) is connected to a tenth conductor track (L10).

The seventh contact doping (KD7) is connected to an eleventh conductor track (L11).

The eighth contact doping (KD8) is connected to a twelfth conductor track (L12).

The first conductor track (L1) is connected to a second conductor track (L2) by a first via (V1).

The fifth conductor track (L5) is connected to the second conductor track (L2) by a third via (V3).

The tenth conductor track (L10) is connected to the second conductor track (L2) by a sixth via (V6).

The twelfth conductor track (L12) is connected to the second conductor track (L2) by an eighth via (V8).

The third conductor track (L3) is connected to the fourth conductor track (L4) by a second via (V2).

The eleventh conductor track (L11) is connected to the fourth conductor track (L4) by a seventh via (V7).

The sixth conductor track (L6) is connected to the seventh conductor track (L7) by a fourth via (V4).

The eighth conductor track (L8) is connected to the ninth conductor track (L9) by a fifth via (V5).

Figure 8

8th shows the same perspective drawing of the exemplary cross section of the ESD protective structure according to the invention as 7 . In addition, the position of the first bipolar transistor (T1) and the position of the second bipolar transistor (T2) and the position of the third bipolar transistor (T3) and the position of the fourth bipolar transistor (T4) are shown.

The first bipolar transistor (T1) lies between the fifth conductor track (L5) and the seventh conductor track (L7).

The second bipolar transistor (T2) lies between the third conductor track (L3) and the fifth conductor track (L5). For reasons of symmetry, the second bipolar transistor (T2) is also located between the tenth conductor track (L10) and the eleventh conductor track (L11).

The third bipolar transistor (T3) is located between the seventh conductor track (L7) and the ninth conductor track (L9).

The fourth bipolar transistor (T4) is located between the ninth conductor track (L9) and the tenth conductor track (L10).

Figure 9

9 shows the difference in area between the active areas of a common ESD protection structure made of discrete bipolar transistors and the ESD protection structure according to the invention. On the left side, the active areas of a common ESD protection structure made of discrete bipolar transistors are shown by black horizontal lines. On the right side, the active areas of the ESD protective structure according to the invention are shown by black horizontal lines. The area occupied by black horizontal lines on the right is smaller than the corresponding area on the left. This corresponds to the approximately 15% smaller area of the ESD protective structure according to the invention.

Reference symbol list

A

first signal connection;

A1

sixth signal port;

b

second signal connection;

B1

seventh signal port;

BL

first buried layer;

BL2

second buried layer;

C

third signal connection;

d

first distance;

D1

first tub;

D2

second tub;

D3

third tub;

D4

fourth tub;

D5

fifth tub;

D6

sixth tub;

D7

seventh tub;

D8

eighth tub;

D9

ninth tub;

D10

tenth tub;

D11

eleventh tub;

D12

twelfth tub;

D13

thirteenth tub;

D14

fourteenth tub;

D15

fifteenth tub;

D16

sixteenth tub;

D17

seventeenth tub;

D18

eighteenth tub;

D19

nineteenth tub;

D20

twentieth tub;

D21

twenty-first tub;

D22

twenty-second tub;

D23

twenty-third tub;

D24

twenty-fourth tub;

D25

twenty-fifth tub;

D26

twenty-sixth tub;

D27

twenty-seventh tub;

D28

twenty-eighth tub;

D29

twenty-ninth tub;

G1

first area;

G2

second area;

G3

third area;

G4

fourth area;

G5

fifth area;

G6

sixth area;

GND

first reference potential;

GND2

second reference potential;

I

first insulation layer;

I2

second insulation layer

K

first node;

KD1

first contact doping;

KD2

second contact doping;

KD3

third contact doping;

KD4

fourth contact doping;

KD5

fifth contact doping;

KD6

sixth contact doping;

KD7

seventh contact doping;

KD8

eighth contact doping;

KD9

ninth contact doping;

KD10

tenth contact doping;

KD11

eleventh contact doping;

KD12

twelfth contact doping;

KD13

thirteenth contact doping;

KD14

fourteenth contact doping;

KD15

fifteenth contact doping;

L1

first conductor track;

L2

second conductor track;

L3

third conductor track;

L4

fourth conductor track;

L5

fifth conductor track;

L6

sixth conductor track;

L7

seventh conductor track;

L8

eighth conductor track;

L9

ninth conductor track;

L10

tenth conductor track;

L11

eleventh conductor track;

L12

twelfth conductor track;

MIN

fourth signal connection;

PLUS

fifth signal port;

PN1

first discrete PN diode;

PN2

second discrete PN diode;

PN3

third discrete PN diode;

PN4

fourth discrete PN diode;

PN5

fifth discrete PN diode;

PN6

sixth discrete PN diode;

PN7

seventh discrete PN diode;

PN8

eighth discrete PN diode;

PN9

ninth discrete PN diode;

PN10

tenth discrete PN diode;

PSUB2

second substrate voltage;

S

first tension;

SdT

State of the art;

SUB

first substrate;

SUB2

second substrate;

T1

first bipolar transistor;

T2

second bipolar transistor;

T3

third bipolar transistor;

T4

fourth bipolar transistor;

V1

first via;

V2

second via;

V3

third via;

V4

fourth via;

V5

fifth via;

V6

sixth via;

V7

seventh via;

V8

eighth via;

Claims (4)

ESD protection structure for protecting a first signal connection (A) and a second signal connection (B) with a first node (K) and with a first reference potential (GND) and with a first bipolar transistor (T1) and with a second bipolar transistor (T2) and with a third bipolar transistor (T3) and with a fourth bipolar transistor (T4), wherein the first bipolar transistor (T1) is a bipolar transistor of a transistor type and wherein the second bipolar transistor (T2) is a bipolar transistor of the same transistor type and wherein the third bipolar transistor (T3 ) is a bipolar transistor of the same transistor type and wherein the fourth bipolar transistor (T4) is a bipolar transistor of the same transistor type and wherein the transistor type is a PNP bipolar transistor or an NPN bipolar transistor and wherein the collector of the first bipolar transistor (T1) is connected to the first signal terminal ( A) is connected and wherein the base of the first bipolar transistor (T1) is connected to the first node (K) and wherein the emitter of the first bipolar transistor (T1) is connected to the first node (K) and wherein the collector of the second bipolar transistor (T2) is connected to the reference potential (GND) and wherein the base of the second bipolar transistor (T2) is connected to the first node (K) is connected and wherein the emitter of the second bipolar transistor (T2) is connected to the first node (K) and wherein the collector of the third bipolar transistor (T3) is connected to the first signal terminal (A) and wherein the base of the third bipolar transistor (T3) is connected to the first node (K) and wherein the emitter of the third bipolar transistor (T3) is connected to the second signal terminal (B) and wherein the collector of the fourth bipolar transistor (T4) is connected to the second signal terminal (B). and wherein the base of the fourth bipolar transistor (T4) is connected to the first node (K) and wherein the emitter of the fourth bipolar transistor (T4) is connected to the first node (K). ESD protection structure for protecting a first signal connection (A) and a second signal connection (B), with a first node (K) and with a first reference potential (GND) and with a first bipolar transistor (T1) and with a second bipolar transistor (T2) and with a third bipolar transistor (T3) and with a fourth bipolar transistor (T4), wherein the first bipolar transistor (T1) is a bipolar transistor of a transistor type and wherein the second bipolar transistor (T2) is a bipolar transistor of the same transistor type and wherein the third bipolar transistor ( T3) is a bipolar transistor of the same transistor type and wherein the fourth bipolar transistor (T4) is a bipolar transistor of the same transistor type and wherein the transistor type is a PNP bipolar transistor or an NPN bipolar transistor and wherein in a first substrate (SUB) a highly doped buried first buried -Layer (BL) is incorporated and wherein above the first buried layer (BL) there is a first trough (D1), a second trough (D2), a third trough (D3), a sixth trough (D6) and a seventh trough (D7), whereby a fourth trough (D4) is embedded in the third trough (D3) and a fifth trough (D5) is embedded in the third trough (D3), and these troughs are opposite by means of a first insulation layer (I). the surface are shielded and wherein openings for contacts are inserted into the first insulation layer (I) and an eighth trough (D8) is incorporated in the first trough (D1) at such a contact opening in the first insulation layer (I), this trough extends to the surface of the first substrate (SUB) and wherein a first contact doping (KD1) is incorporated into the eighth well (D8) and a ninth well (KD1) is incorporated in the second well (D2) at such a contact opening in the first insulation layer (I). D9) is incorporated, this trough extending to the surface of the first substrate (SUB) and a second contact doping (KD2) being incorporated into the ninth trough (D9) and wherein in the third trough (D3) at such a contact opening A tenth well (D10) is incorporated into the first insulation layer (I), this well extending to the surface of the first substrate (SUB) and wherein a third contact doping (KD3) is incorporated into the tenth well (D10) and wherein in the third Well (D3) a thirteenth well (D13) is incorporated into such a contact opening of the first insulation layer (I), this well extending to the surface of the first substrate (SUB) and a sixth contact doping (D13) being incorporated into the thirteenth well (D13). KD6) is incorporated and an eleventh well (D11) is incorporated in the fourth well (D4) at such a contact opening in the first insulation layer (I), this well extending to the surface of the first substrate (SUB) and in which eleventh well (D11), a fourth contact doping (KD4) is incorporated and a twelfth well (D12) is incorporated in the fifth well (D5) at such a contact opening in the first insulation layer (I), this well extending up to the surface of the first Substrate (SUB) extends and wherein a fifth contact doping (KD5) is incorporated into the twelfth well (D12) and a fourteenth well (D14) is incorporated into the sixth well (D6) at such a contact opening in the first insulation layer (I), wherein this trough extends to the surface of the first substrate (SUB) and wherein a seventh contact doping (KD7) is incorporated into the fourteenth trough (D14) and wherein in the seventh trough (D7) at such a contact opening of the first insulation layer (I) a fifteenth well (D15) is incorporated, this well extending to the surface of the first substrate (SUB) and wherein an eighth contact doping (KD8) is incorporated into the fifteenth well (D15) and the second well (D2) preferably with the sixth tub (D6) and wherein the second tub (D2) and the sixth tub (D6) preferably comprise the third tub (D3) and wherein the third tub (D3) preferably includes the fourth Tub (D4) and the fifth tub (D6) and wherein preferably the first tub (D1) is connected to the seventh tub (D7) and wherein the first tub (D1) and the seventh tub (D7) preferably the second tub ( D2) and the sixth trough (D6) and wherein the first trough (D1) and the second trough (D2) and the third trough (D3) and the sixth trough (D6) and the seventh trough (D7) are preferably from the first insulation layer (I) on the surface of the first substrate (SUB) extend to the first buried layer (BL) and the fourth well (D4) and the fifth well (D5) preferably extend from the first insulation layer (I) at the Surface of the first substrate (SUB) extends into the third well (D3), but not to the first buried layer (BL), with a first region (G1) the second well (D2) and the ninth well (D9) and the second contact doping (KD2) and wherein a second region (G2) comprises the tenth well (D10) and the third contact doping (KD3) and wherein a third region (G3) comprises the fourth well (D4) and the eleventh well (D11) and the fourth contact doping (KD4) and wherein a fourth region (G4) comprises the fifth well (D5) and the twelfth well (D12) and the fifth contact doping (KD5) and wherein a fifth region (G5) comprises the thirteenth well (D13 ) and the sixth contact doping (KD6) and wherein a sixth region (G6) comprises the sixth well (D6) and the fourteenth well (D14) and the seventh contact doping (KD7) and wherein the second well (D2) and the fourth well (D4) and the fifth tub (D5) and the sixth tub (D6) and the ninth tub (D9) and the tenth tub (D10) and the eleventh tub (D11) and the twelfth tub (D12) and the thirteenth tub ( D13) and the first substrate (SUB) and the second contact doping (KD2) and the third contact doping (KD3) and the fourth contact doping (KD4) and the fifth contact doping (KD5) and the sixth contact doping (KD6) and the seventh contact doping (KD7 ) have p-doping when using the PNP bipolar transistor type and have n-doping when using the NPN bipolar transistor type and where the first well (D1) and the third well (D3) and the seventh well (D7) and the eighth well (D8) and the fifteenth well (D15) and the first buried layer (BL) and the first contact doping (KD1) and the eighth contact doping (KD8) have an n-doping when using the PNP bipolar transistor type and when using the NPN Bipolar transistor type have a p-doping and wherein the collector of the first bipolar transistor (T1) is realized by the third region (G3) and wherein the emitter of the first bipolar transistor (T1) is realized by the second region (G2) and wherein the collector of the second bipolar transistor (T2) is realized by the first region (G1) and by the sixth region (G6) and the emitter of the second bipolar transistor (T2) is realized by the second region (G2) and by the fifth region (G5) is realized and wherein the collector of the third bipolar transistor (T3) is realized by the third region (G3) and wherein the emitter of the third bipolar transistor (T3) is realized by the fourth region (G4) and wherein the collector of the fourth bipolar transistor (T4) is realized by the fourth region (G4) and wherein the emitter of the fourth bipolar transistor (T4) is realized by the fifth region (G5) and wherein the third well (D3) is the common base well of the first bipolar transistor (T1) and the second bipolar transistor ( T2) and the third bipolar transistor (T3) and the fourth bipolar transistor (T4) and wherein the first signal connection (A) is connected to the fourth contact doping (KD4) and wherein the second signal connection (B) is connected to the fifth contact doping (KD5). is and wherein a third signal connection (C) is connected to the second contact doping (KD2) and to the seventh contact doping and wherein the first reference potential (GND) is applied to the third signal connection (C) and wherein the first contact doping (KD1) and the third contact doping (KD3) and the sixth contact doping (KD6) and the eighth contact doping (KD8) are connected to the first node (K). Method for adjusting the breakdown voltage of the third bipolar transistor (T3) of the ESD protection structure according to Claim 2 with the step of forming the ESD protection structure according to Claim 2 , wherein the breakdown voltage of the third bipolar transistor (T3) is adjusted by varying the first distance (d) between the fifth well (D5) and the sixth well (D6), the breakdown voltage of the third bipolar transistor (T3) increasing as the first distance (d) between the fifth trough (D5) and the sixth trough (D6) becomes larger. Method for adjusting the breakdown voltage of the third bipolar transistor (T3) according to an ESD protection structure Claim 2 with the step of forming the ESD protection structure according to Claim 2 , whereby the breakdown voltage of the third bipolar transistor (T3) is adjusted by varying the doping profile between the fifth Well (D5) and the sixth well (D6), the breakdown voltage increasing as the doping concentration decreases at the edges of the doping region between the fifth well (D5) and the sixth well (D6).

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