DE102019107170A1 - LOW-POWER AMPLIFIER STRUCTURES AND CALIBRATIONS FOR LOW-POWER AMPLIFIER STRUCTURES - Google Patents

Abstract

Amplifiers can be found in pipeline ADCs and pipeline SAR ADCs as interstage amplifiers. The amplifiers may in some cases implement and provide gains in high-speed track-and-hold circuits. The amplifier structures may be open loop amplifiers and the amplifier structures may be used in MDACs and high speed ADC samplers. The amplifiers can be used without reset and with incomplete oscillation to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

Description

PRIORITY DATA

The present patent application claims priority and receives the benefit of the provisional US patent application serial no. 62 / 646.181 and entitled "LOW POWER AMPLIFIER STRUCTURES AND CALIBRATIONS FOR THE LOW POWER AMPLIFIER STRUCTURES", filed March 21, 2018, which is hereby incorporated in its entirety.

TECHNICAL FIELD OF THE DISCLOSURE

The present disclosure relates to the field of integrated circuits, particularly low power amplifier structures and calibrations for the low power amplifier structures.

BACKGROUND

In many electronic applications, an analog-to-digital converter (ADC) converts an analog input signal into a digital output signal, e.g. B. for additional digital signal processing or for storage by digital electronics. Generally speaking, ADCs can be analog electrical signals representing real-world phenomena, e.g. As light, sound, temperature, electromagnetic waves or pressure, translate for data processing purposes. For example, in measurement systems, a sensor takes measurements and generates an analog signal. The analog signal would then be provided to an ADC as an input to produce a digital output signal for additional processing. In another case, a transmitter generates an analog signal using electromagnetic waves to carry information in the air, or a transmitter transmits an analog signal to carry information over a cable. The analog signal is then provided to an ADC at a receiver as an input to provide a digital output, e.g. B. for additional processing by digital electronics.

Because of their wide applicability in many applications, ADCs can be found in locations such as broadband communication systems, audio systems, receiver systems, and so on. Designing a circuit in an ADC is not a trivial task because each application may have different performance, performance, cost, and size needs. ADCs are used in a wide range of applications, including communications, energy, healthcare, instrumentation and measurement, engine and power control, industrial automation, and aerospace / defense. As the number of applications requiring ADCs increases, so does the need for fast and accurate low power conversion.

list of figures

• 1 stellt ein Blockdiagramm eines Pipeline-ADC dar, gemäß manchen Ausführungsformen der Offenbarung;
• 2 stellt eine multiplizierende Digital-Analog-Wandler-Schaltungsstruktur mit einem Verstärker mit geschlossener Schleife (Closed-Loop Verstärker bzw. geregelter Verstärker oder Regelverstärker) dar;
• 3 stellt eine beispielhafte Multiplizierender-Digital-Analog-Wandler-Schaltungsstruktur mit einem Open-Loop Verstärker (Verstärker mit offener Schleife bzw. offener oder ungeregelter Verstärker) dar, gemäß manchen Ausführungsformen der Offenbarung;
• 4-24 stellen verschiedene beispielhafte Open-Loop Verstärker dar, gemäß manchen Ausführungsformen der Offenbarung;
• 25 veranschaulicht eine beispielhafte Verstärkungsboosterschaltung, gemäß manchen Ausführungsformen der Offenbarung.
• 26-30 stellen verschiedene beispielhafte Open-Loop Verstärker dar, gemäß manchen Ausführungsformen der Offenbarung;
• 31-32 stellen beispielhafte analoge Tracking-Schaltungen zum Erzeugen einer Gate-Spannung V_G zum Ansteuern eines Gates eines Lasttransistors dar, gemäß manchen Ausführungsformen der Offenbarung;
• 33 stellt ein Blockdiagramm eines Pipeline-ADC mit in die Signalpfade injizierten Dither-Signalen dar, gemäß manchen Ausführungsformen der Offenbarung;
• 34 veranschaulicht eine Kalibrations-Dither-Injektion für eine nichtlineare Kalibration eines Verstärkers, gemäß manchen Ausführungsformen der Offenbarung;
• 35 veranschaulicht eine Linearisierungs-Dither-Injektion zum Desensibilisieren einer Kalibration gegenüber der Eingangssignalverteilung, gemäß manchen Ausführungsformen der Offenbarung;
• 36 veranschaulicht eine Injektion von sowohl Kalibrations- als auch Linearisierungs-Dither-Injektion, gemäß manchen Ausführungsformen der Offenbarung;
• 37 veranschaulicht eine Injektion einer Kalibrations-Dither-Injektion, gemäß manchen Ausführungsformen der Offenbarung;
• 38 veranschaulicht eine Verstärkungskalibration mit analoger Korrektur, gemäß manchen Ausführungsformen der Offenbarung;
• 39 stellt ein variables Dämpfungsglied in einem Frontend eines ADC dar, gemäß manchen Ausführungsformen der Offenbarung;
• 40-41 stellen beispielhafte variable Dämpfungsgliedschaltungen dar, gemäß manchen Ausführungsformen der Offenbarung.
• 42 veranschaulicht eine Memory- und Kickback-Kalibration, gemäß manchen Ausführungsformen der Offenbarung;
• 43 veranschaulicht einen multiplizierenden Digital-Analog-Wandler mit offener Schleife, gemäß manchen Ausführungsformen der Offenbarung;
• 44 stellt ein Timing-Diagramm von Abtastschaltern dar, gemäß manchen Ausführungsformen der Offenbarung;
• 45-46 stellen eine Digitalsignalverarbeitung zum Aktualisieren von Koeffizienten dar, um Kickback- und Memory-Fehler anzusprechen, gemäß manchen Ausführungsformen der Offenbarung;
• 47 stellt einen multiplizierenden Digital-Analog-Wandler mit offener Schleife dar, gemäß manchen Ausführungsformen der Offenbarung;
• 48-50 veranschaulichen verschiedene Techniken zur Kalibrations- und Linearisierungs-Dither-Injektion, gemäß manchen Ausführungsformen der Offenbarung;
• 51 veranschaulicht eine gemeinsame Nutzung eines Verstärkers, gemäß manchen Ausführungsformen der Offenbarung;
• 52 stellt ein Timing-Diagramm für den Schaltkreis 5100 von 51 dar, gemäß manchen Ausführungsformen der Offenbarung;
• 53 veranschaulicht eine gemeinsame Nutzung eines Verstärkers, gemäß manchen Ausführungsformen der Offenbarung;
• 54 stellt ein Wandlersystem dar, gemäß manchen Ausführungsformen der Offenbarung; und
• 55 stellt einen anderen beispielhaften Open-Loop Verstärker dar, gemäß manchen Ausführungsformen der Offenbarung; und
• 56 stellt einen beispielhaften IntegrationsOpen-Loop Verstärker dar, gemäß manchen Ausführungsformen der Offenbarung.

In order to provide a more complete understanding of the present disclosure and the features and advantages thereof, reference is now made to the following description, taken in conjunction with the accompanying drawings, wherein like reference numerals represent like parts, in which:

• 1 FIG. 12 illustrates a block diagram of a pipeline ADC, in accordance with some embodiments of the disclosure; FIG.
• 2 Fig. 12 illustrates a multiplying digital-to-analog converter circuit structure with a closed loop amplifier (closed loop amplifier or variable gain amplifier);
• 3 FIG. 10 illustrates an exemplary multiplying digital-to-analog converter circuit structure with an open loop amplifier (open loop amplifier) in accordance with some embodiments of the disclosure; FIG.
• 4-24 illustrate various exemplary open loop amplifiers, in accordance with some embodiments of the disclosure;
• 25 FIG. 12 illustrates an exemplary boost booster circuit, in accordance with some embodiments of the disclosure. FIG.
• 26-30 illustrate various exemplary open loop amplifiers, in accordance with some embodiments of the disclosure;
• 31-32 illustrate exemplary analog tracking circuits for generating a gate voltage V _G for driving a gate of a load transistor, according to some embodiments of the disclosure;
• 33 FIG. 12 illustrates a block diagram of a pipeline ADC having dither signals injected into the signal paths, in accordance with some embodiments of the disclosure; FIG.
• 34 FIG. 12 illustrates a calibration dither injection for a non-linear calibration of an amplifier, in accordance with some embodiments of the disclosure; FIG.
• 35 FIG. 12 illustrates a linearization dither injection for desensitizing calibration versus input signal distribution, in accordance with some embodiments of the disclosure; FIG.
• 36 FIG. 10 illustrates an injection of both calibration and linearization dither injection, in accordance with some embodiments of the disclosure; FIG.
• 37 FIG. 10 illustrates an injection of a calibration dither injection, in accordance with some embodiments of the disclosure; FIG.
• 38 FIG. 12 illustrates gain amplification with analog correction, according to some embodiments of the disclosure; FIG.
• 39 illustrates a variable attenuator in a front end of an ADC, in accordance with some embodiments of the disclosure;
• 40-41 illustrate exemplary variable attenuator circuits, in accordance with some embodiments of the disclosure.
• 42 illustrates a memory and kickback calibration, in accordance with some embodiments of the disclosure;
• 43 FIG. 10 illustrates an open-loop multiplying digital-to-analog converter according to some embodiments of the disclosure; FIG.
• 44 FIG. 12 illustrates a timing diagram of sampling switches, according to some embodiments of the disclosure; FIG.
• 45-46 illustrate digital signal processing for updating coefficients to address kickback and memory errors, in accordance with some embodiments of the disclosure;
• 47 FIG. 10 illustrates an open-loop multiplying digital-to-analog converter according to some embodiments of the disclosure; FIG.
• 48-50 illustrate various techniques for calibration and linearization dither injection, in accordance with some embodiments of the disclosure;
• 51 illustrates a sharing of an amplifier according to some embodiments of the disclosure;
• 52 provides a timing diagram for the circuit 5100 from 51 according to some embodiments of the disclosure;
• 53 illustrates a sharing of an amplifier according to some embodiments of the disclosure;
• 54 FIG. 12 illustrates a transducer system according to some embodiments of the disclosure; FIG. and
• 55 FIG. 12 illustrates another example open-loop amplifier according to some embodiments of the disclosure; FIG. and
• 56 FIG. 12 illustrates an example integration loop loop amplifier, according to some embodiments of the disclosure. FIG.

DETAILED DESCRIPTION

Overview

This document describes new and improved structures and calibration techniques for open-loop amplifiers for the multiplying digital-to-analog converter (MDAC) and the samplers of high-speed ADCs. The amplifiers can be used as interstage amplifiers in pipeline and pipeline SAR ADCs (SAR: Successive Approximation Registers - Successive Approximation Registers). The amplifiers can be used to provide gains in high-speed track-and-hold circuits. These structures are used without reset and with incomplete vibration to maximize their speed and minimize their power consumption.

The following sections describe examples of: analog amplifier structures, analog and digital techniques for enhancing the efficiency of non-linear amplifier calibration, techniques for calibrating the open-loop amplifier by feeding back an analog control signal to adjust its gain in the analog domain; coarse and fine gain adjustment techniques, analog and digital techniques for effectively performing inter-stage gain error (IGE) calibration, inter-stage memory errors (IME), and kickback (KB) errors in closed loop Loop amplifiers or open loop amplifiers, and techniques for effectively sharing an amplifier while correcting the resulting memory and kickback errors.

Design challenges for amplifiers in pipeline ADCs

Amplifiers are an essential block in pipeline ADCs (and many other circuits and systems). As part of the MDAC of pipeline ADCs, amplifiers act as inter-stage amplifiers that amplify the residual signal (i.e., the quantization error) of a stage before passing the residual signal to the next stage. An accurate and linear amplifier has traditionally been the hallmark and key to designing a pipeline ADC. It ensures the accurate delivery of the quantization error along the pipeline from one stage to the next for further quantization. In the process, its gain relaxes the accuracy requirements along the pipeline, simplifying the quantization process.

These amplifiers have been a significant design challenge and contribution to performance, especially in high-speed and high-resolution ADCs. In addition, the auxiliary circuits needed to drive these amplifiers (clocks, biases, etc.) have also contributed to power consumption, area, and design time in terms of layout and design resources. For example, in some 28nm pipeline ADCs, the MDAC amplifier requires approximately 15 bias and bias circuits and 5 clock circuits per stage. It can be seen that the amount of design, layout and area for the amplifier and auxiliary circuits is significant when multiplied by the number of stages (e.g., 4 or 5 stages in the pipeline). In addition, they require power-hungry reference buffers that add significantly to overall power consumption. Sometimes measures are taken to lower the power in these amplifiers. However, the improvement tends to be incremental and often results in the increase in performance in other areas. Addressing these blocks may be advantageous for changing the power curve as well as the development cost curve of high speed ADCs.

Digitally supported open-loop amplifier

To ensure a certain level of performance during lower power consumption, digitally-assisted open-loop amplifiers can be used in MDAC and sampling circuitry of ADCs. Digitally-supported open-loop amplifiers are amplifiers that do not rely on feedback but rely on digital calibration techniques to improve the performance of the amplifier. These amplifier structures may be used in pipeline ADCs (or other multi-stage ADCs that implement inter-stage amplification) and may benefit from higher speed, lower noise, substantially lower power, smaller footprint, and shorter development time. The area savings can be in the order of 4-10-fold. The power savings can be 4-10x compared to some other approaches. In addition to the power savings in the amplifier itself, the MDAC can save power in the reference buffer that may need to provide charge only to support the parasitic capacitance on the summing node because the closed loop (including a feedback capacitor) no longer exists. In addition, the design can save power in clock generation and other auxiliary circuits.

A major design challenge is that open-loop amplifiers may require nonlinear calibration for the high-precision stages (usually Stage-1 or other front-end stages in the pipeline). Some reliable algorithms have been developed to address this problem in an efficient manner. For example, a histogram and / or Counting calibration method the gain error and the non-linearity up to the distortion 5 , Calibrate order for about 3 mV in 16 nm and 5 mV in 28 nm at 3 GS / s. The calibration procedure shows the form of certain nonlinearities to extract errors. This digital overhead is very small compared to the power consumed by the amplifier at this sampling rate. Generally, the digital calibration power must be added to the amplifier power budget when making comparisons to ensure a total power saving of the combined analog and digital power. The advantage of open-loop structures is that they exploit the efficiently achievable calibrations to significantly reduce analog power, area, cost, and effort compared to closed-loop structures. The savings are in the amplifier itself, in the reference buffer, in the clocks and in the auxiliary circuits.

In this disclosure, some techniques are discussed that are used to calibrate the various non-ideal states of these structures and to improve their effectiveness and robustness. These techniques ensure the accurate correction of non-ideal conditions in an efficient and simple way that preserves the savings in performance, area and complexity.

Various circuits in a pipeline ADC

1 provides a block diagram of a pipeline ADC 100 According to some embodiments of the disclosure. This exemplary pipeline ADC may have a number n of stages (n is at least two). The pipeline ADC receives an analog input signal V _in and may be a sample buffer or amplifier 102 for buffering / amplifying the analog input signal V _in exhibit.

In the first stage of the pipeline ADC (Level 1 ) becomes the buffered analog input signal from the amplifier 102 through a k1-bit ADC 104 (eg a flash ADC). The ADC 104 generates an output / digital code D ₁ with k1 bits. The source / digital code D ₁ is used by a k1-bit Digital-to-Analog Converter (DAC) 106 to reconstruct the original analog input signal and provide a reconstructed analog input signal (e.g. V _dac1 ) to create. A residual signal is obtained by subtracting, e.g. By a summation node 108 , the reconstructed analog input signal V _dac1 formed by the buffered analog input signal. That through the summation node 108 The residual signal formed is also the quantization error of the ADC 104 , The rest is through an amplifier 110 amplified to the amplified residual signal (eg. V _o1 ) to create. The ideal gain of the amplifier 110 , z. B. G ₁ , can be 2 ^k1-1 . In summary form the DAC 106 , the summation node 108 and the amplifier 110 a first MDAC of the first stage, through a box 112 designated. An MDAC circuit structure may be provided to all of the DACs 106 , the summation node 108 and the amplifier 110 to implement associated functionalities and operations.

In the second stage of pipeline ADC (Level 2 ) the amplified residual signal (e.g. V _o1 ) through a k2-bit ADC 114 (eg a flash ADC). The ADC 114 generates an output / digital code D ₂ with k2 bits. The source / digital code D ₂ is through a k2 bit DAC 116 used to reconstruct the original analog input signal and a reconstructed analog input signal (e.g. V _dac2 ) to create. A residual signal is obtained by subtracting, e.g. By a summation node 118 , the reconstructed analog input signal V _dac2 from the amplified residual signal (eg V _o1 ) educated. That through the summation node 118 The residual signal formed is also the quantization error of the ADC 114 , The rest is through an amplifier 120 amplified to the amplified residual signal (eg. V _o2 ) to create. The ideal gain of the amplifier 110 , z. B. G ₂ , can be 2 ^k2-1 . In summary form the DAC 116 , the summation node 118 and the amplifier 120 a second MDAC, through a box 152 designated. An MDAC circuit structure may be provided to all of the DACs 116 , the summation node 118 and the amplifier 120 to implement associated functionalities and operations.

One or more further stages, each for quantizing and reconstructing the residual signal from a previous stage to form another residual signal, may be included.

An amplifier has an kn-bit ADC 122 for digitizing the final residual signal and for generating a digital code D _n with kn bits on.

All digital codes D ₁ . D ₂ , ... D _n from the steps become a digital error correction 124 so that the digital output codes are combined and filtered to the final digital output of the pipeline ADC 100 to build.

Pipeline ADCs can have stages that use Flash ADCs or other types of ADCs. For example, it is possible to have a SAR-based pipeline ADC. However, pipeline ADCs with different types of ADCs as their stages would still require inter-stage gain to implement inter-stage gain. Because linearity is important for gain between stages for performance reasons, it is typical for pipeline ADCs to use closed loop amplifiers. 2 represents an MDAC circuit structure 200 with an amplifier 202 with closed loop. The MDAC circuit structure is through the amplifier 202 characterized by a closed loop, the feedback capacitances 204 and 206 having. As previously discussed, closed loop amplifiers may have disadvantages and design challenges.

3 Fig. 10 illustrates an exemplary MDAC circuit structure 300 with an open-loop amplifier 302 or open loop amplifier according to some embodiments of the disclosure; The amplifier 302 Open loop is characterized by having no feedback paths or feedback capacitances. The MDAC circuit structure 300 receives, in differential form, analog differential inputs V _inp and V _inn and a digital code D and generates an amplified residual signal V _outp and V _outn , More specifically, the switched capacitor circuit shown in the figure has 310 Switches and capacitors that are configured in such a way that they have the functionality of the DAC 106 and the summation node 108 from 1 carry out. The switches operate in accordance with the phases indicated next to the switches, for. Sample operations in the circuit (e.g., sampling of V _inp and V _inn on the capacitors). Furthermore, some switches are additionally controlled by the digital code D to perform DAC operations (eg, providing a charge representing the digital code D). The digital code D is the output code of the ADC of the stage. The switched capacitor circuit 310 is configured in such a manner and is controlled in such a way as to perform a subtraction so that a residual signal is formed. The result or the output of the switched capacitor circuit 310 (ie the residual signal) is through the amplifier 302 with open loop in an open-loop configuration amplified to produce the amplified remainder, ie the differential outputs V _outp and V _outn , An MDAC is shown with open loop and shared capacity, meaning that the same capacitors perform the sense and DAC operations in the switched capacitor circuit 310 carry out. However, the capacitances may be shared between the sample and DAC operations in certain embodiments. Other configurations of the switched capacitor circuit 310 and other circuitry for performing the operations of the DAC 106 and the summation node 108 are considered by the revelation.

Improvements to the open-loop amplifiers

While some open-loop amplifiers in MDAC circuit structures (such as the in 4 seen amplifier 400 with open loop), such open loop amplifier structures suffered from limited dynamic range, poor linearity, and limited speed / gain tradeoff flexibility.

The open-loop amplifiers described herein receive differential inputs v _inp and v _inn and generate differential outputs v _outn and _Voutp . The open-loop amplifier implements a gain to the signal at the inputs (ie the differential inputs v _inp and v _inn ) to reinforce. Depending on the circuit structure, the gain and other characteristics of the open-loop amplifier may vary. Within an MDAC, such an open-loop amplifier can provide a residual signal at its differential inputs v _inp and v _inn , receives and generates an amplified residual signal at the differential outputs v _outn and _Voutp . The exemplary open loop amplifiers described herein may be suitable for MDAC circuits and other applications / contexts besides MDAC circuits (eg, the open loop amplifier may be used in a continuous time fashion as a variable gain amplifier or amplifier). ,

An exemplary circuit structure of an open-loop amplifier 500 or amplifier with open loop is in 5 shown. The amplifier 500 open loop has a differential pair of active load transistors and a load resistor. The amplifier 500 with open loop has an input transistor M _N1 502 and an input transistor M _N2 504 on, whose gates v _inp respectively. v _inn receive. The input transistor M _N1 502 and the input transistor M _N2 504 serve as the differential pair of (input) transistors. In the example shown, the input transistor M _N1 502 and the input transistor M _N2 504 N-type metal oxide semiconductor (NMOS) transistors. The drains of the input transistor M _N1 502 and the input transistor M _N2 504 form the difference output nodes v _outn and _Voutp . The input transistor M _N1 502 and the input transistor M _N2 504 are in a common source configuration (the sources of the input transistor M _N1 502 and the input transistor M _N2 504 are interconnected). The sources of the input transistor M _N1 502 and the input transistor M _N2 504 are connected to a power source that provides a current I. A transistor M _Nc 506 (eg, an NMOS transistor) may serve as the power source. The power source may provide a current for the open-loop amplifier (eg, the differential pair of (input) transistors). The gate of the transistor M _Nc 506 can by a bias V _B1 be controlled. A load resistance, z. B. a load of 2R _L , is about the difference output node v _outn and v _outp coupled. The amplifier 500 with open loop also has a transistor M _P1 508 and a transistor M _P2 510 on. The transistor M _P1 508 and the transistor M _P2 510 may be P-type metal oxide semiconductor (PMOS) transistors. The transistor M _P1 508 and the transistor M _P2 510 may serve as the active load on the output node of the open-loop amplifier. The drains of the transistor M _P1 508 and the transistor M _P2 510 are with the difference output nodes v _outn respectively. v _outp and thus also with the drains of the input transistor M _N1 502 or the input transistor M _N2 504 connected. The gates of the transistor M _P1 508 and the transistor M _P2 510 be through a bias V _B2 driven.

The reinforcement A of the amplifier 500 with open loop is determined by the following expression:

wobei g_{m N} die Transkonduktanz eines NMOS-Transistors ist und R_L der Lastwiderstand ist, der den Ausgangswiderstand der NMOS- und PMOS-Einrichtungen einschließt. Die Bandbreite (BW: Bandwidth) des Open-Loop Verstärkers ist durch Folgendes gegeben: $$A~G_{m_N}{R}_L$$

in which g _{m N} the transconductance of an NMOS transistor is and R _L is the load resistance that includes the output resistance of the NMOS and PMOS devices. The bandwidth (BW: Bandwidth) of the open-loop amplifier is given by the following:

wobei C_L die Lastkapazität ist, einschließlich der parasitären Kapazitäten an den Ausgangsknoten. $$BW~\frac{1}{2\pi R_L{C}_L}$$

in which C _L the load capacitance is, including the parasitic capacitances at the output node.

6 represents another possible circuit structure for an open-loop amplifier 600 or open loop amplifier using cascaded differential pairs. The amplifier 600 open loop has a differential pair of active load transistors and a load resistor. The input transistor M _N1 502 and the input transistor M _N2 504 are cascoded by a pair of cascode transistors. For example, the input transistor M _N1 502 and the input transistor M _N2 504 by z. B. a cascode transistor M _N3 602 or a cascode transistor M _N4 604 (eg, NMOS transistors) cascoded. The sources of the cascode transistor M _N3 602 and the cascode transistor M _N4 604 are with drains of the input transistor M _N1 502 and the input transistor M _N2 504 connected. The drains of the cascode transistor M _N3 602 and the cascode transistor M _N4 604 form (now) the difference output nodes v _{outn respectively.} v _outp , The gates of the cascode transistor M _N3 602 and the cascode transistor M _N4 604 be through a bias V _B3 driven. The transistor M _P1 528 and the transistor M _P2 510 are also controlled by a pair of cascode transistors, e.g. B. a cascode transistor M _P3 606 or a cascode transistor M _P4 608 (eg PMOS transistors), cascoded. The gates of the cascode transistor M _P3 606 and the cascode transistor M _P4 608 be through a bias V _B4 driven. The circuit structure has better gain and input capacitance, but may suffer from significantly poorer linearity.

To reduce power consumption, a push-pull circuit structure may be used as in 7 shown. 7 provides an open-loop amplifier 700 or open loop amplifier having two complementary pairs of input transistors forming the push-pull circuit structure. The amplifier 700 with open loop has a load resistance. A first pair of input transistors has an input transistor M _N1 702 and an input transistor M _N2 704 (eg, NMOS transistors). Gates of the input transistor M _N1 702 and the input transistor M _N2 704 receive v _inp respectively. v _inn , A second pair of input transistors has an input transistor M _P1 706 and an input transistor M _P2 708 (eg, PMOS transistors). Gates of the input transistor M _P1 706 and the input transistor M _P2 708 receive v _inp respectively. v _inn , The drains of the input transistor M _N1 702 and the input transistor M _P1 706 are interconnected and form a first differential output node v _outn , The drains of the input transistor M _N2 704 and the input transistor M _P2 708 are connected to each other and form a second differential _{output node Voutp} . A load of 2R _L is about the difference output nodes v _outn and v _outp coupled. The input transistor M _N1 702 and the input transistor M _N2 704 are in a common source configuration (the sources of the input transistor M _N1 702 and the input transistor M _N2 704 are interconnected). The sources of the input transistor M _N1 704 and the input transistor M _N2 704 are connected to a first power source that has a current I provides. A transistor M _Nc 710 (eg, an NMOS transistor) may serve as the first current source. The first current source is located at source terminals of the input transistor M _N1 702 and the input transistor M _N2 704 , The gate of the transistor M _Nc 710 can by a bias V _B1 be controlled. The input transistor M _P1 706 and the input transistor M _P2 708 are in a common source configuration (the sources of the input transistor M _P1 706 and the input transistor M _P2 708 are interconnected). The sources of the input transistor M _P1 706 and the input transistor M _P2 708 are connected to a second current source, which provides a current I. A transistor M _Nc 712 (eg, a PMOS transistor) may serve as the second current source. The second current source is located at source terminals of the input transistor M _P1 706 and the input transistor M _P2 708 , The gate of the transistor M _Pc 712 can by a bias V _B2 be controlled. This circuit structure helps reduce power consumption at the expense of dynamic range because it requires an additional power source. The gain A would be given by:

wobei g_{m N} die Transkonduktanz eines NMOS-Transistors ist und g_{m P} die Transkonduktanz eines PMOS-Transistors ist, und die BW würde durch Folgendes gegeben sein: $$A~\left(G_{m_N}+G_{m_P}\right)R_L$$

in which g _{m N} the transconductance of an NMOS transistor is and g _{m P} is the transconductance of a PMOS transistor, and the BW would be given by:

$$BW~\frac{1}{2\pi R_L{C}_L}$$

The net reinforcement G the MDAC circuit is given by the following:

wobei N die Anzahl von MDAC-Kapazitäten ist, C_i der Wert jeder Abtast-/DAC-Kapazität ist, C der Wert der Gesamtabtastkapazität ist, C_p die parasitäre Kapazität am Eingang des Verstärkers ist und A die Verstärkung des Verstärkers ist. $$G=\frac{N{C}_i}{N{C}_i+C_p}A=\frac{C}{C+C_p}$$

in which N the number of MDAC capacities is C _i the value of each sample / DAC capacity is C the value of the total sampling capacity is C _p is the parasitic capacitance at the input of the amplifier and A is the gain of the amplifier.

To optimize the dynamic range independently for the NMOS and PMOS transistors, level shifters can be used. 8th provides an open-loop amplifier 800 or open-loop amplifier based on the open-loop amplifier 700 with (optional) level shifters. A level shifter 1 802 and a level shifter 1 804 set the level of the differential inputs v _inp respectively. v _inn around. The outputs of the level shifter- 1 802 the level converter- 1 804 control the gates of an input transistor M _P1 706 or an input transistor M _P2 708 at. The level converter 1 802 and the level shifter 1 804 can optimize the dynamic range for the PMOS transistors. A level shifter 2 806 and a level shifter 2 808 set the level of the differential inputs v _inp respectively. v _inn around. The outputs of the level shifter- 2 806 the level converter- 2 808 control the gates of an input transistor M _N1 702 or an input transistor M _N2 704 at. The level converter 2 806 and the level shifter 2 808 can optimize the dynamic range for the NMOS transistors. Level shifters may be used for any of the open-loop amplifiers described herein.

9 provides an open-loop amplifier 900 or open-loop amplifier based on the open-loop amplifier 700 where the amplifier 900 but is cascaded with an open loop. The input transistor M _N1 702 and the input transistor M _N2 704 are cascoded by a pair of cascode transistors: a cascode transistor M _N3 902 or a cascode transistor M _N4 904 (eg, NMOS transistors). The gates of the cascode transistor M _N3 902 and the cascode transistor M _N4 904 be through a bias V _B3 driven. The input transistor M _P1 706 and the input transistor M _P2 708 are also cascoded by a pair of cascode transistors: a cascode transistor M _P3 906 or a cascode transistor M _P4 908 (eg PMOS transistors). The drains of the cascode transistor M _P3 906 and the cascode transistor M _P4 908 are with drains of the cascode transistor M _N3 902 or the cascode transistor M _N4 904 connected. The drains of the cascode transistor M _N3 902 and the cascode transistor M _N4 904 form (now) the difference output nodes v _outn respectively. v _outp and the drains of the cascode transistor M _P3 906 and the cascode transistor M _P4 908 also form (now) the differential output nodes v _outn or _Voutp . This embodiment may suffer from poorer linearity, but enjoys lower input capacitance and possibly higher gain.

NMOS / PMOS transistor device operating in the linear region as a load

As in the 5-9 seen, is a load resistance of 2R _L via the difference output nodes v _outn and v _outp coupled. To improve the linearity and reduce the variability of the open-loop amplifiers, an NMOS and / or PMOS resistor (eg, NMOS and / or PMOS transistor devices operating in the linear region) may be used, as in the 10-12 shown.

10 provides an open-loop amplifier 1000 or open-loop amplifier based on the open-loop amplifier 500 but the load resistance of 2R _L is with a load transistor 1002 (eg, an NMOS transistor). Connections of the load transistor 1002 , z. B. the drain and the source of the load transistor 1002 , are with the difference output nodes v _outn respectively. v _outp coupled. A gate of the load transistor 1002 gets through a tension V _G driven.

11 makes an amplifier 1100 with open loop based on the amplifier 800 with open loop, but the load resistance of 2R _L is through a load transistor 1102 (eg, a PMOS transistor or a first load transistor of a first type) and a load transistor 1104 (eg, an NMOS transistor or a second load transistor of a second type different from / complementary to the first type). The load transistor 1104 is in parallel with the load transistor 1102 connected. The drain and the source of the load transistor 1102 are with the difference output nodes v _outn respectively. v _outp coupled. The drain and the source of the load transistor 1104 are with the difference output nodes v _outn respectively. v _outP coupled. A gate of the load transistor 1102 gets through a tension V _GP driven. A gate of the load transistor 1104 gets through a tension V _GN driven.

12 makes an amplifier 1200 with open loop based on the amplifier 900 with open loop, but the load of 2R _L is through a load transistor 1202 (eg, a PMOS transistor or a first load transistor of a first type) and a load transistor 1204 (eg, an NMOS transistor or a second load transistor of a second type different from / complementary to the first type). The load transistor 1202 is in parallel with the load transistor 1204 connected. The drain and the source of the load transistor 1202 are with the difference output nodes v _outn respectively. v _outp coupled. The drain and the source of the load transistor 1204 are with the difference output nodes v _outn respectively. v _outP coupled. A gate of the load transistor 1202 gets through a tension V _Gp driven. A gate of the load transistor 1204 gets through a tension V _GN driven.

Load transistors are driven / controlled at the gate by a gate voltage that can drive the load transistors in a linear region. The load resistance is determined by the g _ds of the NMOS / PMOS transistor device in the linear region. Since the gain is due to the ratio of g _m / g _ds Given NMOS and PMOS transistor devices, this structure of using load transistors suffers less variability compared to the resistive load (resistance-based load). In addition, the variation of the load resistance with the output amplitude tends to be opposite to the variation of g _m to be with the output, which significantly improves the linearity of the amplifier. Using load transistors can result in an improvement of 8-10 dB in linearity.

An NMOS / PMOS transistor device resistance as a load may be added to the load of 2R _L be used (instead of the load of 2R _L to replace). The one or more load transistors may be connected in parallel with the resistor (eg, the resistor-based load).

13 makes an amplifier 1300 with open loop based on the amplifier 500 with open loop, the load resistance of 2R _L is in addition to the load resistance 1302 (eg, an NMOS transistor). The load resistance of 2R _L is about the difference output nodes v _outn and v _outp coupled. The drain and the source of the load transistor 1302 are with the difference output nodes v _outn respectively. v _outp coupled. The load transistor 1302 is through a gate voltage V _G driven.

14 makes an amplifier 1400 with open loop based on the amplifier 600 with open loop, the load resistance of 2R _L is about the difference output nodes v _outn and v _outp coupled and the drain and the source of the load transistor 1402 (eg, an NMOS transistor) are connected to the differential output nodes v _outn respectively. v _outp coupled. The load transistor 1402 is through a gate voltage V _G driven.

15 makes an amplifier 1500 with open loop representing the amplifier 1400 similar to open loop, but the cascode transistor M _N3 602 and the cascode transistor M _N4 604 are omitted. It is understood that a suitable combination of one or more resistors and one or more load transistors for the various open-loop amplifiers described herein with the differential output nodes v _outn and v _outp can be cross-coupled.

Open loop amplifier with source degeneration

16 make another amplifier 1600 with open loop having a push-pull circuit structure with a load resistor, wherein a source degeneration using a resistor R _d is used to improve the linearity of the amplifier. Similar to the push-pull structures described herein, the amplifier 1600 with open loop on two complementary pairs of input transistors, which form the push-pull circuit structure. A first pair of input transistors has an input transistor M _N1 1602 and an input transistor M _N2 1604 (eg, NMOS transistors). Gates of the input transistor M _N1 1602 and the input transistor M _N2 1604 received v _inp respectively. v _inn , A second pair of input transistors has an input transistor M _P1 1606 and an input transistor M _P2 1608 (eg, PMOS transistors). Gates of the input transistor M _P1 1606 and the input transistor M _P2 1608 received v _inp respectively. v _inn , The drains of the input transistor M _N1 1602 and the input transistor M _P1 1606 are interconnected and form a first differential output node v _outn , The drains of the input transistor M _N2 1604 and the input transistor M _P2 1608 are connected together to form a second differential _{output node Voutp} . In this example, the source of the input transistor M _N1 1602 and the source of the input transistor M _N2 1604 connected to respective power sources that provide a current I / 2. A transistor M _Nc 1610 (eg, an NMOS transistor) and a transistor M _Nc 1612 (eg, an NMOS transistor) may serve as the current sources. The gates of the transistor M _Nc 1610 and the transistor M _Nc 1612 can by a bias V _B1 be controlled. The source of the input transistor M _P1 1606 and the source of the input transistor M _P2 1608 are connected to respective power sources that provide a current I / 2. A transistor M _Pc 1614 (eg a PMOS transistor) and a transistor M _Pc 1616 (eg a PMOS transistor) may serve as the current sources. The gate of M _Pc 1614 and the transistor M _Pc 1616 can by a bias V _B2 be controlled. A resistance 2R _d is over the sources of the input transistor M _N1 1602 and the input transistor M _N2 1604 coupled. A resistance 2R _d is also about the sources of the input transistor M _P1 1606 and the input transistor M _P2 1608 coupled. The load via the differential output nodes v _outn and v _outp can be done using resistors ( 2R _L ) or using NMOS / PMOS devices operating in the linear region, such as 10-15 illustrated.

Common mode rejection for open-loop amplifiers

Common mode (CM) suppression may be beneficial in open-loop amplifiers, such as the open-loop amplifiers described herein. An uncontrolled CM variation can change the gain at a rate too fast for the calibration to track. A CM analog control can have slow and fast loops to ensure good CM control. Illustrative embodiments that include CM feedback control are disclosed in U.S. Patent Nos. 4,194,954 17-19 shown. One skilled in the art would recognize that the CM feedback control techniques herein can be applied to any of the open loop amplifiers.

17 makes an amplifier 1700 with open loop having a push-pull circuit structure and CM feedback control. The CM feedback control is applied to both the NMOS and PMOS sides of the push-pull circuit structure to improve ruggedness. The push-pull circuit structure includes two pairs of input transistors and respective current source devices, as previously described with other push-pull circuit structures (eg, as shown in FIG. 7 ). A gate of the transistor M _Nc 1702 , which serves as the NMOS side power source, is biased V _B1 driven and the gates of the transistors M _Pc 1704 , which serve as the PMOS-side current sources, are biased by one V _B2 driven. The CM feedback control circuit 1406 captures the output common mode and adjusts the bias voltages V _B1 and V _B2 accordingly (separately). More specifically, the CM feedback control circuit 1706 differential outputs V _outp and V _outn using buffers 1708 respectively. 1710 buffer and the output common mode voltage V _{out_CM} over the voltage divider of two resistors (in the figure with " R Form "). The feedback action of the amplifiers 1712 and 1714 can the output common mode voltage V _{out_CM} close to the ideal common mode voltage V _CM drive. In other words, the outputs of the amplifiers controlling respective current sources (eg, varying the bias voltages) would be the current sources (by varying the bias voltages V _B1 and V _B2 ) to match the output common mode voltage V _{out_CM} closer to the ideal common mode voltage V _CM bring to. The CM feedback control circuit 1706 is considered to be a closed-loop CM feedback control circuit.

18 makes an amplifier 1800 with open loop with "fast" CM feedback control. The amplifier 1800 open-loop based on a push-pull circuit structure previously through 17 was illustrated. In this example, the CM feedback control circuit has switched capacitor circuits 1802 and 1804 on that a bias V _B2 control the gates of the transistor M _Pc 1704, which serves as the PMOS side current sources. The switched capacitor circuits 1802 and 1804 can send the CM to the difference output node V _outp and V _outn capture and adjust the preload V _B2 accordingly. The capacitors C _CM are provided to create an ideal expedient CM voltage, and the bias voltage V _B2 is adjusted to drive the detected CM voltage closer to the ideal common mode voltage.

19 makes an amplifier 1900 with open loop with CM feedback with switched capacitor (similar to 18 ) and a closed-loop CM feedback (similar to 17 ). A CM feedback circuit 1902 with closed loop (similar to the CM feedback control circuit 1706 ) can be the bias voltage V _B1 Taxes. A switched capacitor circuit can be the bias voltage V _B2 control and an additional CM feedback circuit 1904 with closed loop can the bias V _B2 that is used in the switched-capacitor circuit control. In some embodiments, a closed-loop CM feedback loop may be the bias voltage V _B2 , which is used in the switched capacitor CM feedback circuit, can control or part of the current source transistors (transistors M _Pc 1704 and transistor M _Nc 1702 ) directly. The closed loop CM feedback circuit provides very tight control for a relatively low frequency, while the switched capacitor CM feedback circuit controls common mode to very high frequencies.

It should be noted that the CM control can be applied to both the NMOS and the PMOS side to take advantage of the push-pull operation in the CM feedback control loop.

Reduce CM gain with unbalanced load resistors (load resistors or load transistors operating in a linear region)

In some embodiments, the CM gain may be further reduced using unbalanced load resistors. 20 makes an amplifier 2000 with open loop with a push-pull circuit structure based on the amplifier 700 with open loop and unbalanced load resistors. The unbalanced load resistors are in the figure with 2R _L designated. The load resistors connected between supply and ground (two load resistors in series with one load resistor connected to supply and the other load resistor connected to ground) form a voltage divider between supply and ground. Providing load resistors, as shown, for each differential output node can help increase the CM gain at the differential output node v _outn and v _outp to reduce. A node in series between the two load resistors is connected to a differential output node.

Alternatively, the load resistances may be with the CM voltage V _CM be connected (two load resistors in series, with a load resistor with a CM voltage V _CM is connected and the other load resistance also with the CM voltage V _CM connected is).

In the example shown form a load resistor 2002 and a load resistor 2004 two series resistors, the load resistance 2002 connected to supply and the load resistance 2004 connected to ground. A node between the load resistor 2002 and the load resistance 2004 is with the difference output node v _outn connected. A load resistor 2006 and a load resistor 2008 form two series resistors, the load resistance 2006 connected to supply and the load resistance 2008 connected to ground. A node between the load resistor 2006 and the load resistance 2008 is with the difference output node v _outp connected.

21 makes an amplifier 2100 with open loop having an inverter with a resistive load. The load can be differential or unbalanced to reduce CM gain. As shown, the amplifier points 2100 with open loop similar load resistances as in 20 seen. In the example shown form a load resistor 2102 and a load resistor 2104 two series resistors, the load resistance 2102 connected to supply and the load resistance 2104 connected to ground. A node between the load resistor 2102 and the load resistance 2104 is with the difference output node v _outn connected. A load resistor 2106 and a load resistor 2108 form two series resistors, the load resistance 2106 associated with care and the load resistance 2108 connected to ground. A node between the load resistor 2106 and the load resistance 2108 is with the difference output node v _outp connected.

In addition, NMOS / PMOS transistor devices operating in the linear region may be used instead of or in addition to the single ended resistors to improve performance as previously mentioned. 22 makes an amplifier 2000 with open loop with a push-pull circuit structure based on the amplifier 700 with open loop and NMOS / PMOS transistor devices as the ohmic loads. In the illustrated example, the drain is a load transistor 2206 (eg PMOS transistor) to the drain of a load transistor 2202 (eg, NMOS transistor). The drains of the load transistors 2206 and 2202 are with the difference output node v _outn connected. The sources of the load transistors 2206 and 2202 are with a CM voltage V _CM connected. A gate of the load transistor 2206 is by a bias V _GP driven. A gate of the load transistor 2202 is by a bias V _GN driven. The drain of a load transistor 2208 (eg PMOS transistor) is connected to the drain of a load transistor 2204 (eg, NMOS transistor). The drains of the load transistors 2208 and 2204 are with the difference output node v _outp connected. The sources of the load transistors 2208 and 2204 are with a CM voltage V _CM connected. A gate of the load transistor 2208 is by a bias V _GP driven. A gate of the load transistor 2204 is by a bias V _GN driven. In the 22 NMOS / PMOS devices can also be used for the amplifier of 20 be used.

It will be understood that the NMOS / PMOS devices, such as load transistors described herein, may be used in various embodiments illustrated and illustrated by the disclosure instead of or in addition to the load resistors.

It will also be understood that the various examples of unbalanced load resistors may be added to various open-loop amplifiers having the load resistances across the differential output nodes.

It will also be understood that the various examples of unbalanced load resistors may be applied to various types of open-loop amplifiers illustrated and illustrated by the disclosure.

Boost boost for open-loop amplifiers

23 provides an open-loop amplifier 2300 or open loop amplifier, where boost boosting is used to control the effective g _m of the amplifier without increasing the input capacitance. The amplifier 2300 with open loop is similar to the amplifier 500 with open loop. A boost booster circuit 2302 can with the difference output node v _outn and v _outP be coupled. Load resistors are used in a similar way as in the 20 and 21 at the differential output node v _outn and v _outp provided.

24 makes an amplifier 2400 with open loop, where a boost boosting is used to control the effective g _m of the amplifier using a positive feedback without increasing the input capacitance. The amplifier 2400 with open loop is similar to the amplifier 2300 with open loop. The boost booster circuit has a cross-coupled transistor M _N3 2402 and a cross-coupled transistor M _N4 2404 (eg NMOS transistors) on. The gate of the cross-coupled transistor M _N3 2402 is with the difference output node v _outp coupled and the gate of the cross-coupled transistor M _N4 2404 is with the difference output node v _outn coupled. The drains of the cross-coupled transistor M _N3 2402 and the cross-coupled transistor M _N4 2404 are with the difference output nodes v _outn respectively. v _outp coupled. The sources of the cross-coupled transistor M _N3 2402 and the cross-coupled transistor M _N4 2404 are connected to the drain of the transistor M _Nc 506 , which serves as a power source, coupled. The widths and lengths of the cross-coupled transistor M _N4 3402 and the cross-coupled transistor M _N4 2404 are much smaller than those of the input transistor M _N1 502 and the input transistor M _N2 504 ,

25 illustrates an exemplary boost booster circuit 2500 According to some embodiments of the disclosure. The boost booster circuit 2500 can with the difference output node v _outn and v _outp be coupled as shown. The boost booster circuit 2500 has a cross-coupled transistor M _N3 2502 and a cross-coupled transistor M _N4 2504 (the cross-coupled transistor M _N3 2102 and the cross-coupled transistor M _N4 2404 from 24 can resemble). The gate of the cross-coupled transistor M _N3 2502 is with the difference output node v _outp coupled and the gate of the cross-coupled transistor M _N4 2504 is with the difference output node v _outn coupled. The drains of the cross-coupled transistor M _N3 2502 and the cross-coupled transistor M _N4 2504 are with the difference output nodes v _outn respectively. v _outp coupled. The sources of the cross-coupled transistor M _N3 2502 and the cross-coupled transistor M _N4 2504 are with the drains of the transistor M _NB1 2506 and the transistor M _NB2 Coupled 2508. The gates of the transistor M _NB1 2506 and the transistor M _NB2 2508 be through a bias V _Bgn driven. The boost booster circuit 2500 can be used for CM control.

26 makes an amplifier 2600 with an open loop in which a boost boosting is used. The amplifier 2600 with open loop based on the amplifier 1100 with open loop of 11 (having a push-pull circuit structure). Load resistors are used in a similar way as in the 20 and 21 at the differential output node v _outn and v _outp provided. The boost booster circuit 2602 can with the difference output node v _outn and v _outP and can be implemented based on the gain boost circuits described herein.

27 makes an amplifier 2700 with an open loop with an illustrative implementation of the in 26 seen boost booster circuit 2602 The boost booster circuit has a cross-coupled transistor M _N3 2702 and a cross-coupled transistor M _N4 2704 (eg, NMOS transistors). The gate of the cross-coupled transistor M _N3 2702 is with the difference output node v _outp coupled and the gate of the cross-coupled transistor M _N4 2704 is with the difference output node v _outn coupled. The drains of the cross-coupled transistor M _N3 2702 and the cross-coupled transistor M _N4 2704 are with the difference output nodes v _outn respectively. v _outp coupled. The sources of the cross-coupled transistor M _N3 2702 and the cross-coupled transistor M _N4 2704 are connected to the drain of the transistor M _Nc 710, which serves as a power source. The boost booster circuit further includes a cross-coupled transistor M _P3 2706 and a cross-coupled transistor M _P4 2708 (eg, PMOS transistors). The gate of the cross-coupled transistor M _P3 2706 is with the difference output node v _outp coupled and the gate of the cross-coupled transistor M _P4 2708 is with the difference output node v _outn coupled. The drains of the cross-coupled transistor M _P3 2706 and the cross-coupled transistor M _P4 2708 are with the difference output nodes v _outn respectively. v _outp coupled. The sources of the cross-coupled transistor M _P3 2706 and the cross-coupled transistor M _P4 2708 are connected to the drain of the transistor M _Pc 712 , which serves as a power source, coupled. The widths and lengths of the cross-coupled transistor M _N4 2704 , the cross-coupled transistor M _N4 2404 , the cross-coupled transistor M _P3 2706 and the cross-coupled transistor M _P4 2708 are much smaller than those of the input transistor M _N1 702 , the input transistor M _N2 704 , the input transistor M _P1 706 and the input transistor M _P2 708 ,

Variations on the open-loop amplifier

28 represents an exemplary amplifier 2800 with open loop showing some modifications to the amplifier 1500 with open loop of 15 according to some embodiments of the disclosure. One modification involves source degeneration, e.g. B. a part of the transistor M _Nc 506 acting as a power source in 15 serves, in two transistors M _Nc 2802 and M _Nc 2804 (each providing a current I / 2). The transistors M _Nc 2802 and M _Nc 2804 may be NMOS transistors. In this example, the sources are the input transistors M _N1 502 and M _N2 504 with respective drains of M _Nc 2802 and M _Nc 2804 connected. The gates of the transistors M _Nc 2802 and M _Nc 2804 can by a bias V _B1 be controlled. In a similar way as 16 is a resistance 2R _d (to source degeneration) via the sources of the input transistor M _N1 502 and the input transistor M _N2 504 coupled. Another modification involves buffering the differential inputs V _inp and V _inn with source followers 2806 respectively. 2808 before the buffered differential inputs go to the gates of the input transistors M _N1 502 and M _N2 504 to be provided.

29 represents an exemplary amplifier 2900 with open loop showing some modifications to the amplifier 2800 with open loop of 28 according to some embodiments of the disclosure. The source follower 2806 and 2808 from 28 be through push-pull source follower 2906 respectively. 2908 for buffering the differential inputs v _inp and v _inn replaced before the buffered differential inputs to the gates of the input transistors M _N1 502 and M _N2 504 to be provided.

30 represents an exemplary amplifier 3000 with open loop showing some modifications to the amplifier 2900 with open loop of 29 according to some embodiments of the disclosure. Cross coupled transistors 3002 and 3004 (eg NMOS transistors) are added. The gate of the cross-coupled transistor 3002 is connected to the gate of the input transistor M _N1 502 coupled. The drain of the cross-coupled transistor 3002 is with the source of the input transistor M _N2 504 coupled. The gate of the cross-coupled transistor 3004 is connected to the gate of the input transistor M _N2 504 coupled. The drain of the cross-coupled transistor 3004 is with the source of the input transistor M _N1 502 coupled.

Analog tracking circuits for driving a load transistor

In some embodiments, one or more NMOS / PMOS transistor devices operating in the linear region may be provided across the differential output nodes of a main open loop amplifier circuit, as seen in the examples incorporated in FIGS 11-15 and 28-30 are illustrated. An analog tracking circuit may be provided to adjust the gate voltage, e.g. B. V _G to generate to drive the load transistor. An NMOS / PMOS transistor device as a load with analog tracking control for the gate voltages of the NMOS / PMOS transistor device V _G has advantages for distortion cancellation and can be applied to all open-loop amplifier circuits described herein. Analog tracking circuits capable of tracking variations can linearize the open-loop amplifier and ensure good performance. Analog tracking circuits are particularly useful for linearizing and improving the performance of open-loop amplifiers (e.g., even open-loop amplifiers used as variable-gain amplifiers) that may not have available calibrations to linearize the open-loop amplifiers. Loop amplifier (or not).

Ideally, the gate voltage V _G a sum of the gate-source voltage of a transistor device V _GS and the ideal CM voltage V _CM and such a gate voltage would ensure that the NMOS / PMOS transistor operating as a load operates in the linear region. The ideal gate-source voltage of a transistor device V _GS however, to operate the load transistor in the linear region may vary with one or more of the following: process, temperature and voltage, and other factors. Factors may include: voltage across transistors in the main open loop amplifier circuit, transconductance / resistance of transistors in the main open loop amplifier circuit, gain settings of the main open loop amplifier circuit, and bias current settings in the main open loop amplifier circuit. An analog tracking circuit can ensure that the gate-source voltage of a transistor device V _GS for operating the load transistor in the linear region and the resulting gate voltage gate voltage V _G be controlled accordingly.

31 provides an exemplary analog tracking circuit 3100 for generating a gate voltage V _G for driving a gate of a load transistor, according to some embodiments of the disclosure. The analog tracking circuit 3100 may be used to perform analog tracking of the temperature and adjust the gate voltage to drive an NMOS / PMOS load transistor device accordingly. The analog tracking circuit 3100 has a first power source 3102 , a second power source 3104 , a first operational amplifier (Opamp) 3108 , a second opamp 3110 and a resistance R _g 3106 on. The first power source 3102 has a fixed current I _firmly that does not change with temperature. The second power source 3104 has a variable current I _PTAT which is proportional to an absolute temperature of the circuit. The first opamp 3108 is in a negative feedback configuration where the first opamp 3108 receives a (ideal) CM voltage at the non-inverting input and the output of the first opamp 3108 (as a node 3120 designated) at the inverting input receives. As a result, the voltage follows at the output of the first opamp 3108 at the node 3120 the voltage at the non-inverting input V _CM , The tension at the knot 3122 is a sum of the voltage across the resistor R _g 3106 (when V _GS referred to) and the voltage of the node 3120 (the V _CM is). The voltage across the resistor R _g 3106 (when V _GS ) is based on the current through the first current source 3102 and the second power source 3104 , As a result, the voltage across the resistor R _g 3106 (when V _GS due to the fact that the second power source 3104 a variable current I _PTAT has, the temperature track. The second opamp 3110 is also in a negative feedback configuration where the second opamp 3110 a tension at the node 3122 at the non-inverting input and receives the output of the second opamp 3110 receives at the inverting input. As a result, the voltage follows at the output of the second opamp 3110 the voltage at the non-inverting input, ie V _GS + V _CM , and can be considered a gate voltage V _G for driving an NMOS / PMOS transistor serving as a load.

In some cases, the analog tracking circuit 3100 modified to perform track changes in the bias current setting in the main open loop amplifier circuit. The bias current setting is used when changing the gain of the main loop amplifier by modifying the amount of current flowing through the one or more current sources in the main loop amplifier. The modification may include changing the bias of the analog tracking circuit 3100 based on each setting of the bias current in the main open loop amplifier circuit. The settings for the current I _firmly and / or the electricity I _PTAT For example, they may be adjusted based on the bias current setting in the main open loop amplifier circuit. In another example, the analog tracking circuitry may include an additional variable current source coupled to a node 3122 is coupled and may vary based on the adjustment of the bias current in the main open loop amplifier circuit. As a result, the current through the resistor R _g 3106 , and thus the voltage across the resistor V _GS , Track gain changes in the main open loop amplifier circuit.

32 provides an exemplary analog tracking circuit 3200 for generating a gate voltage V _G for driving a gate of a load transistor of a main open-loop amplifier, in accordance with some embodiments of the disclosure. The analog tracking circuit 3200 can track various changes in the main loop amplifier, including changes in the bias current settings (ie, gain) in the main open loop amplifier circuit. The analog tracking circuit 3200 has a first opamp 3202 and a second opamp 3204 on. The first opamp 3202 is used to generate a voltage V _GS used. The first opamp 3202 is operated to control the voltage at the inverting input and at the non-inverting input of the first opamp 3202 to equalize and the optimal gate-source voltage V _GS derive. A load current flows at the non-inverting input I _L (eg, a maximum current flowing through the load of the main open-loop amplifier) through a first replica load circuit including a transistor M _NL 3206 and a resistance 3208 (provided in parallel). The first replica load circuit may replicate a load transistor and a load resistor of the main open-loop amplifier (eg, as in FIGS 13-15 and 28-30 seen). The output of the first Opamp 3202 V _GS controls the gate of the transistor M _NL 3206 the first replica circuit. The circuit at the non-inverting input tracks a voltage across the load devices (eg, voltage / transconductance / resistance across the load devices). At the inverting input, a load current flows I _L through a second replica circuit, which is a transistor M _{N1_sc} 3218 and a resistance 3216 (provided in parallel). The transistor in the second replica circuit replicates an input transistor of the main open-loop amplifier (eg, transistors shown in the figures) M _N1 and may be a scaled version of the input transistor. The circuit at the inverting input thus tracks a voltage across an input transistor. The circuit at the inverting input also tracks a bias current I _B (a bias current setting of the main open-loop amplifier) and a temperature / heat variation by the resistor 2R ₀ 3220 , The circuit at the inverting input thus tracks a voltage across an input transistor (eg, voltage / transconductance / resistance across the input resistor), a bias current setting of the main open-loop amplifier, and a temperature / heat variation. Through the feedback mechanism of the first Opamp 3202 (ie using the output of the first opamp 3202 to the gate of the transistor M _NL 3206 to drive) can the first Opamp 3202 an optimal gate-source voltage V _GS for operating the load transistor in the main open loop amplifier circuit. The second opamp 3204 is in a negative feedback configuration and a summation point of the voltages V _GS and V _CM is connected to the non-inverting input of the opamp. The voltage at the output of the second opamp 3204 follows the non-inverting input, ie V _GS + V _CM , and the second opamp 3204 operates as a non-inverting summing amplifier (or voltage adder) to produce an output that is a positive sum of the voltages V _GS and V _CM represents (or is proportional to). The voltage at the output of the second opamp 3110 can be considered a gate voltage V _G for driving an NMOS / PMOS transistor serving as a load, and may be used as a gate voltage V _G for driving an NMOS / PMOS transistor serving as a load.

Dither injection and gain calibration

The ability to calibrate the nonlinearity of the open loop amplifier structure, if necessary, may be important. There are several methods for calibrating the nonlinearity, some of which involve injecting a calibration dither and using the correlations and / or histograms / counts based on open intervals that define certain points of inspection (thresholds or values that define open intervals of a signal). are assigned to estimate the nonlinearity of the transfer characteristic. In these algorithms, the input signal, which is composed of the ADC input signal plus an internally generated (large) linearization dither signal, helps to traverse the transfer characteristics of the amplifier. The calibration dither becomes the detected nonlinearity which causes the response to differ if the dither is positive and the dither is negative.

33 FIG. 10 illustrates a block diagram of a pipeline ADC with dither signals injected into the signal paths, in accordance with some embodiments of the disclosure. FIG. The dither signals can be used for interstage gain and nonlinear calibration. The pipeline ADC 3300 based on the pipeline ADC 100 but with a few modifications. A (large) linearization dither signal ("linearization dither-1") can be passed through a summing node 3302 in the analog input V _in be injected. The linearization dither signal, e.g. B. the one at the entrance to the 1 The calibration may desensitize to a dependence on the input signal (making the calibrations independent of the input signal). Optionally, there may be an open-loop amplifier acting as the sample buffer or amplifier for the analog input V _in serves. A (large) linearization dither signal ("linearization dither-2") may be passed through a summing node 3304 in the reinforced rest V _o1 be injected. At the entrance of the stage 2 The injected linearization dither signal can be used to measure the nonlinear calibration of the 1 desensitize to the non-ideal states / nonlinearity of the backend steps. The linearization dither signals can be used in both the MDAC and Flash ADC stages 1 and 2 be injected. A calibration dither signal ("Kal-Dither-1") may be passed through a summing node 108 be injected to a nonlinearity of the amplifier 110 to detect or detect. A calibration dither signal ("Kal Dither-2") may be passed through a summing node 118 be injected to a nonlinearity of the amplifier 120 to detect or detect. The calibration dither signals ("Kal-Dither-1" and "Kal-Dither-2") can only be injected into the MDAC and can be used for the calibration of a gain error and a non-linearity of the respective stages (step). 1 and level 2 ) be used.

34 FIG. 12 illustrates a calibration dither injection for a non-linear calibration of an amplifier, in accordance with some embodiments of the disclosure. FIG. Although only a simplified balanced circuit is illustrated, it will be understood that the circuit can be implemented in a differential manner. An MDAC circuit structure 3400 (similar to the MDAC circuit structure 300 from 3 ) has an amplifier 3402 with an open loop (eg, a suitable open-loop amplifier as described herein) and a switched capacitor circuit 3404 which can perform sampling and DAC operations. The switched capacitor circuit 3404 has a number of capacitors C, which are used as sampling capacitors and as the DAC capacitors of the MDAC circuit structure 3400 should serve. In this exemplary switched capacitor circuit 3404 There are 8 capacitors. The number of capacitors depends on how many bits the ADC of the stage generates as the output code D (the ADC of the stage is not shown in the figure). A plate (lower plate) of each capacitor is connected to a common node. The common node is at the inverting input of the amplifier 3402 with open loop. The common node serves as the summing node 3410 the MDAC circuit structure 3400 , During a sampling phase (designated by φ1), the switched capacitor circuit samples 3404 the entrance V _in on the capacitors C from. During a hold phase (denoted by φ2), the switched capacitor circuit connects 3404 selectively (upper) plates of the capacitors C of the switched capacitor circuit 3404 with either the positive voltage reference V _Ref or - V _Ref based on an output code D from an ADC of the stage. As a result, a residual signal is generated and the residual signal is at the summing node 3410 presents. During the hold phase, the amplifier performs 3402 (with open loop) amplifies and creates a boosted rest V _out ,

The MDAC circuit structure 3400 further includes a switched capacitor circuit 3406 for calibration dither injection. More specifically, the switched capacitor circuit injects 3406 a charge into the switched capacitor circuit 3404 based on the calibration dither voltage V _{d_cal} , As a result, a calibration dither signal is generated in the MDAC circuit structure 3400 added. The switched capacitor circuit 3406 has a dither capacitor C _{d_cal} on. A first plate of the dither capacitor C _{d_cal} is with the summation node 3410 the MDAC circuit structure 3400 connected. During a sampling phase is a second plate of the dither capacitor C _{d_cal} connected to ground. During a hold phase, the second plate is the dither capacitor C _{d_cal} with the calibration dither voltage V _{d_cal} connected to an amount of charge in the summation node 3410 to inject that represents the calibration dither. Accordingly amplifies the amplifier 3402 (with open loop) a signal at the summing node 3410 including the residual signal and the calibration dither. The calibration dither can be used to calibrate the amplifier 3402 (with open loop) can be used.

35 illustrates a linearization dither injection for desensitizing a calibration against e.g. , The input signal distribution, in accordance with some embodiments of the disclosure. Although only a simplified symmetric circuit is shown, it will be understood that the circuit is based on a differential way can be implemented. A circuit 3500 has an MDAC circuit structure (similar to the MDAC circuit structure 3400 from 34 ) and a sub ADC (Flash ADC) 3504 of the stage. The MDAC circuit structure has an amplifier 3402 with an open loop (eg, a suitable open-loop amplifier as described herein) and a switched capacitor circuit 3404 which can perform sampling and DAC operations. The MDAC circuit structure further includes a switched capacitor circuit 3502 for linearization dither injection. More specifically, the switched capacitor circuit 3502 a charge into the switched capacitor circuit 3404 based on the linearization dither voltage V _{d_dither} inject. The switched capacitor circuit 3502 has a dither capacitor C _{d_dither} on. A first plate of the dither capacitor C _{d_dither} is with the summation node 3410 connected to the MDAC circuit structure. During a sampling phase is a second plate of the dither capacitor C _{d_dither} connected to ground. During a hold phase, the second plate is the dither capacitor C _{d_dither} with the calibration dither voltage V _{d_dither} connected to an amount of charge in the summation node 3410 to inject that represents the linearization dither. Accordingly amplifies the amplifier 3402 (with open loop) a signal at the summing node 3410 including the residual signal and the linearization dither. Furthermore, a linearization dither signal V _{d_dither_flash} through a summing node 3506 located at the entrance of the sub-ADC 3504 located in the analog input V _in be injected. This means that the output code D from the sub-ADC 3504 the stage the analog input V _in and that at the summing node 3506 represents injected linearization dither. In some cases, the linearization dither may be digital at the output of the sub-ADC 3504 be injected. V _{d_dither_flash} can equal V _{d_dither} × C _{d_dither} / C. As a result, the linearization dither signals can be injected into both the MDAC and the flash ADC. The linearization signal can be used to make the calibrations independent of the input signal and / or the input signal distribution.

36 FIG. 12 illustrates an injection of both calibration and linearization dither injection, in accordance with some embodiments of the disclosure. FIG. A circuit 3600 has an MDAC circuit structure (similar to the MDAC circuit structure 3400 from 34 ) and a sub ADC (Flash ADC) 3602 on. The MDAC circuit structure has an amplifier 3402 with an open loop (eg, a suitable open-loop amplifier as described herein) and a switched capacitor circuit 3404 which can perform sampling and DAC operations. The MDAC circuit structure further includes a switched capacitor circuit 3604 for calibration dither injection. More specifically, the switched capacitor circuit injects 3604 a charge into the switched capacitor circuit 3404 based on the calibration dither voltage V _d , As a result, a calibration dither signal is added in the MDAC circuit structure. The switched capacitor circuit 3604 is similar to the switched capacitor circuit 3406 from 34 , The MDAC circuit structure further includes a switched capacitor circuit 3606 for linearization dither injection. Both the switched capacitor circuit 3604 as well as the switched capacitor circuit 3606 are with the summation node 3410 connected. More specifically, the switched capacitor circuit 3606 a charge into the switched capacitor circuit 3404 based on the linearization dither voltage V _{d_lg} inject. Furthermore, a linearization dither signal V _{d_lg_flash} through a summing node 3608 located at the entrance of the sub-ADC 3602 located in the analog input V _in be injected. V _{d_lg_flash} can be equal to V _{d_lg} × C _{d_lg} / C. As a result, the linearization dither signals can be injected into both the MDAC and the flash ADC. The switched capacitor circuit 3606 is similar to the switched capacitor circuit 3502 , The summation node 3608 and the sub-ADC 3602 are similar to the summation node 3506 and the sub-ADC 3504 from 35 ,

37 illustrates an injection of a calibration dither injection into an amplifier 3700 with open loop, in accordance with some embodiments of the disclosure. In this example, the calibration dither signal (e.g., 1-bit dither signal) may be injected into the open-loop amplifier, e.g. To the differential output node v _outn and v _outp and the calibration dither signal can be used to calibrate the open-loop amplifier. Nonlinearity may be dominant at the output of the open loop amplifier, and such a calibration dither injection at the output of the open loop amplifier may detect the nonlinearities (eg, compression). The amplifier 3700 with open loop on the amplifier 2800 open-loop based is illustrated, but it is understood that other open-loop amplifiers described herein have such dither at the differential output node v _outn and v _outp on the through 37 illustrated manner can be injected. The dither injection circuit has a differential pair of dither transistors M _Nd1 3702 and M _Nd2 3704 (eg, NMOS transistors) and a current source transistor M _Ndc 3706 (eg, NMOS transistor). The current source transistor M _Ndc 3706 is biased, a current I _d for the dither injection circuit. The drains of the dither transistors M _Nd1 3702 and M _Nd2 3704 are with the difference output nodes v _outn respectively. v _outp coupled. The differential pair of dither transistors M _Nd1 3702 and M _Nd2 3704 is in a common source configuration and its sources are connected to the drain of the current source transistor M _Ndc 3706 coupled. The gates of the dither transistors M _Nd1 3702 and M _Nd2 3704 are determined by the 1-bit dither signal, e.g. B. differential dither signals V _dithp respectively. V _dithn , controlled / controlled. A lot of electricity I _d gets into the difference output node v _outn and v _outp according to the value of the 1-bit dither signal (differential) injected / steered.

The calibration dither injection based on the in 37 The illustrated example may be particularly advantageous for scenarios in which the open-loop amplifier is not associated with a switched-capacitor circuit (eg, not within a track-and-hold circuit with a switched capacitor circuit) used within an MDAC) but is used as an independent open loop amplifier or variable gain amplifier. Although a calibration dither injection into a switched capacitor circuit can be achieved (as discussed in various examples herein), however, a calibration dither injection is for an open loop amplifier operating as a continuous time circuit (without a associated with it switched capacitor circuit), not insignificant. This in 37 The illustrated example, in effect, allows a 1-bit calibration dither to be injected into an open-loop amplifier operating as a continuous-time circuit so that calibration can be performed to tune the open-loop amplifier in the analog domain (eg, to adjust currents and / or resistances), or so that the calibration can be performed to digitally correct digital output data generated downstream of the open-loop amplifier. For example, an error obtained from a calibration of the open-loop amplifier (eg, gain error) using the 1-bit calibration dither may be used to tune a load transistor in the open-loop amplifier (e. B. the gate voltage seen in the figure V _G to change).

A suitable calibration algorithm may be used to calibrate the open-loop amplifier and / or an analog circuit with non-ideal conditions. A few exemplary MDAC circuit structures and open-loop amplifiers described herein may accommodate dither injection to achieve the required performance, regardless of the specific algorithm used. The following describes an example of a calibration algorithm that may be used to extract non-ideal states of the amplifier or other non-ideal analog circuit of interest.

und $$\begin{array}{c}\epsilon \left(-V_{insp}\right)=Cumsum{p}_{-V_{insp}}\left(V_{ou{t}_{cal}}\left[n\right]-V_d\left[n\right]\right)|{}_{Dither=V_d}\\ -Cumsum{p}_{-V_{insp}}\left(V_{ou{t}_{cal}}\left[n\right]+V_d\left[n\right]\right)|{}_{Dither=-V_d}\end{array}$$

In some embodiments, a histogram scheme may be used as part of the calibration algorithm to count samples of an output signal based on open intervals set by symmetric inspection points to correct for second and third harmonics (eg, HD2 and HD3). For the histogram scheme, the error at the symmetrical inspection points can be defined as follows: $$\begin{array}{c}\epsilon \left(V_{insp}\right)=Cumsum{p}_{V_{insp}}\left(V_{Ou{t}_{cal}}\left[n\right]-V_d\left[n\right]\right)|{}_{DitHer=V_d}\\ -Cumsum{p}_{V_{insp}}\left(V_{Ou{t}_{cal}}\left[n\right]+V_d\left[n\right]\right)|{}_{DitHer=-V_d}\end{array}$$

and $$\begin{array}{c}\epsilon \left(-V_{insp}\right)=Cumsum{p}_{-V_{insp}}\left(V_{Ou{t}_{cal}}\left[n\right]-V_d\left[n\right]\right)|{}_{DitHer=V_d}\\ -Cumsum{p}_{-V_{insp}}\left(V_{Ou{t}_{cal}}\left[n\right]+V_d\left[n\right]\right)|{}_{DitHer=-V_d}\end{array}$$

V _insp is the inspection point for HD2 and HD3 estimation, V _d is the injected calibration dither signal and V _{out cal} is the output (residual) voltage after calibration. The term Cumsum _x (y) is defined as the cumulative histogram (ie, count) of digital codes of a digital signal y less than or equal to x. Cumsump _x (y) is defined as the cumulative histogram (ie count) of digital codes of a digital signal y greater than or equal to x. Accordingly, the error at the positive inspection point ε ( V _insp ) (a) the count of the output voltage after calibration and removal of the dither signal V _d [n] is greater than or equal to a positive inspection point when the dither is positive (eg, cump _{V insp} (V _{out cal} [n] - V _d [n]) | _{Dither = V d} ) and (b) the count of the output voltage after the calibration and removal of the dither signal V _d [n] is greater than or equal to a positive inspection point when the dither is negative (eg, cump _{V insp} (V _{out cal} [n] + V _d [n]) | _{Dither = -V d} ). More precisely, the error at the positive inspection point subtracts ε ( V _insp ) (b) of (a), compares z. B. the two counts. Furthermore, the examined Error at the negative inspection point ε (- V _insp ) (c) the count of the output voltage after calibration and removal of the dither signal V _d [n] less than or equal to a negative inspection point if the dither is positive (eg cumsumn _{-V insp} (V _{out cal} [n] - V _d [n]) | _{Dither = V d} ) and (d) the count of the output voltage after calibration and removal of the dither signal V _d [n] is less than or equal to a negative inspection point when the dither is negative (eg, cumsumn _{-V insp} (V _{out cal} [n] + V _d [n]) | _{Dither = -V d} ). Specifically, the error at the negative inspection point subtracts ε (- V _insp ) (d) of (c), compares z. B. the two counts.

und $${\epsilon }_{HD3}=\epsilon \left(V_{insp}\right)-\epsilon \left(-V_{insp}\right)$$

The error terms associated with the second order and third order harmonics (eg, ε _HD2 and ε _HD3, respectively) can be defined as follows: $${\mathrm{<figure-callout\; id="2"\; label="\epsilon \; H\; D"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">\epsilon \; </figure-callout>}}_{HD}=\epsilon \left(V_{insp}\right)+\epsilon \left(-V_{insp}\right)$$

and $${\epsilon }_{HD3}=\epsilon \left(V_{insp}\right)-\epsilon \left(-V_{insp}\right)$$

The above error terms reveal the shape of the second order harmonic (which has a straight symmetry) and the third order harmonic (which has an odd symmetry). ε _HD2 sums the error at the positive inspection point and the error at the negative inspection point. ε _HD3 subtracts the error at the negative inspection point from the error at the positive inspection point.

und $${\propto }_3\left(n+1\right)={\propto }_3\left(n\right)-{\mu }_3\times {\epsilon }_{HD3}$$

Once the error terms are defined, Least Means Square (LMS) equations in convergence loops can be used to update the calibration coefficients of the second and third order nonlinearities (eg, α ₂ (n) and α ₃ (n)). The convergence loops can update the calibration coefficients to obtain the error terms (eg, ε _HD2 and ε _HD3 ) to zero. The LMS equations can be given by: $${\alpha }_2\left(n+1\right)={\alpha }_2\left(n\right)-{\mathrm{<figure-callout\; id="2"\; label="\mu "\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">\mu </figure-callout>}}_2\times {\mathrm{<figure-callout\; id="2"\; label="\epsilon \; H\; D"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">\epsilon \; </figure-callout>}}_{HD}$$

and $${\alpha }_3\left(n+1\right)={\alpha }_3\left(n\right)-{\mu }_3\times {\epsilon }_{HD3}$$

μ ₂ and μ ₃ are the LMS step sizes for the second and third order convergence, respectively. For HD2 and HD3 correction, the calibration coefficients updated by the LMS equations may be applied in a correction equation as follows: $$v_{Ou{t}_{cal}}=v_{Out}+{\alpha }_2{v}_{\mathrm{<figure-callout\; id="2"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut}^2+2{\mathrm{<figure-callout\; id="2"\; label="\alpha "\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">\alpha </figure-callout>}}_2^2{v}_{Out}^3+3{\alpha }_3^2{v}_{\mathrm{<figure-callout\; id="5"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0134.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut}^5$$

The convergence loop has a closed-loop operation, which means that the calibrated output v _{out cal} back into equations (6) and (7). The high order terms in equation (12) can be used to correct for the effects of applying our correction at the output (instead of the input since the calibration scheme has no access to the input). Applying the correction at the output (which is non-linear) may cause the correction to generate even higher order terms that may need to be canceled.

Such a calibration algorithm or other suitable calibration algorithms may inspect the transfer characteristic at certain inspection points (or thresholds) while the calibration dither is used to detect the non-linearity, since the response of a non-linear amplifier is expected to be a function of value or of polarity of the calibration dither (eg, when dither is added to the input as compared to when subtracted).

When the calibration algorithm is used in MDAC and pipeline structures, such as 33 some measures may need to be taken to ensure that the non-linear calibration algorithm works effectively and in the presence of backend non-linear calibration algorithms. Ideal states converged correctly to the desired nonlinear coefficients. That is, the digital representations of the input, linearization dither, and calibration dither signals are not perfect, and therefore, they can significantly degrade the calibration accuracy. This takes place independently of the specific calibration algorithm used. These measures may be needed to ensure that the non-linearity estimation of a front-end (eg, Stage-1) is not negatively impacted by the non-ideal states of the back-end stages. If no additional measures are taken, these backend non-ideal states would result in false estimates, input dependent convergence, and / or even failure of the algorithms. Similar problems are encountered when IGE is calibrated. However, the measures taken for the IGE calibration are not necessarily effective for nonlinear calibration, which may require other measures.

For example, the "linearization dither-1" injected in both the MDAC and the flash ADC in stage-1 may be effective in linearizing the backend for IGE calibration and partially desensitizing to the backend non-ideal conditions as long as it has a reasonable number of levels. However, the same dither is treated as an input signal by the non-linear calibration algorithms and is therefore completely ineffective in the "linearization" of the backend for nonlinear calibration. This happens regardless of how many bits / level it has or whether it has a binary or odd number of levels. It is effective in desensitizing the nonlinear calibration to the sinusoidal input signal characteristics, but not to the non-ideal states of the backend. This is due to the nature of the nonlinear calibration algorithms and their dependency on measuring the transfer characteristic of the amplifier at different signal levels, where the "signal" has both the input and the dither.

Instead, an additional dither (eg, "Linearization Dither-2") may be injected into the following stage (s), as by 33 illustrated. This linearization dither signal may be injected after the amplifier to be calibrated in a manner that does not significantly change its output. For example, during the stage-2 hold phase, the linearization dither signal may be injected into both the stage 2 MDAC and flash ADCs to effectively dither the stage 2 non-linearities for stage 1 nonlinear calibration and to linearize. In addition, this linearization dither signal in the digital domain is subtracted from the stage 1 residue prior to stage-1 nonlinear calibration. Similarly, if a level 2 non-linearity is calibrated, a "linearization dither-3" is injected into the input of level-3, and so on.

• - Injizieren eines „Linearisierungs-Dithers“ in der folgenden Stufe in sowohl den MDAC als auch Flash. Die Dither-Amplitude ist vorzugsweise groß genug, um einen vollen Teilbereich der Stufe-2 abzudecken. Das Dither wird digital vom Signal subtrahiert, das für die nichtlineare Kalibration verwendet wird. Dies kann die effektivste Technik sein.
• - Randomisieren (oder Dithern) der Inspektionspunkte (Schwellenwerte für offene Intervalle), die für die nichtlineare Kalibration verwendet werden. Der Bereich der Inspektionspunktwerte ist vorzugsweise mindestens gleich einem Stufe-2-Teilbereich und deckt weiter vorzugsweise den doppelten Stufe-2-Teilbereich ab. Diese Technik ist effektiv, aber nicht so effektiv wie das Anwenden des Stufe-2-Linearisierungs-Dithers.
• - Verwenden mehrerer Inspektionspunkte (Schwellenwerte für offene Intervalle) für die nichtlineare Kalibration und Mittelwertbildung der Ergebnisse. Der Bereich der Inspektionspunkte ist vorzugsweise mindestens gleich dem Stufe-2-Teilbereich und weiter vorzugsweise zweimal der Stufe-2-Teilbereich.
• - Verwenden mehrerer Dither-Pegel im Kalibrations-Dither der gegebenen Stufe. Dies hilft bei diesem Problem, solange die Korrelation/das Histogramm an den mehreren Pegeln des Dithers durchgeführt wird. Dies mittelt die Kalibration über den Bereich der Dither-Pegel, was als ein Linearisierer für die Backend-Nicht-Idealzustände wirkt. Der Bereich des IGE-Dithers muss größer als ein Stufe-2-Teilbereich und vorzugsweise das Doppelte dieses Bereichs sein.

Examples of the techniques used to make the non-linear calibration of a given block (e.g., in stage-1) insensitive to the non-ideal conditions of the back stages following this given block are:

• Inject a "linearization dither" in the following stage in both the MDAC and Flash. The dither amplitude is preferably large enough to cover a full portion of the level-2. The dither is digitally subtracted from the signal used for non-linear calibration. This can be the most effective technique.
• Randomize (or dither) inspection points (open interval thresholds) used for non-linear calibration. The range of inspection point values is preferably at least equal to a level 2 subarea, and more preferably covers the double level 2 subarea. This technique is effective, but not as effective as applying the Stage 2 linearization dither.
• - Using multiple inspection points (open interval thresholds) for nonlinear calibration and averaging the results. The range of the inspection points is preferably at least equal to the stage 2 portion, and more preferably twice the stage 2 portion.
• - Using multiple dither levels in the calibration dither of the given level. This helps with this problem as long as the correlation / histogram is performed at the multiple levels of the dither. This averages the calibration over the range of dither levels, acting as a linearizer for the backend non-ideal states. The range of the IGE dither must be greater than a level 2 subrange, and preferably twice this range.

The above mentioned measures are examples of techniques that can be used to ensure that the calibration is effective in the presence of backend non-ideal conditions. However, not all of the measures are needed at the same time. If done correctly, only one of these can be adequate and a combination of two of these can help to increase the ruggedness improve. Tests have shown that linearization dithering is the most effective technique, and it can be used alone or in conjunction with another method to improve ruggedness.

The cost of these measures can be very small and can be helpful for the other existing calibrations in addition to amplifier calibration. For example, by injecting a linearization dither into the second stage, it is possible to reduce the number of levels that were otherwise injected into the first stage so that the total number of levels is the same. Therefore, this does not necessarily increase the overall power consumption.

Gain adjustment / calibration with analog correction

To correct for gain error, a closed-loop approach may be used in which the LMS algorithm controls the gain of the amplifier in a manner that minimizes the squared gain error. The control parameter ε [n] for correcting the gain can be updated by the following LMS equation: $$\epsilon \left[n+1\right]=\epsilon \left[n\right]+\mu \cdot V_d\cdot \left(V_R\left[n\right]-G{V}_d\left[n\right]\right)$$

V _d is the calibration dither signal, V _R is the output (remainder) of the stage-1, G is the ideal gain of the stage and μ is the LMS step size. The control parameter ε [n] is then used to control the gain of the open-loop amplifier. The control parameter ε [n] can be calculated by correlating V _d versus V _R minus a dither estimate. In other words, will V _d relative to the output signal removed with the dither estimate. The dither estimate is based on a product of V _d and the ideal gain G. The result of the correlation is used to update the control parameter ε [n] using equation (13). When the control parameter ε [n] converges, it is expected that V _d With V _R [n] - GV _d [n] (the output that removes the dither estimate) is uncorrelated.

Controlling the gain of the open-loop amplifier can be done by adjusting the current (ie, the current source (s) in the amplifier that the g _m and thereby control the gain of the amplifier) is controlled. In some cases, controlling the gain of the open-loop amplifier may be performed by adjusting the load resistances (e.g. R _L , Gate voltage V _G a load transistor) and / or source degeneration resistors R _S (as seen in the figures) are controlled / varied.

38 FIG. 12 illustrates gain amplification with analog correction, according to some embodiments of the disclosure. FIG. An ADC system 3800 has an amplifier 3802 with an open loop (for example, part of an MDAC circuit structure), an ADC 3804 that the output of the amplifier 3802 digitized with open loop, and a digital processing and calibration block 3806 on. The digital processing and calibration block 3806 can measure the output (eg the one through the ADC 3804 digitized remainder) and update the control parameter ε [n] to correct the gain. The digital processing and calibration block 3806 can the amplifier 3802 tune with open loop based on the control parameter.

In some alternative embodiments, if the MDAC stages have different references, controlling the references may be used to correct the interstage gain. However, directly controlling the gain of the amplifier as discussed above may correct the actual gain of the amplifier and avoid possible negative side effects of changing the references between the various stages.

Tuning the components of the open loop amplifier (eg, bias currents and resistors) may advantageously provide fine gain matching of the open loop amplifier and the overall circuit. In some embodiments, it is advantageous to provide a rough gain adjustment. Fine and / or coarse gain adjustment may be used for calibration and / or configurability purposes.

To implement a coarse gain adjustment, a variable attenuator may be included in front of an open-loop amplifier. 39 represents a variable attenuator 3902 in a frontend 3900 an ADC according to some embodiments of the disclosure. The frontend 3900 can accommodate a fine gain adjustment or coarse gain adjustment. The frontend 3100 receives an analog input signal V _{in_g} and delivers a signal V _sh that followed by the ADC the frontend 3900 to digitize. The frontend 3100 has the variable attenuator 3902 , an amplifier 3904 with variable gain and a track-and-hold (T / H) circuit 3906 on. In addition to meeting coarse gain adjustment requirements, the variable attenuator 3902 reduce the input stroke to the amplifier and the input V _amp provide a fixed impedance that is independent of the damping setting. Preferably, the variable attenuator deteriorates 3902 not the distortion and can handle a relatively large input with acceptable distortion levels.

The amplifier 3904 Variable gain may be implemented based on any of the open-loop amplifiers described herein. Using an open-loop amplifier as the amplifier 3904 with variable gain means that the open-loop amplifier would work in the time-continuous domain. This can have some effects and benefits on the entire ADC system. Improving the efficiency of the amplifier 3904 variable gain may rely on analog linearization schemes, such as the analog tracking circuits provided by the 31-32 are illustrated. Due to the continuous-time operation of the amplifier 3904 With variable gain, it is possible to avoid frequency-dependent calibrations. Calibrations that depend on the input frequency for linearization can be costly and cumbersome. If desired, it is possible to perform a digital calibration and mixed signal calibration, insofar as z. B. a calibration dither in the amplifier 3904 with variable gain (eg as through 37 illustrated) and includes mechanisms for coarse and / or fine gain adjustments. Digital and mixed-signal calibration techniques can use a digital output that outputs the amplifier 3904 with variable gain, observe and extract non-linearities / non-ideal states accordingly.

The T / H circuit 3906 can be implemented in a suitable way. In the illustrated example, the T / H circuit 3906 the frontend 3100 are seen as an open-loop T / H circuit which is a buffer 3908 , a switched capacitor network 3910 and an amplifier 3912 having. The switched capacitor network 3910 may be a scanning network. The buffer 3908 may be a sample buffer and the amplifier 3912 may be a hold buffer / amplifier (eg, any of the open-loop amplifiers described herein). A dither can enter the switched capacitor network 3910 be injected (eg by injecting a charge into the switched capacitor network 3910 and the dither may be used to calibrate a circuit downstream of the dither injection point. The switched capacitor network 3910 may include a dither injection circuit at the dither injection point, for. B. to inject a charge representing a dither signal. The buffers may be source followers, emitter followers, push-pull topology, any other suitable buffer structure, and open-loop amplifiers described herein. The buffer 3908 can be optimized for scan linearity. The amplifier 3912 can be optimized for low power, small size, small input capacity and good isolation. The isolation for the amplifier 3912 can help with input-related noise of the ADC, that of the T / H circuit 3906 follows, reduce. The linearity of the amplifier 3912 is not as critical as the linearity of the buffer 3908 because of the amplifier 3912 a held signal edited. In addition to that, there dither into the switched capacitor network 3910 can be injected, the nonlinearity of the amplifier 3912 calibrated, which also helps to increase the performance and size of the amplifier 3912 to lower.

The variable attenuator 3902 may have a circuit with a network of switches and resistors. The network is configurable with switches. Depending on the state of the switches (eg, transistor devices), a certain amount of resistance may be configured and used to attenuate the input. In other words, the effective gain of the variable attenuator can be configured via the state of the switches. Specific resistors can be switched into or out of the network by the total resistance and thus the gain of the variable attenuator 3902 to change.

If the variable attenuator and open-loop amplifiers are provided in the front-end (possibly as variable-gain amplifiers), the overall gain can be distributed across various circuits in the front-end (to potentially achieve higher overall gain). Due to the programmability (fine or coarse) of the gain for the variable attenuator and the open-loop amplifier, various ways of programming the overall gain are also possible. A rough gain adjustment may be made with the variable attenuator and / or by reducing the amplifier resistance load. Fine gain adjustment may be accomplished by adjusting the current (s) in the amplifier (eg, adjusting a current source in an open loop amplifier using a bias voltage or changing a bias voltage) Current source transistor controls to adjust an amount of current and the gain of the open-loop amplifier).

40 represents an exemplary circuit 4000 variable attenuator according to some embodiments of the disclosure. The circuit 4000 with variable attenuator receives an input V _{in_g} and puts a muted exit V _amp and has a network of resistors (eg, referred to as "R") and switches (eg, by control signals S0 - S6 controlled). The switches are implemented using transistor devices whose gates are driven by respective control signals to switch the switches "on" or "off". The amount of amplifiers may be varied according to the following table (eg, 1, ½, ¼, and 1/8) showing the states of the switches (1 = "on" and 0 = "off"), while the Input impedance is kept constant at 2R: Gain = 1 Gain = 1/2 Gain = 1/4 Gain = 1 / 8th S0 1 0 0 0 S1 0 1 0 0 S2 0 0 1 1 S3 0 0 1 0 S4 0 0 0 1 S5 0 0 0 1 S6 0 0 0 0 input impedance 2R 2R 2R 2R

41 represents another exemplary circuit 4100 variable attenuator according to some embodiments of the disclosure. The circuit 4100 with variable attenuator receives an input V _{in_g} and puts a muted exit V _amp and has a network of resistors (eg, referred to as "R") and switches (eg, by control signals S0 - S9 controlled). The switches are implemented using transistor devices whose gates are driven by respective control signals to switch the switches "on" or "off". The circuit 4100 with variable attenuator is similar to the circuit 4000 with variable attenuator. However, there are additional switches (by S7 . S7 ' . S8 . S8 ' . S9 and S9 ' controlled) as selectable impedances to the output impedance variation of the circuit 4100 to improve with variable attenuator. If S7 1 is and S7 ' 0, both of the pair of NMOS and PMOS transistor devices are turned on. If S8 1 is and S8 ' 0, both of the pair of NMOS and PMOS transistor devices are turned on. If S9 1 is and S9 ' 0, both of the pair of NMOS and PMOS transistor devices are turned on. The amount of amplifiers can be varied according to the following table (eg 1, ½, ¼, and 1/8), which indicate the states of the switches ( 1 = "On" and 0 = "off") while holding the input impedance constant at 2R: Gain = 1 Gain = 1/2 Gain = 1/4 Gain = 1 / 8th S0 1 0 0 0 S1 0 1 0 0 S2 0 0 1 1 S3 0 0 1 0 S4 0 0 0 1 S5 0 0 0 1 S6 0 0 0 0 S7 1 0 0 0 S8 0 1 0 0 S9 0 0 1 0 input impedance 2R 2R 2R 2R

Memory and kickback calibration

In some MDAC circuit structures, the capacitances are fully reset when switching between the hold phase and the sample phase to avoid memory and kickback errors. This can be done using switches included in the 2 and 3 are designated as φ2_rst. However, resetting can consume some of the time and a significant amount of power. In order to save both time and power, it is possible to avoid having to reset the capacitances and instead calibrate the resulting memory and kickback errors.

A first calibration dither V _d1 will be added to the 1 injected and a second calibration dither V _d2 will be added to the 2 injected. The calibration dithers can be used for memory and kickback calibrations. Preferably, the kickback error is first extracted. The kickback error can be extracted based on a correlation between the second calibration dither and a stage 1 (digital) output. The kickback error can be removed from the Stage-1 digital output to produce a first calibrated Stage-1 output. Then the memory error is extracted. The memory error may be based on a correlation between the first calibration dither and the first calibrated output of the stage 1 be extracted. The memory error can be removed from the first calibrated output of stage-1 to produce a second (final) calibrated output of stage-1.

42 illustrates a memory and kickback calibration, in accordance with some embodiments of the disclosure. More specifically, a digital processing circuit 4200 the interstage memory and kickback errors for e.g. For example, calibrate the Stage-1 of a pipeline ADC. The level 1 digital output V _out1 [n ] can z. B. by a delay block 4202 be delayed. An estimated kickback error V _{KB1_est} [n] is through a summing node 4204 from the delayed digital output of the 1 subtracted. The result from the summation node 4204 can correlate with the calibration dither of the stage 2 V _d2 , illustrated by a correlator 4206 , be used. The correlation result from the correlator 4206 Can be used to set a kickback coefficient α _m21 in the kickback calibration block 4208 to update. This kickback coefficient α _m21 is used to remove most of the kickback components at the output of the stage 1 that are derived from dithering 2 V _d2 , the DAC of the 2 V _DAC2 and some memory of the output of the stage 1 even V _out1 come, used. The kickback coefficient α _m21 , the DAC of the stage 2 V _DAC2 , the calibration dither of the stage 2 V _d2 and some memory of the output of the stage 1 even V _out1 can through the kickback calibration block 4208 used to the kickback error term / kickback error component V _{KB1_est} [n] to appreciate / generate. The estimated kickback error V _{KB1_est} [n] can through a summation node 4210 from the digital output of the stage 1 V _out1 [n] be subtracted to an output signal V _{out1_KB} [n] (digital output of the 1 to remove with the kickback error removed).

Once the estimated kickback error V _{KB1_est} [n] from the level 1 digital output V _out1 [n] is removed, the remainder of the memory at the stage 1 through a first delay V _{out1_KB} [n] through a delay block 4212 away. An estimated memory error V _{mem1_est} [n] is through a summing node 4212 from the delayed digital output of the 1 , with the kickback error removed, subtracted. The result from the summation node 4212 can correlate with the calibration dither of the stage 1 V _d1 , illustrated by a correlator 4216 , be used. The correlation result from the correlator 4216 can be used to calculate a memory coefficient α _m11 in a memory calibration block 4218 to update. This memory coefficient α _m11 is used to calculate the (remaining) memory of the output of the stage 1 to remove. The memory coefficient α _m11 and some memory of the output of the stage 1 even V _out1 can through the memory calibration block 4218 used to get the estimated memory error V _{mem1_est} [n] to create. The memory error V _{mem1_est} [n] can through a summation node 4220 from the digital output of the stage 1 , with the kickback error removed, V _{out1_KB} [n] be subtracted to an output signal V _{out1_cal} [n] (digital output of the 1 to remove with the kickback error and memory error removed). The removal of the kickback error and removal of the memory Fs are performed sequentially to show the calibration scheme, but one skilled in the art would understand that the removal of the kickback error and the removal of the memory Fs can also be performed in parallel , The details of what components are removed in each step may depend on the implementation.

In MDACs with open loop, errors due to inter-stage memory and kickback are similar to those in closed-loop MDACs. They can be corrected using dither-based IGE, IME, and KB calibrations. However, implementing some of these calibrations can be costly and requires that multiple calibration dithers be injected into each stage. The accuracy can also be limited. There are subtle differences in the behavior of the open loop MDACs compared to closed loop MDACs; more specifically, the summation node voltage is not forced to a virtual ground in the hold phase. These differences may need to be considered to change the implementations in a way that improves the IGE, IME, and KB calibrations.

43 illustrates an MDAC 4300 with open loop, in accordance with some embodiments of the disclosure. As an example, the MDAC is located 4300 with open loop in the stage 2 (but the teachings are also applicable to other levels). The MDAC 4300 has an amplifier 4304 (eg, a suitable open loop amplifier described herein) and a switched capacitor circuit 4302 which can perform sampling and DAC operations. The MDAC 4300 has a summation node 4310 (or summing node) at the non-inverting input of the amplifier 4304 on. The MDAC circuit structure 4300 further includes a switched capacitor circuit 4306 for calibration dither injection. More specifically, the switched capacitor circuit injects 4306 a charge into the switched capacitor circuit 4302 based on the calibration dither voltage V _d2 , The calibration dither signal is injected in a hold phase (φ2) and the capacitance is connected to ground in the sense phase (φ1). As a result, a calibration dither signal is generated in the MDAC circuit structure 4300 added.

The output of an open loop MDAC, e.g. B. V _out1 [n] the level-1, can be represented as: $$V_{Out1}\left[n\right]=V_{Out{1}_{nOmen}}\left[n\right]+V_{Out{1}_{men}}\left[n\right]+V_{KB\_OL1}\left[n\right]$$

V _out1 is the output of the Stage 1 MDAC, V _{out1 Nomem} is the output of the stage 1 in the absence of a memo, V _{out1 mem} is the self-memory component in the output that is independent of stage 2 kickback, V _{KB_OL1} is the level-1 component that comes from the kickback of the stage 2 at the level 1 results. The self-memory term is given by: $$V_{Out{1}_{men}}\left[n\right]={\alpha }_{m1}{V}_{Out1}\left[n-1\right]$$

α _m1 is the self-memory coefficient. The self-memory terms represented in equations (14) and (15) are infinite impulse response functions (IIR functions) that represent the accumulation of an infinite set of previous memory terms, since the current output is one Memory component that is proportional to the previous output (not input).

The kickback term can be given by: $$\begin{array}{c}{}_{L1}\left[n\right]={\alpha }_{KB1}(V_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2C"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}+V_{in2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}-V_{d2}[n\\ -1)\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}]\end{array}$$

V _DAC2 is the DAC voltage of the stage 2 MDAC digitally controlled by the ADC (Flash) output bits of the 2 is represented, V _in2 is the entrance to the level 2 which equals the output of the stage 1 is and V _d2 is the calibration dither of the stage 2 , V _DAC2 . V _in2 and V _d2 are each scaled by a corresponding ratio of capacities in the second stage. C _d2 is the dither capacitance in the switched capacitor circuit 4306 from 43 for injecting a calibration dither into the stage 2 , C _p2 is the parasitic capacitance in the summing node 4310 (shown as a capacitor) of 43 , C ₂ is the capacitance in the switched capacitor circuit 4302 (the sample / DAC capacities) of 43 , Equation (16) can be determined by the Kickback calibration block 4208 from 42 be calculated. The coefficient α _KB1 is the kickback coefficient, which depends on the settling of the kickback of the 2 during the holding phase of the stage 1 depends. For a first-order settling, the coefficient is α _KB1 roughly by the following: $${\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}~e^{-t_s/R_1{\mathrm{<figure-callout\; id="1"\; label="C\; L"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_L}$$

t _s is the settling time, R ₁ is the output resistance of the stage 1 amplifier and C _L1 is the load capacity of the stage-1.

Kickback voltage equation (16) in open loop MDACs is different from the kickback voltage in the case of a closed loop amplifier which would be given by: $$V_{KB\_CL1}\left[n\right]~{\alpha }_{KB1}{V}_{DAC2}\left[n-1\right]$$

Equation (18) does not include a ratio of capacities V _in2 and V _d , In practice, a sampling clock φ1a is usually advanced in comparison to the other clocks. This causes the summing node capacity to be partially reset before the scan starts. 44 FIG. 12 illustrates a timing diagram of sampling switches, in accordance with some embodiments of the disclosure. FIG. The graphic representation 4402 shows the timing of the sampling clock φ1a (clock for controlling the switch on the lower plate of the sampling capacitances) and the graph 4404 shows the timing of the sampling clock Φ2 , There is a short period of reset time ("partial reset") which may cause the kickback voltage to deviate from the expression given in equation (16): $$\begin{array}{c}{V}_{KB\_\mathrm{<figure-callout\; id="1"\; label="O\; L"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}L1\_\mathrm{<figure-callout\; id="2"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}={\alpha }_{KB1}(V_{DAC2}\left[n-1\right]-{\alpha }_{RST2}{V}_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}\\ +{\alpha }_{RST2}{V}_{in2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}-{\alpha }_{RST2}{V}_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}})\end{array}$$

α _RST2 represents the fraction of the summing node voltage (or, more precisely, the sample capacitor charge) remaining after reset. If fully reset, then α _RST2 = 0, and the kickback voltage is given by: $$V_{KB\_\mathrm{<figure-callout\; id="1"\; label="O\; L"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}L1\_\mathrm{<figure-callout\; id="2"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}={\alpha }_{KB1}{V}_{DAC2}\left[n-1\right]$$

Equation (20) is similar to the kickback of a closed-loop MDAC as shown in equation (18). On the other hand, if the reset does not exist, then α _RST2 = 1, and the equation (19) is reduced to the equation (16). The following sections will discuss a partial reset as it is the most general scenario.

As stated in Equation (19), in the open loop MDAC (eg, an in 43 illustrated), the kickback from the following stage components from the IGE dither V _d2 , the quantized input V _DAC2 and the unquantized input V _in2 (the level 2 ) on. The three contributions have a kickback with different coefficients, such as α _RST2 and represents the ratio of capacities. On the other hand, for the closed-loop MDAC and with full reset of the summation node in the open-loop MDAC, only the next stage quantized input will kickback at the current stage. The additional components / contributions require a different scheme for addressing the kickback error for a system with open loop MDACs.

was auch als Folgendes repräsentiert werden kann: $$\begin{array}{c}{}_L\left[n\right]=V_{out{1}_{nomem}}\left[n\right]+{\alpha }_{m1}{V}_{out1}\left[n-1\right]\\ +{\alpha }_{KB1}(V_{out1}\left[n-1\right]-V_{out1q}\left[n-1\right]+V_{out1q}\left[n-1\right]\frac{{\alpha }_{RST2}{C}_2}{C_2+C_{d2}+C_{p2}}-V_{d2}[n\\ -1]\frac{{\alpha }_{RST2}{C}_{d2}}{C_2+C_{d2}+C_{p2}})\end{array}$$

From the equations (14), (15) and (19), the output of the stage 1 for an MDAC with an open loop are represented as follows: $$\begin{array}{c}{}_{Out1}\left[n\right]=V_{Out{1}_{nOmem}}\left[n\right]+{\alpha }_{m1}{V}_{Out1}\left[n-1\right]\\ +{\alpha }_{KB1}(V_{DAC2}\left[n-1\right]-V_{DAC2}\left[n-1\right]\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}\\ +V_{Out1}\left[n-1\right]\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}-V_{d2}\left[n-1\right]\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}})\end{array}$$

which can also be represented as: $$\begin{array}{c}{}_L\left[n\right]=V_{Out{1}_{nOmem}}\left[n\right]+{\alpha }_{m1}{V}_{Out1}\left[n-1\right]\\ +{\alpha }_{KB1}(V_{Out1}\left[n-1\right]-V_{Out1q}\left[n-1\right]+V_{Out1q}\left[n-1\right]\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}-V_{d2}[n\\ -1]\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}})\end{array}$$

V _out1q is the quantization error of the Stage 1 output after passing through the stage 2 which can be approximated by the difference between the Stage 1 output and the Stage 2 ADC (Flash) output bits. This means: $$V_{Out1q}\left[n-1\right]~V_{Out1}\left[n-1\right]-V_{DAC2}\left[n-1\right]$$

Therefore, all memory and kickback components can actually be calculated by correlating the output of the stage 1 with the calibration dither 1 V _d1 and the calibration dither 2 V _d2 be removed, as by 42 has been illustrated without the need for any additional kickback dither. It is noted that the output of the stage 1 has a component which, due to the dithering 1 that is in the stage 1 injection to correct the IGE and IME corrections of the 1 perform.

46 provides a digital signal processing 4500 for updating a coefficient to address a kickback error, in accordance with some embodiments of the disclosure. The digital signal processing 4500 is commonly used as a correlator for removing memory and kickback terms from the stage 2 to the level 1 denoting the following correlation LMS equation for updating the kickback coefficient α _m21 implemented: $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot \left(V_{Out1}\left[n\right]-{\alpha }_{m21}\left[n\right]\cdot V_{d2}\left[n-1\right]\right)$$

A PN generator block 4502 generates a calibration dither signal V _d2 [n] for the stage 2 and the dither signal V _d2 [n] is through a delay block 4506 delayed to V _d2 [n - 1] to create. The delayed dither signal V _d2 [n - 1] is through a multiplier 4508 With α _m21 [n] multiplied to obtain α _m21 [n] ▪ V _d2 [n-1] (shown as an estimated dither signal V _{d2_est} [n-1] in the figure). A summation node 4510 subtracts α _m21 [n] ▪ V _d2 [n - 1] from the output of the stage 1 V _out1 [n] to obtain V _out1 [n] _{-α m21} [n] ▪ V _d2 [n-1]. V _out1 [n] - α _m21 [n] ▪ V _d2 [n - 1] also forms the output signal of the stage 1 , with the estimated dither signal removed, as V _{out1_KB} [n] shown for the memory error calibration of 46 can be used. To the estimate for the coefficient α _m21 [n] to update, the output of the stage 1 , with the estimated dither signal removed, V _out1 [n] -α _m21 [n] ▪ V _d2 [n-1], through a multiplier 4512 with the delayed dither signal V _d2 [n - 1] multiplied to obtain V _d2 [n - 1] ▪ (V _out1 [n] - α _m21 [n] ▪ V _d2 [n - 1]). The multiplier 4512 performs a correlation and generates an error term that the LMS equation attempts to reduce or minimize as the LMS process converges. In this example, when the LMS process converges, the error term is reduced if it is expected that V _d2 [n - 1] , is not _correlated with (V _out1 [n] - α _m21 [n] ▪ V _d2 [n - 1]). The result of the multiplier 4512 , V _d2 [n - 1] ▪ (V _out1 [n] - α _m21 [n] ▪ V _d2 [n - 1] ), is by a multiplier 4514 multiplied by the LMS step size μ to obtain μ ▪ V _d2 [n-1] ▪ (V _out1 [n] _{-α m21} [n] _▪ V _d2 [n-1]). A summation node 4516 adds the result from the multiplier 4514 , μ ▪ V _d2 [n - 1] ▪ (V _out1 [n] - α _m21 [n] ▪ V _d2 [n - 1]), to the kickback coefficient α _m21 [n], to obtain: α _m21 [n] + μ ▪ V _d2 [n - 1] ▪ (V _out1 [n] - α _m21 [n] ▪ V _d2 [n - 1]). The result from the summation node 4516 , α _m21 [n] + μ ▪ V _d2 [n - 1] ▪ (V _out1 [n] - α _m21 [n] ▪ V _d2 [n - 1]), is represented by a delay block 4518 delayed to form the updated kickback coefficient α _m21 [n + 1].

46 provides a digital signal processing 4600 for updating a coefficient to address a (remaining) memory error, in accordance with some embodiments of the disclosure. The digital signal processing 4600 is commonly referred to as a correlator for removing a Level-1 memory at the output of the correlator 46 denotes the following correlation LMS equation for updating a memory coefficient α _m11 implemented: $$\begin{array}{c}{\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\\ \cdot \left(V_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]-{\alpha }_{m11}\left[n\right]\cdot V_{Out1}\left[n-1\right]\right)\end{array}$$

A delay block 4602 delays the output signal of the stage 1 , with the estimated dither signal removed, as V _{out1_KB} [n] presented to V _{out1_KB} [n - 1] to obtain. V _{out1_KB} [n - 1] is through a multiplier 4604 with a memory coefficient α _m11 [n] multiplied to form α _m11 [n] ▪ V _out1 [n-1], which may represent an estimate of the memory error. A summation node 4606 subtracts α _m11 [n] ▪ V _out1 [n-1] from V _{out1_KB} [n] to obtain V _{out1_KB} [n] _{-α m11} [n] ▪ V _out1 [n-1]. The result of the summation node 4606 may represent the kickback calibrated output, with an estimated memory error removed. The multiplier 4608 multiplies the delayed dither signal of level-1 V _d1 [n - 1] and V _{out1_KB} [n] _{-α m11} [n] ▪ V _out1 [n-1] to V _d1 [n-1] ▪ (V _{out1_KB} [n] _{-α m11} [n] ▪ V _out1 [n-1] ) to obtain. The multiplier 4608 performs a correlation and generates an error term that the LMS equation attempts to reduce or minimize as the LMS process converges. In this example, when the LMS process converges, the error term is reduced if V _d1 [n-1] is not _correlated with V _{out1_KB} [n] _{-α m11} [n] ▪ V _out1 [n-1]. A multiplier 4610 multiplies the LMS step size μ and V _d1 [n-1] ▪ (V _{out1_KB} [n] _{-α m11} [n] ▪ V _out1 [n-1]) to get μ ▪ V _d1 [n-1] ▪ (V _{out1_KB} [n] - α _m11 [n] ▪ V _out1 [n-1]). A summation node 4612 adds the result from the multiplier 4610 to the memory coefficient α _m11 [n] to obtain: α _m11 [n] + μ▪ V _d1 [n-1] ▪ (V _{out1_KB} [n] _{-α m11} [n] ▪ V _out1 [n-1 ]). The result of the summation node 4612 , α _m11 [n] + μ ▪ V _d1 [n - 1] ▪ (V _{out1_KB} [n] - α _m11 [n] ▪ V _out1 [n - 1]), is represented by a delay _block 4614 delayed to the memory coefficient α _m11 [n + 1]. to update.

und $$\begin{array}{c}{\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d1}\left[n-1\right]\right)\\ \cdot \text{sgn}\left(V_{out1\_KB}\left[n\right]-{\alpha }_{m11}\left[n\right]\cdot V_{out1}\left[n-1\right]\right)\end{array}$$

Alternatively, if a histogram / count technique is used to extract a gain and for nonlinearity calibration, the LMS equations ( 23 ) and (24) for kickback and memory calibration (respectively) are: $$\begin{array}{c}{\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d2}\left[n-1\right]\right)\\ \cdot \text{sgn}\left(V_{Out1}\left[n\right]-{\alpha }_{m21}\left[n\right]\cdot V_{d2}\left[n-1\right]\right)\end{array}$$

and $$\begin{array}{c}{\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d1}\left[n-1\right]\right)\\ \cdot \text{sgn}\left(V_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]-{\alpha }_{m11}\left[n\right]\cdot V_{Out1}\left[n-1\right]\right)\end{array}$$

V _{out1_KB} [n] is the output of the stage 1 after the through α _m21 collected kickback terms are removed. Sgn () is a sign function. Sign bits of the magnitudes used in the correlations formulated in equations (26) (27) ultimately perform a correlation of magnitudes. As the LMS process converges, the kickback coefficient and the memory coefficient would convert to a value that compensates for the kickback and memory errors of the stage. 1 would best reduce.

By using α _m21 and α _m11 In this particular embodiment of the calibration dither injection, the memory and kickback errors in the stage 1 be corrected approximately. For example, can α _m21 used to the dither kickback V _d2 and remove the portion of the signal memory resulting from the kickback while α _m11 can be used to determine the remaining level 1 -Object memory error to remove. If the kickback is the only memory source, only will α _m21 needed. For example, in the presence of both self-memory and kickback, the correction may be performed as follows: $$\begin{array}{c}{V}_{Out{1}_{cal}}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\\ +{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{Out1}\left[n-1\right]-{\alpha }_{m11}{V}_{Out1}\left[n-1\right]\end{array}$$

und $$V_{out{1}_{cal}}\left[n\right]=V_{out1\_KB}\left[n\right]-{\alpha }_{m11}{V}_{out1}\left[n-1\right]$$

The amount of V _out1 [n - 1] using by α _m21 is removed (by a correlation between the dither 2 V _d2 and the remainder 1 V _out1 ), influences the value of α _m11 which converges to remove the remaining memory. This means: $$\begin{array}{c}{V}_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\\ +{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{Out1}\left[n-1\right]\end{array}$$

and $$V_{Out{1}_{cal}}\left[n\right]=V_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]-{\alpha }_{m11}{V}_{Out1}\left[n-1\right]$$

The calibrated outputs V _{out1 cal} can z. In equations (24) and (25) or equations (26) and (27).

und $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot V_{out{1}_{cal}}\left[n\right]$$

Generally speaking, can V _{out1 cal} in equations (24) to (27). This means: $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot V_{Out{1}_{cal}}\left[n\right]$$

and $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot V_{Out{1}_{cal}}\left[n\right]$$

und $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d1}\left[n-1\right]\right)\cdot \text{sgn}\left(V_{out{1}_{cal}}\left[n\right]\right)$$

V _{out1 cal} [N] is given by equation (28). Similarly, equations (26) and (27) can be represented as: $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d2}\left[n-1\right]\right)\cdot \text{sgn}\left(V_{Out{1}_{cal}}\left[n\right]\right)$$

and $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d1}\left[n-1\right]\right)\cdot \text{sgn}\left(V_{Out{1}_{cal}}\left[n\right]\right)$$

und $${\alpha }_{m11}\sim -{\alpha }_{KB1}\frac{{\alpha }_{RST2}{C}_{d2}}{C_2+C_{d2}+C_{p2}}$$

From Equation (24) to (30), the converged parameters are given by: $${\alpha }_{m11}~{\mathrm{<figure-callout\; id="1"\; label="\alpha \; m"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_m+{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}$$

and $${\alpha }_{m11}~-{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}$$

It should be noted that the quantization error due to kickback α _KB1 V _out1q [n - 1] was not removed in equation (28), which may be a limitation on the use of traditional calibration dithering when both self-memory and kickback memory are present.

und $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot \left(V_{out{1}_{cal}}\left[n\right]-{\alpha }_{m21}\left[n\right]\cdot V_{d2}\left[n-1\right]\right)$$

If the self-memory term α _m1 is negligible, the correlation can be performed using the following equations: $$\begin{array}{c}{\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\\ \cdot \left(V_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]-{\alpha }_{m11}\left[n\right]\cdot V_{DAC2}\left[n-1\right]\right)\end{array}$$

and $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot \left(V_{Out{1}_{cal}}\left[n\right]-{\alpha }_{m21}\left[n\right]\cdot V_{d2}\left[n-1\right]\right)$$

und $$\begin{array}{c}{V}_{out{1}_{cal}}\left[n\right]=V_{out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]+{\alpha }_{m21}\frac{C_2}{C_{d2}}{V}_{out1}\left[n-1\right]\\ -{\alpha }_{m21}\frac{C_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]-{\alpha }_{m11}{V}_{DAC2}\left[n-1\right]\end{array}$$

The correction or error removal can be performed using the following correction equations: $$\begin{array}{c}{V}_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]+{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{Out1}\left[n-1\right]\\ -{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\end{array}$$

and $$\begin{array}{c}{V}_{Out{1}_{cal}}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]+{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{Out1}\left[n-1\right]\\ -{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]-{\alpha }_{m11}{V}_{DAC2}\left[n-1\right]\end{array}$$

und $${\alpha }_{m21}\sim -{\alpha }_{KB1}\frac{{\alpha }_{RST2}{C}_{d2}}{C_2+C_{d2}+C_{p2}}$$

In Equation (36), the quantization error is effectively removed using the dither 1 correlation and ratio metric capacitances made possible due to the absence of the self memory term. In the absence of self-memory, therefore, all kickback errors can be effectively removed using ratio metric capacitances using the traditional calibration dither injection. The memory parameters are given by the following: $${\alpha }_{m11}~{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}$$

and $${\alpha }_{m21}~-{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}$$

Therefore, using only one traditional IGE dither injection, it is possible to approximately remove the inter-stage memory and kickback errors in open-loop amplifiers. If the self-memory term is negligible, the removal of the kickback errors is complete. Choosing the right implementation depends on the assumptions and behavior in the analog circuits. However, there are limitations to this technique that make it difficult to handle the most common cases.

oder unter Verwendung: $${\alpha }_2\left[n+1\right]={\alpha }_2\left[n\right]+\mu \cdot \text{sgn}\left(V_{d2}\left[n\right]\right)\cdot \text{sgn}\left(V_{out2}\left[n\right]-{\alpha }_2\left[n\right]\cdot V_{d2}\left[n\right]\right)$$

In some embodiments, the calibration dither signal ("Kal-Dither-2") in the stage 2 during the sampling phase (φ1) to be connected to the input instead of being connected to ground. 47 puts an MDAC 4,700 with an open loop representing the MDAC 4300 with open loop of 43 modified, according to some embodiments of the disclosure. The MDAC with open loop is part of the 2 and illustrates the injection of the calibration dither signal connected to the input in the sampling phase (φ1) instead of being connected to ground. During the exemplary MDAC 4,700 with open loop in the stage 2 is used, it will be understood that the same dither injection technique can be applied to other stages as well. A switched capacitor circuit 4702 differs from the switched capacitor circuit 4306 from 43 , More precisely, the capacitor is C _d2 in the switched capacitor circuit 4702 during the sampling phase φ1 with the input V _in2 connected (rather than with mass, as in 43 seen). This dither injection technique is opposite to that in FIG 43 as it may allow this calibration to effectively capture the IGE, KB, and IME in open-loop MDACs, improve noise performance, and reduce the limitations of traditional calibration dithering (in 43 seen). Level 2 IGE calibration using this Kickback Calibration Dither signal V _d2 from 47 is performed as follows using the following LMS update equation: $${\alpha }_2\left[n+1\right]={\alpha }_2\left[n\right]+\mu \cdot V_{d2}\left[n\right]\cdot \left(V_{Out2}\left[n\right]-{\alpha }_2\left[n\right]\cdot V_{Out2}\left[n\right]\right)$$

or using: $${\alpha }_2\left[n+1\right]={\alpha }_2\left[n\right]+\mu \cdot \text{sgn}\left(V_{d2}\left[n\right]\right)\cdot \text{sgn}\left(V_{Out2}\left[n\right]-{\alpha }_2\left[n\right]\cdot V_{d2}\left[n\right]\right)$$

This is similar to how the IGE calibration is performed using an IGE dither connected to ground in the sampling phase, as in FIG 43 seen.

In this case, the kickback calibration dither signal V _d2 from 47 the kickback voltage is given by the following: $$\begin{array}{l}{V}_{KB\_\mathrm{<figure-callout\; id="1"\; label="O\; L"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}L1}={\alpha }_{KB1}(V_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}+V_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_{d2}}\\ -{\alpha }_{RST2}{V}_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}+{\alpha }_{RST2}{V}_{in2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{V}_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}})\end{array}$$

Therefore, the stage 1 output voltage is given by: $$\begin{array}{l}{V}_{Out1}\left[n\right]=V_{Out{1}_{nOmem}}\left[n\right]+{\alpha }_{m1}{V}_{Out1}\left[n-1\right]\\ +{\alpha }_{KB1}(V_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}+V_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_{d2}}\\ -{\alpha }_{RST2}{V}_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}\\ +{\alpha }_{RST2}{V}_{Out1}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{V}_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}})\end{array}$$

When the level 1 output is with the calibration dither signal V _d1 and the calibration dither signal V _d2 is correlated, z. For example, as in equations (24) and (25) or (26) and (27), (29a) and (30a) or (29b) and (30b), the calibrated output is: $${}_{al}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]-{\alpha }_{m11}{V}_{Out1}\left[n-1\right]$$

und $${\alpha }_{m21}\sim {\alpha }_{KB1}{C}_{d2}\left(\frac{1}{C_2+C_{d2}}-\frac{{\alpha }_{RST2}}{C_2+C_{d2}+C_{p2}}\right)$$

That's hot, the calibration dither signal V _d2 is used to control the kickback components from the DAC2 (DAC in stage 2) and the calibration dither signal V _d2 while removing the calibration dither signal V _d1 is used to remove the memory components of the output. In equation (43), all parameters are from α _RST2 and the parasitic capacity C _p2 independently. In this case, the convergence parameters obtained using equations (24) and (25) are given by: $${\alpha }_{m11}~{\mathrm{<figure-callout\; id="1"\; label="\alpha \; m"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_m+{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}\frac{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}$$

and $${\alpha }_{m21}~{\alpha }_{KB1}{C}_{d2}\left(\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_{d2}}-\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\right)$$

Therefore, this is through 47 The dither injection technique illustrated has the ability to allow the accurate removal of all error sources, dithers, and quantization errors due to IME, IGE, and KB while providing a ratio metric correction that is independent of parasitic capacitances without additional complexity compared to MDACs with closed loop. The technique uses only two correlators (or two counters, depending on the calibration technique).

If the quantization error and dither kickback from stage-2 to stage-1 can be ignored, equation (42) can be reduced to: $$V_{Out1}\left[n\right]~V_{Out{1}_{nOmem}}\left[n\right]+{\alpha }_{m1}{V}_{Out1}\left[n-1\right]+{\alpha }_{KB1}{V}_{Out1}\left[n-1\right]$$

In this case will only α _m11 needed to correct the IME and kickback errors in stage-1, and therefore the technique would use only one correlator.

In addition to its effectiveness in removing the error components, this structure has a noise advantage. Since both the dither and the input capacitances sense the input, the input-related noise is improved. The noise is improved even if the total sampling capacity is not increased. To fully exploit this noise enhancement while avoiding over-range of the amplifier, the DAC reference voltage can be increased by the same factor. [this is not claimed] That is, if the total sampling capacitor is held at C: $$\frac{v_{nKB}^2}{v_{n\mathrm{<figure-callout\; id="2"\; label="I\; G\; e"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">I\; </figure-callout>}Ge}^2}~\frac{C+C_p}{C+C_p+C_d}$$

ist die Rauschleistung unter Verwendung des KB-Dither-Verfahrens in diesem Abschnitt, $v_{nIGE}^2$

ist die Rauschleistung unter Verwendung des in 43 gesehenen IGE-Dithers. Der Referenzwert muss um denselben Faktor heraufskaliert werden: $$\frac{V_{Ref\_KB}}{V_{Ref\_IGE}}\sim \frac{C+C_d}{C}$$

$v_{\mathrm{<figure-callout\; id="2"\; label="n\; K\; B"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">n\; </figure-callout>}KB}^2$

is the noise performance using the KB dither method in this section, $v_{n\mathrm{<figure-callout\; id="2"\; label="I\; G\; e"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">I\; </figure-callout>}Ge}^2$

is the noise power using the in 43 seen IGE dithers. The reference value must be scaled up by the same factor: $$\frac{V_{Ref\_KB}}{V_{Ref\_IGe}}~\frac{C+C_d}{C}$$

Referring again to 47 can be the reference voltage V _Ref to be scaled up (C ₂ + C _{d 2)} / C ₂ in order to prevent an over range of the amplifier.

Despite the differences between the open-loop and closed-loop MDACs, removing the different IGE, IME, and KB components does not require additional complexity. In fact, it may be easier for the open-loop amplifier because of the charge sharing that takes place. This allows the same dither to be used effectively for IGE, IME and KB. By using V _d1 and V _d2 All memory and kickback components of the 1 be removed.

48 illustrates a circuit 4800 with both linearization and calibration dither injection, in accordance with some embodiments of the disclosure. The circuit 4800 has an MDAC 4300 with open loop and a sub ADC2 (flash ADC) 4802 on. As an example, the circuit is located 4800 in the stage 2 (but the teachings are also applicable to other levels). The circuit 4800 further includes a switched capacitor circuit 4804 for injecting a charge into the switched capacitor circuit 4302 based on the linearization dither voltage V _{d2_lg} on. The linearization dither signal is injected in a hold phase and the capacitance C _{d2_lg} is connected to ground in the sampling phase. Furthermore, the linearization dither signal V _{d2_lg_flash} through a summing node 4806 in the analog input V _in2 be injected. V _{d2_lg_flash} can be equal to V _{d2_lg} × C _{d2_lg} / C ₂ . As a result, the linearization dither signal can be injected into both the MDAC and the flash ADC become. As in 48 seen, both the linearization dither and the calibration dither are connected to ground in the sampling phase, the kickback is given by: $$\begin{array}{c}{V}_{KB\_\mathrm{<figure-callout\; id="1"\; label="O\; L"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}L1}={\alpha }_{KB1}(V_{DAC2}-{\alpha }_{RST2}{V}_{\mathrm{<figure-callout\; id="2C"\; label="D\; A\; C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">D\; </figure-callout>}AC2}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}\\ +{\alpha }_{RST2}{V}_{in2}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{\mathrm{<figure-callout\; id="2C"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\frac{C_d}{}\frac{{2\_\mathrm{<figure-callout\; id="2"\; label="l\; G\; C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">l\; </figure-callout>}G}_{}}{C_{}})\end{array}$$

Therefore, the output of stage-1 is given by: $$\begin{array}{c}{V}_{Out1}\left[n\right]=V_{Out{1}_{nOmem}}\left[n\right]\\ +{\alpha }_{KB1}(V_{DAC2}\left[n-1\right]-{\alpha }_{RST2}{V}_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}\\ +{\alpha }_{RST2}{V}_{Out2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{V}_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{}})\end{array}$$

Using the LMS update equations, such as For example, in equations (24) through (25) or (26) through (27), the calibrated output is given by: $$\begin{array}{c}{V}_{Out{1}_{cal}}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\\ +{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{Out1}\left[n-1\right]{\alpha }_{m11}{V}_{Out1}\left[n-1\right]\\ -{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{d2}}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\end{array}$$

Therefore, using the IGE dither connected to ground in the sampling phase, it is possible to partially calibrate the kickback and memory terms, but a part of the quantization error kickback α _KBI V _out1q [n - 1] would remain.

und $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot \left(V_{out1}\left[n\right]-{\alpha }_{m21}\left[n\right]\cdot V_{d2}\left[n-1\right]\right)$$

If the self-memory term α _m1 , is negligible, the correlation can be performed using equations (33) and (34). This means: $$\begin{array}{c}{\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\\ \cdot \left(V_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]-{\alpha }_{m11}\left[n\right]\cdot V_{DAC2}\left[n-1\right]\right)\end{array}$$

and $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot \left(V_{Out1}\left[n\right]-{\alpha }_{m21}\left[n\right]\cdot V_{d2}\left[n-1\right]\right)$$

The correction can be performed using the following: $$\begin{array}{c}{V}_{Out{1}_{cal}}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\\ +{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{Out1}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{d2}}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\\ -{\alpha }_{m11}{V}_{DAC2}\left[n-1\right]\end{array}$$

Therefore, in the absence of self-memory at the stage 1 the IGE dither, which is in the sampling phase in the stages 1 and 2 is connected to ground, effectively eliminating all errors due to kickback from the stage 2 to the level 1 remove.

49 illustrates a circuit 4900 with both linearization and calibration dither injection, in accordance with some embodiments of the disclosure. As an example, the circuit is located 4900 in the stage 2 (but the teachings are also applicable to other levels). The circuit 4900 indicates the switched capacitor circuit 4702 for injecting a kickback calibration dither, wherein the capacitor C _d2 in the switched capacitor circuit 4702 during the sampling phase φ1 with the input V _in2 connected is. The circuit 4900 also has the switched capacitor circuit 4804 for injecting a charge into the switched capacitor circuit 4302 based on the linearization dither voltage V _{d2_lg} on, with the capacity C _{d2_lg} is connected to ground in the sampling phase φ1. The MDAC reference V _Ref can be scaled up to (C ₂ + C _{d 2)} / C ₂ in order to prevent an over range of the amplifier.

If a Kickback calibration dither is used in conjunction with a (large) linearization dither such that the calibration dither is connected to the input in the sampling phase while the large dither capacitance is C _{d2_lg} connected to ground, the kickback voltage can be given by: $$\begin{array}{c}{V}_{KB\_OL\_RST}={\alpha }_{KB}(V_{DAC}\frac{C}{C+C_d}+V_d\frac{C_d}{C+C_d}-{\alpha }_{RST}{V}_{DAC}\frac{C}{C+C_d+C_{d\_lG}+C_p}\\ +{\alpha }_{RST}{V}_{in}\frac{C+C_d}{C+C_d+C_{d\_lG}+C_p}-{\alpha }_{RST}{V}_d\frac{C_d}{C+C_d+C_{d\_lG}+C_p}\\ -{\alpha }_{RST}{V}_{d\_lG}\frac{C_{d\_lG}}{C+C_d+C_{d\_lG}+C_p})\end{array}$$

The output of stage-1 due to the memory effect of this kickback from stage-2 is given by: $$\begin{array}{c}{}_1\left[n\right]=V_{Out{1}_{nOmem}}\left[n\right]\\ +{\alpha }_{KB1}(V_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_{d2}}-{\alpha }_{RST2}{V}_{DAC2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}\\ +{\alpha }_{RST2}{V}_{Out1}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}+V_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_{d2}}\\ -{\alpha }_{RST2}{V}_{d2}\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{}})\end{array}$$

und $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot V_{out{1}_{cal}}\left[n\right]$$

The correlators of z. Equations (24) and (25) or (29a) and (30a) or the counters in (26) and (27) or (29b) and (30b) can be used to construct the KB and IME components to remove as described above: $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot V_{Out{1}_{cal}}\left[n\right]$$

and $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot V_{Out{1}_{cal}}\left[n\right]$$

However, from Equation (56), if the resetting of the summing node is not completed, the large dither coefficient may differ from that of the calibration dither. Therefore, it is preferred to have an additional correlator to effectively remove it before applying Equations (57) and (58), such that: $$\begin{array}{c}{\alpha }_{m21\_lG}\left[n+1\right]={\alpha }_{m21\_lG}\left[n\right]+\mu \cdot {\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\\ \cdot \left(V_{Out1}\left[n\right]-{\alpha }_{m21\_lG}\left[n\right]\cdot {\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\right)\end{array}$$

und $${\alpha }_{m21}\sim {\alpha }_{KB1}{C}_{d2}\left(\frac{1}{C_2+C_{d2}}-\frac{{\alpha }_{RST2}}{C_2+C_{d2}+C_{d2\_lg}+C_{p2}}\right)$$

und $${\alpha }_{m21\_lg}\sim {\alpha }_{KB1}{\alpha }_{RST2}\frac{C_{d2\_lg}}{C_2+C_{d2}+C_{d2\_lg}+C_{p2}}$$

Equation (59) correlates the linearization dither and the output of stage-1, with an estimate of the linearization dither removed. The estimate of the linearization dither is an estimate of an amount of kickback attributed to the linearization dither injected in stage-1. The memory parameters are given by the following: $${\alpha }_{m21}~{\mathrm{<figure-callout\; id="1"\; label="\alpha \; m"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_m+{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}\frac{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}$$

and $${\alpha }_{m21}~{\alpha }_{KB1}{C}_{d2}\left(\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_{d2}}-\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\right)$$

and $${\alpha }_{m21\_lG}~{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{}}$$

und $$\begin{array}{c}{V}_{out\_KB}\left[n\right]=V_{out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{C_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\\ -{\alpha }_{m21\_lg}{V}_{d2\_lg}\left[n-1\right]\end{array}$$

The corrected output is given by: $$\begin{array}{c}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]-{\alpha }_{m11}{V}_{Out1}\left[n-1\right]\\ -{\alpha }_{m21\_l\mathrm{<figure-callout\; id="2"\; label="G\; V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">G\; </figure-callout>}}{V}_d{2\_lG}_{}\left[n-1\right]\end{array}$$

and $$\begin{array}{c}{V}_{Out\_KB}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\\ -{\alpha }_{m21\_l\mathrm{<figure-callout\; id="2"\; label="G\; V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">G\; </figure-callout>}}{V}_d{2\_lG}_{}\left[n-1\right]\end{array}$$

The calibrated output V _{out1 cal} can then be substituted into equations (57) and (58).

Therefore, all memory and kickback components can be effectively removed. The costs are in an additional correlator (or counter). The following sections describe a procedure that does not require the additional counter.

50 illustrates a circuit 5000 with both linearization and calibration dither injection, in accordance with some embodiments of the disclosure. As an example, the circuit is located 5000 in the stage 2 (but the teachings are also applicable to other levels). The circuit 5000 indicates the switched capacitor circuit 4702 for injecting a kickback calibration dither, where the capacitor C _d2 in the switched capacitor circuit 4702 during the sampling phase φ1 with the input V _in2 connected is. The circuit 5000 also has the switched capacitor circuit 5002 for injecting a charge into the switched capacitor circuit 4302 based on the linearization dither voltage V _{d2_lg} on, with the capacity C _{d2_lg} during the sampling phase φ1 with the input V _in2 connected is.

If both the (large) linearization dither and the calibration dither are connected to the input during the sampling phase, the analysis for Kickback and Memory may be different. More specifically, the correction can be performed without the need for an additional correlator, as previously discussed. For the implementation of in 50 The large and calibration dither injection seen is the kickback voltage given by the following: $$\begin{array}{c}{V}_{KB\_\mathrm{<figure-callout\; id="1"\; label="O\; L"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}L1}={\alpha }_{KB1}(V_{\mathrm{<figure-callout\; id="2C"\; label="D\; A\; C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">D\; </figure-callout>}AC2}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}+{\mathrm{<figure-callout\; id="2C"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}\\ +{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\frac{C_d}{}\frac{{2\_\mathrm{<figure-callout\; id="2"\; label="l\; G\; C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">l\; </figure-callout>}G}_{}}{C_{}}-{\alpha }_{RST2}{V}_{\mathrm{<figure-callout\; id="2C"\; label="D\; A\; C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">D\; </figure-callout>}AC2}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{\mathrm{<figure-callout\; id="2C"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\\ -{\alpha }_{RST2}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\frac{C_d}{}\frac{{2\_\mathrm{<figure-callout\; id="2"\; label="l\; G\; C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">l\; </figure-callout>}G}_{}}{C_{}}\\ +{\alpha }_{RST2}{V}_{in2}\frac{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{}})\end{array}$$

Therefore, the output of stage-1 is given by: $$\begin{array}{c}{}_{ut1}\left[n\right]=V_{Out{1}_{nOmem}}\left[n\right]+{\alpha }_{m1}{V}_{Out1}\left[n-1\right]\\ +{\alpha }_{KB1}({\alpha }_{RST2}{V}_{Out1}\left[n-1\right]\frac{C_2+C_{d2}+C_{d2\_lG}}{C_2+C_{d2}+C_{d2\_lG}+C_{p2}}\\ +V_{DAC2}\left[n-1\right]\frac{C_2}{C_2+C_{d2}+C_{d2\_lG}}+V_{d2}\left[n-1\right]\frac{C_{d2}}{C_2+C_{d2}+C_{d2\_lG}}\\ +V_{d2\_lG}\left[n-1\right]\frac{C_{d2\_lG}}{C_2+C_{d2}+C_{d2\_lG}}\\ -{\alpha }_{RST2}{V}_{DAC2}\left[n-1\right]\frac{C_2}{C_2+C_{d2}+C_{d2\_lG}+C_{p2}}\\ -{\alpha }_{RST2}{V}_{d2}\left[n-1\right]\frac{C_{d2}}{C_2+C_{d2}+C_{d2\_lG}+C_{p2}}\\ +{\alpha }_{RST2}{V}_{d2\_lG}\left[n-1\right]\frac{C_{d2\_lG}}{C_2+C_{d2}+C_{d2\_lG}+C_{p2}})\end{array}$$

und $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot V_{out{1}_{cal}}\left[n\right]$$

The correlation is then performed similarly to equations (29a) and (30a), so that: $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\cdot V_{Out{1}_{cal}}\left[n\right]$$

and $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot V_{Out{1}_{cal}}\left[n\right]$$

und $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d1}\left[n-1\right]\right)\cdot \text{sgn}\left(V_{out{1}_{cal}}\left[n\right]\right)$$

Equations (29b) and (30b) can also be used as follows: $${\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d2}\left[n-1\right]\right)\cdot \text{sgn}\left(V_{Out{1}_{cal}}\left[n\right]\right)$$

and $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot \text{sgn}\left(V_{d1}\left[n-1\right]\right)\cdot \text{sgn}\left(V_{Out{1}_{cal}}\left[n\right]\right)$$

und $$\begin{array}{c}{}_l\left[n\right]=V_{out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{C_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]-{\alpha }_{m11}{V}_{out1}\left[n-1\right]\\ -{\alpha }_{m21}\frac{C_{d2\_lg}}{C_{d2}}{V}_{d2\_lg}\left[n-1\right]\end{array}$$

The coefficient α _m21 is subtracted to subtract the large dither with the appropriate capacitive scaling in addition to the KB components, giving the following: $$\begin{array}{c}{V}_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]\\ -{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{d2}}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\end{array}$$

and $$\begin{array}{c}{}_l\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m21}{V}_{d2}\left[n-1\right]-{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2}\left[n-1\right]-{\alpha }_{m11}{V}_{Out1}\left[n-1\right]\\ -{\alpha }_{m21}\frac{{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_{d2}}{\mathrm{<figure-callout\; id="2"\; label="V\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_d\left[n-1\right]\end{array}$$

und $${\alpha }_{m21}\sim {\alpha }_{KB1}{C}_{d2}\left(\frac{1}{C_2+C_{d2}}-\frac{{\alpha }_{RST2}}{C_2+C_{d2}+C_{d2\_lg}+C_{p2}}\right)$$

The convergence parameters are similar to equations (44) and (45): $${\alpha }_{m11}~{\mathrm{<figure-callout\; id="1"\; label="\alpha \; m"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_m+{\mathrm{<figure-callout\; id="1"\; label="\alpha \; K\; B"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">\alpha \; </figure-callout>}}_{KB}{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}\frac{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; p"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_p}$$

and $${\alpha }_{m21}~{\alpha }_{KB1}{C}_{d2}\left(\frac{1}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_{d2}}-\frac{{\alpha }_{\mathrm{<figure-callout\; id="2C"\; label="R\; S\; T"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">R\; </figure-callout>}ST2}}{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+{\mathrm{<figure-callout\; id="2"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d+C_{p2}}\right)$$

In addition to its effectiveness in removing the error components, this structure has a noise advantage, as previously discussed. Since both the dithers and the input capacitances sample the input, the input-related noise is improved. The noise is improved even if the total sampling capacity is not increased. To fully exploit this noise enhancement while avoiding over-range of the amplifier, the DAC reference voltage can be increased by the same factor. That is, if the entire sampling capacitor is held at C: $$\frac{v_{nKB}^2}{v_{n\mathrm{<figure-callout\; id="2"\; label="I\; G\; e"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">I\; </figure-callout>}Ge}^2}~\frac{C+C_p}{C+C_p+C_d+C_{d\_lG}}$$

ist die Rauschleistung unter Verwendung des KB-Dithers (das während der Abtastphase mit dem Eingang verbunden ist), $v_{nIGE}^2$

ist die Rauschleistung unter Verwendung des IGE-Dithers (das während der Abtastphase mit Masse verbunden ist). Der Referenzwert muss um denselben Faktor heraufskaliert werden: $$\frac{V_{Ref\_KB}}{V_{Ref\_IGE}}\sim \frac{C+C_d+C_{d\_lg}}{C}$$

$v_{\mathrm{<figure-callout\; id="2"\; label="n\; K\; B"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">n\; </figure-callout>}KB}^2$

is the noise power using the KB dither (which is connected to the input during the sampling phase), $v_{n\mathrm{<figure-callout\; id="2"\; label="I\; G\; e"\; filenames="DE102019107170A1\_0102.png,DE102019107170A1\_0103.png"\; state="\{\{state\}\}">I\; </figure-callout>}Ge}^2$

is the noise power using the IGE dither (which is grounded during the sampling phase). The reference value must be scaled up by the same factor: $$\frac{V_{Ref\_KB}}{V_{Ref\_IGe}}~\frac{C+C_d+C_{d\_lG}}{C}$$

Referring again to 50 can be the MDAC reference V _{RefF scaled} up (C ₂ + C _d2 + C _{d2_lg} ) / C ₂ to prevent the range from exceeding the amplifier.

Sharing an amplifier

An advantage of the open-loop amplifier structures described herein is that sharing of the amplifier between multiple stages and / or slices of an ADC is simplified.

51 FIG. 12 illustrates sharing of an amplifier between multiple stages of a pipeline ADC, in accordance with some embodiments of the disclosure. A circuit 5100 has two levels, Level 1 and level 2 where both stages are the same amplifier 5102 use with open loop. The stage- 1 is to receive and sample an analog input signal from the pipeline ADC. The stage- 2 should this be in the 1 receive and sample generated amplified residual signal. The amplifier 5102 Open loop may be implemented with the open loop amplifiers described herein. Similar to other MDAC circuits described herein, the stage 1 a switched capacitor circuit 5104 for performing sample and DAC operations on and the stage 2 has a switched capacitor circuit 5106 for performing sample and DAC operations. The stage- 1 is a sampling of the analog input signal (eg. V _inp and V _inn ) and is to perform a digital-to-analog conversion (based on output bits of a DAC in the 1 ) carry out. The stage- 1 should be a sample of the amplified residual signal of the stage 1 (eg V _outp1 and V _outn1 ) and is to perform a digital-to-analog conversion (based on output bits of a DAC in the 2 ) carry out. The switched capacitor circuit 5104 generates a first residual signal for the stage 1 to the summation node 5120A and 5120b , The switched capacitor circuit 5106 generates a second residual signal for the stage 2 to the summation node 5122a and 5122b , The shared amplifier 5102 with an open loop reinforces this in the stage 1 generated first residual signal during a first period. The amplifier 5102 open loop generates a first amplified residual signal, ie V _outp1 and V _outn1 , The shared amplifier 5102 with an open loop reinforces this in the stage 2 generated second residual signal during a second / other period. The amplifier 5102 open-loop generates a second amplified residual signal, ie V _outp2 and V _outn2 ,

The switched capacitor circuit 5104 comprises a first set of sampling capacitors, which in this example is referred to as ( C _i -C1) × 8 are shown. The switched capacitor circuit 5106 comprises a second set of sampling capacitors which are known as ( C _i -C2) × 8 are shown. The number of capacitors in each set may depend on the resolution of the ADC and DAC in the respective stages. The upper plates of the first set of sampling capacitors and the second set of sampling capacitors are selectively connected to a positive or negative voltage reference (e.g. V _{Ref / 2} or V _{Ref / 2} ) when DAC operations are performed. The lower plates of the first set of sampling capacitors ( C _i -C1) × 8 are connected to each other and form the summation nodes 5120A and 5120b , The lower plates of the second set of sampling capacitors (C _i -C 2) x 8 are connected together and form the summing nodes 5122a and 5122b ,

The switched capacitor circuit 5104 for the level 1 has input switch 5130a and 5130B which are associated with φ1 (or φ1 if the switches are in a bootstrap relationship). When they are closed, the input switches connect 5130a and 5130B the upper plates of the sampling capacitors (C _i -C1) × 8 with the inputs V _inp and V _inn , The switched capacitor circuit 5104 for the level 1 has sampling switch 5124a and 5124b which are associated with φ1a. When closed, the sampling switches connect 5124a and 5124b the lower plates of the sampling capacitors ( C _i -C1) × 8 with a common mode voltage V _cm , The sampling switches 5124a and 5124b are advanced, which means that the sampling switch 5124a and 5124b be opened before the input switch 5130a and 5130B (for example, to do a scan of the lower plate). The switched capacitor circuit 5104 also has a common mode switch 5180 which is associated with φ1a. When closed, the common mode switch connects 5180 the summation nodes 5120A and 5120b together. The switched capacitor circuit 5104 has switch 5110a and 5110B which are associated with φs1. The switches 5110a and 5110B can serve as selector switches that control whether the amplifier 5102 with open loop, the remainder signal to the summing node 5120A and 5120b strengthened. When they are closed, the switches connect 5110a and 5110B the summation nodes 5120A and 5120b with non-inverting or inverting inputs of the amplifier 5120 with open loop.

The switched capacitor circuit 5106 for the level 2 has input switch 5140A and 5140b which is associated with φ2 (or φ2btst if the switches are in a bootstrap relationship). When they are closed, the input switches connect 5140A and 5140b the upper plates of the Sampling capacitors ( C _i -C2) × 8 with the amplifier outputs V _outp1 and V _outn1 to recieve. The switched capacitor circuit 5106 for the level 2 has sampling switch 5126 and 5126b which are associated with φ2a. When closed, the sampling switches connect 5126 and 5126b the lower plates of the sampling capacitors ( C _i -C2) × 8 with a common mode voltage V _cm , The sampling switches 5126 and 5126b are advanced, which means that the sampling switch 5126 and 5126b be opened before the input switch 5140A and 5140b (for example, to do a scan of the lower plate). The switched capacitor circuit 5106 also has a common mode switch 5190 which is associated with φ2a. When closed, the common mode switch connects 5190 the summation nodes 5122a and 5122b together. The switched capacitor circuit 5106 has switch 5112a and 5112b on, which are associated with φs2. The switches 5112a and 5112b can serve as selector switches that control whether the amplifier 5102 with open loop, the remainder signal to the summing node 5122a and 5122b strengthened. When they are closed, the switches connect 5112a and 5112b the summation nodes 5122a and 5122b with non-inverting or inverting inputs of the amplifier 5120 with open loop.

The MDAC circuits in the 51 omit certain circuit details for simplicity. One skilled in the art can understand that the MDAC circuits may be implemented based on the MDAC open-loop circuits described herein (eg, including various dither injection techniques).

To the same amplifier 5102 With open loop sharing, the outputs (ie the remainder) of the switched capacitor circuit 5104 the level 1 the amplifier 5102 with open loop during a first period according to φs1 provided as inputs. The outputs (ie the remainder) from the switched capacitor circuit 5106 the level 2 be the amplifier 5102 with open loop as inputs provided to the amplifier 5102 with open loop for a second / other period according to φs2.

Switches controlled by phases φs1 (the switch 5110a and the switch 5110B at the output of the switched capacitor circuit 5104 the level 1 connecting the output to the input of the amplifier 5102 connect with open loop), and switches which are controlled by phases φs2 (the switch 5112a and the switch 5112b at the output of the switched capacitor circuit 5106 the level 2 ), manage the mutual benefit of the amplifier 5102 with open loop by coupling the appropriate signal to the inputs of the amplifier 5102 with open loop.

During the first period, the shared amplifier amplifies 5102 with open loop, the remainder signal to the summing node 5120A and 5120b , The amplified output (ie the amplified residual signal of the 1 ) at the output of the amplifier 5102 with open loop ( V _outn1 ) becomes the switched capacitor circuit 5106 the level 2 provided as inputs. The switches 5110a and 5110B are closed to the summation nodes 5120A and 5120b with inputs of the amplifier 5102 to pair with an open loop. The switches 5112a and 5112b are opened to the summation node 5122a and 5122b from inputs of the amplifier 5102 decouple with open loop.

During the second period, the shared amplifier amplifies 5102 with open loop, the remainder signal to the summing node 5122a and 5122b , The amplified output (ie the amplified residual signal of the 2 ) at the output of the amplifier 5102 with open loop ( V _outn2 ) the level 3 provided by the pipeline ADC as inputs. The switches 5112a and 5112b are closed to the summation nodes 5122a and 5122b with inputs of the amplifier 5102 to pair with an open loop. The switches 5110a and 5110B are opened to the summation node 5120A and 5120b from inputs of the amplifier 5102 decouple with open loop.

52 provides a timing diagram 5200 for the circuit 5100 from 51 According to some embodiments of the disclosure. In order to help reset the summing node, the clocks controlling the switching of the amplifier are purposely caused to overlap φs1 and φs2, the sample clocks φ1a and φ2a, respectively.

φs1 overlaps φ1a as if by a circle 5202 and a circle 5204 specified. While the switches 5110a and 5110B are closed, go the sampling switch 5124a and 5124b from open to closed over. In addition, while the switch goes 5110a and 5110B are closed, the common mode switch 5180 from open to closed over. This helps keep the input node of the amplifier 5102 with the loop open, reset to the common mode voltage before the amplifier 5102 with open Loop is used to amplify the residual signal from the 2 (before φs2 goes from low to high and the switches 5112a and 5112b closes).

φs2 overlaps φ2a as if by a circle 5206 and a circle 5208 specified. While the switches 5112a and 5112b are closed, go the sampling switch 5126 and 5126b from open to closed over. In addition, while the switch goes 5112a and 5112b are closed, the common mode switch 5190 from open to closed over. This helps keep the input node of the amplifier 5102 with the loop open, reset to the common mode voltage before the amplifier 5102 is used with an open loop to amplify the residual signal from the 1 (before φs1 goes from low to high and the switches 5110a and 5110B closes).

φ1 and φ2 can be delayed slightly further so that they overlap φ1a and φ2a, respectively. This can reset / unload summing node capacity and remove its effect on kickback.

φ1 overlaps φ1a as if by a circle 5210 and a circle 5202 specified. After the switches associated with φ1a (eg, the sampling switches 5124a and 5124b and the common mode switch 5180 ) are closed to the summation nodes 5120A and 5120b to reset to a common mode voltage, the input switches associated with φ1 become 5130a and 5130B closed. This helps to prevent kickback from sampling capacitors ( C _i -C1) × 8 and the input nodes V _inp and V _inn significantly affected by causing any capacity at the summing node 5120A and 5120b is reset or discharged before the sampling capacitors ( C _i -C1) × 8 with the input nodes V _inp and V _inn get connected.

φ2 overlaps φ2a as if by a circle 5212 and a circle 5206 specified. After the switches associated with φ2a (eg, the sampling switches 5126 and 5126b and the switch 5190 ) are closed to the summation nodes 5122a and 5122b to reset to a common mode voltage, the input switches associated with φ2 become 5140A and 5140b closed. This helps to prevent kickback the sampling capacitors (C _i -C 2) x 8 and the input nodes (as V _outp1,2 and V _outn1,2 designated) by causing any capacity at the summing node 5122a and 5122b is reset or discharged before the sampling capacitors (C _i -C 2) × 8 with the input nodes (as V _outp1,2 and V _outn1,2 to be connected).

Using the IME and KB calibrations described above, resetting the output of the amplifier between phases can be eliminated. A calibration dither may be injected into stage-1 and an additional calibration dither may be injected into stage-2. The dithers can be used to extract kickback and memory errors affecting the first stage and the second stage. In some cases, a linearization dither may be injected into stage-2 (in both the MDAC and the sub-ADC). This reduces the timing performance that has been a disadvantage of sharing amplifiers. The effect of the memory error, if the amplifier is shared, can be given by: $$\begin{array}{c}{V}_{Out1}\left[n\right]=V_{Out{1}_{nOmem}}\left[n\right]\\ +{\alpha }_{KB1}\left(V_{Out1}\left[n-1\right]-{\alpha }_{q2}{V}_{Outq1}\left[n-1\right]+{\alpha }_{d2}{V}_{d2}\left[n-1\right]\right)\\ -{\alpha }_{21}{V}_{Out2}\left[n-1\right]\end{array}$$

Likewise, the output of stage-2 may have a memory component due to the kickback from stage-3 plus another component due to the sharing of the amplifier between stage-1 and stage-2. This is represented as follows: $$\begin{array}{c}{V}_{Out2}\left[n\right]=V_{Out{2}_{nOmem}}\left[n\right]\\ +{\alpha }_{KB2}\left(V_{Out2}\left[n-1\right]-{\alpha }_{q3}{V}_{Outq2}\left[n-1\right]+{\alpha }_{d3}{V}_{d3}\left[n-1\right]\right)\\ +{\alpha }_{12}{V}_{Out1}\left[n\right]\end{array}$$

These equations describe the approximate behavior of the kickback and memory terms due to kickback and sharing of the amplifier. Using IME and KB calibrations as described above, these terms can be eliminated. Since the "Memory" effect of level-1 on Stage-2 is present due to the current Stage 1 scan V _out1 [n] in equation (78) instead of V _out1 [n-1] in front. Therefore, the effect of sharing the amplifier from stage-1 at stage-2 appears as a gain error term that can be detected by stage I-1 IGE calibration.

und $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot \left(V_{out1}\left[n\right]-{\alpha }_{m11}\left[n\right]\cdot V_{DAC2}\left[n-1\right]\right)$$

To remove the memory and kickback terms in (77) and (78) with amplifier sharing, only two correlators are needed, which may be the same correlators given by equations (24) and (25) , This means: $$\begin{array}{c}{\alpha }_{m21}\left[n+1\right]={\alpha }_{m21}\left[n\right]+\mu \cdot V_{d2}\left[n-1\right]\\ \cdot \left(V_{\mathrm{<figure-callout\; id="1"\; label="O\; u\; t"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">O\; </figure-callout>}ut1\_KB}\left[n\right]-{\alpha }_{m21}\left[n\right]\cdot V_{Out2}\left[n-1\right]\right)\end{array}$$

and $${\alpha }_{m11}\left[n+1\right]={\alpha }_{m11}\left[n\right]+\mu \cdot V_{d1}\left[n-1\right]\cdot \left(V_{Out1}\left[n\right]-{\alpha }_{m11}\left[n\right]\cdot V_{DAC2}\left[n-1\right]\right)$$

The term α _m11 which is used to describe level 1 "self-memory" now describes the kickback memory term in level-1 output from level-2. Any remaining memory at the output of level-1 may be due to the memory of V _out2 be present and can through α _m21 , because the remainder of the memory that exists due to kickback is effectively removed α _m11 has been removed.

If IGE dither is used (which is connected to ground during the sampling phase), the corrected level 1 output can be given by: $$V_{Out{1}_{cal}}\left[n\right]=V_{Out1}\left[n\right]-{\alpha }_{m11}{V}_{DAC2}\left[n\right]-{\alpha }_{m21}{V}_{Out2}\left[n-1\right]$$

If KB Dither is used (which is connected to the input during the sampling phase), the corrected Level 1 output can be given by: $$\begin{array}{l}{V}_{Out{1}_{cal}}\left[n\right]\hfill \\ =V_{Out1}\left[n\right]-{\alpha }_{m11}{V}_{DAC2}\left[n\right]-{\alpha }_{m11}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C\; d"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C\; </figure-callout>}}_d}{C_2}{V}_{d2}\left[n-1\right]\hfill \\ -{\alpha }_{m21}{V}_{Out2}\left[n-1\right]\hfill \end{array}$$

und $$V_{out2}\left[n\right]\sim V_{out{2}_{nomen}}\left[n\right]+{\alpha }_{KB2}{V}_{out2}\left[n-1\right]+{\alpha }_{12}{V}_{out1}\left[n\right]$$

If the quantization and dither components are negligible, equations (77) and (78) can be reduced to: $$V_{Out1}\left[n\right]~V_{Out{1}_{nOmen}}\left[n\right]+{\alpha }_{KB1}{V}_{Out1}\left[n-1\right]+{\alpha }_{21}{V}_{Out2}\left[n-1\right]$$

and $$V_{Out2}\left[n\right]~V_{Out{2}_{nOmen}}\left[n\right]+{\alpha }_{KB2}{V}_{Out2}\left[n-1\right]+{\alpha }_{12}{V}_{Out1}\left[n\right]$$

Therefore, it is possible to remove any memory, kickback, or gain errors in the MDAC open-loop structure without any additional complexity. In fact, the complexity may be lower compared to closed loop amplifiers. In addition, any memory errors due to shared use of amplifiers can be calibrated without additional complexity.

In some embodiments, sharing of amplifiers may take place between different slices of a time-interleaved ADC. Different slices of a time-interleaved ADC sample the analog input sequentially to increase the overall sampling rate of the ADC. 53 FIG. 10 illustrates an amplifier sharing different open-loop MDACs of a time-interleaved ADC according to some embodiments of the disclosure. FIG. A circuit 5300 has a switched capacitor circuit 5304 in a level 1 from a first slice / ADC of a time-interleaved ADC and a switched capacitor circuit 5306 in a level 1 from a second slice / ADC of the time-interleaved ADC, where both stages of different slices of the time-interleaved ADC have the same amplifier 5302 use with open loop. The amplifier 5302 Open loop may be implemented with the open loop amplifiers described herein. Similar to the other MDAC circuits described herein, both the switched capacitor circuit 5304 as well as the switched capacitor circuit 5306 Scanning and DAC operations. The MDAC circuits in the 53 omit certain circuit details for simplicity. One skilled in the art can understand that the MDAC circuits may be implemented based on the MDAC open-loop circuits described herein (eg, including various dither injection techniques). Furthermore, a person skilled in the art can see that the sharing of amplifiers for other stages (in addition to the stage 1 ) between different slices of a time-interleaved ADC.

Switches controlled by phases φss1 (the switch 5310a and the switch 5310b at the output of the switched capacitor circuit 5304 connecting the output to the input of the amplifier 5302 connect with open loop), and switches controlled by phases φss2 (the switch 5312a and the switch 5312b at the output of the switched capacitor circuit 5304 ), manage the mutual benefit of the amplifier 5302 with an open loop by coupling the appropriate signal to the input of the amplifier 5302 with open loop.

To the same amplifier 5302 with open loop, the outputs (ie the residual signal for the stage 1 the first slice / ADC) from the switched capacitor circuit 5304 (according to a phase φss1) as inputs to the amplifier 5302 provided with an open loop. When they are closed, the switches connect 5310a and 5310b Summing node of the switched capacitor circuit 5304 with inputs of the amplifier 5302 with open loop. The amplifier 5302 with open loop generates an amplified residual signal for the stage 1 of the first slice / ADC, e.g. B. V _outp1 and V _outn1 , The outputs (ie the residual signal for the stage 1 second slice / ADC) from the switched capacitor circuit 5306 the level 1 be as inputs in the amplifier 5302 provided with open loop to the amplifier 5302 to reuse with open loop (during another period according to the phase φss2). When they are closed, the switches connect 5312a and 5312b Summing node of the switched capacitor circuit 5306 with inputs of the amplifier 5302 with open loop. The amplifier 5302 with open loop generates an amplified residual signal for the stage 1 of the second slice / ADC, e.g. B. V _outp2 and V _outn2 ,

The shared amplifier 5302 with open loop, the output ({ V _outp1 and V _outn1 } or { V _outp2 and V _outn2 }) provide another circuit which would process the different amplified residual signals.

In this scenario, the analysis is similar to the previous case of sharing a level of 51 , but the memory elements come from the outputs of different slices.

The effect of the memory, if the amplifier is shared between slices, is given by: $$\begin{array}{c}{V}_{Out1s1}\left[n\right]=V_{Out1s{1}_{nOmem}}\left[n\right]\\ +{\alpha }_{KB1s1}\left(V_{Out1s1}\left[n-1\right]-{\alpha }_{q2s1}{V}_{Outq1s1}\left[n-1\right]+{\alpha }_{d2s1}{V}_{d2s1}\left[n-1\right]\right)\\ +{\alpha }_{s21}{V}_{Out1s2}\left[n-1\right]\end{array}$$

Similarly, the output of stage-1 at the second slice may have a memory component due to its stage-2 kickback plus another component due to the sharing of the amplifier between the slices. This is represented as follows: $$\begin{array}{c}{V}_{Out1s2}\left[n\right]=V_{Out1s{2}_{nOmem}}\left[n\right]\\ +{\alpha }_{KB1s2}\left(V_{Out1s2}\left[n-1\right]-{\alpha }_{q2s2}{V}_{Outq1s2}\left[n-1\right]+{\alpha }_{d2s2}{V}_{d2s2}\left[n-1\right]\right)\\ +{\alpha }_{s12}{V}_{Out1s1}\left[n-1\right]\end{array}$$

The suffix " s1 "Denotes slice-1 and" s2 "Means slice-2. These equations (85) and (86) describe the approximate behavior of the kickback and memory terms due to kickback and sharing of the amplifier between slices.

A calibration dither can be placed in the switched capacitor circuit 5304 An additional calibration dither can be injected into the switched capacitor circuit 5306 be injected. The dithers can be used to extract kickback and memory errors affecting the switched capacitor circuit and the second stage.

und $$\begin{array}{c}{\alpha }_{m11s1}\left[n+1\right]={\alpha }_{m11s1}\left[n\right]+\mu \cdot V_{d1s1}\left[n-1\right]\\ \cdot \left(V_{out1s1\_KB}\left[n\right]-{\alpha }_{m11s1}\left[n\right]\cdot V_{out1s1}\left[n-1\right]\right)\end{array}$$

To use the memory and kickback terms in ( 85 ) and ( 86 ) with a shared use of an amplifier, the same two correlators are needed for each slice. For slice-1, these are given by: $$\begin{array}{c}{\alpha }_{m21s1}\left[n+1\right]={\alpha }_{m21s1}\left[n\right]+\mu \cdot V_{d2s1}\left[n-1\right]\\ \cdot \left(V_{Out1s1}\left[n\right]-{\alpha }_{m21s1}\left[n\right]\cdot V_{d2s1}\left[n-1\right]\right)\end{array}$$

and $$\begin{array}{c}{\alpha }_{m11s1}\left[n+1\right]={\alpha }_{m11s1}\left[n\right]+\mu \cdot V_{d1s1}\left[n-1\right]\\ \cdot \left(V_{Out1\mathrm{<figure-callout\; id="1"\; label="s"\; filenames="DE102019107170A1\_0104.png,DE102019107170A1\_0106.png"\; state="\{\{state\}\}">s</figure-callout>}1\_KB}\left[n\right]-{\alpha }_{m11s1}\left[n\right]\cdot V_{Out1s1}\left[n-1\right]\right)\end{array}$$

und für Slice-2: $$\begin{array}{c}{\alpha }_{ms12}\left[n+1\right]={\alpha }_{ms12}\left[n\right]+\mu \cdot V_{d1s1}\left[n-1\right]\\ \cdot \left(V_{out1s2}\left[n\right]-{\alpha }_{ms12}\left[n\right]\cdot V_{out1s1}\left[n-1\right]\right)\end{array}$$

Additionally, one correlator is needed for each slice to capture the inter-slice coupling. Therefore, to capture a coupling from slice-2 to slice-1: $$\begin{array}{c}{\alpha }_{ms21}\left[n+1\right]={\alpha }_{ms21}\left[n\right]+\mu \cdot V_{d1s2}\left[n-1\right]\\ \cdot \left(V_{Out1s1}\left[n\right]-{\alpha }_{ms21}\left[n\right]\cdot V_{Out1s2}\left[n-1\right]\right)\end{array}$$

and for slice-2: $$\begin{array}{c}{\alpha }_{ms12}\left[n+1\right]={\alpha }_{ms12}\left[n\right]+\mu \cdot V_{d1s1}\left[n-1\right]\\ \cdot \left(V_{Out1s2}\left[n\right]-{\alpha }_{ms12}\left[n\right]\cdot V_{Out1s1}\left[n-1\right]\right)\end{array}$$

V _d2s2 is the level 1 dither in slice-2, V _d1s1 is the level-1 dither in slice-1, V _out1s1 is the output of level-1 in slice-1 and V _out1s2 is the output of level-1 in slice-2.

If a KB calibration dither is used (connected to the input during the sampling phase), the corrected Level 1 output is given by: $$\begin{array}{c}{}_{ut1s{1}_{cal}}\left[n\right]=V_{Out1s1}\left[n\right]-{\alpha }_{m21s1}{V}_{d2s1}\left[n-1\right]-{\alpha }_{m21s1}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2s1}\left[n-1\right]\\ -{\alpha }_{ms21}{V}_{Out1s2}\left[n-1\right]\end{array}$$

This applies equally to level 2. The corrected output is given by: $$\begin{array}{c}{}_{ut1s{2}_{cal}}\left[n\right]=V_{Out1s2}\left[n\right]-{\alpha }_{m21s2}{V}_{d2s2}\left[n-1\right]-{\alpha }_{m21\mathrm{<figure-callout\; id="2C"\; label="s"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">s</figure-callout>}2}\frac{{\mathrm{<figure-callout\; id="2C"\; label="C"\; filenames="DE102019107170A1\_0102.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}{C_{d2}}{V}_{DAC2s2}\left[n-1\right]\\ -{\alpha }_{ms12}{V}_{Out1s1}\left[n-1\right]\end{array}$$

Therefore, the same two correlators can be used for each slice to detect the kickback at each stage of the following stage in the same slice, and an additional correlator can be used to detect the coupling between the slices.

Further variations on the open-loop amplifier

55 represents another example amplifier 5500 with open loop according to some embodiments of the disclosure. The amplifier 5500 with open loop represents the amplifier 700 with open loop with capacitive loads (as C _L designated) at each differential output node V _outn and V _outp Specifically, there is a first capacitor C _L between the differential output node V _outn and ground and a second capacitor C _L is located between the second differential output node V _outp and mass. With a load resistor, z. B. R _L , the amplifier behaves 5500 with an open loop like a "settling" amplifier, where the gain of the amplifier 5500 with open loop through g _m * R _L ie a transconductance g _m multiplied by the load resistance R _L , is determined.

56 represents an exemplary integration amplifier 5600 with open loop according to some embodiments of the disclosure. The amplifier 5500 with open loop represents a modified version of the amplifier 5500 with open loop without the load resistance (eg the in 55 seen R _L ). The amplifier 5600 with open loop has capacitive loads (as C _L designated) at each differential output node V _outn and V _outp on. More precisely, there is a first capacitor C _L between the differential output node V _outn and ground and a second capacitor C _L is located between the second differential output node V _outp and mass. Without a load resistance behaves the amplifier 5600 with an open loop as an "integrating" or "dynamic" amplifier, where the gain of the amplifier 5600 with open loop through g _m * T * C _L ie a transconductance g _m multiplied by an integration time T and divided by the load capacity C _L , is determined.

In comparison, the amplifier can 5600 with open loop for the same current a final output much faster than the amplifier 5500 reach with open loop. In addition, the amplifier can 5600 with open loop for a much lower current, a final output value at the same time as the amplifier 5500 reach with open loop.

The integration amplifier 5600 with open loop, ie the lessons of removing the load resistance R _L , may be combined with any of the embodiments and teachings described herein (eg, transistor as load with analog tracking and distortion cancellation, dither injection, calibration, gain adaptation, amplifier sharing, etc.).

Technical advantages

As shown herein, improved open loop MDAC circuits may be implemented in pipeline ADCs. Nonlinear calibration, analog calibration, IGE, IME, and kickback calibration can be included if required. The analog circuit for the described open-loop amplifier is programmable for gain adaptation and may include various analog circuits for improving the performance of the open-loop amplifier. The open-loop amplifiers can benefit from lower power consumption, smaller size, and lower complexity without the penalty of calibrations.

In addition to improving the MDACs of pipeline ADCs, the present disclosure describes integrating an open loop amplifier in the front end of an ADC and using the open loop amplifier in a continuous time fashion (without associated switched capacitor circuits). An open loop amplifier may be included before the T / H circuit as a variable gain amplifier. Advantages and implications of providing the open loop amplifier as a variable gain amplifier with respect to 39 explained. In addition, an open-loop amplifier can be implemented in a T / H circuit in the frontend. Optionally, a variable attenuator may be included in front of the variable gain amplifier for coarse gain adjustment.

In some cases, an IGE calibration algorithm may be used to feed back a control signal that controls the gain of the open loop amplifier by controlling it g _m , its output resistance and / or the reference (reference voltages used in the DAC operations) optimized.

The calibration of the non-linearity of the open-loop amplifier in this context and the techniques used for the non-linear calibration have been shown effective in the present disclosure in the presence of non-ideal states in the following stages. Certain measures relating to a dither injection are used to ensure that the calibration can be carried out effectively.

Furthermore, the present disclosure describes certain techniques for effectively correcting IGE, IME and kickback errors in MDACs with open loop, e.g. B. dither injection techniques and correlators.

A common usage structure of an open loop amplifier that relies on interstage memory and kickback calibration while minimizing memory errors through calibration and timing optimization. Sharing may occur between two consecutive stages in the same ADC slice or between the same stages in multiple ADC slices of a nested ADC.

It should be noted that many of the open-loop amplifiers described herein do not require a negative supply (thereby reducing power consumption). Furthermore, in some cases no frequency-dependent non-linear calibration is needed, e.g. When the open loop amplifier is used without associated switched capacitor circuits.

The teachings of various parts of a transducer system of the present disclosure can achieve many advantages at the system level. 54 provides a transducer system 5400 According to some embodiments of the disclosure. The converter system 5400 has an amplifier 5402 with variable gain, an ADC 5404 (eg, a pipeline ADC with open-loop MDACs) and a digital calibration block 5406 on. The amplifier 5402 variable gain amplification is implemented based on the open-loop amplifiers described herein. The amplifier 5402 Variable gain can be an analog tracking circuit 5408 (through the 31-32 illustrated), for the purpose of an analog linearization (ie, to improve the performance of the amplifier 5402 with variable gain by analog circuit techniques) can serve. Using an open-loop amplifier in a time-continuous domain without an associated switched capacitor circuit as the amplifier 5402 Variable gain means that frequency-dependent calibrations are no longer required. Calibration techniques in the digital domain through the digital calibration block 5406 (eg, nonlinear IGE, IME, KB calibrations described herein to extract errors and correct the digital output code) may also improve the performance of the amplifier 5402 with variable gain and any open-loop amplifier in the ADC 5404 improve. In some cases, mixed signal linearization techniques may be supported by the digital calibration block 5406 , can be used to adjust an analog circuit (eg, variable attenuator circuits and open loop amplifiers), thus also improving the performance of the entire converter system. For example, calibration techniques may tune the analog circuit, e.g. By directly adjusting the gain in the analog circuit using a control signal generated based on a gain error calculated in the digital domain.

Examples

Example 1 is an open-loop amplifier, comprising: a differential pair of input transistors for receiving differential inputs at respective gates of the differential pair of input transistors; a first current source for providing a current to the open-loop amplifier; an active load on differential output nodes of the open-loop amplifier; and a load resistor at the differential output node of the open-loop amplifier.

In Example 2, the open loop amplifier of Example 1 may optionally include the load resistor having a load resistance across the differential output nodes of the open loop amplifier.

In Example 3, the open loop amplifier of any of Examples 1-2 may optionally include the load resistor having a load transistor across the differential output nodes of the open loop amplifier.

In Example 4, the open loop amplifier of any of Examples 1-4 may optionally include the load resistor having a load resistor across the differential output nodes of the open loop amplifier and a load transistor in parallel with the resistor.

In Example 5, the open-loop amplifier of any of Examples 3 or 4 may optionally include driving the load transistor through a gate voltage to operate the load transistor in a linear region.

In Example 6, the open-loop amplifier of any one of Examples 3-5 may optionally include an analog tracking circuit to generate a gate voltage for driving the load transistor.

In Example 7, the open loop amplifier of Example 6 may optionally include the analog tracking circuit performing analog temperature tracking and adjusting the gate voltage based on the analog tracking of the temperature.

In Example 8, the open loop amplifier of Example 6 or 7 may optionally include the analog tracking circuit tracking a bias current setting in the open loop amplifier and adjusting the gate voltage based on the bias current setting.

In Example 9, the open loop amplifier of any of Examples 6-8 may optionally include the analog tracking circuit tracking a temperature variation and adjusting the gate voltage based on the temperature variation.

In Example 10, the open-loop amplifier of any of Examples 1-9 may optionally include the load resistor having two series load resistors, wherein a node between the two series load resistors is connected to a first differential output node of the open loop amplifier.

In Example 11, the open-loop amplifier of Example 10 may optionally include: a first of the two series load resistors connected to supply; and a second of the two series load resistors is connected to ground.

In Example 12, the open loop amplifier of Example 10 may optionally include: a first of the two series load resistors connected to a common mode voltage; and a second of the two series load resistors is connected to the common mode voltage.

In Example 13, the open-loop amplifier of Example 10 may optionally include: the two series load resistors have transistors operating in a linear region.

In Example 14, the open loop amplifier of any of Examples 1-13 may optionally include cascoding the differential pair of input transistors through a pair of cascode transistors.

In Example 15, the open-loop amplifier of any of Examples 1-14 may optionally include the active load having a first transistor and a second transistor respectively at the differential output node, the first and second transistors having gates connected through a first transistor Bias biased.

In Example 16, the open loop amplifier of Example 15 may optionally include the first transistor and the second transistor being cascoded by a pair of cascode transistors.

In Example 17, the open-loop amplifier of any one of Examples 1-16 may optionally include: level shifters for converting a level of the differential inputs and driving the gates of the differential pair of input transistors.

In Example 18, the open-loop amplifier of any of Examples 1-17 may optionally include: gain-boosting transistors at the differential output nodes of the open-loop amplifier, with gates of the boosting transistors cross-coupled to the differential output nodes of the open-loop amplifier.

In Example 19, the open loop amplifier of any of Examples 1-18 may optionally include source followers for buffering the differential inputs before providing the buffered differential inputs to the gates of the differential pair of input transistors.

In Example 20, the open-loop amplifier of any of Examples 1-19 may optionally include: cross-coupled transistors at sources of the differential pair of input transistors, wherein gates of the cross-coupled transistors are cross-coupled to the gates of the differential pair of input transistors.

In Example 21, the open loop amplifier of any of Examples 1-20 may optionally include: a dither injection circuit at the differential output node of the open loop amplifier.

In Example 22, the open loop amplifier of any of Examples 1-21 may optionally include: a differential pair of dither transistors each coupled to the differential output node of the open loop amplifier, wherein gates of the differential pair of dither transistors are differentially coupled Be controlled dither signal; and a current source transistor to provide the differential output node with a current to be injected.

Example 23 is an open-loop amplifier comprising: a first pair of input transistors for receiving differential inputs at respective gates of the first pair of input transistors; a second pair of input transistors complementary to the first differential pair of transistors for receiving differential inputs on respective gates of the second pair of input transistors; a first current source at terminals of the first pair of input transistors for providing a current to the open loop amplifier; and a load resistor at the differential output node of the open-loop amplifier.

In Example 24, the open-loop amplifier of Example 23 may optionally include the load resistor having a load resistance element.

In Example 25, the open loop amplifier of Example 23 or 24 may optionally include the load resistor comprising: a first load transistor of a first type across the differential output nodes of the open loop amplifier and a second load transistor of a second type of the first type different, parallel to the first load transistor.

In Example 26, the open-loop amplifier of Example 25 may optionally include controlling the first load transistor and the second load transistor to operate in a linear region.

In example 27, the open-loop amplifier of example 25 or 26 may optionally include: an analog tracking circuit for generating a gate voltage to drive the first load transistor and the second load transistor, wherein the gate voltage changes in one or more the following tracks: process, voltage, temperature and gain setting of the open-loop amplifier.

In Example 28, the open loop amplifier of any of Examples 23-27 may optionally include the load resistor having two series load resistors, with one node between the two series load resistors connected to a first differential output node of the open loop amplifier.

In Example 29, the open-loop amplifier of Example 28 may optionally include: a first of the two series load resistors connected to supply; and a second of the two series load resistors is connected to ground.

In Example 30, the open loop amplifier of Example 28 may optionally include: a first of the two series load resistors connected to a common mode voltage; and a second of the two series load resistors is connected to the common mode voltage.

In example 31, the open-loop amplifier of example 28 may optionally include the two series load resistors having transistors operating in a linear region.

In example 32, the open loop amplifier of one of examples 23-31 may optionally include cascoding the first pair of input transistors through a pair of cascode transistors.

In Example 33, the open-loop amplifier of one of Examples 23-32 may optionally include that the second pair of input transistors is cascoded by a pair of cascode transistors.

In Example 34, the open loop amplifier of any of Examples 23-33 may optionally include: a second current source at terminals of the second pair of input transistors to provide power to the open loop amplifier.

In Example 35, the open-loop amplifier of any of Examples 23-34 may optionally include: first level shifters for converting a level of the differential inputs and driving the gates of the first pair of input transistors.

In Example 36, the open-loop amplifier of any of Examples 23-35 may optionally include: second level shifters for converting a level of the differential inputs and driving the gates of the second pair of input transistors.

In Example 37, the open-loop amplifier of any of Examples 23-36 may optionally include: the first current source having first and second current transistors connected to respective terminals of the first pair of input transistors; and a resistor coupled across the terminals of the first pair of input transistors.

Example 38, the open loop amplifier of any of Examples 23-37 may optionally include: a common mode feedback control circuit for detecting an output common mode and adjusting one or more biases of the open loop amplifier to bring the output common mode closer to an ideal common mode open loop To bring amplifier.

In Example 39, the open loop amplifier of any of Examples 23-38 may optionally include: boosting transistors at the differential output nodes of the open loop amplifier, with gates of the boosting transistors cross coupled to the differential output nodes of the open loop amplifier.

In Example 40, the open loop amplifier of any of Examples 23-39 may optionally include: source followers for buffering the differential inputs before providing the buffered differential inputs to the gates of the differential pair of input transistors.

Example 41 is a method of improving the performance of an open-loop amplifier, comprising: tracking one or more factors that affect an ideal gate-source voltage to drive a load transistor across differential output nodes of the open-loop amplifier in a linear region ; and generating a gate voltage to drive the load transistor based on the one or more factors and an ideal common mode voltage.

In example 42, the method of example 41 may optionally include the one or more factors including one or more of the following: process, temperature, and stress.

In Example 43, the method of Example 41 or 42 may optionally include the one or more factors of one or more of the following: voltage across transistors in the open loop amplifier, transconductance or resistance of transistors in the open loop amplifier, gain setting in the Open loop amplifier and bias current setting in open loop amplifier.

In example 44, the method of one of examples 41-43 may optionally include that the tracking of the one or more factors is performed by an analog circuit.

In Example 45, the method of any of Examples 41-44 may optionally include the one or more factors including an error resulting from a calibration of the open-loop amplifier.

Example 46 is an open-loop amplifier, comprising: a differential pair of input transistors for receiving differential inputs at respective gates of the differential pair of input transistors; a first current source for providing a current to the open-loop amplifier; an active load on differential output nodes of the open-loop amplifier; and a capacitive load on differential output nodes of the open-loop amplifier.

In some embodiments, the open loop amplifier of Example 45 may have one or more of the features described in Examples 3 and 5-22.

Example 47 is an open-loop amplifier comprising: a first pair of input transistors for receiving differential inputs at respective gates of the first pair of input transistors; a second pair of input transistors complementary to the first differential pair of transistors for receiving differential inputs on respective gates of the second pair of input transistors; a first current source at terminals of the first pair of input transistors for providing a current to the open loop amplifier; and a capacitive load on differential output nodes of the open-loop amplifier.

In some embodiments, the open-loop amplifier of Example 46 may have any one or more features described in any of the other examples mentioned herein, particularly Examples 25-40.

In some embodiments, the open-loop amplifiers of Examples 1-40, 46, and 47 may be used / implemented in combination with other examples mentioned herein.

Example 101 is a method of enhancing calibration in a pipeline analog-to-digital converter (ADC), comprising: injecting a first dither into a first multiplying digital-to-analog converter (MDAC) to a first open-loop amplifier calibrate in the first MDAC a first stage of the pipeline ADC; Injecting a second dither into the first stage of the pipeline ADC to desensitize a calibration of the first open loop amplifier to a dependence on an input signal to the pipeline ADC; and injecting a third dither into a second stage of the pipeline ADC to desensitize the calibration of the first open loop amplifier to non-ideal second stage states of the pipeline ADC.

In example 102, the method of example 101 may optionally include injecting the first dither comprising: injecting the first dither at a summing node in the first MDAC.

In example 103, the method of example 101 or 102 may optionally include injecting the first dither comprising: injecting a first charge representing the first dither in the first MDAC during a hold phase of the first MDAC.

In example 104, the method of one of examples 101-103 may optionally include injecting the first dither comprising: connecting a first dither capacitor to a summing node of the first MDAC during a hold phase of the first MDAC with a first dither voltage.

In Example 105, the method of any of Examples 101-104 may optionally include injecting the first dither comprising: directing a current to output nodes of the first open loop amplifier based on a value of a 1-bit dither signal.

In example 106, the method of one of examples 101-105 may optionally include injecting the second dither comprising: injecting the second dither into an analog input signal into the first stage.

In Example 107, the method of any of Examples 101-106 may optionally include injecting the second dither comprising: injecting the second dither into both the first MDAC and a first first stage ADC.

In example 108, the method of one of examples 101-107 may optionally include injecting the second dither comprising: connecting a second dither capacitor to a summing node of the first MDAC at a second dither voltage corresponding to the second dither during a holding phase of the first MDAC; and adding a third dither voltage corresponding to the second dither to an analog input to a first first stage ADC.

In Example 109, the method of any of Examples 101-108 may optionally include injecting the third dither comprising injecting the third dither into an analog input signal into the second stage.

In example 110, the method of one of examples 101-109 may optionally include injecting the third dither comprising: injecting the third dither into both a second MDAC and a second second stage ADC.

In Example 111, the method of any one of Examples 101-110 may optionally include injecting the third dither comprising: connecting a third dither capacitor to a summing node of a second second stage MDAC having a third dither voltage corresponding to the third dither during a hold phase of the second MDAC; and adding a fourth dither voltage corresponding to the third dither to an analog input to a second second stage ADC.

In Example 112, the method of any of Examples 101-111 may optionally include: subtracting the third dither from a digital signal used in the calibration of the first open-loop amplifier.

Example 201 is a method for kickback and memory calibration of an amplifier, comprising: injecting a first dither into a first stage of a pipeline analog-to-digital converter, wherein the amplifier is in the first phase; Injecting a second dither into a second stage of the pipeline analog-to-digital converter; Extracting a kickback error by correlating the second dither and a first stage digital output; Removing the kickback error from the first stage digital output to produce a first calibrated first stage output; Extracting a memory error by correlating the first dither and the first calibrated output; and removing the memory error from the first calibrated output to produce a second calibrated first stage output.

In example 202, the method of example 201 may optionally include injecting the second dither comprising: injecting a charge corresponding to the second dither at a summing node of a multiplying digital-to-analog converter in the second stage.

In example 203, the method of example 201 or 202 may optionally include injecting the second dither comprising: connecting a dither capacitor to a summing node of a second stage multiplying digital-to-analog converter having a dither voltage equal to the second dither Dither corresponds during a hold phase of the multiplying digital-to-analog converter; and connecting the dither capacitor to ground during a sampling phase of the multiplying digital-to-analog converter.

In example 204, the method of example 201 or 202 may optionally include injecting the second dither comprising: connecting a dither capacitor to a summing node of a second stage multiplying digital-to-analog converter having a dither voltage equal to the second dither Dither corresponds during a hold phase of the multiplying digital-to-analog converter; and connecting the dither capacitor to a second stage analog input during a sampling phase of the multiplying digital-to-analog converter.

In example 205, the method of one of examples 201-204 may optionally include extracting the kickback error comprising: calculating the kickback error based on a second-stage digital-to-analog converter voltage, an analog input voltage on the second Stage and a voltage corresponding to the second dither.

In example 206, the method of one of examples 201-205 may optionally include extracting the kickback error comprising: calculating the kickback error based on a second stage sampling capacitance, a parasitic capacitance at a summing node of a multiplying digital analog sample Converter and a dither injection capacity, which is used for injecting the second dither in the second stage.

In Example 207, the method of any of Examples 201-206 may optionally include extracting the kickback error comprising: calculating the kickback error based on a second-stage digital-to-analog converter voltage, the first-stage digital output and a voltage corresponding to the second dither.

In example 208, the method of one of examples 201-207 may optionally include that extracting the kickback error comprises: calculating the kickback error based on a Second stage sense capacitance and a dither injection capacitance used to inject the second dither into the second stage.

In example 209, the method of one of examples 201-208 may optionally include the correlating the second dither and the digital output of the first stage comprising: multiplying a sign of the second dither and a sign of the digital output of the first stage with an estimate removed from the second dither.

In example 210, the method of one of examples 201-209 may optionally include where the correlating of the first dither and the first calibrated output comprises: multiplying a sign of the first dither and a sign of the first calibrated first-stage output with an estimate of the first dither Memory error removed.

In example 211, the method of one of examples 201-210 may optionally include extracting the memory error comprising: calculating the memory error based on a memory coefficient multiplied by the first-stage digital output.

In example 212, the method of one of examples 201-211 may optionally include extracting the memory error comprising: calculating the memory error based on a memory coefficient multiplied by a second-stage digital-to-analog converter voltage.

In example 213, the method of any of examples 201-212 may optionally include injecting a third dither into both the second stage multiplying digital to analog converter and the second stage analog to digital converter.

In example 214, the method of example 213 may optionally include extracting the kickback error comprising: calculating the kickback error further based on a second-stage digital-to-analog converter voltage, the first-stage digital output; Voltage corresponding to the second dither and a voltage corresponding to the third dither.

In example 215, the method of example 213 or 214 may optionally include extracting the kickback error comprising: calculating the kickback error further based on a second stage sample capacitance, a parasitic capacitance at a summing node of a multiplying digital analog sample Transducer, a dither injection capacitance used to inject the second dither in the second stage, and a dither injection capacitance used to inject the third dither in the second stage.

In example 216, the method of one of examples 213-215 may optionally include injecting the third dither into the multiplying digital to analog converter comprising: connecting a dither capacitor to a summing node of a second stage multiplying digital to analog converter with a dither voltage corresponding to the third dither during a hold phase of the multiplying digital-to-analog converter; and connecting the dither capacitor to ground during a sampling phase of the multiplying digital-to-analog converter.

In example 217, the method of one of examples 213-215 may optionally include injecting a third dither into the multiplying digital to analog converter comprising: connecting a dither capacitor to a summing node of a second stage multiplying digital to analog converter with a dither voltage corresponding to the third dither during a hold phase of the multiplying digital-to-analog converter; and connecting the dither capacitor to a second stage analog input during a sampling phase of the multiplying digital-to-analog converter.

In Example 218, the method of one of Examples 213-217 may optionally include extracting the kickback error comprising correlating the third dither and a first stage digital output with an estimate of the third dither removed.

Example 219 is a multiplying digital-to-analog converter with dither injection, comprising: a switched capacitor circuit for performing sampling and digital-to-analog conversion and generating a residual signal at a summing node; an amplifier for amplifying the residual signal; and a first capacitor coupled to the summing node for injecting a calibration dither at the summing node, wherein the first capacitor during a Scanning phase of the multiplying digital-to-analog converter is connected to an input in the switched capacitor circuit.

In Example 220, the multiplying digital-to-analog converter of Example 219 may optionally include a second capacitor coupled to the summing node for injecting a linearization dither at the summing node, the second capacitor during the sampling phase of the multiplying digital-analog Converter connected to ground.

In Example 221, the multiplying digital-to-analog converter of Example 219 may optionally include a second capacitor coupled to the summing node for injecting a linearization dither at the summing node, the second capacitor during the sampling phase of the multiplying digital-analog Converter connected to the input to the switched capacitor circuit.

Example 222 is a multiplying digital-to-analog converter with dither injection, comprising: a switched capacitor circuit for performing sampling and digital-to-analog conversion and for generating a residual signal at a summing node; an amplifier for amplifying the residual signal; and a first capacitor coupled to the summing node for injecting a calibration dither at the summing node, the first capacitor being connected to ground during a sampling phase of the multiplying digital to analog converter.

In Example 223, the multiplying digital to analog converter of Example 222 may optionally include a second capacitor coupled to the summing node for injecting a linearization dither at the summing node, the second capacitor during the sampling phase of the multiplying digital analog Converter connected to ground.

In Example 224, the multiplying digital-to-analog converter of Example 222 may optionally include a second capacitor coupled to the summing node for injecting a linearization dither at the summing node, the second capacitor during the sampling phase of the multiplying digital-analog Converter is connected to an input in the switched capacitor circuit.

Example 301 is a method of calibrating a gain of an open loop amplifier, comprising: determining, by a digital calibration block, a control parameter to control a gain of the open loop amplifier in a digital domain; and tuning one or more portions of the open-loop amplifier in an analog domain based on the control parameter.

In example 302, the method of example 301 may optionally include determining a control parameter comprising: correlating a calibration dither versus an output of the open-loop amplifier with an estimate of the calibration dither removed, wherein the estimate of the calibration dither based on an ideal gain of the open-loop amplifier and the calibration dither; and updating an estimate of the control parameter based on a result of the correlating.

In example 303, the method of example 301 or 302 may optionally include tuning the one or more portions of the open loop amplifier to: controlling a current source in the open loop amplifier based on the control parameter.

In example 304, the method of one of examples 301-303 may optionally include the tuning of the one or more portions of the open loop amplifier comprising: varying a load resistance in the open loop amplifier based on the control parameter.

In example 305, the method of one of examples 301-304 may optionally include the tuning of the one or more portions of the open loop amplifier comprising: controlling a load resistance in the open loop amplifier based on the control parameter.

In example 306, the method of one of examples 301-305 may optionally include tuning the one or more portions of the open loop amplifier to: varying a source degeneration resistance in the open loop amplifier based on the control parameter.

Example 307 is a front-end circuit to an analog-to-digital converter, comprising: a variable attenuator for receiving an analog input signal; a variable gain amplifier for receiving an output of the variable attenuator, the variable gain amplifier having an open loop amplifier; a track and hold circuit for tracking and holding an output of the variable gain amplifier, wherein an output of the track and hold circuit is to be digitized by the analog to digital converter.

In example 308, the front end circuit of example 307 may optionally include: the variable attenuator to reduce an input swing into the variable gain amplifier.

In example 309, the front-end circuit of example 307 or 308 may optionally include: the variable attenuator to generate the output with a fixed impedance that is independent of a damping setting of the variable attenuator.

In example 310, the front-end circuit of any of examples 307-309 may optionally include: the variable attenuator to provide a coarse gain adjustment.

In example 311, the front-end circuit of any of examples 307-310 may optionally include the variable attenuator, comprising: a network of switches and resistors; and wherein the network is configurable by controlling states of the switches to vary an amount of resistance usable for attenuating the analog input signal.

In example 312, the front-end circuit of any of examples 307-311 may optionally include the variable gain amplifier to provide fine gain adjustment.

In example 313, the front-end circuit of any of examples 307-312 may optionally include the open-loop amplifier having a current source that is adaptable for fine gain adjustment of the open-loop amplifier.

In example 314, the front end circuit of any of examples 307-313 may optionally include the variable gain amplifier further comprising: an analog tracking circuit for driving a load resistor of the open loop amplifier and linearizing the open loop amplifier.

In example 315, the front end circuit of one of examples 307-314 may optionally include the variable gain amplifier further comprising: a dither injection circuit coupled to output nodes of the open loop amplifier for extracting a dither of non-ideal states of the open-loop amplifier is usable to inject.

In example 316, the front-end circuit may optionally include one of examples 307-315, such that the track-and-hold circuit comprises: a buffer; a scan network following the buffer; and another open-loop amplifier following the sampling network.

In example 317, the frontend circuitry of example 316 may optionally include the sensing network comprising: a dither injection circuit for injecting a dither useful for calibrating a circuit subsequent to a dither injection point.

Example 401 is a pipelined analog to digital converter (ADC) sharing an amplifier, comprising: a first stage for receiving and sampling an analog input signal of the pipeline ADC; a shared open-loop amplifier for amplifying a first signal generated in the first stage during a first time period and amplifying a second residual signal generated in the second stage during a second time period; and a second stage for receiving and sampling the first amplified residual signal.

In example 402, the pipeline ADC of example 401 may optionally include: the first stage includes a switched capacitor circuit for sampling the analog input signal and digital-to-analog conversion; and the second stage comprises a second switched capacitor circuit for sampling the first amplified residual signal and a digital-to-analogue conversion.

In example 403, the pipeline ADC of example 401 or 402 may optionally include the first stage having first switches at first summation nodes of the first stage for connecting the first summation nodes of the first stage to inputs of the shared open loop amplifier during the first time period ; and the second stage comprises second switches at second summation nodes of the second stage for connecting the second summation nodes of the second stage to inputs of the shared open-loop amplifier during the second time period.

In example 404, the pipeline ADC of one of examples 401-403 may optionally include: the first stage having third switches at first summation nodes of the first stage for connecting the first summation nodes of the first stage to a common mode voltage; and the second stage has fourth switches at second summing nodes of the second stage for connecting the second summing nodes of the second stage to the common mode voltage.

In example 405, the pipeline ADC of one of examples 401-404 may optionally include: the first stage having a fifth switch interconnecting the first summation nodes of the first stage; and the second stage has a sixth switch interconnecting the second second stage summing nodes.

In example 406, the pipeline ADC of example 404 or 405 may optionally include: the third switches transition from open to closed while the first switches are closed to reset the first summation nodes; and the fourth switches transition from open to closed while the second switches are closed to reset the second summing nodes.

In example 407, the pipeline ADC of example 405 or 406 may optionally include: the third switches and the fifth switch transitioning from open to closed while the first switches are closed to reset the first summing nodes; and the fourth switches and the sixth switch transition from open to closed while the second switches are closed to reset the second summing nodes.

In Example 408, the pipeline ADC of any of Examples 401-407 may optionally include: the first stage having seventh switches for connecting first stage sampling capacitors to receive and sample the analog input signal; and the second stage includes eighth switches for connecting second stage sampling capacitors to receive and sample the first amplified residual signal.

In example 409, the pipeline ADC of example 408 may optionally include: the seventh switches transitioning from open to closed after the third switches and the fifth switch are closed to reset capacitances to the first summing node; and the eighth switches transition from open to closed after the fourth switches and the sixth switch are closed to reset capacitances to the second summing node.

In example 410, the pipeline ADC of one of examples 401-409 may optionally include: the first stage includes a first dither capacitor for injecting a first dither; the second stage has a second dither capacitor for injecting a second dither; and the first dither and the second dither are usable to extract kickback and memory errors affecting the first stage and the second stage.

In example 411, the pipeline ADC of example 410 may optionally include: the second dither capacitor is coupled to a second stage input during a second stage sampling phase.

Example 412 is a time shared analog to digital converter (ADC) sharing an amplifier, comprising: a first switched capacitor circuit of a first ADC for receiving and sampling an analog input signal; a second switched capacitor circuit of a second ADC for receiving and sampling the analog input signal; and a shared open loop amplifier for amplifying a first residual signal generated in the first switched capacitor circuit during a first period and amplifying a second residual signal in the second switched capacitor circuit during a second period is produced.

In Example 413, the time-interleaved ADC of Example 412 may optionally include: the first stage having first switches at first summing nodes of the first switched capacitor circuit for connecting the first summing nodes to inputs of the shared open loop amplifier during the first time period; and the second stage has second switches at second summing nodes of the second switched capacitor circuit for connecting the second summing nodes to inputs of the shared open-loop amplifier during the second time period.

In example 414, the time-interleaved ADC of example 412 or 413 may optionally include the first switched capacitor circuit having a first dither capacitor for injecting a first dither; the second switched capacitor circuit comprises a second dither capacitor for injecting a second dither; and the first dither and the second dither are operable to cause kickback and memory errors affecting the first switched capacitor circuit and the second switched capacitor circuit and an error caused by coupling between the first switched capacitor Circuit and the second switched capacitor circuit is caused to extract.

In Example 415, the time-interleaved ADC of Example 414 may optionally include: the first dither capacitor connected to an input of the time-interleaved ADC during a sample phase of the first switched capacitor circuit; and the second dither capacitor is connected to the input of the time interleaved ADC during a sampling phase of the second switched capacitor circuit.

Example 416 is a method of sharing an open loop amplifier, comprising: connecting first summing nodes of a first switched capacitor circuit having a first residual signal during a first period with a shared open loop amplifier; Amplifying, by the shared open-loop amplifier, the first residual signal during the first period; and connecting second summing nodes of a second switched capacitor circuit having a second residual signal during a second period to a shared open-loop amplifier; and amplifying, by the shared open-loop amplifier, the second residual signal during the second period.

In example 417, the method of example 416 may optionally include: resetting the first summing node to a common-mode voltage before the shared open-loop amplifier amplifies the second residual signal.

In example 418, the method of example 416 or 417 may optionally include: resetting capacitances to the first summing node; and connecting the first switched capacitor circuit to an input after resetting capacitances to the first summing node.

In example 419, the method of one of examples 416-418 may optionally include: injecting a first dither into the first switched capacitor circuit; and injecting a second dither into the first switched capacitor circuit.

In example 420, the method of example 419 may optionally include: extracting one or more errors based on the first dither and the second dither.

Variations and implementations

Amplifiers can be found in pipeline ADCs and pipeline SAR ADCs as interstage amplifiers. The amplifiers may in some cases implement and provide gains in high-speed track-and-hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and high-speed ADC samplers. The amplifiers can be used without reset and with incomplete oscillation to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.

It is noted that the activities discussed above with reference to the figures are applicable to any integrated circuits including processing analog signals and converting the analog signals to digital signals using one or more ADCs. The features can especially advantageous for high-speed ADCs where input frequencies are relatively high in the gigahertz range. The ADC may be applicable to medical systems, scientific systems, wireless and wired communication systems (especially systems requiring a high sampling rate), radar, industrial process control, audio and video equipment, instrumentation, and other systems using ADCs. The level of performance afforded by high speed ADCs may be particularly advantageous for products and systems in demanding markets, such as high speed communications, medical imaging, synthetic aperture radar, digital beamforming communication system, broadband communication systems, high performance imaging, and advanced test / measurement systems (oscilloscope).

The present disclosure includes devices that can perform the various methods described herein. The devices may include a suitable combination of means for implementing any of the methods described herein. Such devices may include a circuit illustrated by the figures and described herein. Portions of various devices may include an electronic circuit for performing the functions described herein. The circuit can operate in an analog domain, a digital domain, or a mixed signal domain. In some cases, one or more portions of the device may be provided by a processor specifically designed to perform the functions described herein (eg, control-related functions, timing-related functions). In some cases, this processor may be an on-chip processor with the ADC. The processor may include one or more application specific components or may include programmable logic gates configured to perform the functions described herein. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on one or more non-transitory computer media.

It is also imperative to note that all of the specifications, dimensions, and relationships outlined herein (eg, the number of processors, logic operations, etc.) are set forth for exemplary and instructional purposes only. Such information may be varied considerably without departing from the spirit of the present disclosure or the scope of the appended claims or the examples described herein. The specifications are only for a non-limiting example and accordingly they should be construed as such. In the foregoing description, exemplary embodiments have been described with reference to certain processor and / or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the appended claims or the examples described herein. Accordingly, the description and drawings are to be considered in an illustrative rather than a limiting sense.

It is noted that with the numerous examples provided herein, interactions may be described in terms of two, three, four or more electrical components or parts. However, this was done for purposes of clarity and example only. It will be understood that the system may be composed in any suitable manner. Along with similar design alternatives, any of the illustrated components, modules, blocks, and elements of the figures may be combined in various possible configurations, all of which are clearly within the broad scope of this description. In certain cases, it may be easier to describe one or more of the functionalities of a given set of flows by merely referring to a limited number of electrical elements. It will be understood that the figures' electrical circuits and teachings are readily scalable and can accommodate a large number of components as well as more complicated / complex arrangements and configurations. Accordingly, the examples provided should not limit the scope or limit the broad teachings of the electrical circuits that may be applied to a variety of other architectures.

It is noted that throughout this specification, references to various features (eg, elements, structures, modules, components, steps, acts, characteristics, etc.) described in "one embodiment,""anembodiment,""oneembodiment." , "Another embodiment", "some embodiments", "various embodiments", "other embodiments", "an alternative embodiment" and the like are intended to mean that any such features are included in one or more embodiments of the present disclosure, possibly combined in the same embodiments or not necessarily combined. It is also important to note that the functions described herein merely illustrate some of the possible functions performed by or within systems / circuits illustrated in the figures are, can be executed. Some of these operations may be deleted or removed as appropriate, or these operations may be significantly modified or changed without departing from the scope of the present disclosure. In addition, the timing of these processes can be changed considerably. The previous operating flows were presented for illustrative and discussion purposes only. Substantial flexibility is provided by embodiments described herein insofar as any suitable arrangements, chronologies, configurations, and timing mechanisms can be provided without departing from the teachings of the present disclosure. Numerous other changes, substitutions, variations, changes, and modifications may be ascertained by one of ordinary skill in the art, and it is intended that the present disclosure cover all such changes, substitutions, variations, alterations, and modifications as come within the scope of the appended claims or the claims described herein Examples fall, encloses. It is noted that all optional features of the device described above may also be implemented with respect to the method or process described herein, and details in the examples may be used anywhere in one or more embodiments.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 62/646181 [0001]

Claims (20)

Open loop amplifier, comprising: a differential pair of input transistors for receiving differential inputs at respective gates of the differential pair of input transistors; a first current source for providing power to the open loop amplifier; an active load on differential output nodes of the open-loop amplifier; and a load resistor at the differential output node of the open-loop amplifier. Open-loop amplifier after Claim 1 wherein the load resistor comprises a load transistor across the differential output nodes of the open-loop amplifier. Open-loop amplifier after Claim 1 or 2 wherein the load resistor comprises a load resistor across the differential output nodes of the open loop amplifier and a load transistor in parallel with the load resistor. Open-loop amplifier after Claim 3 further comprising: an analog tracking circuit for generating a gate voltage to drive the load transistor. Open-loop amplifier after Claim 4 wherein the analog tracking circuit is to perform an analog tracking of the temperature and to adjust the gate voltage based on the analog tracking of the temperature. Open-loop amplifier after Claim 4 or 5 wherein the analog tracking circuit is to track a bias current setting in the open loop amplifier and adjust the gate voltage based on the bias current setting. An open-loop amplifier according to any one of Examples 4 to 6, wherein the analog tracking circuit is to track a temperature variation and adjust the gate voltage based on the temperature variation. An open-loop amplifier as claimed in any one of the preceding claims, further comprising: Level shifter for converting a level of the respective differential inputs and driving the respective gates of the differential pair of input transistors. An open-loop amplifier as claimed in any one of the preceding claims, further comprising: Gain booster transistors at the differential output nodes of the open loop amplifier, wherein gates of the boosting transistors are cross coupled to the differential output nodes of the open loop amplifier. An open-loop amplifier as claimed in any one of the preceding claims, further comprising: A source follower for buffering the respective differential inputs before providing buffered differential inputs to the respective gates of the differential pair of input transistors. An open-loop amplifier as claimed in any one of the preceding claims, further comprising: cross-coupled transistors at sources of the differential pair of input transistors, wherein gates of the cross-coupled transistors are cross-coupled to the gates of the differential pair of input transistors. An open-loop amplifier as claimed in any one of the preceding claims, further comprising: a dither injection circuit at the differential output node of the open-loop amplifier. An open-loop amplifier as claimed in any one of the preceding claims, further comprising: a differential pair of dither transistors each coupled to the differential output nodes of the open loop amplifier, wherein gates of the differential pair of dither transistors are controlled by a differential dither signal; and a current source transistor for supplying a current to be injected to the differential output nodes. An open loop amplifier comprising: a first pair of input transistors for receiving differential inputs on respective gates of the first pair of input transistors; a second pair of input transistors complementary to the first pair of input transistors for receiving differential inputs on respective gates of the second pair of input transistors; a first current source at terminals of the first pair of input transistors to provide power to the open loop amplifier; and a load resistor at differential output nodes of the open-loop amplifier. Open-loop amplifier after Claim 14 wherein the load resistor comprises a first load transistor of a first type across the differential output nodes of the open loop amplifier and a second load transistor of a second type different from the first type in parallel with the first load transistor. Open-loop amplifier after Claim 15 further comprising: an analog tracking circuit for generating a gate voltage to drive the first load transistor and the second load transistor, the gate voltage tracking changes in one or more of: process, voltage, temperature and gain setting of the Open loop amplifier. Open loop amplifier after one of the Claims 14 to 16 further comprising: a second current source at terminals of the second pair of input transistors to provide power to the open loop amplifier. Open loop amplifier after one of the Claims 14 to 17 wherein: the first current source comprises: first and second current transistors connected to respective terminals of the first pair of input transistors; and a resistor coupled across the terminals of the first pair of input transistors. Open loop amplifier after one of the Claims 14 to 18 further comprising: a common mode feedback control circuit for detecting an output common mode and adjusting one or more biases of the open loop amplifier to bring the output common mode closer to an ideal common mode of the open loop amplifier. A method of improving the performance of an open-loop amplifier, comprising: Tracking one or more factors affecting an ideal gate-source voltage to drive a load resistor across differential output nodes of the open-loop amplifier in a linear region; and Generating a gate voltage to drive a load resistor based on the one or more factors and an ideal common mode voltage.

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