DE102019103660A1 - Operating circuit for operating several loads - Google Patents

Abstract

The invention relates to an operating circuit for operating load branches (13) connected in parallel between a first node (11) and a second node (12), each with a load (16) and a controllable switch (17) connected in series with the load (16). The controllable switches (17) can, for example, be controlled by a pulse-width modulated switching signal (P1, P2, P3) to control the current through a respective load branch (13) and toggle between the conductive and the blocking state. A monitoring circuit (28) has a comparator (31) by means of which the total current at the second node (12) is recorded and compared with a reference value. If the total current at the second node (12) is too high, the comparator (31) generates a corresponding signal at its comparator output (34), which can switch at least one flip-flop circuit (38) connected to the comparator output (34) from a normal operating state to an interrupt request state . In the interrupt request state of the at least one flip-flop circuit (38), the controllable switch (17) of the at least one load branch (13), which is assigned to the relevant flip-flop circuit (38), is kept in its blocking state in order to end the overcurrent state and the components of the operating circuit (10) protect from damage.

Description

The invention relates to an operating circuit for operating a plurality of loads connected in parallel. For example, the loads can be lighting means of a lighting means arrangement.

Out EP 3 280 228 A1 an arrangement with several load branches connected in parallel is known, a load in the form of a light-emitting diode being arranged in each load branch. A measuring resistor connected in series with the load branches is used to detect the current through the load branches and to transmit it to a control unit. A controllable switch is arranged in series with the load in each load branch. The control unit can switch the controllable switches in such a way that only one load branch is conductive at a time. This makes it possible to determine a current through an individual load branch and, for example, to recognize an interruption in a load branch.

DE 10 2006 005 521 B3 describes a similar one with operating circuit with several load branches connected in parallel, each of which has a load and a controllable switch. The parallel connection of load branches is connected to a controllable voltage source. In an initialization mode, the threshold voltages in the load branches are detected and the controllable voltage source is set in such a way that the voltage provided is at least as large as the largest threshold voltage of a load branch. This ensures that all load branches can be operated. Analogous to EP 3 280 228 A1 For example, only one load branch can be conductive in a measurement interval, so that interruptions in this load branch can be detected.

Out EP 1 118 251 B1 an operating circuit is known in which the current through each load branch is recorded and subjected to a separate regulation. The current measured as part of the regulation (voltage drop across a measuring resistor) can be fed to a comparator via a multiplexer and compared with a reference value. An interruption in the load branch selected by the multiplexer can be detected via the comparator and saved as an error by activating a flip-flop.

DE 20 2011 052 203 U1 discloses an operating circuit for light-emitting diodes or light-emitting diode chains. The current through each LED chain is recorded and evaluated. The errors are evaluated in a microcontroller and a response adapted to the type of error is initiated. This arrangement is very complex and, due to the signal processing via the microcontroller, the reaction time to errors that occur is very long, which leads to a large amount of energy being converted into heat until an excessively large current through the light-emitting diode chain is switched off.

Starting from the prior art, it is an object of the present invention to create an operating circuit with a simply designed monitoring circuit which can very quickly interrupt one or more load branches in the event of an overcurrent.

Another goal is to minimize the space required for the monitoring circuit. The losses that occur in the measuring circuit should also be minimized in order to achieve a high overall efficiency of the device.

This object is achieved by the operating circuit according to claim 1.

The operating circuit has a first node and a second node, between which several load branches are connected in parallel. A load is arranged in each load branch and, in series with the load, a switch that can be controlled by means of a control input is arranged. The direction of current flow is from the first node to the second node. For example, a current source or voltage source, preferably a constant voltage source, can be connected to the first node. All currents through the load branches connected in parallel add up in the second node.

A control circuit is provided and set up to generate a switching signal for each of the controllable switches. For this purpose, each control input of the controllable switches is indirectly connected to an assigned switching signal output of the control circuit. The switching signals can be pulse-width modulated signals in order to control the currents through the individual load branches or the individual loads.

Each load is preferably at least one light source. Each load can have a plurality of lighting means that are connected in series and / or in parallel with one another. The at least one lighting means is in particular a semiconductor lighting means, for example a light-emitting diode. The brightness of the at least one luminous means arranged in a common load branch can be set by controlling the controllable switch connected in series by means of the assigned switching signal, in particular by pulse width modulation.

The operating circuit also has a monitoring circuit. Preferably has the monitoring circuit has a central circuit part and exactly one decentralized circuit part for each load branch. The monitoring circuit includes a comparator, at least one flip-flop circuit and an interrupt logic circuit for each load branch present. In one embodiment, the central circuit part has the comparator and a single central flip-flop circuit for all load branches. In another exemplary embodiment, the central circuit part can be omitted. A separate comparator and a separate flip-flop circuit can then be present in each decentralized circuit part. In yet another exemplary embodiment, the number of decentralized circuit parts is smaller than the number of load branches, so that two or more load branches are each assigned to a common decentralized circuit part, each with a comparator and a flip-flop circuit.

It is preferred if the monitoring circuit or the central circuit part has a single comparator for all load branches.

The comparator has a first comparator input, a second comparator input and a comparator output. The first comparator input is connected to a reference voltage potential. The reference voltage potential is preferably given constant and does not change during the operation of the loads on the operating circuit. Depending on the type and number of loads or load branches, the reference voltage potential is specified and permanently set for operation. The reference voltage can be set at the start of operation, for example using a microcontroller. This allows different maximum current values to be set for different operating voltages, so that the electrical power of the device remains constant, e.g. 5A maximum current at 24V operating voltage and 2.5A maximum current at 48V operating voltage.

The second comparator input is connected to the second node. The second node is preferably connected to a reference potential, for example a ground potential, via a measuring resistor. The voltage applied to the measuring resistor or a voltage potential that characterizes the voltage applied to the measuring resistor is thus applied to the second comparator input. The voltage applied to the measuring resistor characterizes the total current through all load branches. The comparator output is connected to the flip-flop circuit or all existing flip-flop circuits.

The at least one flip-flop circuit has a set input, a reset input and a flip-flop output. Either all set inputs of the existing flip-flop circuits or all reset inputs of the existing flip-flop circuit are connected to the comparator output. The respective other input, that is to say the reset input or the set input, of each flip-flop circuit can, in one embodiment, be connected to an initialization circuit which can be formed, for example, by the control circuit. An initialization signal can be applied to the at least one flip-flop circuit via the initialization or control circuit. The initialization signal can be generated once during a start or a restart (for example after an error has been corrected). It is used to switch the at least one flip-flop circuit into a defined initial state which corresponds to a normal operating state.

The at least one flip-flop circuit can be switched from the normal operating state to an interrupt request state via the comparator if the voltage potential at the second node exceeds the reference voltage potential. In this case, it is concluded that the total current through the load branches is too large and that there is an overcurrent condition. The signal state at the comparator output of the comparator, which characterizes the overcurrent state (voltage potential at the second node exceeds the reference voltage potential), is either a necessary or sufficient condition for switching the connected flip-flop circuit to the interrupt request state. In one embodiment, it may be necessary for at least one or precisely one further condition to be met in order to switch the connected flip-flop circuit to the interrupt request state. By activating the corresponding input of each flip-flop circuit, in particular the reset input, the at least one flip-flop circuit is switched from the normal operating state to the interrupt request state. The flip-flop output is preferably switched from digital HIGH to digital LOW. Depending on the external circuitry, the at least one flip-flop circuit can also have and use a flip-flop output in which the normal operating state is digital HIGH and in the interrupt request state digital HIGH.

There is an interrupt logic circuit for each load branch. The interrupt logic circuit has a first logic input, a second logic input and a logic output. The logic output is connected to the control input of the assigned controllable switch. The first logic input is connected to the assigned switching signal output of the control circuit, so that the respective switching signal for the controllable switch is present at the first logic input. Of the The second logic input is connected to the flip-flop output of the respectively assigned flip-flop circuit. Each interrupt logic circuit is set up to switch the assigned controllable switch to the blocking state when the assigned flip-flop circuit is in the interrupt request state. The interruption logic circuit is preferably also set up to switch the controllable switch between the conductive and the blocking state in accordance with the specifications of the switching signal when the associated flip-flop circuit is in the normal operating state. For example, the interrupt logic circuit can be designed as an AND gate or as an OR gate.

The execution of the interrupt logic circuit depends on whether the flip-flop output of the flip-flop circuit is digital HIGH or digital LOW in the interrupt request state. In the first case (flip-flop output is digitally HIGH in the interrupt request state), the interrupt logic circuit can be designed as an OR gate, for example, in the second case (flip-flop output is digitally LOW in the interrupt request state) as an AND gate.

The monitoring circuit according to the present invention has a very simple structure. Overcurrent states are recognized via the comparator, and if an overcurrent state is recognized, the at least one flip-flop circuit is switched to the interrupt request state. This leads directly to the fact that, via the link with the interruption logic circuit, the switching signal no longer has any influence on the associated controllable switch, but instead it is switched over in the blocking state. If a central flip-flop circuit is available, all load branches are switched over to the blocking state in the event of an overcurrent. If a separate flip-flop circuit is assigned to each load branch, individual load branches can be selectively switched to the blocking state.

The monitoring circuit works without a microcontroller. Only a few components connected in series are required in each case. In particular, all components are clock-independent and can change their switching state immediately without having to wait for a clock signal as soon as a state changes at one or more of the inputs. The time delay between the occurrence of an overcurrent condition (excessive total current through all load branches) and the interruption of the current flow through one or more load branches can thus be kept in the nanosecond range below one millisecond. The operating circuit is therefore very well protected against the risk of damage from overcurrents. Energy losses due to heat in the overcurrent state are reduced due to the fast response time. In addition, the monitoring circuit has a simple and inexpensive structure.

In a preferred embodiment, the monitoring circuit has only a single central flip-flop circuit for all load branches, which is arranged in the central circuit section. As a result, the circuit complexity and the costs of the monitoring circuit or the operating circuit can be reduced.

As an alternative to this, it is also possible to assign a separate flip-flop circuit to each load branch, which is arranged in the respective decentralized circuit section. This enables the individual separation of a single load branch or several of the existing load branches in the event of an overcurrent. A selection logic circuit may be included in this implementation. The selection logic circuit has a first logic input to which the assigned switching signal is applied, a second logic input connected to the comparator output and a logic output connected to the set input or the reset input of the assigned flip-flop circuit. A separate selection logic circuit is present in each decentralized circuit part, so that a separate selection logic circuit is provided for each load branch. The selection logic circuit can be used to identify whether the assigned load branch was in a conducting state at the time at which the comparator detected an excessively high current, due to the switching signal applied. If this is the case, this load branch is interrupted by switching the flip-flop circuit to the interrupt request state and the resulting switching of the controllable switch into the blocking state. If the load branch in question was not conducting at the time the overcurrent condition occurred, the overcurrent condition cannot be attributed to this load branch and the flip-flop circuit remains in the normal operating state so that the load branch is not interrupted or deactivated by the monitoring circuit.

It is also advantageous if the at least one flip-flop circuit is each formed by an RS flip-flop. Each existing flip-flop circuit preferably has only one RS flip-flop. Further components can be omitted. The RS flip-flop can be constructed using one or more standard ICs, for example by combining two NAND gates (NAND gates).

It is also advantageous to design the flip-flop circuit in such a way that the information provided by the comparator and at the set input or Reset input (preferably reset input) applied comparator output signal has a dominant effect on the output. This means that other input signals at the flip-flop circuit can be overwritten, so to speak, with this comparator output signal. The flip-flop circuit gives priority to the comparator output signal. This ensures that in the event of an error immediately when the operating circuit is started, in particular during initialization, the signal at the output of the flip-flop circuit continues to be defined by the comparator output signal.

The interruption logic circuit and / or the selection logic circuit is preferably formed by one or more logic gates and preferably an AND gate in each case.

It is also advantageous if the at least one flip-flop output of the at least one flip-flop circuit is connected to the second logic input of the associated interruption logic circuit without the interposition of further logic components. This can avoid further time delays. In particular, the at least one flip-flop output is connected directly to the second logic input of the interruption logic circuit or indirectly via a resistor.

Whenever a "resistor" is mentioned in the registration, an ohmic resistor is meant.

It is also advantageous if each logic output of the interruption logic circuits is connected to the associated control connection of the controllable switch without the interposition of further logic components. The connection between a relevant logic output of an interruption logic circuit and the controllable switch can be made directly or indirectly via a resistor.

In a preferred embodiment, each controllable switch is formed by a MOSFET.

As mentioned, the second node can be connected to a reference potential via a measuring resistor. This measuring resistor can also be referred to as a shunt. The measuring resistor is preferably formed by connecting several individual resistors in parallel.

It is preferred if there is only a single controllable switch in each power branch. In addition to the controllable switches in the power branches, the monitoring circuit preferably has no further controllable switches. Thus, in each possible current path from the current or voltage source connected to the first node to the reference potential, there is only one single controllable switch. The number of possible current paths corresponds in particular to the number of power branches connected in parallel.

It is preferred if the current or voltage source is arranged in a separate housing independently of the rest of the operating circuit. The control circuit and / or the monitoring circuit can each be arranged in separate housings or in a common housing. This enables a modular structure of the operating circuit depending on the type and number of loads or load branches. A modular system can thereby be created.

• 1 ein Blockschaltbild eines Ausführungsbeispiels einer Betriebsschaltung mit einer Überwachungsschaltung, die einen zentralen Schaltungsteil und mehrere dezentrale Schaltungsteile hat,
• 2 ein Schaltbild eines Ausführungsbeispiels zur Bildung eines Messwiderstandes aus parallel geschalteten Einzelwiderständen für die Betriebsschaltung in 1,
• 3 ein Blockschaltbild eines Ausführungsbeispiels einer Betriebsschaltung mit einer Überwachungsschaltung, die einen zentralen Schaltungsteil und mehrere dezentrale Schaltungsteile hat,,
• 4 ein Blockschaltbild eines Ausführungsbeispiels eines dezentralen Schaltungsteils der Überwachungsschaltung aus 3,
• 5 ein Blockschaltbild eines weiteren Ausführungsbeispiels einer Betriebsschaltung mit einer Überwachungsschaltung, die einen zentralen Schaltungsteil und mehrere dezentrale Schaltungsteile hat,
• 6 ein Blockschaltbild eines weiteren Ausführungsbeispiels eines dezentralen Schaltungsteils der Überwachungsschaltung aus 5, und
• 7 eine alternative Ausgestaltung der vorstehenden Ausführungsbeispiele für den Anschluss des Komparators.

Advantageous embodiments of the operating circuit emerge from the dependent claims, the description and the drawings. Preferred exemplary embodiments of the invention are explained in detail below with reference to the accompanying drawings. Show it:

• 1 a block diagram of an embodiment of an operating circuit with a monitoring circuit which has a central circuit part and several decentralized circuit parts,
• 2 a circuit diagram of an exemplary embodiment for the formation of a measuring resistor from individual resistors connected in parallel for the operating circuit in FIG 1 ,
• 3 a block diagram of an embodiment of an operating circuit with a monitoring circuit which has a central circuit part and several decentralized circuit parts,
• 4th a block diagram of an embodiment of a decentralized circuit part of the monitoring circuit 3 ,
• 5 a block diagram of a further embodiment of an operating circuit with a monitoring circuit that has a central circuit part and several decentralized circuit parts,
• 6 a block diagram of a further embodiment of a decentralized circuit part of the monitoring circuit 5 , and
• 7th an alternative embodiment of the above embodiments for connecting the comparator.

In 1 Figure 3 is a circuit diagram of one embodiment of an operating circuit 10 illustrated. The operating circuit 10 has multiple between a first node 11 and a second knot 12th load branches connected in parallel 13th on. The first knot 11 the operating circuit 10 is connected to a current or voltage source, in the exemplary embodiment to a constant voltage source 14th . At the first knot 11 is therefore that of the constant voltage source 14th voltage potential provided for all load branches 13th on. The second knot 12th is via a measuring resistor 15th with a reference potential, for example a ground potential M. , connected.

Like it in 2 is illustrated, the measuring resistor 15th in one embodiment by several resistors connected in parallel 15p are formed. As a result, the power loss is at each of the resistors connected in parallel 15p compared to a single measuring resistor.

There is a load in each load branch 16 and a controllable switch 17th connected in series. Any burden 16 is formed in the embodiment by at least one lamp. Are several light sources to form the load 16 present, they can be connected in parallel and / or in series. The at least one lighting means is, for example, a light-emitting diode.

Any controllable switch 17th has a control input for control 18th . The controllable switch is preferably 17th formed by a MOSFET or another field effect transistor ( 4th and 6 ). The control input 18th is formed in this case by the gate of the MOSFET. Instead of a MOSFET, other controllable semiconductor switches could alternatively also be used.

The number of load branches 13th may vary. For example, three or alternatively four load branches 13th each with a controllable switch 17th to be available. For every controllable switch 17th is controlled by a control circuit 22nd a corresponding switching signal P1 , P2 , P3 generated. With the switching signals P1 , P2 , P3 these are preferably pulse-width modulated signals that are used to switch the controllable switch 17th serve between a conductive and a blocking state. This allows an average current to flow through each load branch 13th due to the pulse-width modulated switching of the relevant controllable switch 17th being controlled. In this way, for example, the brightness of the at least one light source can be adjusted, which is the respective load 16 forms.

The operating circuit 10 also has a monitoring circuit 28 . The monitoring circuit 28 has a central circuit part 29 , as well as for each existing load branch 13th a decentralized circuit part 30th . The central circuit part 29 generates an output signal A, which the decentralized circuit parts 30th is transmitted.

The central circuit part 29 the monitoring circuit 28 has a comparator 31 with a first comparator input 32 , a second comparator input 33 and a comparator output 34 on. The first comparator input 32 is at a reference voltage potential UR connected. The second comparator input 33 is with the second knot 12th connected so that the between the second node 12th and the ground potential M. at the measuring resistor 15th applied voltage at the second comparator input 33 is applied. The first comparator input is preferably 32 an inverting input of an operational amplifier and the second comparator input 33 is the non-inverting input of the operational amplifier, part of the comparator 31 is ( 3 and 5 ). In one embodiment, the output signal A of the central circuit part 29 at the comparator output 34 provided and to the respective decentralized circuit parts 30th the monitoring circuit 28 be transmitted ( 5 ).

The in 3 and 4th illustrated embodiment of the monitoring circuit 28 has the central circuit part 29 in addition to the comparator 31 a flip-flop circuit 38 with a set input S, a reset input R and a flip-flop output Q. The flip-flop circuit is preferred 38 formed by an RS flip-flop. The RS flip-flop can be constructed using at least one logic gate that is available as a standard component, in particular using two linked NAND gates (NAND gates). The flip-flop output Q used according to the example is a non-inverting output of the flip-flop circuit 38 or the RS flip-flop. The comparator output 34 is in the embodiment with the reset input R of the flip-flop circuit 38 connected. At the flip-flop output Q, the output signal A of the central circuit part 29 provided.

The set input S has an initialization output 39 the control circuit 22nd connected. Via the initialization output 39 can the control circuit 22nd provide an initialization signal SI that the flip-flop circuit 38 is transmitted. The flip-flop circuit is activated via the initialization signal SI 38 switched to an initial state or normal operating state. The output signal A at the flip-flop output Q is then digital HIGH or A = 1. The initialization signal SI is only applied for a certain period of time during initialization (SI is then digital HIGH or SI = 1). Otherwise that remains in further operation Initialization signal SI digital LOW (SI = 0). The flip-flop circuit 38 maintains its normal operating state as long as there is no signal at reset input R that is digitally HIGH (R = 1).

When starting the operation of the operating circuit 10 or with a restart, for example after a defect in one or more load branches 13th has been remedied, generates the control circuit 22nd the initialization signal SI to the at least one flip-flop circuit 38 to switch to their normal operating state. The at least one flip-flop circuit maintains this normal operating state 38 at as long as the comparator circuit 31 no overcurrent condition (excessive current at the second node 12th ) Has been established.

About the comparator 31 can the flip-flop circuit 38 be switched from the normal operating state to an interrupt request state, the flip-flop output Q in the exemplary embodiment then switching the output signal A from digital HIGH to digital LOW. The comparator 31 switches the flip-flop circuit 38 then to the interrupt request state when the measuring resistor 15th and at the second comparator input 33 applied voltage is the reference voltage potential UR exceeds. The comparator output will then be 34 digital HIGH, so that via the reset input R of the flip-flop circuit 38 , which is then also digitally HIGH (R = 1), the switching of the flip-flop circuit 38 into the interrupt request state. In the interrupt request state, the flip-flop output Q and therefore the output signal A is digital LOW (Q = 0).

• - Initialisierung nach dem Start oder Neustart der Betriebsschaltung 10 (Schalten der Flipflopschaltung 38 in den Normalbetriebszustand) durch kurzzeitiges Anlegen SI = 1: S = 1 (kurzzeitig) und R = 0 ist, wodurch Q = 1 (Normalbetriebszustand) geschaltet wird;
• - Vorliegen eines Überstromzustandes: S = 0 und R = 1, wodurch Q = 0 (Unterbrechungsanforderungszustand) geschaltet wird.

For the flip-flop circuit 38 applies to the embodiment:

• - Initialization after starting or restarting the operating circuit 10 (Switching the flip-flop circuit 38 in the normal operating state) by briefly applying SI = 1: S = 1 (briefly) and R = 0, whereby Q = 1 (normal operating state) is switched;
• - Existence of an overcurrent condition: S = 0 and R = 1, whereby Q = 0 (interrupt request condition) is switched.

All decentralized circuit parts 30th are preferably constructed identically. 4th illustrates an example of a load branch 13th with an assigned decentralized circuit part 30th the monitoring circuit 28 . Every decentralized circuit part 30th has an interrupt logic circuit 40 with a first logic input 41 , a second logic input 42 and a logic output 43 on. The logic output 43 is via an optionally available current limiting resistor 44 with the control input 18th of the controllable switch 17th of the relevant load branch 13th connected and according to the example with the gate of the MOSFET ( 4th ). At the first logic input 41 this is the relevant load branch 13th assigned switching signal P1 or P2 or P3 on. At the second logic input 42 the output signal A of the flip-flop output Q is present.

The interrupt logic circuit 40 is set up for this at the logic output 43 generate a signal to the associated controllable switch 17th to switch between the conductive and the blocking state. According to the example, the controllable switch 17th (MOSFET) the blocking state, if there is no voltage at the gate of the MOSFET, if as the logic output 43 the interrupt logic circuit 40 digital is LOW. The interrupt logic circuit 40 is designed as an AND gate, for example. Accordingly, when the output signal A is in the interrupt request state of the flip-flop circuit 38 digital is LOW (A = 0), then the logic output is 43 the interrupt logic circuit 40 also always digital LOW and the controllable switch 17th is switched to the blocking state and remains in this state as long as A = 0 (second logic input 42 the interrupt logic circuit 40 is digital LOW), regardless of whether the relevant switching signal P1 , P2 , P3 digital is HIGH or LOW.

The embodiment of the operating circuit 10 according to the 3 and 4th works as follows:

After the initialization by means of the initialization signal SI, the flip-flop circuit is in the normal operating state with Q = 1, S = 0 and R = 0 after starting the operating circuit. The comparator detects this 31 too large a total current at the second node 12th because the voltage potential at the second node 12th the reference voltage potential UR exceeds the comparator output 34 of the comparator 31 digital HIGH, so that at the reset input R of the flip-flop circuit 38 applied signal is digital HIGH (R = 1). This causes the flip-flop circuit to be switched 38 from the normal operating state to the interrupt request state in which the flip-flop output Q and consequently the output signal A is digitally LOW (Q = A = 0). There then the second logic inputs 42 of the interrupt logic circuits 40 are digital LOW, the controllable switches are 17th held in the blocking states and all load branches 13th remain interrupted (de-energized) until a new initialization (switching of the flip-flop circuit 38 to normal operating state) after the error has been rectified that led to the overcurrent state.

In contrast to the embodiment according to 3 and 4th instructs the monitoring circuit 28 according to the embodiment of 5 and 6 in every decentralized circuit part 30th a selection logic circuit 45 with a first logic input 46 , a second logic input 47 and a logic output 48 on. The first logic input 46 the selection logic circuit 45 is with the assigned switching signal output 24 the control circuit 22nd connected so that at the first logic input 46 the selection logic circuit 45 the relevant switching signal P1 or P2 or P3 is applied. At the second logic input 47 the selection logic circuit 45 the output signal A is present, which in this exemplary embodiment corresponds to the signal at the comparator output 34 of the central circuit part 29 the monitoring circuit 28 corresponds. The logic output 48 the selection logic circuit 45 is connected to the reset input R of the flip-flop circuit 38 connected. The flip-flop output Q is analogous to the exemplary embodiment in FIG 3 and 4th with the second logic input 42 the interrupt logic circuit 40 connected. The set input S of the flip-flop circuit is also corresponding to the previous exemplary embodiment 38 with the initialization output 39 the control circuit 22nd connected.

• Erkennt der Komparator 31 einen zu großen Gesamtstrom am zweiten Knoten 12, weil das Spannungspotenzial am zweiten Knoten 12 das Referenzspannungspotenzial UR überschreitet, wird der Komparatorausgang 34 des Komparators 31 digital HIGH, was beim Ausführungsbeispiel gemäß der 5 und 6 dazu führt, dass das Ausgangssignal A digital HIGH ist (A = 1). Das Ausgangssignal A wird an alle dezentralen Schaltungsteile 30 und dort an den zweiten Logikeingang 47 der Auswahllogikschaltung 45 übermittelt. Die Auswahllogikschaltung 45 ist beispielsgemäß als UND-Gatter ausgebildet. Der Logikausgang 48 der Auswahllogikschaltung 45 wird aber nur dann digital HIGH, wenn zum Zeitpunkt, zu dem der Komparator 31 einen Überstromzustand feststellt, das betreffende Schaltsignal P1 oder P2 oder P3 ebenfalls digital HIGH ist bzw. wird und das Umschalten des zugeordneten ansteuerbaren Schalters 17 in den leitenden Zustand anfordert. Somit kann über die Auswahllogikschaltung 45 erkannt werden, ob der Überstromzustand mit dem zugeordneten Lastzweig 13 in Zusammenhang stehen kann. Ist nämlich das betreffende Schaltsignal P1 oder P2 oder P3 digital LOW, wird der Überstrom durch einen anderen Lastzweig verursacht und die Flipflopschaltung 38 bleibt in ihrem Normalbetriebszustand, in dem der Flipflopausgang Q digital HIGH ist (Q = 1). Somit kann dann, wenn der Komparator 31 keinen Überstromzustand mehr feststellt, der betreffende Lastzweig 13 durch Betreiben des ansteuerbaren Schalters 17 weiter verwendet werden.

In contrast to the embodiment of the 3 and 4th the monitoring circuit works 28 according to the 5 and 6 as follows:

• Detects the comparator 31 too large a total current at the second node 12th because the voltage potential at the second node 12th the reference voltage potential UR exceeds the comparator output 34 of the comparator 31 digital HIGH, which in the embodiment according to 5 and 6 leads to the output signal A being digital HIGH (A = 1). The output signal A is sent to all decentralized circuit parts 30th and there to the second logic input 47 the selection logic circuit 45 transmitted. The selection logic circuit 45 is designed as an AND gate, for example. The logic output 48 the selection logic circuit 45 but only becomes digital HIGH if at the time at which the comparator 31 detects an overcurrent condition, the relevant switching signal P1 or P2 or P3 also digital is or will be HIGH and the switching of the assigned controllable switch 17th Requests in the conductive state. Thus, via the selection logic circuit 45 it can be recognized whether the overcurrent condition with the assigned load branch 13th may be related. That is the relevant switching signal P1 or P2 or P3 digital LOW, the overcurrent is caused by another load branch and the flip-flop circuit 38 remains in its normal operating state, in which the flip-flop output Q is digital HIGH (Q = 1). Thus, if the comparator 31 no longer detects an overcurrent condition, the relevant load branch 13th by operating the controllable switch 17th continue to be used.

On the other hand, it is determined that the switching signal is during the occurrence of the overcurrent condition P1 , P2 or P3 digital is or becomes HIGH, the reset input R of the flip-flop circuit becomes 38 via the selection logic circuit 45 activated (R = 1) and the flip-flop output Q of the flip-flop circuit 38 the flip-flop circuit 38 switched to digital LOW (Q = 0 in the interrupt request state). This causes the logic output 43 the interrupt logic circuit 40 remains on digital LOW and the controllable switch 17th regardless of the relevant switching signal P1 , P2 or P3 can no longer be switched to the conductive state.

Thus, in the embodiment according to FIG 5 and 6 possible, specifically one or more of the existing load branches 13th to block or interrupt which may have caused the overcurrent condition indicated by the comparator 31 was determined. One or more load branches 13th that were blocking during the occurrence of the overcurrent condition due to the applied switching signal cannot be the cause of the overcurrent condition and can therefore continue to be operated.

7th illustrates a connection option for the comparator 31 at the second knot 12th . This embodiment can be used in all embodiments of the operating circuit 10 be used. The second comparator input 33 is indirect via a coupling resistance 50 with the second knot 12th connected. Between the coupling resistance 50 and the second comparator input 33 is a voltage divider between a voltage potential UB and the ground potential M. switched. The voltage divider has a first voltage divider resistor 51 and a second voltage dividing resistor 52 which are connected in series with one another, the connection point 53 between the two voltage divider resistors 51 , 52 with the second comparator input 33 and the coupling resistance 50 connected is. The first voltage divider resistor 51 is between the voltage potential UB and the connection point 53 switched, while the second voltage divider resistor 52 between the connection point 53 and the ground potential M. is switched.

With this modified circuit it can be ensured that the second comparator input 33 applied voltage potential is sufficiently large and therefore sufficiently different from the ground potential M. differs.

The monitoring circuit preferably has 28 no further logic modules or logic gates than those in the exemplary embodiments explained above according to FIG 3 and 4th or according to the 5 and 6 are illustrated. In particular, the monitoring circuit 28 also no microcontroller on. All components of the monitoring circuit 28 are preferably not clocked by a clock signal, but switch their respective outputs without waiting for a clock signal depending on the signals present at the inputs. As a result, if too high a current occurs at the second node 12th switching off all load branches very quickly 13th ( 3 and 4th ) or one or more load branches 13th ( 5 and 6 ) respectively. The time delay between the occurrence of the overcurrent condition and the interruption of one or more load branches 13th is very short and is particularly in the nanosecond range.

The invention relates to an operating circuit for operating between a first node 11 and a second knot 12th load branches connected in parallel 13th with one load each 16 and one in series to the load 16 switched controllable switch 17th . The controllable switches 17th can for example by means of a pulse-width modulated switching signal P1 , P2 , P3 to control the current through a respective load branch 13th controlled and switched between the conductive and the blocking state. A monitoring circuit 28 has a comparator 31 , by means of which the total current at the second node 12th is detected and compared with a reference value. Is the total current at the second node 12th too big, the comparator generates 31 a corresponding signal at its comparator output 34 , the at least one at the comparator output 34 connected flip-flop circuit 38 can switch from a normal operating state to an interrupt request state. The signal at the comparator output, which characterizes the overcurrent condition, is a necessary or sufficient condition for switching over the connected flip-flop circuit 38 in the interrupt request state - optionally at least one further condition must be met in order to activate the connected flip-flop circuit 38 switch to the interrupt request state. In the interrupt request state of the at least one flip-flop circuit 38 becomes the controllable switch 17th of the at least one load branch 13th that of the relevant flip-flop circuit 38 is assigned, held in its blocking state in order to end the overcurrent state and the components of the operating circuit 10 to protect against damage.

List of reference symbols

10

Operating circuit

11

first knot

12th

second knot

13th

Load branch

14th

Constant voltage source

15th

Measuring resistor

15p

parallel resistor

16

load

17th

controllable switch

18th

Control input

22nd

Control circuit

24

Switching signal output of the control circuit

28

Monitoring circuit

29

central circuit part

30th

decentralized circuit part

31

Comparator

32

first comparator input

33

second comparator input

34

Comparator output

38

Flip-flop circuit

39

Initialization output

40

Interrupt logic circuit

41

first logic input of the interrupt logic circuit

42

second logic input of the interrupt logic circuit

43

Logic output of the interrupt logic circuit

44

Current limiting resistor

45

Selection logic circuit

46

first logic input of the selection logic circuit

47

second logic input of the selection logic circuit

48

Logic output of the selection logic circuit

50

Coupling resistance

51

first voltage divider resistor

52

second voltage divider resistor

A.

Output signal

M.

Ground potential

P1

Switching signal

P2

Switching signal

P3

Switching signal

Q

Flip-flop output

R.

Reset input

S.

Set input

SI

Initialization signal

UB

Voltage potential

UR

Reference voltage potential

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• EP 3280228 A1 [0002, 0003]
• DE 102006005521 B3 [0003]
• EP 1118251 B1 [0004]
• DE 202011052203 U1 [0005]

Claims (14)

Operating circuit (10) with load branches (13) connected in parallel between a first node (11) and a second node (12), with a load (16) and a controllable switch (17) having a control input (18) in each load branch (13) ) are connected in series, with a control circuit (22) which is set up to generate a switching signal (P1, P2, P3) for each controllable switch (17), by means of which the assigned controllable switch (17) can be switched between a conducting and a blocking state , with a monitoring circuit (28) comprising: a comparator (31) having a first comparator input (32) connected to a reference voltage potential (UR), a second comparator input (33) connected to the second node (12) and a comparator output (34), at least one flip-flop circuit (38) each having a set input (S), a reset input (R) and a flip-flop output (Q), the comparator output (34) with the at least one set input (S) or the at least one reset input (R) of the at least a flip-flop circuit (38) is connected, so that by means of the comparator (31) the at least one flip-flop circuit (38) can be switched to an interrupt request state when the voltage potential at the second node (12) exceeds the reference voltage potential (UR), one interrupt logic circuit (40) for each controllable switch (17), which has a first logic input (41) to which the assigned switching signal (P1, P2, P3) is applied and one connected to the flip-flop output (Q) of the assigned flip-flop circuit (38) has a second logic input (42) and a logic output (43) which is connected to the control input (18) of the associated controllable switch (17), wherein each interrupt logic circuit (40) is set up to switch the associated controllable switch (17) to the blocking state when the signal applied to the second logic input (42) indicates that the associated flip-flop circuit (38) is in the interrupt request state. Operational switching after Claim 1 , characterized in that the monitoring circuit (28) has a single central flip-flop circuit (38) for all load branches (13). Operational switching after Claim 1 , characterized in that a separate flip-flop circuit (38) is provided for each load branch (13). Operational switching after Claim 3 , characterized in that for each load branch (13) there is a selection logic circuit (45) which has a first logic input (46) at which the assigned switching signal (P1, P2, P3) is applied, a second one connected to the comparator output (34) The logic input (47) and a logic output (48) connected to the set input (S) or the reset input (R) of the associated flip-flop circuit (38). Operating circuit according to one of the preceding claims, characterized in that the at least one flip-flop circuit (38) is formed by an RS flip-flop. Operating circuit according to one of the preceding claims, characterized in that each at least one flip-flop output (Q) is connected to the second logic input (42) of the associated interrupt logic circuit (40) without the interposition of further logic components. Operating circuit according to one of the preceding claims, characterized in that each logic output (43) of the interruption logic circuits (40) is connected to the assigned control connection (18) of the assigned controllable switch (17) without the interposition of further logic components. Operating circuit according to one of the preceding claims, characterized in that the control circuit (22) is set up to generate an initialization signal (SI) which is sent to the reset input (R) or the set input (S) of the at least one not connected to the comparator output (34) a flip-flop circuit (38) is applied. Operating circuit according to one of the preceding claims, characterized in that the at least one flip-flop circuit (38) is designed without a clock signal input. Operating circuit according to one of the preceding claims, characterized in that each controllable switch (17) is formed by a MOSFET. Operating circuit according to one of the preceding claims, characterized in that the second node (12) is connected to a reference potential via a measuring resistor (15). Operating circuit according to one of the preceding claims, characterized in that the first node (11) is connected to a current or voltage source (14). Operating circuit according to one of the preceding claims, characterized in that there is only one single controllable switch (17) in each load branch (13). Operational switching after Claim 11 and after Claim 12 and after Claim 13 , characterized in that there is only a single controllable switch (17) in each possible current path from the current or voltage source (14) via one of the load branches (13) to the reference potential.

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