DE102019101845A1 - Photorealistic image stylization using a neural network model - Google Patents

Abstract

Photorealistic image stylization involves transferring a style of a reference photograph to a content photograph, with the restriction that the stylized photograph should remain photorealistic. Examples of styles include seasons (summer, winter, etc.), weather (sunny, rainy, fog, etc.), illumination (time of day, night time, etc.). A photorealistic image styling process includes a stylization step and a smoothing step. The styling step transfers the style of the reference photo to the content photo. A photostimulation-neuronal network model receives a photorealistic content image and a photorealistic style image and produces a stylized photorealistic intermediate image comprising the contents of the style image modified content image. A smoothing function receives the stylized photorealistic intermediate image and pixel similarity data, creating the stylized photorealistic image that ensures spatially consistent stylization.

Description

TECHNICAL AREA

The present disclosure relates to photorealistic images and, more particularly, to transferring a style of a reference photograph to a content photograph to produce a photorealistic image.

BACKGROUND

Photorealistic image stylization involves transferring a style of a reference photograph to a content photograph, with the restriction that the stylized photograph should remain photorealistic. Examples of styles include seasons (summer, winter, etc.), weather (sunny, rainy, fog, etc.), illumination (time of day, night time, etc.). Artistic stylization techniques that transform images into paintings without preserving photorealism often introduce structural artifacts and distortions when used for photorealistic image stylization. Conventional photorealistic image styling techniques tend to create spatially inconsistent stylizations with notable artifacts. There is a need to address these problems and / or other problems associated with the prior art.

SUMMARY

A photorealistic image styling technique includes a stylization step and a smoothing step. During the stylization step, transferring the style of the reference photo to the content photo, the smoothing step ensures spatially consistent styling. Each of the steps has a solution in closed form and can be calculated efficiently. The stylization step is based on a whitening and coloring transform (WCT) and the smoothing step is based on a manifold ranking algorithm. The stylization step and the smoothing step are independent and can each be used with other smoothing and styling techniques.

A method, a computer-readable medium and a system are disclosed for performing image stylization. A photorealistic content image and a photorealistic style image are processed by a max-pooling layer of a coder portion of a photostable transfer neural network model to generate location data that identifies a location within a feature map of a maximum value output from the max-pooling layer , An output of the encoder section is processed by a dispersing layer of a decoder section of the phototransport neural network model based on the location data to produce a stylized photorealistic image comprising the contents of the photorealistic content image modified according to the photorealistic style image.

list of figures

• 1A FIG. 12 illustrates a block diagram of a photo-style transfer neural network model according to one embodiment. FIG.
• 1B illustrates a photorealistic style image, a photorealistic content image, and a stylized photorealistic image according to one embodiment.
• 1C FIG. 12 illustrates a flowchart of a method of styling a photorealistic image according to one embodiment.
• 1D illustrates the stylized photorealistic image and a smoothed stylized photorealistic image according to one embodiment.
• 1E FIG. 12 illustrates a block diagram of a photo-transfer system according to an embodiment. FIG.
• 1F FIG. 12 illustrates a flowchart of a method for generating a smoothed stylized photorealistic image according to one embodiment.
• 1G FIG. 12 illustrates a flowchart of another method for generating a smoothed stylized photorealistic image according to one embodiment.
• 2A FIG. 12 illustrates a block diagram of another photo-transfer system according to an embodiment. FIG.
• 2 B FIG. 12 illustrates a flowchart of a method of producing a smoothed stylized photorealistic image using the photo-resist transfer system of FIG 2A according to one embodiment.
• 2C Figure 11 illustrates a style image, a content image, and corresponding style segmentation data and content segmentation data, respectively, according to an embodiment.
• 2D FIG. 12 illustrates a flow chart of a method of generating a smoothed stylized photorealistic image using segmentation data in accordance with one embodiment.
• 3 illustrates a parallel processing unit according to an embodiment.
• 4A illustrates a general processing cluster within the Parallel processing unit of 3 according to one embodiment.
• 4B illustrates a memory partition unit of 3 according to one embodiment.
• 5A illustrates the streaming multiprocessor of 4A according to one embodiment.
• 5B FIG. 4 is a conceptual diagram of a processing system using the PPU of FIG 3 is implemented, according to one embodiment.
• 5C FIG. 12 illustrates an exemplary system in which the various architecture and / or functionality of the various previous embodiments may be implemented.

DETAILED DESCRIPTION

Photorealistic image stylization involves transferring the style of a reference photograph to a content photograph with the restriction that the stylized photograph should remain photorealistic. Although various photorealistic image stylization techniques exist, they tend to produce spatially inconsistent stylizations with notable artifacts.

Photorealistic image styling concerns the picture-to-picture translation problem, the goal being to learn to translate an image from one domain to another. However, photorealistic image stylization does not require a training record of content and style images to learn the translation function. Photorealistic image stylization may be considered as a special type of image-to-image translation. Photorealistic image stylization not only can be used to translate a photo into a different domain (e.g., from daytime to nighttime), but also to transfer the style (e.g., extent of darkness) of a specific reference image to the content image.

In one embodiment, the photorealistic image stylization technique described herein includes a stylization step and a smoothing step. The styling step transfers the style of the reference photo to the content photograph and the smoothing step ensures spatially consistent stylizations. Each of the steps has a solution in closed form and can be calculated efficiently. In the context of the following description, a closed-loop solution means that the solution can be obtained in a fixed number of operations, including convolutions, max-pooling, lightening, and so forth. The stylization step is based on the Brightening and Coloring Transformation (WCT), and the smoothing step is based on a multiple ranking algorithm. The stylization step and the smoothing step are independent and can each be used with other smoothing and styling techniques. The photorealistic image styling technique produces photorealistic stylized images faster than conventional techniques, and during testing, photorealistic stylized images of human subjects were more preferred than photorealistic images produced using conventional techniques.

1A illustrates a block diagram of a photo-style transfer neural network model 110 according to one embodiment. The photo-style transfer neuronal network model 110 includes two encoders 165 , two feature projection modules, P _C and P _S , and a decoder 170 , The two projection function modules, P _C and P _S , be between the encoder 165 and decoder 170 used. Although the photo-transfer neuronal network model 110 in the context of processing units, one or more of the encoders, decoders, P _C and P _S , be carried out by a program, custom circuits or by a combination of custom circuits and a program. For example, the photo-transfer-neuronal network model 110 can be implemented by a GPU (graphics processing unit), a CPU (central processing unit) or any processor capable of implementing layers of a neural network. In one embodiment, the parallel processing unit (PPU) is 300 from 3 configured to the Photostiltransfer neural network model 110 to implement. Furthermore, professionals understand that any system that performs the operations of the Photostiltransfer neural network model 110 is within the scope and spirit of embodiments of the present disclosure.

The photostable transfer-neuronal network model 110 receives a photorealistic content image I _c and a photorealistic style image, and generates a stylized photorealistic image Y comprising the content of the content image modified according to the style image. The photo-style transfer algorithm can be expressed as $$\text{Y}=F_1\left({\text{I}}_{\text{C}}.{\text{I}}_{\text{S}}\right),$$

The projection function modules, P _C and P _S , each perform a projection based on features (parameters) provided by respective encoders 165 , namely H _C and H _S to be received

More illustrative information will now be set forth with respect to various optional architectures and features with which the previous framework may be implemented according to the wishes of the user. It should be emphasized that the following information is presented for illustrative purposes and should not be construed as limiting in any way. Each of the following features may optionally be included with or without the exclusion of other described features.

1B FIG. 12 illustrates a style image, a content image, and a stylized photorealistic image according to one embodiment. The photorealistic style image is in the encoder 165 entered and the photorealistic content image I _c is in the second encoder 165 entered. The photorealistic style image and the photorealistic content image I _c are from the Photostiltransfer neural network model 110 processed to the stylized photorealistic image Y to create. The cloud pattern in the photorealistic content image is retained in the stylized photorealistic image, while a blue color of the sky and the green color of the landscape appear in the photorealistic style image in the stylized photorealistic image - the color of the sky and landscape areas is compared with changed the photorealistic content image. The shape of the street in the stylized photorealistic image is consistent with the street in the photorealistic content image, while the color is changed to resemble the street in the photorealistic style image. In addition to transferring color, the photostrip-transfer neuronal network model 110 may also be configured to synthesize patterns contained in the photorealistic content image, such as a cloud, snow, rain, and the like, in the stylized photorealistic image to be consistent with the content of the photorealistic content image.

Stylization is formulated as an image reconstruction problem with feature projections. With reference to 1A form the encoder 165 and the decoder 170 a car coder that has an encoder 165 includes that with the decoder 170 (without the second encoder and projection modules P _C and P _S ) is directly coupled for general image reconstruction. In one embodiment, the encoder implements 165 a pre-trained neural folding network VGG- 19 (the weights are recorded) and the decoder 170 is trained to reconstruct input images corresponding to the encoder 165 to be provided. In one embodiment, the decoder is 170 symmetric to the encoder 165 , In one embodiment, the decoder becomes 170 by minimizing the sum of the L ₂ Reconstruction loss and loss of perception trained.

Once the auto-coder is trained, become a second encoder 165 and the projection modules P _c and P _s at the network bottleneck between the encoders 165 and the decoder 170 used as in 1A shown to perform stylization using the whitening and coloring transformation, each from the projection modules, P _C and P _S , is carried out. The second encoder 165 is configured to have the same weights as the pre-trained encoder 165 to use. In one embodiment (not shown), the second encoder becomes 165 omitted and a single encoder 165 used to I _C to process and is serial rather than parallel.

wobei ${\text{P}}_{\text{C}}={\text{E}}_{\text{C}}{\mathrm{\Lambda }}_{\text{C}}^{-\frac{1}{2}}{\text{E}}_{\text{C}}^{\text{T}}{\text{ und P}}_{\text{S}}={\text{E}}_{\text{S}}{\mathrm{\Lambda }}_{\text{S}}^{-\frac{1}{2}}{\text{E}}_{\text{S}}^{\text{T}}.$

Hier sind Λ_C und Λ_S jeweils die Diagonalmatrizen mit den Eigenwerten der Kovarianzmatrix ${\text{H}}_{\text{C}}{\text{H}}_{\text{C}}^{\text{T}}{\text{ und H}}_{\text{S}}{\text{H}}_{\text{S}}^{\text{T}}.$

Die Matrizen E_C und E_S sind jeweils die entsprechenden orthonormalen Matrizen der Eigenvektoren. Nach der Transformation stimmen die Korrelationen von transformierten Merkmalen mit denen der Stilmerkmale, d.h., ${\text{H}}_{\text{C}}{\text{H}}_{\text{CS}}^{\text{T}}={\text{H}}_{\text{S}}{\text{H}}_{\text{S}}^{\text{T}},$

überein. Schließlich wird das stilisierte Bild durch direktes Zuführen der transformierten Merkmalsabbildung H_CS in den Decodierer 170 $\left(D\right):\text{Y}=D\left({\text{H}}_{\text{CS}}\right)$

erhalten.The key idea behind the whitening and coloring transformation is to directly adjust feature correlations of the content image with those of the style image across the two projections. Specifically, the encoder (s) extract (extract) 165 (ε) first the vectorized VGG features for the photorealistic content image I _C and the photorealistic style image to respectively produce H _C = ε (I _C ) and H _S = ε (I _S ), and the content feature H _C is transformed via $${\text{H}}_{\text{CS}}={\text{P}}_{\text{S}}{\text{P}}_{\text{C}}{\text{H}}_{\text{C}}$$

in which ${\text{P}}_{\text{C}}={\text{e}}_{\text{C}}{\mathrm{\Lambda }}_{\text{C}}^{-\frac{1}{2}}{\text{e}}_{\text{C}}^{\text{T}}{\text{and P}}_{\text{S}}={\text{e}}_{\text{S}}{\mathrm{\Lambda }}_{\text{S}}^{-\frac{1}{2}}{\text{e}}_{\text{S}}^{\text{T}},$

Here are Λ _C and Λ _S in each case the diagonal matrices with the eigenvalues of the covariance matrix ${\text{H}}_{\text{C}}{\text{H}}_{\text{C}}^{\text{T}}{\text{and H}}_{\text{S}}{\text{H}}_{\text{S}}^{\text{T}},$

The matrices E _C and E _S are respectively the corresponding orthonormal matrices of the eigenvectors. After transformation, the correlations of transformed features are consistent with those of the style features, ie ${\text{H}}_{\text{C}}{\text{H}}_{\text{CS}}^{\text{T}}={\text{H}}_{\text{S}}{\text{H}}_{\text{S}}^{\text{T}}.$

match. Finally, the stylized image is rendered by directly feeding the transformed feature map H _CS in the decoder 170 $\left(D\right):\text{Y}=D\left({\text{H}}_{\text{CS}}\right)$

receive.

A traditional whitening and coloring transformation (WCT) performs well for artistic picture stylization. However, conventional WCT generates structural artifacts (eg, object boundary distortion) for photorealistic image stylization. The WCT, referred to as transfer, implemented by the photostrip-transfer neuronal network model 110 , is designed to suppress structural artifacts.

The design of the Photostile Transfer Neural Network Model 110 is motivated by the observation that the max-pooling operation in an encoder section of the conventional WCT reduces spatial information into feature maps that are processed within the encoder section. The conventional decoder section of the conventional WCT uses upsampling layers to increase the spatial resolutions of the feature maps within the decoder section. Simple upsampling of feature maps in the decoder section fails to recover detailed structures of the input image that are lost when the max-pooling operation is performed in the encoder section of the conventional WCT.

wobei $\overline{D}$

der Decodierer 170 ist, der die Zerstreuungs-Schichten enthält 120 und für die Bildrekonstruktion trainiert ist.Therefore, in contrast to the conventional WCT for the by the photostriplex neuronal network model 110 implemented photoWCT, the lost spatial information from the encoder 165 to the decoder 170 forwarded as location data to facilitate reconstructing the fine details. Each processing layer of the encoder 165 comprises one or more folding layers 105 , a max-pooling layer 115 and a max pooling layer 118 , In one embodiment, only the location data for the photorealistic content image from the encoder 165 to the decoder 170 forwarded and the max-pooling layers 118 are from the second encoder 165 omitted. In one embodiment H _C and H _S from a final convolutional layer 105 of the encoder (s) 165 generated. Each processing layer of the decoder 170 comprises one or more folding layers 125 and a diverging layer 120 , In one embodiment H _CS from a first convolutional layer 125 of the decoder 170 receive. To preserve spatial information, the PhotoWCT replaced by the Photostiltransfer neural network model 110 are also upsampled layers in the conventional WCT with the Zeur scattering layers 120 , The PhotoWCT function is formulated as $$\text{Y}=F_1\left({\text{I}}_{\text{C}}.{\text{I}}_{\text{S}}\right)=\overline{D}\left({\text{P}}_{\text{S}}{\text{P}}_{\text{C}}{\text{H}}_{\text{C}}\right).$$

in which $\overline{D}$

the decoder 170 is that contains the divergent layers 120 and trained for image reconstruction.

The divergent layers 120 in the decoder 170 be along with those from the max pooling layer 118 generated location data used to build the stylized photorealistic image. In one embodiment, the location data is a max-pooling mask that records where the maximum is above each max-pooling region in the corresponding max-pooling layer 115 will be carried. In one embodiment, the max pooling mask is a single bit for each feature, with one bit set for the maximum value in each max pooling region.

1C illustrates a flowchart of a method 130 for styling a photorealistic image according to an embodiment. Although the procedure 130 in the context of a processing unit, the method may 130 also from a program,
customer-specific circuits or by a combination of custom circuits and a program. For example, the method 130 by a GPU (graphic processing unit), a CPU (central processing unit), or any processor capable of implementing a neural network model. Furthermore, those skilled in the art will understand that every system that uses the method 130 is within the scope and spirit of embodiments of the present disclosure.

At step 135 processes a max pooling layer 115 of the encoder 165 within the photostable transfer neural network model 110 a photorealistic content image and a photorealistic style image to generate the location data that identifies a location within a feature map of a maximum value that is determined by the max-pooling layer 115 is issued. In one embodiment, the location data for each layer in the encoder 165 a corresponding layer in the decoder 170 provided as in 1A shown.

At step 140 Processes a dispersion layer 120 of the decoder 170 of the photostable transfer neural network model 110 an output of the encoder 165 to the stylized photorealistic image Y to create. The stylized photorealistic image includes content from the photorealistic content image that is modified according to the photorealistic style image. In one embodiment, the location data is determined by max-pooling location layers 118 generated by the max-pooling layer 115 correspond, and are from the dispersal layer 120 used to create the stylized photorealistic image. In one embodiment, the output of the encoder is 165 at least one of H _C and H _S , In one embodiment, the output of the encoder 165 further processed to H _CS the decoder 170 provide.

den Stil an das photorealistische Inhaltsphoto I_C , während strukturelle Artefakte in dem ausgegeben stilisierten photorealistischen Bild Y minimiert werden. In einer Ausführungsform wird der Stil unter Verwendung der photoWCT-Stilisierungstransformation transferiert. Obwohl I_c durch das Stiltransfer-Neuronale-Netzwerkmodell 110 originalgetreu stilisiert werden kann, erzeugt das Stiltransfer-Neuronale-Netzwerkmodell 110 manchmal inkonsistente Stilisierungen in semantisch ähnlichen Regionen. Das stilisierte photorealistische Bild in 1B kann weniger wie ein Photo aussehen, wobei semantisch ähnliche Regionen inkonsistent stilisiert werden. Eine photorealistische Glättungsfunktion $F_2$

kann verwendet werden, um die Artefakte zu verringern oder zu beseitigen. In einer Ausführungsform führt eine zweistufige Abbildungsfunktion Stilisierung und Glättung durch: $$F_2\left(F_1\left({\text{I}}_{\text{C}},{\text{I}}_{\text{S}}\right),{\text{I}}_{\text{C}}\right).$$

Given a photorealistic style image Is, the style transfer neuronal network model transfers 110 $\left(F_1\right)$

the style to the photorealistic content photo I _C while minimizing structural artifacts in the output stylized photorealistic image Y. In one embodiment, the style is transferred using the photoWCT stylization transformation. Even though I _c by the style transfer neuronal network model 110 true to style, generates the style transfer neural network model 110 sometimes inconsistent stylizations in semantically similar regions. The stylized photorealistic image in 1B may look less like a photo, with semantically similar regions becoming inconsistently stylized. A photorealistic smoothing function $F_2$

can be used to reduce or eliminate the artifacts. In one embodiment, a two-step mapping function performs stylization and smoothing: $$F_2\left(F_1\left({\text{I}}_{\text{C}}.{\text{I}}_{\text{S}}\right).{\text{I}}_{\text{C}}\right),$$

In one embodiment, pixel affinities may be used to enhance photorealism during smoothing of the stylized photorealistic image. 1D illustrates the stylized photorealistic image and a smoothed stylized photorealistic image according to one embodiment. The smoothed stylized photorealistic image in 1D It looks more like a photo than the stylized photorealistic image because semantically similar regions are smoothed based on pixel affinities for the photorealistic content image.

empfängt das stilisierte photorealistische Bild Y und das photorealistische Inhaltsbild und erzeugt ein geglättetes stilisiertes photorealistisches Bild. In einer Ausführungsform (wie gezeigt) wird das photorealistische Inhaltsbild von dem Glättungsfunktionsmodul 145 empfangen und wird verwendet, um die Pixelähnlichkeitsdaten zu erzeugen. In einer Ausführungsform empfängt das Glättungsfunktionsmodul 145 die Pixelähnlichkeitsdaten. In einer Ausführungsform sind die Pixelähnlichkeitsdaten eine Affinitätsmatix für das Inhaltsbild. 1E illustrates a block diagram of a photo-transfer system 100 according to one embodiment. The smoothing function module 145 $\left(F_2\right)$

receives the stylized photorealistic image Y and the photorealistic content image, creating a smoothed stylized photorealistic image. In one embodiment (as shown), the photorealistic content image becomes the smoothing function module 145 is received and used to generate the pixel similarity data. In one embodiment, the smoothing function module receives 145 the pixel similarity data. In one embodiment, the pixel similarity data is an affinity matrix for the content image.

wobei y_i die Pixelfarbe in dem stilisierten photorealistischen Bild Y und ri die Pixelfarbe in dem gewünschten geglätteten stilisierten photorealistischen Bild R ist. Die Variable d_ii = ∑_j w_ij ist das Diagonalelement in der Gradmatrix D von W, d. h. , D = diag {d₁₁ , d₂₂ , ..., d_NN } . Gleichung (5) gewährleistet, dass Pixelwerte in dem geglätteten stilisierten photorealistischen Bild Pixelwerten in dem stilisierten photorealistischen Bild Y ähneln (aufgrund des zweiten Terms, basierend auf Unterschieden zwischen r_i und y_i ), wobei die Ähnlichkeiten jedoch Pixeln in dem photorealistischen Inhaltsbild ähneln (aufgrund des ersten Terms basierend auf Pixelaffinitätswerten w_ij ).The smoothing operation has two goals. First, similarly populated pixels in a local neighborhood should be stylized in a similar manner. Second, the output of the stylized photorealistic image, that of the style transfer neural network model 110 does not differ significantly to maintain the global styling effects. In one embodiment, all pixels may be represented as nodes in a graphical representation, and an affinity matrix W = {w _ij } ε ℝ ^{N x N} (N is the number of pixels) is defined to describe pixel similarities. A smoothing term and an adjustment term are defined, which model the two goals in the following optimization problem: $$\underset{\text{r}}{{\displaystyle \text{<figure-callout id="1" label="argmin r" filenames="DE102019101845A1\_0035.png" state="{{state}}">argmin </figure-callout>}}}\text{1/}2\left({\displaystyle {\Sigma }_{\text{i}.\text{j}=\text{1}}^{\text{N}}{\text{w}}_{\text{ij}}{\Vert \frac{{\text{r}}_{\text{i}}}{\sqrt{{\text{d}}_{\text{ii}}}}-\frac{{\text{r}}_{\text{j}}}{\sqrt{{\text{d}}_{\text{jj}}}}\Vert }^2+\mathrm{\lambda }{\displaystyle {\Sigma }_{\text{i}=1}^{\text{N}}{\Vert {\text{r}}_{\text{i}}-{\text{y}}_{\text{i}}\Vert }^2}}\right).$$

in which y _i the pixel color in the stylized photorealistic image Y and ri is the pixel color in the desired smoothed stylized photorealistic image R. The variable d _ii = Σ _j w _ij is the diagonal element in the degree matrix D of W, ie, D = diag { ₁₁ . d ₂₂ , ..., d _NN }. Equation (5) ensures that pixel values in the smoothed stylized photorealistic image are similar to pixel values in the stylized photorealistic image Y (due to the second term based on differences between _i and y _i However, the similarities are similar to pixels in the photorealistic content image (due to the first term based on pixel affinity values w _ij ).

In Equation (5), A controls the equalization of the two terms. A smaller A renders smoother results, while a larger A renders results that are more faithful to the queries (the stylized photorealistic image Y). In general, decreasing A helps to remove artifacts and thus improve photorealism. However, if A is too small, the smoothed stylized photorealistic image tends to be over-smoothed. To find the optimal A, a grid search can be performed. In one embodiment, the similarity between bound maps extracted from stylized and original content images may be used as a criteria for the mesh search, since object boundaries should remain the same despite stylization.

wobei I die Identitätsmatrix, $\mathrm{\alpha }=\frac{1}{1+\mathrm{\lambda }}$

und S die normierte Laplace-Matrix ist, die von I_c , d.h., $\text{S}={\text{D}}^{-1/2}{\text{WD}}^{-1/2}\in {ℝ}^{\text{N}\times \text{N}}$

berechnet wird. Da der konstruierte Graph häufig spärlich verbunden ist (d.h., die meisten Elemente in W sind Null), kann die inverse Operation in Gleichung (6) effizient berechnet werden. Mit der Lösung in geschlossener Form kann der Glättungsschritt als eine Funktionsabbildung geschrieben werden, die gegeben wird durch: $$\text{R}*=F_2\left(\text{Y},{\text{I}}_{\text{C}}\right)=\left(1-\mathrm{\alpha }\right){\left(\text{I}-\mathrm{\alpha }\text{S}\right)}^{-1}\text{Y}.$$

The formulation shown in equation (5) is motivated by graph-based ranking algorithms. In the ranking algorithms, Y is a binary input, where each element indicates whether a specific element is a query (y _i = 1 if y _{i is} a query and y _i = 0 otherwise). The optimal solution R is the ranking values of all elements based on their pairwise affinities. Y can be set as the stylized photorealistic image, and the optimal solution R is the smoothed version of Y based on the pairwise pixel affinities, which supports consistent stylization within semantically similar regions. The above optimization problem is a simple quadratic problem with a closed-form solution given by $$\text{R}*=\left(1-\mathrm{\alpha }\right){\left(\text{I}-\mathrm{\alpha }\text{S}\right)}^{-1}\text{Y}.$$

where I is the identity matrix, $\mathrm{\alpha }=\frac{1}{1+\mathrm{\lambda }}$

and S is the normalized Laplace matrix derived from I _c , ie, $\text{S}={\text{D}}^{-1/2}{\text{WD}}^{-1/2}\in {ℝ}^{\text{N}\times \text{N}}$

is calculated. Since the constructed graph is often sparsely connected (ie, most elements in W are zero), the inverse operation in equation (6) can be calculated efficiently. With the solution in closed form, the smoothing step can be written as a function map given by: $$\text{R}*=F_2\left(\text{Y}.{\text{I}}_{\text{C}}\right)=\left(1-\mathrm{\alpha }\right){\left(\text{I}-\mathrm{\alpha }\text{S}\right)}^{-1}\text{Y},$$

zu definieren, wobei I_i , I_j die RGB-Werte von benachbarten Pixeln i,j sind und σ ein globaler skalierender Hyperparameter ist. In der Praxis ist es jedoch schwierig, den σ Wert für die Gaußsche Affinität zu bestimmen, die global eine gute Leistung bringt. Es führt häufig entweder zu Überglättung des gesamten stilisierten photorealistischen Bildes oder zum inkonsistenten Stilisieren des photorealistischen Bildes. In einer Ausführungsform wird, um Auswählen eines globalen skalierenden Hyperparameters zu vermeiden, eine Mattierungsaffinität (als MattingAff bezeichnet) verwendet, wobei die Affinität zwischen zwei Pixeln auf Mittelwerten und Varianzen von Pixeln in einem lokalen Fenster basiert. Die Mattierungsaffinität ist imstande, unterschiedliche Regionen simultan gut zu glätten.In one embodiment, the affinity matrix W is calculated using the photorealistic content image based on an assumption of an 8-connected image graph. While various choices of affinity metrics exist, it is popular to rate the affinity (referred to as GaussianAff) as ${\text{w}}_{\text{ij}}=e^{\frac{-{\Vert {\text{I}}_{\text{i}}-{\text{I}}_{\text{j}}\Vert }^2}{{\mathrm{\sigma }}^2}}$

to define, where I _i . I _j the RGB values of neighboring pixels are i, j and σ is a global scaling hyperparameter. In practice, however, it is difficult to determine the σ value for the Gaussian affinity that performs well globally. It often results in either over-smoothing the entire stylized photorealistic image or inconsistently styling the photorealistic image. In one embodiment, to avoid selecting a global scaling hyperparameter, a matting affinity (referred to as MattingAff) is used, where the affinity between two pixels is based on averages and variances of pixels in a local window. The matting affinity is capable of smoothing out different regions simultaneously well.

1F illustrates a flowchart of a method 150 for producing a smoothed stylized photorealistic image according to an embodiment. Although the procedure 150 in the context of a processing unit, the method may 150 also be performed by a program, custom circuits or by a combination of custom circuits and a program. For example, the method 150 by a GPU (graphic processing unit), a CPU (central processing unit), or any processor capable of implementing a neural network model. Furthermore, those skilled in the art will understand that every system that uses the method 150 is within the scope and spirit of embodiments of the present disclosure.

steps 135 and 140 are completed as previously in conjunction with 1C described. At step 155 processes the smoothing function module 145 the stylized photorealistic image created by the photo-transfer-neuronal network model 110 according to pixel similarity data for the photorealistic content image, to produce a smoothed stylized photorealistic image.

kann verwendet werden, um strukturelle Artefakte in stilisierten photorealistischen Bildern zu entfernen, die unter Verwendung der herkömmlichen WCT erzeugt wurden. Das Anwenden des Glättungsschrittes

auf stilisierte photorealistische Bilder, die unter Verwendung des Transferschritt-Glättungsschritts

erzeugt wurden, erzeugt photorealistische Bilder höherer Qualität, weil das photorealistische Inhaltsbild und das herkömmliche WCT-stilisierte, photorealistische Bild aufgrund räumlicher Verzerrungen schwerwiegend fehlausgerichtet sind. Die Fehlausrichtungen können falsche Abfragen in Y für den Glättungsschritt einführen. Der Gebrauch der PhotoWCT, um Verzerrungen vor Glättung zu entfernen, führt zu besserem Photorealismus, während originalgetreue Stilisierung weiterhin beibehalten wird.The smoothing step

can be used to remove structural artifacts in stylized photorealistic images created using conventional WCT. Applying the smoothing step

on stylized photorealistic images using the transfer step smoothing step

have generated higher quality photorealistic images because the photorealistic content image and the traditional WCT stylized photorealistic image are seriously misaligned due to spatial distortions. The misalignments may introduce false queries in Y for the smoothing step. Using PhotoWCT to remove distortion from smoothness results in better photorealism while preserving true-to-life stylization.

1G illustrates a flowchart of another method 160 for producing a smoothed stylized photorealistic image according to an embodiment. Although the procedure 160 in the context of a processing unit, the method 160 may also be performed by a program, custom circuits or by a combination of custom circuits and a program. For example, the method 160 by a GPU (graphics processing unit), a CPU (central processing unit), or any processor capable of providing the smoothing function module 145 to implement. Furthermore, those skilled in the art will understand that every system that uses the method 160 is within the scope and spirit of embodiments of the present disclosure.

At step 165 receives the smoothing function module 145 a stylized photorealistic image created by a photo-transfer neuronal network model, the stylized photorealistic image comprising content of a photorealistic content image modified according to a photorealistic style image. In one embodiment, the photostrip-transfer neuronal network model is the photostrip-transfer neuronal network model 110 that is configured to implement the photoWCT. In one embodiment, the stylized photorealistic image is submerged Using the conventional WCT generated to create the stylized photorealistic image.

At step 155 processes the smoothing function module 145 the stylized photorealistic image according to pixel similarity data for the photorealistic content image to produce a smoothed stylized photorealistic image. In one embodiment, the pixel similarity data includes pixel affinities that measure the likelihood of two adjacent pixels that belong to the same object. In one embodiment, the pixel similarity data identifies pixels in the stylized photorealistic image that are consistent in color with neighboring pixels. In one embodiment, the smoothing function module processes 145 the photorealistic content image to produce the pixel similarity data. In one embodiment, the smoothing function module receives 145 the pixel similarity data. In one embodiment, this is by the smoothing function module 145 implemented smoothing function a solution in closed form. In one embodiment, the smoothing function module solves 145 a quadratic function with a closed-form solution to create the smoothed stylized photorealistic image.

2A Fig. 12 illustrates a block diagram of another photo-transfer system 200 according to one embodiment. The photo-style transfer system 200 is a multi-level stylization system that utilizes multiple photostrip-transfer neuronal network models 110 comprising respectively local layers and stratification layers and transforming the pair of features ( P _C . P _S ). Although two photo-style transfer neuronal network models 110 in 2A can be shown more than two photo-type transfer neural network models 110 be sequentially configured to create the stylized photorealistic image. A single smoothing function module 145 is used to process the final stylized photorealistic image created by the multiple levels of stylization created by the sequence of photostrip-transfer neural network models 110 was implemented. In one embodiment, each of the photostenergy transfer neural network models 110 in terms of the number of layers in the encoder 165 and / or decoder 170 vary. In one embodiment, the second photostenergy-transfer neuronal network model 110 a lower feature representation compared to the first phototransport neural network model 110 on.

In one embodiment, four photostrip transfer neuronal network models 110 coupled in series to create the photorealistic style image created by the single smoothing function module 145 is smoothed. In one embodiment, the depth of the encoder decreases 165 and decoder 170 within the four photo-transfer neuronal network models 110 from the first of the four photostenergy-transfer neural network models 110 to the fourth of the four photo-transfer neuronal network models 110 from. In one embodiment, the four decoders 170 trained separately for image reconstruction and the four decoders 170 do not use the weights together.

2 B illustrates a flowchart of a method 220 for producing a smoothed stylized photorealistic image using the photo-resist transfer system of 2A according to one embodiment. Although the procedure 220 in the context of a processing unit, the method may 220 also be performed by a program, custom circuits or by a combination of custom circuits and a program. For example, the method 220 by a GPU (graphic processing unit), a CPU (central processing unit) or any processor capable of implementing a neural network model and a smoothing function. Furthermore, those skilled in the art will understand that every system that uses the method 220 is within the scope and spirit of embodiments of the present disclosure.

steps 135 and 140 are completed as previously in conjunction with 1C described. The photo-style transfer system 200 determines whether another style transfer level should process the stylized photorealistic image, and if so, becomes steps 135 and 140 for another photo-transfer neuronal network model 110 repeated. Otherwise processed at step 155 the smoothing function module 145 the stylized photorealistic image created by the last photo-transfer neuronal network model 110 according to pixel similarity data for the photorealistic content image, to produce a smoothed stylized photorealistic image.

The Photostile Transfer Neuronal Network 110 can be configured to take advantage of semantic tag cards to obtain better stylization results when semantic tag cards are available for at least one of the photorealistic style image and the photo-realistic content image. In one embodiment, when performing the stylization for each semantic tag, a pair of projection matrices ( P _C and P _S ) using the features from the image regions with the same label respectively in the photorealistic content and style photos. The pair is then used to stylize each of the image regions separately. With a semantic Label Card, a content and style comparison can be performed more accurately.

2C 10 illustrates a photorealistic style image, a photorealistic content image, and corresponding style segmentation data and content segmentation data, respectively, according to one embodiment. In one embodiment, the style and / or content segmentation data is provided by semantic tag cards. The photorealistic style image is segmented into a first style region and a second style region. The first style region in the style segmentation data identifies (ie, is labeled as) the road and the second style region in the style segmentation data identifies the landscape. The photorealistic content image is segmented into a first content region and a second content region. The first content region in the content segmentation data identifies the road and corresponds to the first style region. The second content region in the content segmentation data identifies the landscape and corresponds to the second style region. The style and / or content segmentation data may define additional regions, such as the sky.

In one embodiment, the photostrip transfer neuronal network model processes 110 the first style region characterized by the style segmentation data and the corresponding first content region of the photorealistic content images to produce a first region of the photorealistic style image. In one embodiment, the photostrip transfer neuronal network model processes 110 the first content region characterized by the content segmentation data and a corresponding first style region of the photorealistic style image to produce a first region of the photorealistic style image.

Accurate semantic tag cards are not necessary for obtaining good stylization results. The semantic tag cards are used only to find matching areas between content and style images. The specific class information is not used. In addition, the semantic tag card does not need to be drawn exactly along object boundaries. The photorealistic smoothing step, which uses pixel affinities to promote consistent stylization, can accommodate inaccurate annotations. Relaxing the accuracy of boundaries can greatly reduce the tagging burden on users.

2D illustrates a flowchart of a method 250 for generating a smoothed stylized photorealistic image using segmentation data according to one embodiment. Although the procedure 250 in the context of a processing unit, the method may 250 also be performed by a program, custom circuits or by a combination of custom circuits and a program. For example, the method 250 by a GPU (graphic processing unit), a CPU (central processing unit) or any processor capable of implementing a neural network model and a smoothing function. Furthermore, those skilled in the art will understand that every system that uses the method 250 is within the scope and spirit of embodiments of the present disclosure.

At step 230 For example, segmentation data is received for at least one of the photorealistic style image and the photorealistic content image. In one embodiment, the segmentation data comprises a semantic tag card. For a first region of the photorealistic content or style image identified by the segmentation data, steps become 135 . 140 and 155 completed, as previously in conjunction with 1C and 1F described. At step 270 determines the photo-transfer system 100 or 200 whether any other region defined by the segmentation data should be processed, and if so, steps 135 . 140 and 155 repeated for the region. Otherwise, the creation of the smoothed stylized photorealistic image is complete.

The photorealistic image styling technique used by the photostrip-transfer neuronal network model 110 is implemented produces high quality stylized photorealistic images that are consistent with the photorealistic content image. Providing location data (max-pooling masks) from each max-pooling layer of the encoder 165 can be generated to corresponding diffusion layers in the decoder 170 ensures that fine detail of the photorealistic content image can be maintained. The photorealistic photoWCT image sizing technique has a solution in closed form and can be calculated efficiently. The smoothing function improves the photorealism of the stylized images using pixel similarity data, and also has a closed-form solution for efficient computation. The photorealistic image styling technique and the smoothing function are independent and each can be used with other smoothing and stylization techniques.

Parallel processing architecture

3 illustrates a parallel processing unit (PPU) 300 according to one embodiment. In one embodiment, the PPU 300 a multi-threaded processor or multi-stranded Processor implemented on one or more integrated circuit devices. The PPU 300 is a latency-concealing architecture designed to process a large number of threads in parallel. A thread (ie, a thread of execution) is an instantiation of a set of instructions configured to by the PPU 300 to be executed. In one embodiment, the PPU 300 a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data to display two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device; to create. In other embodiments, the PPU 300 used for performing general purpose calculations. While an exemplary parallel processor is provided herein for illustrative purposes, it should be emphasized that such processor is presented for illustrative purposes only and that any processor may be used to supplement and / or replace the same.

One or more PPUs 300 can be configured to accelerate thousands of High Performing Computing (HPC), data center, and machine learning applications. The PPU 300 can be configured to accelerate numerous deep-learning systems and applications including autonomous vehicle platforms, deep learning, high-accuracy speech, image and text recognition systems, intelligent video analysis, molecular simulations, drug discovery, disease diagnosis, weather forecasting, large data analytics, astronomy, Molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations and personalized user recommendations, and the like.

As in 3 shown includes the PPU 300 an input / output (I / O) unit 305 , a front-end unit 315 , a planner unit 320 , a work distribution unit 325 , a hub 330 , a crossbar (Xbar) 370 , one or more general processing clusters (GPCs) 350 and one or more storage partition units 380 , The PPU 300 can connect to a host processor or other PPUs via an interconnect of high-speed NVLink 310 be connected. The PPU 300 can also connect to a host processor or other peripheral devices via an interconnect 302 be connected. In one embodiment, the local memory may include a number of random access memory (DRAM) devices. The DRAM devices may be configured as an HBM (high bandwidth memory) subsystem with multiple DRAM dies stacked within each device.

The interconnect of NVLink 310 allows systems, one or more PPUs 300 To scale and include that are combined with one or more CPUs supports cache coherence between the PPUs 300 and CPUs as well as CPU mastering. Data and / or commands can be obtained by means of NVLink 310 through the hub 330 to / from other units of the PPU 300 , such as one or more copy machines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). The NVLink 310 becomes more in connection with 5B described.

The I / O unit 305 is configured to communicate (ie, commands, data, etc.) from a host processor (not shown) via the interconnect 302 to transmit and receive. The I / O unit 305 can connect to the host processor directly through the interconnect 302 or communicate through one or more intermediate devices, such as a memory bridge. In one embodiment, the I / O unit 305 with one or more other processors, such as one or more of the PPUs, over the interconnect 302 communicate. In one embodiment, the I / O unit implements 305 a PCIe (Peripheral Component Interconnect Express) interface for communications over a PCIe bus and the interconnect 302 is a PCIe bus. In alternative embodiments, the I / O unit 305 other types of well known interfaces for communicating with external devices.

The I / O unit 305 decodes packets over the interconnect 302 were received. In one embodiment, the packets represent commands configured to the PPU 300 to cause to perform various operations. The I / O unit 305 transmits the decoded instructions to various other units of the PPU 300 as the commands can specify. For example, some commands can be sent to the frontend unit 315 be transmitted. Other commands can be sent to the hub 330 or other units of the PPU 300 , such as one or more copy machines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the I / O unit 305 configured to communicate between and among the various logical units of the PPU 300 forward.

In one embodiment, a program executed by the host processor encodes a command stream in a buffer that the PPU 300 Provides workloads for processing. A workload can include multiple statements and data to be processed by these statements. The buffer is a region in memory owned by both the host processor and the PPU 300 is accessible (ie read / write). For example, the host interface unit 305 be configured to access the buffer in a system memory that is connected to the interconnect 302 connected via memory requests over the interconnect 302 be transmitted. In one embodiment, the host processor writes the instruction stream into the buffer and then transmits a pointer to the start of the instruction stream to the PPU 300 , The frontend unit 315 receives pointers to one or more instruction streams. The frontend unit 315 manages the one or more streams, reads commands from the streams, and forwards commands to the various units of the PPU 300 continue.

The frontend unit 315 is with a planner unit 320 coupled to the various GPCs 350 configured to process tasks defined by the one or more streams. The planner unit 320 is configured to track state information concerning various tasks performed by the scheduler unit 320 to get managed. The state may indicate which GPC 350 a task is assigned, whether the task is active or inactive, whether a priority level is assigned to the task, and so on. The planner unit 320 manages the execution of a plurality of tasks on the one or more GPCs 350 ,

The planner unit 320 is with a work distribution unit 325 coupled, which is configured to perform tasks on the GPCs 350 to send. The work distribution unit 325 can track a number of scheduled tasks performed by the scheduler unit 320 be received. In one embodiment, the work distribution unit manages 325 a pending task pool and an active task pool for each of the GPCs 350 , The pending task pool may include a number of slots (eg 32 slots) containing tasks assigned to a particular GPC 350 to be processed. The active task pool may include a number of slots (eg, 4 slots) for tasks performed by the GPCs 350 actively processed. If a GPC 350 completing the execution of a task, this task is taken from the active task pool for the GPC 350 vacated and one of the other tasks is selected from the pool for pending tasks and to run on the GPC 350 planned. If an active task on the GPC 350 was inactive, such as while waiting for a data dependency to be resolved, then the active task can be taken out of the GPC 350 vacated and returned to the pool for pending tasks, while another task is selected in the pool for pending tasks and to run on the GPC 350 is scheduled.

The work distribution unit 325 communicates with the one or more GPCs 350 via a crossbar or XBar 370 , The XBar 370 is an interconnect network that many of the units of PPU 300 with other units of PPU 300 coupled. For example, the XBar 370 be configured to the work distribution unit 325 with a particular GPC 350 to pair. Although not explicitly shown, one or more other units of PPU 300 also with the XBar 370 over the hub 330 be connected.

The tasks are performed by the planner unit 320 managed and sent to a GPC 350 through the work distribution unit 325 shipped. The GPC 350 is configured to process the task and generate results. The results may differ from other tasks within the GPC 350 be consumed to a different GPC 350 over the XBar 370 forwarded or in memory 304 get saved. The results can be stored in memory 304 about the storage partition units 380 which is a memory interface for reading and writing data to / from the memory 304 to implement. In one embodiment, the PPU includes 300 a number U of storage partition units 380 equal to the number of separate and different storage devices 304 is that with the PPU 300 are coupled. A storage partition unit 380 will be discussed in more detail below 4B described.

In one embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to perform operations on the PPU 300 schedule. In one embodiment, multiple computing applications simultaneously from the PPU 300 executed and the PPU 300 provides isolation, quality of service (QoS), and independent address spaces for the multiple computing applications. An application may generate instructions (ie, API calls) that cause the driver kernel to perform one or more tasks for execution by the PPU 300 to create. The driver kernel issues tasks to one or more streams that are sent by the PPU 300 are processed. Each task may include one or more groups of related threads, referred to herein as a warp. In one embodiment, a warp 32 related threads that can be executed in parallel. Cooperating threads can affect a plurality of threads which include instructions to perform the task, and to exchange the data by a shared memory. Threads and cooperating threads are discussed in more detail 5A described.

4A illustrates a GPC 350 the PPU 300 from 3 according to one embodiment. As in 4A shown, everyone includes GPC 350 a number of hardware units for processing tasks. In one embodiment, each GPC includes 350 a pipeline manager 410 , a pre-raster operations unit (PROP) 415 , a raster engine 425 , a Work Distribution Matrix (WDX) 480 , a storage management unit (MMU) 490 and one or more data processing clusters (DPCs) 420 , It is recognized that the GPC 350 from 4A other hardware units instead of or in addition to those in 4A may include units shown.

In one embodiment, the operation of the GPC 350 through the pipeline manager 410 controlled. The pipeline manager 410 manages the configuration of one or more DPCs 420 for processing tasks assigned to the GPC 350 allocated. In one embodiment, the pipeline manager 410 at least one of the one or more DPCs 420 configure to implement at least a portion of a graphics rendering pipeline. For example, a DPC 420 be configured to use a vertex shader program on the programmable streaming multiprocessor (SM) 440 perform. The pipeline manager 410 can also be configured to receive packets from the work distribution unit 325 to the appropriate logical units within the GPC 350 forward. For example, some packages may be attached to hard-function hardware units in the PROP 415 and / or the raster engine 425 be forwarded while other packets to the DPCs 420 for processing by the primitive engine 435 or the SM 440 can be forwarded. In one embodiment, the pipeline manager 410 configure at least one or more DPCs to implement a neural network model and / or a compute pipeline.

The PROP unit 415 is configured to receive data from the raster engine 425 and the DPCs 420 to be forwarded to a raster operations unit (ROP unit), which will be described in more detail below. The PROP unit 415 may also be configured to perform color blending optimizations, organize pixel data, perform address translations, and the like.

The raster engine 425 includes a number of hard-function hardware units configured to perform various raster operations. In one embodiment, the raster engine includes 425 a setup engine, a Grobraster engine, a Disposal Engine, a truncation engine, a fine grid engine, and a Tiling Engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices. The plane equations are passed to the Grobraster engine to generate coverage information (eg, a (x, y) mask for a tile) for the primitives. The output of the coarse grid engine is transferred to the discard engine, where fragments associated with the primitives that do not pass a z-test are discarded and transferred to a clipping engine, where fragments that are out of viewing stub, be cut off. Those fragments that survive the clipping and discarding may be passed to a fine grid engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine 425 includes fragments to be processed by, for example, a fragment shader within a DPC 420 is implemented.

Every DPC 420 who is in the GPC 350 includes an M-Pipe Controller (MPC) 430 , a primitive engine 435 and one or more SMs 440 , The MPC 430 controls the operation of the DPC 420 , where by the pipeline manager 410 received packets to the appropriate units in the DPC 420 be forwarded. For example, packets associated with a vertex may be sent to the primitive engine 435 which is configured to store vertex attributes associated with the vertex from the memory 304 pick up. In contrast, packets associated with a shader program can be sent to the SM 440 be transmitted.

The SM 440 includes a programmable streaming processor configured to process tasks represented by a number of threads. Every SM 440 includes multiple threads (is multi-threaded) and is configured to concurrently execute a plurality of threads (eg, 32 threads) from a particular group of threads. In one embodiment, the SM implements 440 an SIMD (single-instruction, multi-data) architecture, where each thread in a group of threads (ie, a warp) is configured to process a different set of data based on the same set of instructions. All threads in the group of threads perform the same Instructions. In another embodiment, the SM implements 440 a SIMT (Single Instruction, Multiple Threads) architecture, where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but allowing individual threads in the group of threads to diverge during execution. In one embodiment, a program counter, a call stack, and an execution state are maintained for each warp, allowing concurrency between warps and serial execution within warps when threads within the warp diverge. In another embodiment, a program counter, a call stack, and an execution state are maintained for each individual thread, allowing for equal concurrency between all threads, within and between warps. If the execution state is maintained for each thread, threads that execute the same instructions can be converged and executed in parallel for maximum efficiency. The SM 440 will be discussed in more detail below 5A described.

The MMU 490 provides an interface between the GPC 350 and the storage partition unit 380 ready. The MMU 490 can provide translation of virtual addresses into physical addresses, memory protection and arbitration of memory requests. In one embodiment, the MMU 490 one or more translation lookaside buffers (TLBs) for performing the translation of virtual addresses into physical addresses in the memory 304 ready.

4B illustrates a memory partition unit 380 the PPU 300 from 3 according to one embodiment. As in 4B shown includes the memory partition unit 380 a raster operations (ROP) unit 450 , an L2 cache 460 and a memory interface 470 , The storage interface 470 is with the store 304 coupled. The storage interface 470 can 32, 64, 128 , 1024-bit data buses or the like for high-speed data transfer implement. In one embodiment, the PPU includes 300 U memory interfaces 470 , a storage interface 470 per pair of storage partition units 380 where each pair of memory partition units 380 with a corresponding storage device 304 connected is. For example, the PPU 300 with up to Y storage devices 304 , such as high-bandwidth memory stacks or graphics dual data rates, version 5 SDRAM or other types of persistent storage.

In one embodiment, the memory interface implements 470 an HBM2 memory interface and Y equals half a U. In one embodiment, the HBM2 memory stacks are on the same physical package as the PPU 300 which provides significant performance and area savings compared to traditional GDDR5 SDRAM systems. In one embodiment, each HBM2 stack comprises four memory dies and Y is equal to 4, with the HBM2 stack being two 128 -Bit channels per die for a total of 8 channels and a data bus width of 1024 bits.

In one embodiment, the memory supports 304 Error Correction Code (ECC) with Single Error Correction and Double Error Detection (SECDED) to protect data. The ECC provides greater reliability for computing applications that are sensitive to data corruption. Reliability is especially important in large cluster computing environments where PPUs 300 process very large data sets and / or run applications for longer periods of time.

In one embodiment, the PPU implements 300 a multi-level memory hierarchy. In one embodiment, the storage partition unit supports 380 a unified memory to a single unified virtual address space for the memory of the CPU and the memory of the PPU 300 to provide data sharing between virtual storage systems. In one embodiment, the frequency of accesses by a PPU 300 to a memory that is located on other processors, tracks to ensure that memory pages in the physical memory of the PPU 300 moving more frequently to the pages. In one embodiment, the NVLink supports 310 Address translation services provided by the PPU 300 allow access to page tables of a CPU directly and full access to the CPU memory through the PPU 300 provide.

In one embodiment, copy machines transfer data between multiple PPUs 300 or between PPUs 300 and CPUs. The copy machines can generate page faults for addresses that are not mapped in the page tables. The storage partition unit 380 can then service the page faults, mapping the addresses in the page table after the copier can complete the transfer. In a conventional system, the memory is disabled (ie, not swappable) for multiple copy machine operations between multiple processors, which significantly reduces available memory. With hardware page faulting, addresses can be forwarded to the copy machines without worrying about whether the pages are resident and the copy process is transparent.

Data from the memory 304 or any other system memory may be from the memory partition unit 380 and in the L2 cache 460 stored on-chip and between the various GPCs 350 is shared. As shown, each memory partition unit includes 380 a section of the L2 cache 460 that of a corresponding storage device 304 assigned. Lower level caches may then be in different units within the GPCs 350 be implemented. For example, each of the SMs 440 implement an L1 cache. The L1 Cache memory is a private memory that belongs to a specific SM 440 is permanently assigned. Data from the L2 cache 460 can be fetched and stored in each of the L1 cache memory for processing in the functional units of the SMs 440 get saved. The L2 Cache memory 460 is with the memory interface 470 and the XBar 370 coupled.

The ROP unit 450 performs graphics raster operations concerning pixel color, such as color compression, pixel blending, and the like. The ROP unit 450 also implements depth tests in conjunction with the raster engine 425 wherein a depth for a sample location associated with a pixel fragment is provided by the screening engine of the raster engine 425 Will be received. The depth is tested against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the scan sample depth test, then the ROP unit updates 450 the depth buffer and transmits a result of the depth test to the raster engine 425 , It is recognized that the number of memory partition units 380 from the number of GPCs 350 can distinguish, and therefore, any ROP unit 450 with each of the GPCs 350 be coupled. The ROP unit 450 keeps track of packets coming from different GPCs 350 and determines to which GPC 350 one through the ROP unit 450 Result generated by the Xbar 470 is forwarded. Although the ROP unit 450 within the storage partition unit 380 in 4B includes, can the ROP unit 450 outside the storage partition unit 380 his. For example, the ROP unit 450 in the GPC 350 or another unit.

5A illustrates the streaming multiprocessor 440 from 4A according to one embodiment. As in 5A shown, the SM includes 440 an instruction cache 505 , one or more scheduler units 510 , a register file 520 , one or more processing cores 550 , one or more special function units (SFUs) 552 , one or more load / store units (LSUs) 554 , an interconnect network 580 and a shared L1 cache 570 ,

As described above, the work distribution unit ships 325 Tasks to execute on the GPCs 350 the PPU 300 , The tasks become a specific DPC 420 within a GPC 350 and if the task is assigned to a shader program, the task may be assigned to an SM 440 be assigned. The planner unit 510 receives the tasks from the work distribution unit 325 and manages instruction scheduling for one or more thread blocks associated with the SM 440 are assigned. The planner unit 510 schedules thread blocks to execute as warps from parallel threads, with each thread block associated with at least one warp. In one embodiment, each warp performs 32 Threads off. The planner unit 510 may manage a plurality of different thread blocks, which associate the warps with the different thread blocks, and then assign instructions from the plurality of different cooperative groups to the different functional units (ie, cores 550 , SFUs 552 and LSUs 554 ) during each clock cycle.

Cooperative Groups is a programming model for organizing groups of communicating threads that enables developers to express the granularity at which threads communicate, allowing the expression of richer, more efficient, parallel decompositions. Cooperative launch APIs support synchronization among thread blocks for parallel algorithm execution. Traditional programming models provide a single, simple set up to synchronize cooperating threads: a barrier across all thread block threads (i.e., the syncthreads () function). However, programmers would often like to define groups of threads at smaller than thread block granularities and synchronize within the defined groups to allow for greater performance, design flexibility, and software reuse in the form of collective group-wide functional interfaces.

Cooperative Groups allows programmers to explicitly define groups of threads at sub-block (ie, as small as a single thread) and multi-block granularities and perform collective operations, such as synchronization, on the threads in a cooperative set. The programming model supports clean composition across software boundaries so that libraries and helper functions can securely synchronize within their local context without having to make assumptions about convergence. Enable cooperative groups primitives new patterns of cooperative parallelism involving producer-consumer parallelism, opportunistic parallelism and global synchronization across an entire grid of thread blocks.

A shipping unit 515 is configured to transmit instructions to one or more of the functional units. In the embodiment, the scheduler unit comprises 510 two shipping units 515 that allow two different instructions to be dispatched from the same warp during each clock cycle. In alternative embodiments, each scheduler unit 510 a single shipping unit 515 or additional shipping units 515 include.

Every SM 440 includes a register file 520 containing a set of registers for the functional units of the SM 440 provides. In one embodiment, the register file is 520 divided between each of the functional units so that each functional unit is an associated section of the register file 520 allocated. In another embodiment, the register file is 520 split between the different warps coming from the SM 440 be executed. The register file 520 provides temporary storage for operands associated with the data paths of the functional units.

Every SM 440 includes L processing cores 450 , In an embodiment, the SM comprises 440 a large number (eg, 128 , etc.) of different processing cores 450 , Every core 450 may comprise a fully pipelined single precision processing unit comprising a floating point arithmetic logic unit and an integer arithmetic logic unit. In one embodiment, the floating point arithmetic logic units implement the IEEE 754 - 3008 Standard for floating-point arithmetic. In one embodiment, the cores comprise 550 64 Single-precision (32-bit) floating point kernels, 64 integer cores, 32 dual-precision (64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and in one embodiment, one or more tensor cores are in the cores 550 includes. In particular, the tensor cores are configured to perform deep learning matrix arithmetic, such as neuronal network training and inferencing convolution operations. In one embodiment, each tensor core operates on a 4x4 matrix and performs a matrix multiplication and accumulation operation D = A × B + C, where A, B, C, and D are 4x4 matrices.

In one embodiment, the matrix multiply inputs A and B are 16-bit floating point arrays, while the accumulation matrices C and D may be 16-bit floating point or 32-bit floating point arrays. Tensor cores operate on 16-bit floating point input data with 32-bit floating-point accumulation. The 16-bit floating-point multiplication requires 64 operations and yields a product of full precision, which is then accumulated using a 32-bit floating-point addition with the other intermediates for 4x4x4 matrix multiplication. In practice, tensor cores are used to perform much larger two-dimensional or higher-dimensional matrix operations built by these smaller elements. An API, such as the CUDA 9 C ++ API, provides specialized matrix load, matrix multiplication, and matrix accumulation and matrix memory operations to efficiently use tensor cores from a CUDA-C ++ program. At the CUDA level, the warp interface level assumes 16x16 large matrices spanning all 32 threads of the warp.

Every SM 440 also includes M SFUs 552 performing special functions (eg attribute evaluation, reciprocal square root and the like). In one embodiment, the SFUs 552 comprise a tree traversal unit configured to traverse a hierarchical tree data structure. In one embodiment, the SFUs 552 comprise a texture unit configured to perform texture map filtering operations. In one embodiment, the texture units are configured to include texture maps (eg, a 2D array of texels) from the memory 304 to load and scan the texture maps to produce sampled texture values for use in shader programs generated by the SM 440 be executed. In one embodiment, the texture maps in the shared memory / L1 cache 470 saved. The texture units implement texture operations, such as filter operations, using mip maps (ie, texture maps of varying degrees of detail). In one embodiment, each SM includes 340 two texture units.

Every SM 440 also includes N LSUs 554 , the load and store operations between the shared memory / L1 cache 570 and the register file 520 to implement. Every SM 440 includes an interconnect network 580 containing each of the functional units with the register file 520 and the LSU 554 with the register file 520 , the shared memory / L1 cache 570 combines. In one embodiment, the interconnect network is 580 a crossbar, which may be configured to any of the functional units with any of the registers in the register file 520 to connect and the LSUs 554 with the Register file and shared memory / L1 cache memory locations 570 connect to.

The shared memory / L1 cache 570 is an on-chip memory arrangement, data storage and communication between the SM 440 and the primitive engine 435 and between threads in the SM 440 allows. In one embodiment, the shared memory includes / L1 cache memory 570 128KB of storage capacity and is in the path of the SM 440 to the storage partition unit 380 , The shared memory / L1 cache 570 can be used to cache reads and writes. One or more of the shared memory / L1 caches 570 , L2 cache 460 and memory 304 are background storage.

Combining a data cache and shared memory functionality into a single block of memory provides the best overall performance for both types of memory accesses. The capacity is usable as a cache of programs that do not use the shared memory. For example, if the shared memory is configured to use half the capacity, texture and load / store operations can use the remaining capacity. Integration within shared memory / L1 cache 570 allows the shared memory / L1 cache memory 570 as a high throughput line to stream data while providing higher bandwidth and low latency access to frequently reused data.

When configured for general-purpose parallel calculation, a simpler configuration can be used in comparison with graphic processing. In detail, the in 3 bypassed fixed-function graphics processing units, creating a much simpler programming model. In the general purpose parallel calculation configuration, blocks of threads are taken from the work distribution unit 325 directly to the DPCs 420 assigned and distributed. The threads in a block run the same program using a unique thread ID in the calculation to ensure that each thread produces unique results using the SM 440 To run the program and perform calculations on a shared memory / L1 cache 570 to communicate between threads and the LSU 554 off to global memory through the shared memory / L1 cache 570 and the storage partition unit 380 to read and describe. When configured for general purpose parallel computation, the SM can 440 also write commands that the planner unit 320 can use to new work on the DPCs 420 to start.

The PPU 300 may be included in a desktop computer, a laptop computer, a tablet computer, a smartphone (eg, a wireless handheld device), a personal digital assistant (PDA), a digital camera, a handheld electronic device, and the like. In one embodiment, the PPU 300 embodied on a single semiconductor substrate. In another embodiment, the PPU 300 in a system-on-chip (SoC) along with one or more other devices, such as additional PPUs 300 the store 204 , a computer-reduced command set (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like.

In one embodiment, the PPU 300 on a graphics card that includes one or more memory devices 304 includes. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In yet another embodiment, the PPU 300 an integrated graphics processing unit (iGPU) or a parallel processor included in the chipset of the motherboard.

Exemplary calculation system

Systems with multiple GPUs and CPUs are used in a variety of industries as developers expose and leverage more parallelism in applications such as artificial intelligence computing. High-performance GPU-accelerated systems with tens to thousands of compute nodes are being used in data centers, research facilities, and supercomputers to solve ever-increasing problems. As the number of processing devices within the high performance systems increases, the communication and data transfer mechanisms must be adjusted to support the increased bandwidth.

5B is a conceptual diagram of a processing system 500 using the PPU 300 from 3 is implemented, according to one embodiment. The exemplary system 565 can be configured to work in each case 1C . 1F . 1G . 2 B and 2D shown method 130 . 150 . 160 . 220 and 250 to implement. The processing system 500 includes a CPU 530 , a switch 510 and in each case several PPUs 300 and respective memories 304 , The NVLink 310 provides high-speed communication links between each of the PPUs 300 ready. Although a certain number of connections of NVLink 310 and the interconnect 302 in 5B can be illustrated, the number of connections to each PPU and the CPU 530 vary. The desk 510 interfaces between the interconnect 302 and the CPU 530 , The PPUs 300 , Storage 304 and NVLinks 310 can be located on a single semiconductor platform to a parallel processing module 525 to build. In one embodiment, the switch supports 510 two or more protocols to interface between different connections and / or links.

In another embodiment (not shown), the NVLink provides 310 one or more high-speed communication links between each of the PPUs 300 and the CPU 530 ready and the switch 510 is interfaced between the interconnect 302 and each of the PPUs 300 connected. The PPUs 300 , the memory 304 and the interconnect 302 may be located on a single semiconductor platform to a parallel processing module 525 to build. In yet another embodiment (not shown), the interconnect provides 302 one or more communication links between each of the PPUs 300 and the CPU 530 ready and the switch 510 is interfaced between each of the PPUs 300 using the NVLink 310 connected to one or more high-speed communication links between the PPUs 300 provide. In another embodiment (not shown), the NVLink provides 310 one or more high-speed communication links between the PPUs 300 and the CPU 530 through the switch 510 ready. In yet another embodiment (not shown), the interconnect provides 302 one or more high-speed communication links between each of the PPUs 300 ready to go. One or more of the NVLink 310 High-speed communication links may act as a physical NVLink interconnect or as either an on-chip or on-die interconnect using the same protocol as the NVLink 310 be implemented.

In the context of the present description, a single semiconductor platform may refer to a single unitary semiconductor-based integrated circuit fabricated on a die or chip. It should be understood that the term single semiconductor platform may also refer to multi-chip modules with increased connectivity that simulate on-chip operation and make the significant improvements over using a conventional bus implementation. Of course, the various circuits or devices may also be located separately or in various combinations of semiconductor platforms according to the desires of the user. Alternatively, the parallel processing module 525 be implemented as a printed circuit board substrate and each of the PPUs 300 and / or memory 304 can be packaged devices. In one embodiment, the CPU 530 , the desk 510 and the parallel processing module 525 situated on a single semiconductor platform.

In one embodiment, the signal rate is from each NVLink 310 20 to 25 Gigabit / s and every PPU 300 includes six NVLinks 310 Interfaces (as in 5B shown five NVLink 310 Interfaces are for each PPU 300 comprises). Every NVLink 310 provides a data transfer rate of 25 gigabytes / s in each direction, with six links 300 Deploy gigabytes / s. The NVLinks 310 can be used exclusively for PPU-to-PPU communication, as in 5B shown, or a combination of PPU-to-PPU and PPU-to-CPU are used when the CPU 530 also one or more NVLinks 310 Interfaces includes.

In one embodiment, the NVLink allows 310 a direct load / memory / atomic access of the CPU 530 on every store 304 the PPU 300 , In one embodiment, the NVLink supports 310 Coherence operations that enable that from memory 304 read data in the cache hierarchy of the CPU 530 can be stored, which is the cache access latency for the CPU 530 reduced. In one embodiment, the NVLink includes 310 Support for Address Translation Services (ATS), what the PPU 300 allows on page tables within the CPU 530 directly access. One or more of the NVLinks 310 may also be configured to operate in a low power mode.

5C illustrates an exemplary system 565 in which the various architecture and / or functionality of the various previous embodiments may be implemented. The exemplary system 565 can be configured to work in each case 1C . 1F . 1G . 2 B and 2D shown method 130 . 150 . 160 . 220 and 250 to implement.

As shown, a system 565 provided, the at least one central processing unit 530 includes that with a communication bus 575 connected is. The communication bus 575 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI Express, Accelerated Graphics Port (AGP), Hyper-Transport, or any other bus or point-to-point communication protocol (s). The system 565 also includes a main memory 540 , control logic (Software) and data are stored in main memory 540 which may take the form of a random access memory (RAM).

The system 565 also includes input devices 560 , the parallel processing system 525 and display devices 545 That is, a conventional CRT (Cathode Ray Tube), an LCD (Liquid Crystal Display), an LED (Light Emitting Diode), a plasma display, or the like. User input may be from the input devices 560 , eg keyboard, mouse, touchpad, microphone and the like. Any of the foregoing modules and / or devices may even be located on a single semiconductor platform to the system 565 to build. Alternatively, the various modules may also be located separately or in different combinations of semiconductor platforms according to the desires of the user.

Furthermore, the system can 565 with a network (eg, a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) through a network interface 535 be coupled for communication purposes.

The system 565 may also include a secondary memory (not shown). The secondary storage 610 For example, a hard disk drive and / or a removable storage drive constituting a floppy disk drive includes a magnetic tape drive, a compact disk drive, a digital versatile disk (DVD) drive, a recording device, and a universal serial bus (USB) flash memory. The removable storage drive reads from and / or writes to a removable storage device in a well-known manner.

Computer programs or computer control logic algorithms may reside in main memory 540 and / or the secondary storage. Such computer programs, when executed, enable the system 565 to perform various functions. The memory 540 , storage, and / or any other storage are possible examples of computer-readable media.

The architecture and / or functionality of the various previous figures may be implemented in the context of a general computer system, a circuit board system, an entertainment dedicated games console system, an application specific system, and / or any other desired system. For example, the system can 565 the form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smartphone (eg, a wireless hand-held device), a personal digital assistant (PDA), a digital camera, a vehicle, a head-mounted display , a handheld electronic device, a mobile telephone, a television, a workstation, a game console, an embedded system, and / or any other type of logic.

While various embodiments have been described above, it should be understood that they have been presented by way of example only and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only by the following claims and their equivalents.

machine learning

Deep neural networks (DNNs) developed on processors such as the PPU 300 , have been used for a variety of uses, from self-propelled cars to faster drug development, from automatic image capturing to online image databases to smart real-time language translation in video chat applications. Deep learning is a technique that models the neuronal learning process of the human brain, continuously learning, continually becoming smarter, and delivering more accurate results faster over time. A child is initially taught by an adult to correctly identify and classify various forms to eventually be able to identify forms without any tutoring. Similarly, a depth learning system or a neural learning system must be trained in object recognition and classification to make it smarter and more efficient in identifying basic objects, obscured objects, etc. while also assigning context to objects.

At the simplest level, neurons in the human brain look at various inputs being received, assigning importance levels to each of these inputs, and passing an output to other neurons to act upon them. An artificial neuron or perceptron is the most basic model of a neural network. In one example, a perceptron may receive one or more inputs representing various features of an object that the perceptron is trained to recognize and classify, and each of these features will have a particular weight based on the importance of the feature in defining the shape of a feature Assigned to object.

A deep neural network (DNN) model includes multiple layers of many connected nodes (eg perceptrons, Boltzmann machines, radial basis functions, convolution layers, etc.) that can be trained with enormous amounts of input data to quickly solve complex problems with high accuracy to solve. In one example, a first layer of the DNN model breaks up an input image of an automobile into various sections and looks for basic patterns such as lines and angles. The second layer assembles the lines to search for higher level patterns such as wheels, windshields, and mirrors. The next layer identifies the type of vehicle and the last few layers create a label for the input image that identifies the model of a particular automotive brand.

Once the DNN is trained, the DNN can be used and used to identify and classify objects or patterns in a method known as inference. Examples of inference (the process by which a DNN extracts useful information from a given input) include identifying handwritten numbers on checks deposited into cash dispensing machines, identifying pictures of friends in photos, delivering movie recommendations to over fifty Millions of users, identifying and classifying different types of automobiles, pedestrians and road hazards in driverless cars or translating human speech in real time.

During training, data flows through the DNN in a forward propagation phase until a prediction is generated indicating a label corresponding to the input. If the neural network does not identify the input correctly, then errors between the correct label and the predicted label are analyzed and the weights are adjusted for each feature during a reverse propagation phase until the DNN correctly identifies the input and other inputs to a training data set. Complex neural network training requires enormous amounts of parallel computing power, including floating-point multiplication and floating-point additions by the PPU 300 get supported. Inferencing is less computationally intensive than training, which is a latency-sensitive method whereby a trained neural network is applied to new inputs that it has not previously seen to classify images, translate, and generally derive new information.

Neural networks rely heavily on matrix computing operations, and complex multi-layered networks require massive amounts of floating point performance and bandwidth for both efficiency and speed. With thousands of processing cores optimized for matrix arithmetic operations, delivering from ten to hundreds of TFLOPS of performance, the PPU is 300 a computing platform capable of delivering the performance required for deep neural network-based artificial intelligence and machine learning applications.

Claims (16)

Computer-implemented method comprising: Processing a photorealistic content image and a photorealistic style image by a max-pooling layer of a coder portion of a photo-transfer neuronal network model to generate location data indicating a location within a feature map of a maximum value output from the max-pooling layer; and Processing an output of the encoder section from a dispersing layer of a decoder section of the photo-transfer-neuronal network model based on the location data to produce a stylized photorealistic image comprising contents of the photorealistic content image modified according to the photorealistic style image. Computer-implemented method according to Claim 1 further comprising processing the stylized photorealistic image in accordance with pixel similarity data for the photorealistic content image to produce a smoothed stylized photorealistic image. Computer-implemented method according to Claim 2 wherein the pixel similarity data identifies pixels in the stylized photorealistic image that are consistent in color with neighboring pixels. Computer-implemented method according to Claim 2 or 3 solving a quadratic function with a solution in closed form to produce the smoothed stylized photorealistic image. Computer-implemented method according to one of Claims 2 to 4 wherein the pixel similarity data comprises pixel affinity values. The computer-implemented method of any one of the preceding claims, further comprising processing the photorealistic style image by a second photo-transfer neuronal network model to produce an improved photorealistic style image, wherein the second photo-transfer-neuronal network model has a lower feature representation compared to the photo-transfer neuronal network model. The computer-implemented method of claim 1, wherein the photorealistic style image is segmented into a first style region and a second style region, and the photo-style transfer neural network model processes the first style region and a corresponding first content region of the photorealistic content image to include a first region of the photorealistic style image produce. The computer-implemented method of claim 1, wherein the photorealistic content image is segmented into a first content region and a second content region, and the photorelief transfer neural network model processes the first content region and a corresponding first style region of the photorealistic style image to include a first region of the photorealistic style image produce. Computer-implemented method comprising: Receiving a stylized photorealistic image generated by a photo-transfer neuronal network model, the stylized photorealistic image comprising content from a photorealistic content image modified according to a photorealistic style image; and Processing the stylized photorealistic image according to pixel similarity data for the photorealistic content image to produce a smoothed stylized photorealistic image. Computer-implemented method according to Claim 9 wherein the pixel similarity data comprises pixel affinity values. Computer-implemented method according to Claim 9 or 10 wherein the photostenergy transfer neural network model generates the stylized photorealistic image based on segmentation data for at least one of the photorealistic content image and the photorealistic style image. A system comprising a photostenergy transfer neural network model having an encoder section and a decoder section, the encoder section configured to: process a photorealistic content image and a photorealistic style image from a max-pooling layer of the encoder section to produce location data identifying a location within a feature map of a maximum value output from the max-pooling layer; and process an output of the encoder section by a dispersing layer of the decoder section based on the location data to produce a stylized photorealistic image comprising content from the photorealistic content image modified according to the photorealistic style image. System according to Claim 12 , further comprising a smoothing function module configured to process the stylized photorealistic image according to pixel similarity data for the photorealistic content image to produce a smoothed stylized photorealistic image. System according to Claim 12 or 13 , which is further configured to perform a method as in any of Claims 1 to 8th mentioned. System according to one of Claims 12 to 14 , further comprising a second photo-transfer neuronal network model configured to process the photorealistic style image to produce an improved photorealistic style image, wherein the second photo-transfer-neuronal network model has less feature representation as compared with the photo-transfer neuronal network model having. A non-transitory computer-readable storage medium that stores instructions that, when executed by a processing unit, cause the processing unit to perform a method as in any of Claims 1 to 8th mentioned.

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