DE102019100505A1 - Perform a texture detail level approximation - Google Patents

Abstract

A texture detailing (LOD) approximation may be performed using beam differentials and a G-buffer. For example, a scene to be rendered is identified and a G-buffer of the scene is rendered. In addition, ray tracing for the scene is started, and during ray tracing, a beam differential is generated by accessing the G buffer. Furthermore, the generated radiation differential is appended to a current beam and the generated radiation differential tracked.

Description

FIELD OF THE INVENTION

The present invention relates to image rendering, and more particularly to computing texture footprints in reflections during real-time ray tracing.

BACKGROUND

High-quality texturing is desirable for real-time ray tracing to improve the appearance of rendered images. Current methods of performing texturing, however, use ray differentials or covariance matrices or nearest neighbor sampling, which either uses a lot of memory per pixel as well as a large amount of instructions to compute a texture footprint or results in low quality images. Without proper texture filtering, a texture visible in a reflection can alias, which can cause flickering when objects or the camera are moving. Existing methods are either too laborious or lead to low quality results. Therefore, a faster means of texturing is needed.

Thus, there is a need to address these problems and / or other problems associated with the prior art.

SUMMARY

A method, a computer readable medium, and a system are disclosed for performing a texture detail level approximation. For example, a scene to be rendered is identified and a G-buffer of the scene is rendered. In addition, ray tracing for the scene is started and during ray tracing, a ray differential is generated by accessing the G buffer. Furthermore, the generated radiation differential is appended to a current beam and the generated radiation differential tracked.

list of figures

• 1 FIG. 12 illustrates a flow chart of a method of performing a texture detail level approximation according to one embodiment; FIG.
• 2 illustrates a parallel processing unit according to an embodiment;
• 3A FIG. 16 illustrates a general processing cluster of the parallel processing unit of FIG 2 according to an embodiment;
• 3B illustrates a partition unit of the parallel processing unit of 2 according to an embodiment;
• 4 illustrates the streaming multiprocessor of 3A according to an embodiment;
• 5 FIG. 12 illustrates a system-on-chip that includes the parallel processing unit of FIG 2 comprises, according to an embodiment;
• 6 FIG. 12 is a conceptual diagram of a graphics processing pipeline executed by the parallel processing unit of FIG 2 is implemented, according to one embodiment;
• 7 FIG. 4 illustrates an exemplary system in which the various architecture and / or functionality of all embodiments may be implemented; FIG.
• 8th FIG. 12 illustrates an exemplary approximation of a footprint of a pixel in texture space according to an embodiment; FIG. and
• 9 FIG. 12 illustrates an exemplary taper tracking implementation for computing the texture LOD within a scene, according to one embodiment. FIG.
• 10 FIG. 11 illustrates an exemplary geometric arrangement for a cone through a pixel according to an embodiment. FIG.
• 11 FIG. 12 illustrates an exemplary geometric arrangement for texture LOD calculations for reflections according to one embodiment. FIG.
• 12 illustrates an exemplary geometric arrangement to α ₀ and α (τ) according to one embodiment.
• 13 illustrates exemplary reflection interaction on different types of geometry according to one embodiment.
• 14 FIG. 12 illustrates an example exaggerated view of a geometric arrangement for texture LOD calculations for reflections according to one embodiment. FIG.
• 15 Figure 12 illustrates an example geometry used in calculating φ to determine a surface propagation angle β involved, according to one embodiment.
• 16 FIG. 12 illustrates an example relationship between changes in a normal vector and a reflected vector according to one embodiment. FIG.
• 17 FIG. 12 illustrates a flow diagram of a method of performing a texture detail level approximation using one or more ray differentials with a G-buffer according to an embodiment.

DETAILED DESCRIPTION

1 illustrates a flowchart of a method 100 for performing a texture detailing (LOD) approximation according to one embodiment. In one embodiment, the LOD approximation may be used to estimate the size of a texture footprint (eg, by computing a texture footprint for a second hit point, such as a reflection point). As in operation 102 shown, a scene to be rendered is indicated. Besides, as in operation 104 shown projecting a ray passing through a pixel of a screen space, resulting in a first hit point on a feature within the scene.

Further, as in Operation 106 shown determines a footprint angle of the pixel. In one embodiment, the footprint angle may be a propagation angle α which models a spread of the pixel in radians. Furthermore, as in Operation 108 a curvature measure for the feature at the first hit point within the scene is determined. For example, the curvature β can be used to determine an additional spread of the pixel caused by a curvature at the hit point.

In one embodiment, the amount of curvature β are precalculated per vertex and interpolated over a triangle. In another embodiment, determining the amount of curvature may include negating the amount of curvature when the geometry is concave. In yet another embodiment, the propagation angle may be propagated through the scene as a beam skipping within the scene.

Also, as in Operation 110 For example, a texture texture level (LOD) approximation for a component of the scene is calculated using the footprint angle of the pixel and the curvature dimension for the feature. In one embodiment, a distance to the hit point, a beam direction, and a normal at the hit point may also be used to calculate the LOD approximation for the component of the scene.

In another embodiment, the component may include reflection within the scene, recursive reflection within the scene, and so on. In yet another embodiment, the component may include a refraction within the scene, a recursive refraction within the scene, and so on. In yet another embodiment, the LOD approximation may be used to estimate a size of a texture footprint for a second hit point.

In one embodiment, if the component comprises recursive reflection or recursive refraction, a projected footprint may be determined at the first hit point. The projected footprint may be transported from the first hit point to a second hit point, and a size of the projected footprint may be used as the texture LOD approximation for the component at the second hit point.

Besides, as in operation 112 performing one or more rendering operations for the scene using the texture LOD approximation using a hardware processor. In one embodiment, the one or more rendering operations may include one or more Texturing operations include. In another embodiment, the one or more mipmapping operations performed using the texture LOD approximation may include. In yet another embodiment, the one or more rendering operations may include determining multiple mipmapped reflections or reflections, or a combination of the two using the texture LOD approximation.

In this way, a texture LOD approximation based on an isotropic derivative can be calculated. In addition, a footprint angle and a curvature measure can be used in approximate operations. As a result, a number of instructions used to compute texture footprints in reflections as well as an amount of memory bandwidth used to compute texture footprints in reflections can be reduced.

Further illustrative information will now be set forth with regard to various optional architectures and features with which the previous framework may or may not be implemented according to the wishes of the user. It should be emphasized that the following information is presented for illustrative purposes and should not be construed as limiting in any way. Each of the following features may optionally be included with or without the exclusion of other described features.

Texture detail level for real-time ray tracing

overview

Filtered texturing that targets real-time ray tracing can be either at the mip level 0 be accessed with bilinear filtering or a more sophisticated and complex Strahlendifferentialverfahren be used. However, a technique is presented that is about the same performance as accessing mip-level 0 and at the same time gives a much higher image quality. The image quality using this method may even be higher than beam differentials using a single trilinear lookup. This technique may be based on triangular properties, curvature estimation, distance, and angle of incidence.

introduction

wobei (x,y) Pixelkoordinaten sind und die Funktion ρ berechnet werden kann als: $$\rho \left(x,y\right)=\text{max}\left\{\sqrt{{\left(\frac{\partial u}{\partial x}\right)}^2+{\left(\frac{\partial v}{\partial x}\right)}^2},\sqrt{{\left(\frac{\partial u}{\partial y}\right)}^2+{\left(\frac{\partial v}{\partial y}\right)}^2}\right\},$$

für zweidimensionale Textur-Lookups, wobei (u,v) Texelkoordinaten, d.h., Texturkoordinaten (∈ [0, 1]²) multipliziert mit der Texturauflösung sind. 8 veranschaulicht eine beispielhafte Näherung eines Footprint 800 eines Pixels 802 im Texturraum gemäß einer beispielhaften Ausführungsform.Mipmapping is a standard technique to avoid texture aliasing, and all GPUs can support this technique for rasterization. For example, OpenGL specifies the level of detail parameter (LOD parameter), λ, as: $$\lambda \left(x.y\right)={\text{<figure-callout id="2" label="log" filenames="DE102019100505A1\_0052.png,DE102019100505A1\_0053.png" state="{{state}}">log</figure-callout>}}_2\lceil \rho \left(x.y\right)\rceil .$$

where (x, y) are pixel coordinates and the function ρ can be calculated as: $$\rho \left(x.y\right)=\text{Max}\left\{\sqrt{{\left(\frac{\partial u}{\partial x}\right)}^2+{\left(\frac{\partial v}{\partial x}\right)}^2}.\sqrt{{\left(\frac{\partial u}{\partial y}\right)}^2+{\left(\frac{\partial v}{\partial y}\right)}^2}\right\}.$$

for two-dimensional texture lookups, where ( u . v ) Texel coordinates, ie, texture coordinates (∈ [0, 1] ² ) multiplied by the texture resolution. 8th illustrates an exemplary approximation of a footprint 800 of a pixel 802 in texture space according to an exemplary embodiment.

An exemplary goal of these functions may be to ensure that access is made in the mipmap hierarchy in such a way that a screen space pixel is mapped to approximately one texel. In general, GPU hardware can calculate the differentials by evaluating the pixel shader in 2 x 2 pixel squares at a time and using per-pixel differences. Note, however, that even Equation 2 is not conservative because it does not compute a minimal box around the footprint. The maximum side of such a conservative box can be given as p (x, y) = max (| ∂u / ∂x | + | ∂v / ∂x |, | ∂u / ∂y | + | ∂v / ∂y |) be calculated. As a result, most methods can produce both excessive blur and aliasing, which is easily demonstrated using GPU-based texturing.

For ray tracing the same target may be desired, but it must be extended to handle recursive ray paths. Since the above Pixelquad concept may not be generally available for ray tracing (except possibly for ophthalmic rays), other approaches may be needed. For example, a ray differential method using the chain rule can accurately calculate a texture footprint even for reflections and refractions. The use of beam differentials can be computationally expensive and use a considerable amount of per-beam data, and for real-time ray tracing faster methods using a smaller amount of per-beam data may be required. In addition, results show that the beam differential technique may not always be conservative.

As a result, a new texture LOD technique can be implemented that targets real-time ray tracing and that can exploit the mipmap structure. It can describe the beam footprint through a cone and then grow or shrink the cone along the beam path depending on surface interactions. The terms can be used based on a distance, a normal at a hit point, and texture and position coordinates. Results show that the output quality is much better than just using MIP level 0 with bilinear filtering, and may even be better than beam differentials with a single trilinear lookup.

For filtered texture mapping, a hierarchical image pyramid, called a mipmap, can be used to speed up the process. The footprint of the pixel may be mapped into texture space, and an X value may be calculated with a goal consisting in providing an alias-free image without excessive blurring. This λ can then be used along with the texture coordinates of the current fragment to apply trilinear interpolation in the mipmap.

wobei die Variablen T_a und P_a das Zweifache der Texel-Raumbereiche und das Zweifache des Dreieckbereichs im Bildschirmraum sind. Diese werden berechnet als: $$\begin{array}{c}{T}_a=t_w{t}_h\left|\left(t_{1u}-t_{0u}\right)\left(t_{2v}-t_{0v}\right)-\left(t_{2u}-t_{0u}\right)\left(t_{1v}-t_{0v}\right)\right|,\\ P_a=\left|\left(p_{1x}-p_{0x}\right)\left(p_{2y}-p_{0y}\right)-\left(p_{2x}-p_{0x}\right)\left(p_{1y}-p_{0y}\right)\right|,\end{array}$$

wobei t_w × t_h die Dimension der Textur ist, t_i = (t_iu, t_iv) die zweidimensionalen Texturkoordinaten an jedem Vertex sind und p_i = (p_ix, piy), i ∈ {0, 1, 2} die drei Dreieckseckpunkte im Bildschirmraum sind.Many different approximations can be used for a texture LOD. For example, a rough approximation may use a single LOD for an entire triangle. This can be calculated as: $$\Delta ={\text{log}}_2\left(\sqrt{\frac{T_a}{P_a}}\right)=0.5{\text{log}}_2\left(\frac{T_a}{P_a}\right).$$

where the variables T _a and P _a are twice the texel space areas and twice the triangle area in screen space. These are calculated as: $$\begin{array}{c}{T}_a=t_w{t}_H\left|\left(t_{1u}-t_{0u}\right)\left(t_{2v}-t_{0v}\right)-\left(t_{2u}-t_{0u}\right)\left(t_{1v}-t_{0v}\right)\right|.\\ P_a=\left|\left(p_{1x}-p_{0x}\right)\left(p_{2y}-p_{0y}\right)-\left(p_{2x}-p_{0x}\right)\left(p_{1y}-p_{0y}\right)\right|.\end{array}$$

where t _w × t _{h is} the dimension of the texture, t _i = (t _iu , t _iv ) are the two-dimensional texture coordinates at each vertex and p _i = (p _ix , piy), i ∈ {0, 1, 2} there are three triangle vertices in screen space.

wobei p_i = (p_ix, p_iy, p_iz) nun im Welt-Raum sind und × das Vektorprodukt bezeichnet. Diese Anordnung kann ausgenutzt werden, da Gleichung 3 dann ein 1-1-Zuordnung zwischen Pixeln und Texeln geben kann, wenn das Dreieck auf der Ebene z = 1 lokalisiert ist. In diesen Fall kann Δ als ein Basistextur-Detaillierungsgrad des Dreiecks betrachtet werden.The area of the triangle can also be calculated in world space as $$P_a=\Vert \left(p_1-p_0\right)\times \left(p_2-p_0\right)\Vert .$$

where p _i = (p _ix , p _iy , p _iz ) are now in world space and × denotes the vector product. This arrangement can be exploited because Equation 3 can then give a 1-1 mapping between pixels and texels if the triangle is located on the z = 1 plane. In this case can Δ be considered as a base texture detail level of the triangle.

A method of filtered texturing for ray tracing can use ray differentials, track them through the scene, and apply the chain rule to model reflections and refractions. The calculated LOD can be used with either regular mipmapping or anisotropically sampled mipmapping. This can be extended to handle path tracking with general reflection and refraction functions. Other uses have also been found for beam differentials. For example, they can be used to determine what geometrical level of detail is to be accessed in a multi-resolution geometric cache system. Radiation differentials may also be used to calculate a suitable radius of the photon mapping kernel density estimate.

In one embodiment, texture LOD may be computed for rasterization using differences in 2x2 pixel squares with some overshadowing along edges. For real-time ray tracing, quickly calculating the texture detail level can be valuable.

Exemplary procedure

An exemplary method of calculating texture detail level (LOD) may be based on tracking the cone. For example, the method can only be used for the texture LOD. In one embodiment, when the texture LOD λ for a pixel, the texture sampler in the GPU is used to perform trilinear mipmapping.

In one embodiment, an approximation for a texture LOD for ray tracing may be derived. For example, an approximation to screen space mapping may be derived, which may be extended to handle recursive ray tracing with reflections. In another embodiment, all types of surface interactions can be handled.

9 FIG. 12 illustrates an exemplary cone tracking implementation for computing the texture LOD within a scene. FIG 900 according to one embodiment. As shown, becomes a cone 902A-C through a pixel 904 generated and through the scene 900 transported growing and shrinking. In one embodiment, assuming that the rectangle 906 in the scene 900 is textured and the other objects 908 and 910 are perfectly reflective, a texture lookup at the hit point 912 on the rectangle 906 using the width of the cone 902C and the normal can be done there and a textured reflection can be in the far left object 908 appear.

screen space

10 illustrates an exemplary geometric arrangement 1000 for a cone 1002 through a pixel 1004 according to one embodiment. As shown, the footprint angle becomes 1006 , also called propagation angle, of a pixel denoted by α, d ₀ is the vector 1008 from the camera 1010 to the first hit point 1012 and n ₀ is the normal 1014 at the first hit point 1012 , This cone 1002 can through a pixel 1004 and the cone parameters can be updated at each surface of the mid-beam hit.

wobei v eine normierte Richtung von v angibt, n₀ · d ₀ die Quadratwurzel der projizierten Fläche modelliert und a · b das Skalarprodukt zwischen a und b ist. Es gibt den Absolutwert, um nach vorne weisende und nach hinten weisende Dreiecke auf die gleiche Weise zu handhaben. Wenn [-d₀, n₀] = 0, gibt es lediglich die Abstandsabhängigkeit, und wenn [-d₀ , n₀ ] wächst, kann der projizierte Footprint größer und größer gegen unendlich werden, wenn [-d₀, n₀] → π/2.In one embodiment, the footprint width may grow with the distance and at the first hit point 1012 can the cone width w ₀ = 2 || v || tan (α / 2) ≈ α || d ₀ || be the index 0 can be used to specify the first hit. The small angle approximation, that is, tan α ≈ α, can be used in the above expression. The footprint projected onto the plane at the hit point can also change in size due to the angle, labeled [-d, n], between -d and n. The larger the angle, the more the beam can "see" from the triangular surface, and consequently the LOD can increase (ie, texel access can be performed higher in the mipmap pyramid, etc.). Together, these factors can form the approximated projected footprint as: $$\alpha \Vert {\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0\Vert \frac{1}{\left|\overline{{\mathrm{<figure-callout\; id="0"\; label="n"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">n</figure-callout>}}_0}\cdot \overline{{\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0}\right|}.$$

in which v indicates a normalized direction of v, n ₀ · d _{0 is} the square root of the projected area and a · b is the scalar product between a and b. It gives the absolute value to handle forward and backward triangles in the same way. If [-d ₀ , n ₀ ] = 0, there is only the distance dependence, and if [ -d ₀ . n ₀ ], the projected footprint may become larger and larger towards infinity if [-d ₀ , n ₀ ] → π / 2.

wobei Δ, d.h., der Basistextur-LOD an dem aktuellen Dreieck durch Gleichungen 3 und 5 beschrieben werden kann. Zu beachten ist, dass Δ hinzugefügt werden kann, um einen vernünftigen Basis-LOD bereitzustellen, wenn das Dreieck bei z = 1 lokalisiert ist. Dieser Term kann Änderungen in Dreieckseckpunkten und Texturkoordinaten berücksichtigen. Wenn ein Dreieck beispielsweise zweimal so groß wird, dann kann der Basis-LOD um eins abnehmen. Die anderen Faktoren in Gleichung 7 können den LOD in der Mipmap-Pyramide nach oben drücken, wenn der Abstand oder der Einfallswinkel zunimmt.Because the pixel-to-texel ratio (per edge, not per surface) can halve when the above term doubles, it can log ₂ be used on this term. Thus, a heuristic is for the texture LOD for the first hit, ie, similar to what would result from mipmapping generated by the GPU screen space, $$\lambda =\Delta +{\text{log}}_2\left(\underset{{\mathrm{<figure-callout\; id="0"\; label="w"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">w</figure-callout>}}_0}{\underset{\}}{\alpha \Vert {\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0\Vert }}\frac{1}{\left|{\overline{n}}_0\cdot {\overline{d}}_0\right|}\right).$$

where Δ, ie, the base texture LOD at the current triangle can be described by Equations 3 and 5. It should be noted that Δ can be added to provide a reasonable base LOD if the triangle is located at z = 1. This term can take into account changes in triangle vertices and texture coordinates. For example, if a triangle becomes twice as large, then the base LOD may decrease by one. The other factors in Equation 7 can push up the LOD in the mipmap pyramid as the distance or angle of incidence increases.

reflection

In one embodiment, the above method may be generalized to handle reflections as well. 11 illustrates an exemplary geometric arrangement 1100 for calculations for the texture LOD for reflections according to one embodiment. As shown, the camera was 1102 in the plane 1104 of the surface hit point 1106 reflects what makes the rays collinear. The reflected hit point 1108 is also shown.

In one embodiment, the width, w ₁ , the footprint 1110 at the reflected hit point 1108 be calculated. Note that the angle β is a curvature measure at the surface hit point 1106 and it can influence how much the propagation angle will grow or shrink due to the different surface interactions.

Pixelausbreituneswinkel

12 illustrates an exemplary geometric arrangement 1200 , around α ₀ 1202 and α (τ) 1204 according to one embodiment. As shown, α can be a function of angle t 1206 be to the pixel against the main camera axis, so they as α (τ) 1204 can be designated. In one embodiment, it may be assumed that the vertical field of view is the same ψ and that the screen resolution is equal to W × H pixels.

In one embodiment, two methods may be used to determine the propagation angle, α to calculate a pixel, eg for primary rays.

A first method may use a single value as an approximation for all pixels. For example, the calculation is tradable for increased accuracy. The angle, α ₀ 1202 , is calculated as: $$\alpha \left(\tau \right)\approx {\mathrm{<figure-callout\; id="0"\; label="\alpha "\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">\alpha </figure-callout>}}_0=\text{arctan}\left(\frac{2\text{tan}\left(\psi /2\right)}{H}\right)$$

wobei α(τ) ≈ α₀ cos² τ. In extremen Situationen kann, z.B. für VR, die zweite Vorgehensweise verwendet werden. Ebenfalls kann, wenn ein Foveated-Renderer mit Augenverfolgung verwendet wird, ein größerer α in der Peripherie verwendet werden.A second method can increase the accuracy: $$\text{tan}\left(\alpha \left(\tau \right)/2\right)\approx \frac{0.5p\text{cos}\tau }{1/\text{cos}\tau }=0.5\mathrm{<figure-callout\; id="2"\; label="p\; cos"\; filenames="DE102019100505A1\_0052.png,DE102019100505A1\_0053.png"\; state="\{\{state\}\}">p\; </figure-callout>}{\text{cos}}^{}{}^2\tau \iff \alpha \left(\tau \right)\approx \mathrm{<figure-callout\; id="2"\; label="p\; cos"\; filenames="DE102019100505A1\_0052.png,DE102019100505A1\_0053.png"\; state="\{\{state\}\}">p\; </figure-callout>}{\text{cos}}^{}{}^2\tau .$$

where α (τ) ≈ α ₀ cos ² τ , In extreme situations, eg for VR, the second approach can be used. Also, if a foveated eye-tracking renderer is used, a larger α used in the periphery.

Surface propagation angle for reflections

13 illustrates exemplary reflection interaction with different types of geometry 1300 according to one embodiment: a planar surface 1302 , a convex surface 1304 and a concave surface 1306 , Note how the convex surface 1304 An angle of a cone grows while the concave surface 1306 reduces the angle of the cone until it becomes zero, at which point it will start to grow again. The surface propagation angle β modeled as the Cone footprint grows / shrinks due to the curvature of the surface. In this case the surface is convex and as a result the footprint grows (β> 0).

13 illustrates the surface propagation angle β , which will be 0 for planar reflections,> 0 for convex reflections, and <0 for concave reflections. Intuitively modeled β the extra spread caused by the curvature at the hit point. In general, the two major curvatures at the hit point or the radius of average curvature normal could be used. However, a simpler and faster method can be used which uses only a single number β to indicate curvature.

Also illustrated 14 an exemplary exaggerated view of a geometric arrangement 1400 for calculations for a texture LOD for reflections.

und: $$\text{tan}\left(\alpha /2+\beta /2\right)=\frac{w/2}{t\text{'}+t_1}\iff w=2\left(t\text{'}+t_1\right)\text{tan}\left(\alpha /2+\beta /2\right).$$

It should be noted that: $$\text{tan}\left(\alpha /2+\beta /2\right)=\frac{\Vert {\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0\Vert \text{tan}\left(\alpha /2\right)}{t\text{'}}\iff t\text{'}=\frac{\Vert {\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0\Vert \text{tan}\left(\alpha /2\right)}{\text{tan}\left(\alpha /2+\beta /2\right)}$$

and: $$\text{tan}\left(\alpha /2+\beta /2\right)=\frac{w/2}{t\text{'}+t_1}\iff w=2\left(t\text{'}+t_1\right)\text{tan}\left(\alpha /2+\beta /2\right),$$

wobei die Kleinwinkelnäherung tan α ≈ α verwendet wird. Auf diese Weise kann α||d₀|| den Footprint mit dem Abstand vom Auge zu dem ersten Treffer mal der Größe, α, eines Pixels wachsen lassen und der zweite Term kann das Wachsen von dem ersten Treffer zu dem zweitem Treffer modellieren, was daher von dem Abstand t₁ (vom ersten zum zweiten Treffer) und dem Winkel α + β abhängt.In one embodiment, the expression of Eq t ' in equation 9, which leads to the following: $$\begin{array}{c}{\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="DE102019100505A1\_0055.png,DE102019100505A1\_0057.png"\; state="\{\{state\}\}">w</figure-callout>}}_1=2\left(\frac{\Vert {\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0\Vert \text{tan}\left(\alpha /2\right)}{\text{tan}\left(\alpha /2+\beta /2\right)}+t_1\right)\text{tan}\left(\alpha /2+\beta /2\right)\\ =2\Vert {\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0\Vert \text{tan}\left(\alpha /2\right)+2{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102019100505A1\_0055.png,DE102019100505A1\_0057.png"\; state="\{\{state\}\}">t</figure-callout>}}_1\text{tan}\left(\alpha /2+\beta /2\right)\\ \approx \alpha \Vert {\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">d</figure-callout>}}_0\Vert +\left(\alpha +\beta \right){\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102019100505A1\_0055.png,DE102019100505A1\_0057.png"\; state="\{\{state\}\}">t</figure-callout>}}_1={\mathrm{<figure-callout\; id="0"\; label="w"\; filenames="DE102019100505A1\_0059.png"\; state="\{\{state\}\}">w</figure-callout>}}_0+\left(\alpha +\beta \right){\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102019100505A1\_0055.png,DE102019100505A1\_0057.png"\; state="\{\{state\}\}">t</figure-callout>}}_1.\end{array}$$

where the small angle approximation tan α ≈ α is used. In this way, α || d ₀ || the footprint with the distance from the eye to the first hit times the size, α , one pixel, and the second term can model the growth from the first hit to the second hit, hence the distance t ₁ (from the first to the second hit) and the angle α + β depends.

If the primary visibility is rasterized, then the G buffer pass can be used to calculate the surface propagation angle. The normalized normal to the hit point is n and the position of the fragment is p , both in world space, and dFdx and dFdy are used to get their differentials. The differential of p in x will with ∂p / ∂x designated.

15 illustrates an example geometry 1500 used in the calculation of φ to determine a surface propagation angle β involved, according to one embodiment. How through 15 illustrates: $$\phi =2\text{arctan}\left(\frac{1}{2}\sqrt{\frac{\partial n}{\partial x}\cdot \frac{\partial n}{\partial x}+\frac{\partial n}{\partial y}\cdot \frac{\partial n}{\partial y}}\right)\approx \sqrt{\frac{\partial n}{\partial x}\cdot \frac{\partial n}{\partial x}+\frac{\partial n}{\partial y}\cdot \frac{\partial n}{\partial y}}$$

16 illustrates an exemplary relationship 1600 between changes to a normal vector 1602 and a reflected vector 1604 according to one embodiment. An angle change in the normal vector 1602 , in this case φ / 2, leads to a change in the reflected vector 1604 that is twice as big. This means that β = 2φ. Two additional user constants k ₁ and k ₂ are added for β, as well as a sign factor s, which leads to β = 2k ₁ sφ + k ₂ with standard values k ₁ = 1 and k ₂ = 0. In summary: $$\beta =2k_{1}s\phi +k_2\approx 2k_{1}s\sqrt{\frac{\partial n}{\partial x}\cdot \frac{\partial n}{\partial x}+\frac{\partial n}{\partial y}\cdot \frac{\partial n}{\partial y}}+k_2,$$

A positive β indicates a convex surface, while a negative β indicates a concave surface region. Note that φ is always positive. Thus, depending on the type of surface of the s Factor a sign of β switch. s can be calculated as: $$s=\text{sign}\left(\frac{\partial p}{\partial x}\cdot \frac{\partial n}{\partial x}+\frac{\partial p}{\partial y}\cdot \frac{\partial n}{\partial y}\right).$$

(und ähnlich für y) ungefähr die gleiche Richtung, wenn die lokale Geometrie konvex ist (positives Skalarprodukt) und ungefähr entgegengesetzte Richtungen, wenn sie konkav ist (negatives Skalarprodukt), aufweisen werden.where, if the argument is> 0, the sign returns to 1 and otherwise to -1. The basic principle is that $\frac{\partial p}{\partial x}\text{and}\frac{\partial n}{\partial x}$

(and similar for y ) approximately the same direction if the local geometry is convex (positive dot product) and approximately opposite directions if concave (negative dot product).

In another embodiment, the sign factor s may be calculated as: $$s=\text{sign}\left(\left(\frac{\partial p}{\partial y}\times \frac{\partial p}{\partial x}\right)\cdot n\right)$$

Where, if the argument is> 0, the sign returns to 1 and otherwise to -1. If a shiny appearance is desired, the values of k ₁ and k ₂ be enlarged. For planar surfaces, φ will be equal to 0, which means that k ₁ will have no effect. Instead, the term k ₂ be used.

generalization

und wie ersichtlich ist, ist es Gleichung 7 mit sowohl einer Abstand- als auch Normalen-Abhängigkeit ähnlich. Es sei erinnert, dass n_i die Normale an der Oberfläche an dem i-ten Trefferpunkt und d_i der Vektor an dem i-ten Trefferpunkt von dem vorherigen Trefferpunkt ist. Der Basisdreieck-LOD, Δ_i , weist nun ein Subskript i auf, um anzugeben, dass er der Basis-LOD des Dreiecks an dem i-ten Trefferpunkt ist, der verwendet werden sollte. Ähnlich wie zuvor, bedeutet d _i eine normierte Richtung von d_i . Zu beachten ist, dass zwei Absolutwertfunktionen in Gleichung 16 hinzugefügt wurden. Der Absolutwert für den Abstandsterm ist dort, da β negativ sein kann (z.B. für konkave Oberflächenpunkte). Der Absolutwert für den Normalenterm ist dort, um nach hinten zeigende Dreiecke auf eine konsistente Art und Weise zu handhaben.Let i denote the enumerated hit point along a ray path beginning at 0. That is, the first hit is counted with 0 and the second with 1 and so on. All terms for the texture LOD for the ith hit point can then be put together as: $${\lambda }_i={\Delta }_i+{\text{log}}_2\left(\left|w_i\right|\cdot \left|\frac{1}{{\overline{n}}_i\cdot {\overline{d}}_i}\right|\right)=\underset{\text{gl}\text{.3}}{\underset{\}}{{\Delta }_i}}+\underset{\text{distance}}{\underset{\}}{{\text{<figure-callout id="2" label="log" filenames="DE102019100505A1\_0052.png,DE102019100505A1\_0053.png" state="{{state}}">log</figure-callout>}}_2\left|w_i\right|}}-\underset{\text{normal}}{\underset{\}}{{\text{<figure-callout id="2" label="log" filenames="DE102019100505A1\_0052.png,DE102019100505A1\_0053.png" state="{{state}}">log</figure-callout>}}_2\left|{\overline{n}}_i\cdot {\overline{d}}_i\right|}}.$$

and as can be seen, it is similar to Equation 7 with both a distance and a normal dependence. It should be remembered that _i the normal on the surface at the i th hit point and d _i is the vector at the i th hit point from the previous hit point. The basic triangle LOD, Δ _i , now has a subscript i to indicate that it is the base LOD of the triangle at the ith hitpoint that should be used. Similar to before, means d _{i is} a normalized direction of d _i , Note that two absolute value functions have been added in Equation 16. The absolute value for the distance term is there, since β can be negative (eg for concave surface points). The absolute value for the normal term is there to handle backward triangles in a consistent manner.

wobei γ_i = y_i-1 + β_i-1.It should be noted that w ₀ = αt ₀ = γ ₀ t ₀ and w ₁ = αt ₀ + (α + β ₀ ) t ₁ = w ₀ + γ ₁ t ₁ , where γ ₀ = α and γ ₁ = α + β ₀ and β _{0 is} the surface propagation angle at the first hit point. Thus, Equation 16 handles recursion and generally holds that: $$w_i=w_{i-1}+{\gamma }_i{t}_i.$$

where γ _i = y _i-1 + β _i-1 .

pseudocode

Table 1 includes an exemplary pseudocode that implements structures for performing ray tracing, according to one embodiment. Of course, it should be noted that the pseudocode shown in Table 1 is presented for illustrative purposes only and thus should not be construed as limiting in any way.

Zusätzlich können in einer Ausführungsform Strahlendifferentiale zum Berechnen des Textur-Detaillierungsgrads zur Strahlverfolgung verwendet werden. Diese Lösung kann Ergebnisse hoher Qualität bereitstellen. Das Implementieren von Strahlendifferentialen mit einem G-Puffer kann eine Leistung zum Berechnen eines Textur-Detaillierungsgrads zur Strahlverfolgung unter Verwendung von Strahlendifferentialen verbessern.Table 2 includes an exemplary pseudocode for performing ray tracing while handling recursive reflections, according to one embodiment. Of course, it should be noted that the pseudocode shown in Table 2 is presented for illustrative purposes only and thus should not be construed as limiting in any way.

In addition, in one embodiment, beam differentials may be used to calculate the texture detail level for ray tracing. This solution can provide high quality results. Implementing beam differentials with a G buffer can improve performance for computing a texture detail level for beam tracing using beam differentials.

radiation differentials

wobei o der Strahlenursprung und d̂ die normierte Strahlrichtung ist, d.h., d̂ = d/∥d∥. Das entsprechende Strahlendifferential kann aus vier Vektoren bestehen: $$\left\{\frac{\partial o}{\partial x},\frac{\partial o}{\partial y},\frac{\partial \widehat{\text{d}}}{\partial x},\frac{\partial \widehat{\text{d}}}{\partial y}\right\},$$

wobei (x, y) die Bildschirm-Koordinaten mit einer Einheit zwischen benachbarten Pixeln sind. Eine beispielhafte Ausführungsform kann die Verfolgung eines Strahlendifferentials umfassen, wie es in der Szene umherspringt und mit Oberflächen wechselwirkt. Alle Wechselwirkungen, z.B. Reflexionen, Refraktionen, Transfer eines Strahls von einem Punkt zu einem anderen, können differenziert werden und auf das ankommende Strahlendifferential angewendet werden, um ein Anderes als Ausgabe zu erzeugen. Wenn ein Textur-Lookup benötigt wird, kann das aktuelle Strahlendifferential verwendet werden, um den Textur-Footprint zu schätzen. Radiation differentials may include a method of handling filtered texture lookups. In one embodiment, assume that a ray is represented as: $$\text{r}\left(t\right)=\text{O}+t\widehat{\text{d}}.$$

where o is the ray origin and d is the normalized ray direction, ie, d = d / ∥d∥. The corresponding radiation differential can consist of four vectors: $$\left\{\frac{\partial O}{\partial x}.\frac{\partial O}{\partial y}.\frac{\partial \widehat{\text{d}}}{\partial x}.\frac{\partial \widehat{\text{d}}}{\partial y}\right\}.$$

where (x, y) are the screen coordinates with a unit between adjacent pixels. An exemplary embodiment may include tracking a beam differential as it travels around the scene and interacts with surfaces. All interactions, eg reflections, refractions, transfer of a beam from one point to another, can be differentiated and applied to the incoming beam differential to produce something other than output. If a texture lookup is needed, the current ray differential can be used to estimate the texture footprint.

oder unter Verwendung einer geringfügigen Modifikation dieser Anordnung erzeugt werden. Hier, P ∈ [0, 1]², wobei die 0,5s hinzugefügt wurden, um in die Mitte jedes Pixels zu gelangen, d.h., das Gleiche wie in DirectX und OpenGL und somit c ∈ [-1, 1]. Die rechte, orthonormale Kamerabasis ist {r', u', v'}, d.h., r' ist der rechte Vektor, u' ist der Aufwärts-Vektor und v' ist der Ansicht-Vektor, der in Richtung der Kameraposition zeigt. Zu beachten ist, dass {r, u, v} in Gleichung 20 verwendet wird und diese lediglich skalierte Versionen der Kamerabasis sind, d.h., $$\left\{r,u,v\right\}=\left\{afr\text{'},-fu\text{'},-v\text{'}\right\}$$

wobei α das Aspektverhältnis und f = tan(ω/2) ist, wobei ω das vertikale Blickfeld ist. Für Augenstrahlen werden die Strahlendifferentiale für die Richtung berechnet als: $$\frac{\partial d}{\partial x}=\frac{\left(\text{d}\cdot \text{d}\right)\widehat{r}-\left(\text{d}\cdot \widehat{\text{r}}\right)\text{d}}{{\left(\text{d}\cdot \text{d}\right)}^{\frac{3}{2}}},$$

wobei r̂ der Vektor von einem Pixel zu dem nächsten ist, der in unserem Fall ist: $$\widehat{r}=\text{d}\left(x+\mathrm{1,}y\right)-\text{d}\left(x,y\right)=\frac{2af}{s_x}\text{r'},$$

abgeleitet unter Verwendung von Gleichung 20. Für die y-Richtung wird Gleichung 22 verwendet und r̂ mit û ersetzt, was ist: $$\widehat{u}=d\left(x,y+1\right)-d\left(x,y\right)=-\frac{2f}{s_y}u\text{'}.$$

In one embodiment, a beam differential for the eye beam direction may be modified. The non-normalized beam direction d for a pixel start coordinate (x, y) and with screen resolution s = (s _x , s _y ) can be used in DXR as $$\begin{array}{c}\text{p}=\left(\frac{x+0.5}{s_x}.\frac{y+0.5}{s_y}\right).\\ \text{c}=\left(2p_x-1.2p_y-1\right).\\ \text{d}\left(x.y\right)=c_{x}r+c_{y}u+v=\left(\frac{2x+1}{s_x}-1\right)r+\left(\frac{2y+1}{s_y}-1\right)u+v.\end{array}$$

or by using a slight modification of this arrangement. Here, P ∈ [0, 1] ² , where the 0.5s were added to get into the middle of each pixel, ie, the same as in DirectX and OpenGL, and thus c ∈ [-1, 1]. The right orthonormal camera base is {r ', u', v '}, ie, r' is the right vector, u 'is the up vector, and v' is the view vector pointing towards the camera position. Note that {r, u, v} is used in Equation 20 and these are only scaled versions of the camera base, ie $$\left\{r.u.v\right\}=\left\{afr\text{'}.-fu\text{'}.-v\text{'}\right\}$$

where α is the aspect ratio and f = tan (ω / 2), where ω is the vertical field of view. For ophthalmic rays, the ray differentials for the direction are calculated as: $$\frac{\partial d}{\partial x}=\frac{\left(\text{d}\cdot \text{d}\right)\widehat{r}-\left(\text{d}\cdot \widehat{\text{r}}\right)\text{d}}{{\left(\text{d}\cdot \text{d}\right)}^{\frac{3}{2}}}.$$

where r is the vector from one pixel to the next, which in our case is: $$\widehat{r}=\text{d}\left(x+\mathrm{1,}y\right)-\text{d}\left(x.y\right)=\frac{2af}{s_x}\text{r '}.$$

derived using equation 20. For the y direction, equation 22 is used and r replaced with û, which is: $$\widehat{u}=d\left(x.y+1\right)-d\left(x.y\right)=-\frac{2f}{s_y}u\text{'},$$

This can be anything that is needed to set up the beam differential for eye beams.

Radiation differentials with G buffer

und Abständen, t, zu dem nächsten Treffer erzeugt wurde. Die Verfahren beschreiben dann, wie das Strahlendifferential eingerichtet wird, wenn der erste Strahl von der Position im G-Puffer aufgenommen wird.For real-time ray tracing, the ophthalmic rays can be rasterized in a G buffer. When combining beam differentials with a G buffer, the eye beams can not be adjusted as above. Instead, this can be done with the help of the G-buffer. Here, three such methods are presented assuming that a G-buffer with normal, $\widehat{n}.$

and distances, t, to the next hit was generated. The methods then describe how the beam differential is established when the first beam is picked up from the position in the G buffer.

und die Abstände, t, zu den Trefferpunkten normiert. Was nach dem G-Puffer-Durchgang folgt, ist Verfolgen, was mit einem Strahlerzeugungsdurchlauf beginnt, der Strahlen erzeugt. Diese werden von den Positionen erzeugt, die im G-Puffer gespeichert sind (was indirekt durch Speichern des Abstands t durchgeführt wird). Die nachstehenden Verfahren werden alle ihre Arbeit in diesem Strahlerzeugungsdurchgang durchführen und das Ziel ist, eine Strahlendifferentialdarstellung zu erzeugen, so dass das korrekte Strahlendifferential von dem ersten Trefferpunkt und weiter hinaus in der dreidimensionalen Szene verfolgt werden kann.A G-buffer is a screen-sized buffer generated using a pixel shader. In general, the scene is rendered using rasterization (not ray tracing) using the GPU, and a set of values is dumped to each pixel in the G buffer. Subsequent render passes may then exploit the information in the G buffer. The G buffer is used because the GPU is currently faster in order to rasterise eye visibility as compared to eye ray tracking using ray tracing (which would produce the same results but slower). A diffuse texture color, a normal, a world space position, etc. can be stored in the G buffer. Everything is used here. For the purposes here, however, the normals $\widehat{n}$

and normalizes the distances, t, to the hit points. What follows after the G buffer pass is tracking, which begins with a beam generation pass that produces beams. These are generated from the positions stored in the G buffer (which is done indirectly by storing the distance t). The following procedures will all do their work in this beam generation pass and the goal is to generate a beam differential representation so that the correct beam differential can be tracked from the first hit point and farther out in the three-dimensional scene.

1-you procedure

für das aktuelle Pixel, ${\widehat{n}}_{+1:0}$

für das Pixel zur rechten und ${\widehat{n}}_{0:+1}$

für das obige Pixel und auf ähnliche Weise für weitere Variablen bezeichnet. Die Augenstrahlrichtungen, $\widehat{e},$

für diese Nachbarn werden als nächstes unter Verwendung von Standardverfahren berechnet (z.B. unter Verwendung von Gleichung 18). An diesem Punkt wird das Strahlendifferential des Strahlenursprungs an dem ersten Treffer berechnet als: $$\frac{\partial \text{o}}{\partial x}=t_{+1:0}{\widehat{e}}_{+1:0}-t_{0:0}{\widehat{e}}_{0:0},$$

und auf ähnliche Weise für ∂o/∂y. Die Strahlendifferentialrichtung wird berechnet als: $$\frac{\partial \widehat{d}}{\partial x}=r\left({\widehat{e}}_{+1:0},{\widehat{n}}_{+1:0}\right)-r\left({\widehat{e}}_{0:0},{\widehat{n}}_{0:0}\right),$$

wobei r die Shader-Funktion reflect() und $\widehat{e}$

die Strahlrichtung von dem Auge ist. Ähnliche Berechnungen werden für $\partial \widehat{d}/\partial y$

durchgeführt. An diesem Punkt haben wir alle Komponenten, $\left\{\partial \text{o/}\partial x,\partial \text{o/}\partial y,\widehat{d}/\partial x\widehat{d}/\partial y\right\},$

des Strahlendifferentials, was bedeutet, dass eine Strahlverfolgung mit Strahlendifferentialen von dem ersten Treffer beginnen kann.The idea of this method is to simply access the G buffer to the right and above the current pixel and generate a beam differential from these values. The normals and distances, t, for the current pixel (x, y) and for the neighbors (x + 1, y) and (x, y + 1) are read out of the G buffer. It is with ${\widehat{n}}_{0:0}$

for the current pixel, ${\widehat{n}}_{+1:0}$

for the pixel to the right and ${\widehat{n}}_{0:+1}$

for the above pixel and similarly for other variables. The eye beam directions, $\widehat{e}.$

for these neighbors next calculated using standard methods (eg using Equation 18). At this point, the ray differential of the ray origin at the first hit is calculated as: $$\frac{\partial \text{O}}{\partial x}=t_{+1:0}{\widehat{e}}_{+1:0}-t_{0:0}{\widehat{e}}_{0:0}.$$

and similarly for ∂o / ∂y. The beam differential direction is calculated as: $$\frac{\partial \widehat{d}}{\partial x}=r\left({\widehat{e}}_{+1:0}.{\widehat{n}}_{+1:0}\right)-r\left({\widehat{e}}_{0:0}.{\widehat{n}}_{0:0}\right).$$

where r is the shader function reflect () and $\widehat{e}$

is the beam direction of the eye. Similar calculations will be made for $\partial \widehat{d}/\partial y$

carried out. At this point, we have all the components, $\left\{\partial \text{O/}\partial x.\partial \text{O/}\partial y.\widehat{d}/\partial x\widehat{d}/\partial y\right\}.$

of the beam differential, meaning that ray tracing can begin with beam differentials from the first hit.

Note that the 1-dir method is not something we would recommend because it has poor quality along many depth discontinuities. It is presented here to be able to explain the next process in a simple manner. It should also be noted that Table 1 shows the differences between the 2-dir method and the additional G-buffer storage method (below). They have different characteristics.

2-you process

The above method is fast, but sometimes different surfaces are hit when compared with the pixel to the right and above. A simple improvement is to check if | t _{+1: 0} - t _{0: 0} | > ε, where ε is a small number (eg, 0.01, etc.) and if so, instead, access the G buffer at -1: 0 and use the one with the smallest difference in t. The same procedure is used for the y direction. This method can improve the results of the 1-dir method.

Additional G-buffer storage method

This method computes and stores the entire beam differential at the first hit in the G buffer. The ∂o / ∂x and ∂o / ∂y are calculated using the built-in functions ddx () and ddy () on the hit point for the current pixel. Normals for adjacent pixels are also obtained using these functions. The reflected beam directions can be calculated using these normals and the differential ophthalmic directions. This method gives the same results as the original beam differential method, that is, without a G buffer pass.

In one embodiment, the G buffer passage may be modified to deplete the entire beam differential in the G buffer. We are currently doing this as shown below, where passOut.color3-5 are different parts of the G-buffer.

Table 3 includes an exemplary pseudo-code for modifying a G-buffering pass to store an entire beam differential in the G-buffer according to one embodiment. Of course, it should be noted that the pseudocode shown in Table 3 is presented for illustrative purposes only and thus should not be construed as limiting in any way. Table 3 float3 dOdx = ddx (sd.posW); float3 dOdy = ddy (sd.posW); float3 dNdx = ddx (sd.N); float3 dNdy = ddy (sd.N); float3 Nx = normalize (sd.N + dNdx); float3 Ny = normalize (sd.N + dNdy); float3 tmp = sd.posW - gCamera.posW; float3 Dx = normalize (tmp + dOdx); float3 Dy = normalize (tmp + dOdy); float3 R = reflect (-sd.V, sd.N); float3 dRdx = reflect (Dx, Nx) - R; float3 dRdy = reflect (Dy, Ny) - R; passOut.color3 = float4 (dOdx.x, dOdy.x, dRdx.x, dRdy.x); passOut.color4 = float4 (dOdx.y, dOdy.y, dRdx.y, dRdy.y); passOut.color5 = float4 (dOdx.z, dOdy.z, dRdx.z, dRdy.z);

17 illustrates a flowchart of a method 1700 for performing a texture detail level approximation using one or more beam differentials with a G-buffer according to an embodiment. As in operation 1702 shown, a scene to be rendered is indicated. Besides, as in operation 1704 shown a G-buffer of the scene rendered. For example, one or more attributes may be written to the G buffer for each pixel in the scene. Further, as in Operation 1706 shown a ray tracing for the scene started. Furthermore, as in Operation 1708 while beam tracing produces a beam differential by accessing the G buffer. In one embodiment, entries in the G-buffer may be accessed for pixels to the right of the current pixel and / or to the left of the current pixel within the G-buffer.

In another embodiment, entries in the G buffer may be accessed for pixels above the current pixel and / or below the current pixel within the G buffer. In another embodiment, G buffer entries may be accessed for pixels that are both horizontally and vertically closest to the current pixel.

Also, as in Operation 1710 shown attached the generated radiation differential to a current beam. Besides, as in operation 1712 shown tracking the generated radiation differential.

While various embodiments have been described above, it will be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of a preferred embodiment should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Parallel processing architecture

2 illustrates a parallel processing unit (PPU) 200 according to one embodiment. In one embodiment, the PPU 200 a multi-threaded processor implemented on one or more integrated circuit devices. The PPU 200 is a latency-concealing architecture designed to process a large number of threads in parallel. A thread (ie, a thread of execution) is an instantiation of a set of instructions configured to by the PPU 200 to be executed. In one embodiment, the PPU 200 a graphics processing unit (GPU) configured to implement a graphics rendering pipeline for processing three-dimensional (3D) graphics data to display two-dimensional (2D) image data for display on a display device such as a liquid crystal display (LCD) device; to create. In other embodiments, the PPU 200 used for performing general purpose calculations. While an exemplary parallel processor is provided herein for illustrative purposes, it should be emphasized that such processor is presented for illustrative purposes only, and that any processor may be used to supplement and / or replace the same.

As in 2 shown includes the PPU 200 an input / output (I / O) unit 205 , a host interface unit 210 , a front-end unit 215 , a planner unit 220 , a work distribution unit 225 , a hub 230 , a crossbar (Xbar) 270 , one or more general processing clusters (GPCs) 250 and one or more partition units 280 , The PPU 200 can with a host processor or other peripheral devices via a system bus 202 get connected. The PPU 200 can also be connected to a local memory containing a number of memory devices 204 includes. In one embodiment, the local memory may include a number of random access memory (DRAM) devices.

The I / O unit 205 is configured to communicate (ie, commands, data, etc.) from a host processor (not shown) via the system bus 202 to transmit and receive. The I / O unit 205 can with the host processor directly over the system bus 202 or communicate through one or more intermediate devices, such as a memory bridge. In one embodiment, the I / O unit implements 205 a Peripheral Component Interconnect Express (PCIe) interface for communications over a PCIe bus. In alternative embodiments, the I / O unit 205 implement other types of known interfaces for communicating with external devices.

The I / O unit 205 is with a host interface unit 210 coupled, the packets decoded over the system bus 202 were received. In one embodiment, the packets represent commands configured to the PPU 200 to cause to perform various operations. The host interface unit 210 transmits the decoded instructions to various other units of the PPU 200 as the commands can specify. For example, some commands can be sent to the frontend unit 215 be transmitted. Other commands can be sent to the hub 230 or other units of the PPU 200 , such as one or more copy machines, a video encoder, a video decoder, a power management unit, etc. (not explicitly shown). In other words, the host interface unit 210 configured to communicate between and among the various logical units of the PPU 200 forward.

In one embodiment, a program executed by the host processor encodes a command stream in a buffer that the PPU 200 Provides workloads for processing. A workload may include a number of instructions and data to be processed by these instructions. The buffer is a region in memory owned by both the host processor and the PPU 200 is accessible (ie read / write). For example, the host interface unit 210 be configured to access the buffer in a system memory that is connected to the system bus 202 connected via memory requests over the system bus 202 transmitted through the I / O unit 205 access. In one embodiment, the host processor writes the instruction stream into the buffer and then transmits a pointer to the start of the instruction stream to the PPU 200 , The host interface unit 210 Represents the frontend unit 215 Pointer to one or more command streams ready. The frontend unit 215 manages the one or more streams, with instructions read from the streams and commands to the various units of the PPU 200 to get redirected.

The frontend unit 215 is with a planner unit 220 coupled to the various GPCs 250 configured to process tasks defined by the one or more streams. The planner unit 220 is configured to track state information concerning various tasks performed by the scheduler unit 220 to get managed. The state may indicate which GPC 250 a task is assigned, whether the task is active or inactive, if a priority level is assigned to the task, and so on. The planner unit 220 manages the execution of a plurality of tasks on the one or more GPCs 250 ,

The planner unit 220 is with a work distribution unit 225 coupled, which is configured to perform tasks on the GPCs 250 to send. The work distribution unit 225 can track a number of scheduled tasks by the scheduler unit 220 be received. In one embodiment, the work distribution unit manages 225 a pending task pool and an active task pool for each of the GPCs 250 , The pending task pool may include a number of slots (eg 32 slots) containing tasks assigned by a particular GPC 250 to be processed. The active task pool may include a number of slots (eg, 4 slots) for tasks performed by the GPCs 250 actively processed. If a GPC 250 completing the execution of a task, this task is taken from the active task pool for the GPC 250 vacated and one of the other tasks is selected from the pool for pending tasks and to run on the GPC 250 planned. If an active task on the GPC 250 was inactive, such as while waiting for a data dependency to be resolved, then the active task can be taken out of the GPC 250 vacated and returned to the pool for pending tasks, while another task is selected in the pool for pending tasks and to run on the GPC 250 is scheduled.

The work distribution unit 225 communicates with the one or more GPCs 250 via a crossbar or XBar 270 , The XBar 270 is an interconnection network that many of the units of PPU 200 with other units of PPU 200 coupled. For example, the XBar 270 be configured to the work distribution unit 225 with a particular GPC 250 to pair. Although not explicitly shown, one or more other units are the PPU 200 with the host unit 210 coupled. The other units can also work with the XBar 270 over a hub 230 be connected.

The tasks are performed by the planner unit 220 managed and sent to a GPC 250 through the work distribution unit 225 sent. The GPC 250 is configured to process the task and generate results. The results may differ from other tasks within the GPC 250 be consumed to a different GPC 250 over the XBar 270 forwarded or in memory 204 get saved. The results can be stored in memory 204 about the partition units 280 written to a memory interface for reading and writing data to / from memory 204 to implement. In one embodiment, the PPU includes 200 a number U of partition units 280 equal to the number of separate and different storage devices 204 is that with the PPU 200 are coupled. A partition unit 280 will be discussed in more detail below 3B described.

In one embodiment, a host processor executes a driver kernel that implements an application programming interface (API) that allows one or more applications executing on the host processor to perform operations on the PPU 200 schedule. An application may generate instructions (ie, API calls) that cause the driver kernel to perform one or more tasks for execution by the PPU 200 to create. The driver kernel issues tasks to one or more streams from the PPU 200 are processed. Each task may include one or more sets of related threads, referred to herein as a warp. A thread block may refer to a plurality of groups of threads that include instructions to perform the task. Threads in the same set of threads can swap data through shared memory. In one embodiment, a group of threads comprises 32 related threads.

3A illustrates a GPC 250 the PPU 200 from 2 according to one embodiment. As in 3A shown, everyone includes GPC 250 a number of hardware units for processing tasks. In one embodiment, each GPC includes 250 a pipeline manager 310 , a pre-raster operations unit (PROP) 315 , a raster engine 325 , a Work Distribution Matrix (WDX) 380 , a storage management unit (MMU) 390 and one or more texture processing clusters (TPCs) 320 , It is recognized that the GPC 250 from 3A other hardware units instead of or in addition to 3A may include units shown.

In one embodiment, the operation of the GPC 250 through the pipeline manager 310 controlled. The pipeline manager 310 Manages the configuration of one or more TPCs 320 for processing tasks assigned to the GPC 250 allocated. In one embodiment, the pipeline manager 310 at least one of the one or more TPCs 320 configure to implement at least a portion of a graphics rendering pipeline. For example, a TPC 320 be configured to use a vertex shader program on the programmable streaming multiprocessor (SM) 340 perform. The pipeline manager 310 can also be configured to receive packets from the work distribution unit 225 to the appropriate logical units within the GPC 250 forward. For example, some packages may be attached to hard-function hardware units in the PROP 315 and / or the raster engine 325 be forwarded while other packages to the TPCs 320 for processing by the primitive engine 335 or the SM 340 can be forwarded.

The PROP unit 315 is configured to receive data from the raster engine 325 and the TPCs 320 to be generated to a raster operations unit (ROP unit) in the partition unit 280 to be described in more detail below. The PROP unit 315 may also be configured to perform color blending optimizations, organize pixel data, perform address translations, and the like.

The raster engine 325 includes a number of hard-function hardware units configured to perform various raster operations. In one embodiment, the raster engine includes 325 a setup engine, a coarse grid engine, a disambiguation engine, a truncation engine, a fine grid engine, and a tile merging engine. The setup engine receives transformed vertices and generates plane equations associated with the geometric primitives that pass through the vertices are defined. The plane equations are passed to the Grobraster engine to generate coverage information (eg, a (x, y) mask for a tile) for the primitives. The output of the coarse grid engine may be transferred to the discard engine where fragments associated with primitives that fail a z-test are discarded and transferred to a clipping engine where fragments that are out of viewing stub, be cut off. Those fragments that survive clipping and discarding may be passed to a fine grid engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. The output of the raster engine 325 includes fragments to be processed by, for example, a fragment shader within a TPC 320 is implemented.

Every TPC 320 who is in the GPC 250 includes an M-Pipe Controller (MPC) 330 , a primitive engine 335 , one or more SMs 340 and one or more texture units 345 , The MPC 330 controls the operation of the TPC 320 by the pipeline manager 310 received packets to the appropriate units in the TPC 320 forwards. For example, packets associated with a vertex may be sent to the primitive engine 335 which is configured to extract vertex attributes associated with the vertex from memory 204 pick up. In contrast, packets associated with a shader program can be sent to the SM 340 be transmitted.

In one embodiment, the texture units are 345 configured to save texture maps (eg, a 2D array of texels) from memory 204 and sample the texture maps to produce sampled texture values for use in shader programs written by the SM 340 be executed. The texture units 345 implement texture operations, such as filter operations using mip maps (ie, texture maps with a different degree of detail). The texture unit 345 is also called the load / store way for the SM 340 to the MMU 390 used. In one embodiment, each TPC comprises 320 two (2) texture units 345 ,

The SM 340 includes a programmable streaming processor configured to process tasks represented by a number of threads. Every SM 340 includes multiple threads (is multi-threaded) and is configured to concurrently execute a plurality of threads (eg, 32 threads) from a particular group of threads. In one embodiment, the SM implements 340 an SIMD (single-instruction, multi-data) architecture, where each thread in a group of threads (ie, a warp) is configured to process a different set of data based on the same set of instructions. All threads in the set of threads execute the same statements. In another embodiment, the SM implements 340 a SIMT (Single Instruction, Multiple Threads) architecture, where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but allowing individual threads in the group of threads to diverge during execution. In other words, if an instruction is sent for execution by the group of threads, some threads in the group of threads may be active, causing the instruction to execute, while other threads in the group of threads may be inactive, causing no operation ( NOP) instead of executing the instruction. The SM 340 can be discussed in more detail below in connection with 4 to be discribed.

The MMU 390 provides an interface between the GPC 250 and the partition unit 280 ready. The MMU 390 can provide translation from virtual addresses to physical addresses, memory protection and arbitration of memory requests. In one embodiment, the MMU 390 one or more translation lookaside buffers (TLBs) for improving the translation of virtual addresses into physical addresses in the memory 204 ready.

3B illustrates a partition unit 280 the PPU 200 from 2 according to one embodiment. As in 3B shown, includes the partition unit 280 a raster operations (ROP) unit 350 , an L2 cache 360 , a storage interface 370 and an L2 crossbar (XBar) 365 , The storage interface 370 is with the store 204 coupled. The storage interface 370 can implement 16, 32, 64, 128-bit data buses or the like for high-speed data transfer. In one embodiment, the PPU includes 200 U memory interfaces 370 , a storage interface 370 per partition unit 280 where each partition unit 280 with a corresponding storage device 204 connected is. For example, the PPU 200 with up to U storage devices 204 , such as a synchronous dynamic random access memory with graphics double data rate of the version 5 (GDDR5 SDRAM). In one embodiment, the memory interface implements 370 a DRAM interface and U equals 8.

In one embodiment, the PPU implements 200 a multilevel storage hierarchy. The memory 204 is located outside the chip in the SDRAM, which is connected to the PPU 200 connected is. Data from the memory 204 can be fetched and in the L2 cache 360 stored within the chip and between the various GPCs 250 is shared. As shown, each partition unit includes 280 a section of the L2 cache 360 that of a corresponding storage device 204 assigned. Lower level caches may then be in different units within the GPCs 250 be implemented. For example, each of the SMs 340 implement an L1 cache. The L1 Cache memory is a private memory that is specific to a SM 340 is dedicated. Data from the L2 cache 360 can be fetched and stored in each of the L1 cache memory for processing in the functional units of the SMs 340 get saved. The L2 Cache memory 360 is with the memory interface 370 and the XBar 270 coupled.

The ROP unit 350 includes a ROP manager 355 , one color unit ROP (CROP unit) 352 and a Z ROP (ZROP) unit 354 , The CROP unit 352 performs raster operations concerning the pixel color, such as color compression, pixel blending, and the like. The ZROP unit 354 implements depth tests in conjunction with the raster engine 325 , The ZROP unit 354 receives a depth for a sample location associated with a pixel fragment from the screening engine of the raster engine 325 , The ZROP unit 354 checks the depth against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the scan sample depth test, then the ZROP unit updates 354 the depth buffer and transmits a result of the depth test to the raster engine 325 , The ROP manager 355 controls the operation of the ROP unit 350 , It is recognized that the number of partition units 280 from the number of GPCs 250 can distinguish, and therefore each ROP unit 350 with each of the GPCs 250 can be coupled. Therefore, the ROP manager keeps track 355 Packages from the different GPCs 250 and determines to which GPC 250 a result is passed through the ROP unit 350 was generated. The CROP unit 352 and the ZROP unit 354 are with the L2 cache 360 over an L2 XBar 365 coupled.

4 illustrates the streaming multiprocessor 340 from 3A according to one embodiment. As in 4 shown, the SM includes 340 an instruction cache 405 , one or more planner units 410 , a register file 420 , one or more processing cores 450 , one or more special function units (SFUs) 452 , one or more load / store units (LSUs) 454 , an interconnection network 480 , a shared memory 470 and an L1 cache 490 ,

As described above, the work distribution unit ships 225 Tasks to execute on the GPCs 250 the PPU 200 , The tasks become a specific TPC 320 within a GPC 250 and, if the task is associated with a shader program, the task may be assigned to an SM 340 be assigned. The planner unit 410 receives the tasks from the work distribution unit 225 and manages instruction scheduling for one or more groups of threads (ie, warps) associated with the SM 340 are assigned. The planner unit 410 schedules threads to run in groups of parallel threads, with each group called a warp. In one embodiment, each warp comprises 32 Threads. The planner unit 410 can manage a plurality of different warps, with the warps scheduled to execute, and then instructions from the plurality of different warps to the different functional units (ie, cores 350 , SFUs 352 and LSUs 354 ) are sent during each clock cycle.

In one embodiment, each scheduler unit comprises 410 one or more instruction dispatch units 415 , Each shipping unit 415 is configured to transmit instructions to one or more of the functional units. In the in 4 embodiment shown includes the planner unit 410 two shipping units 415 that allow two different instructions to be dispatched from the same warp during each clock cycle. In alternative embodiments, each scheduler unit 410 a single shipping unit 415 or additional shipping units 415 include.

Every SM 340 includes a register file 420 containing a set of registers for the functional units of the SM 340 provides. In one embodiment, the register file is 420 divided between each of the functional units so that each functional unit is an associated section of the register file 420 allocated. In another embodiment, the register file is 420 split between the different warps coming from the SM 340 be executed. The register file 420 provides temporary memory for operands associated with the data paths of the functional units.

Every SM 340 includes L processing cores 450 , In an embodiment, the SM comprises 340 a large number (eg, 128 , etc.) of different processing cores 450 , Every core 450 can a fully pipelined single precision processing unit comprising a floating point arithmetic logic unit and an integer arithmetic logic unit. The core 450 may also comprise a dual precision processing unit comprising a floating-point arithmetic logic unit. In one embodiment, the floating point arithmetic logic units implement the IEEE 754-2008 standard for floating point arithmetic. Every SM 340 also includes M SFUs 452 performing special functions (eg, attribute evaluation, reciprocal square root and the like), and N LSUs 454 , the load and store operations between the shared memory 470 or the L1 cache 490 and the register file 420 to implement. In an embodiment, the SM comprises 340 128 cores 450 . 32 SFUs 452 and 32 LSUs 454 ,

Every SM 340 includes an interconnection network 480 containing each of the functional units with the register file 420 connects and the LSU 454 with the register file 420 , the shared memory 470 and the L1 cache 490 combines. In one embodiment, the interconnect network is 480 a crossbar, which may be configured to any of the functional units with any of the registers in the register file 420 to connect and the LSUs 454 with the register file and locations in the shared memory 470 and L1 Cache memory 490 connect to.

The shared memory 470 is an Ar-ray of on-chip memory, data storage and communication between the SM 340 and the primitive engine 335 and between threads in the SM 340 allows. In one embodiment, the shared memory includes 470 64KB of storage capacity. On L1 Cache memory 490 is in the way of the SM 340 to the partition unit 280 , The L1 Cache memory 490 can be used to save read and write operations. In one embodiment, the L1 cache includes 490 24KB of storage capacity.

The PPU described above 200 can be configured to perform high-level calculations much faster than traditional CPUs. Parallel computing has advantages in graphics processing, data compression, biometrics, power processing algorithms, and the like.

If configured for general-purpose parallelism, a simpler configuration can be used. In this model, as in 2 bypassing fixed-function graphics processing units, creating a much simpler programming model. In this configuration are from the work distribution unit 225 Assigned blocks of threads and directly to the TPCs 320 distributed. The threads in a block execute the same program using a unique thread ID in the calculation to ensure that each thread produces unique results, with the SM 340 is used to run the program and perform calculations to allow the shared memory 470 communicates between threads, and the LSU 454 is used to global memory by partitioning the L1 cache 490 and the partition unit 280 to read and describe.

When configured for general purpose parallel computation, the SM can 340 also write commands to the planner unit 220 can use to new work on the TPCs 320 to start.

In one embodiment, the PPU includes 200 a graphics processing unit (GPU). The PPU 200 is configured to receive commands specifying shader programs for processing graphics data. Graphics data may be defined as a set of primitives, such as points, lines, triangles, squares, triangular stripes, and the like. Typically, a primitive includes data specifying a number of vertices for the primitive (eg, in a model space coordinate system) as well as attributes associated with each vertex of the primitives. The PPU 200 may be configured to process the graphics primitive to generate a frame buffer (ie, pixel data for each of the pixels of the display).

An application writes model data for a scene (ie, a collection of vertices and attributes) to memory, such as system memory or memory 204 , The model data defines each of the objects that may be visible on a display. The application then makes an API call to the driver kernel requesting the model data to render and display. The driver kernel reads the model data and writes commands to the one or more streams to perform operations to process the model data. The commands can reference different shader programs running on the SMs 340 the PPU 200 which may include one or more of a vertex shader, hull shaders, domain shaders, geometry shaders, and a pixel shader. For example, one or more of the SMs 340 be configured to execute a vertex shader program that processes a number of vertices defined by the model data. In one embodiment, the different SMs 340 be configured to concurrently execute different shader programs. For example, a first subset of SMs 340 be configured to execute a vertex shader program while a second subset of SMs 340 may be configured to execute a pixel shader program. The first subset of SMs 340 processes vertex data to produce processed vertex data and writes the processed vertex data to the L2 cache 360 and / or the memory 204 , After the processed vertex data is rasterized (ie, transformed from three-dimensional data into two-dimensional data in screen space) to generate fragment data, the second subset of SMs results 340 a pixel shader to generate processed fragment data which is then mixed with other processed fragment data and into the frame buffer in memory 204 to be written. The vertex shader program and the pixel shader program may be concurrently executed, pipelining different data from the same scene until all of the model data rendered for the scene has been rendered to the frame buffer. Then, the content of the frame buffer is transmitted to a display controller for display on a display device.

The PPU 200 may be included in a desktop computer, a laptop computer, a tablet computer, a smartphone (eg, a wireless handheld device), a personal digital assistant (PDA), a digital camera, a handheld electronic device, and the like. In one embodiment, the PPU 200 embodied on a single semiconductor substrate. In another embodiment, the PPU 200 in a system-on-chip (SoC) along with one or more other logic units, such as a computer-reduced-instruction set (RISC) CPU, a memory management unit (MMU), a digital-to-analog converter (DAC), and the like ,

In one embodiment, the PPU 200 on a graphics card that includes one or more memory devices 204 , such as GDDR5 SDRAM. The graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer that includes, for example, a northbridge chipset and a southbridge chipset. In yet another embodiment, the PPU 200 an integrated graphics processing unit (iGPU) included in the chipset (ie northbridge) of the motherboard.

5 illustrates a system-on-chip (SoC) 500 that the PPU 200 from 2 includes, according to one embodiment. As in 5 shown, includes the SoC 500 a CPU 550 and a PPU 200 , as described above. The SoC 500 can also have a system bus 202 include communication between the various components of the SoC 500 to enable. Memory requests made by the CPU 550 and the PPU 200 can be generated by a system MMU 590 be forwarded by several components of the SoC 500 be shared. The SoC 500 can also have a memory interface 595 include with one or more storage devices 204 is coupled. The storage interface 595 For example, it can implement a DRAM interface.

Although not explicitly shown, the SoC 500 other components in addition to those in 5 include components shown. For example, the SoC 500 several PPUs 200 (eg, four PPUs 200 ), a video encoder / decoder, and a broadband wireless transceiver, as well as other components. In one embodiment, the SoC 500 with the memory 204 in a package-on-package (PoP) configuration.

6 is a conceptual diagram of one of the PPU 200 implemented graphics processing pipeline 600 according to one embodiment. The graphics processing pipeline 600 Figure 4 is an abstract flow chart of the processing steps implemented to generate 2D computer generated images from 3D geometry data. As is known, pipeline architectures can more efficiently perform long latency operations by dividing the operation into a plurality of stages, with the output of each stage coupled to the input of the next consecutive stage. Thus, the graphics processing pipeline receives 600 input data 601 from one level to the next level of the graphics processing pipeline 600 be transferred to output data 602 to create. In one embodiment, the graphics processing pipeline 600 represent a graphics processing pipeline defined by the ^OpenGL® API. As an option, the graphics processing pipeline 600 in the context of the functionality and architecture of the previous figures and / or any subsequent figure (s).

As in 6 includes the graphics processing pipeline 600 a pipeline architecture that includes a number of stages. The stages include, but are not limited to, a data assembly stage 610 , a vertex shading level 620 , a primitive assembly stage 630 , a geometry shading level 640 , a viewport scaling, screening and truncating (VSCC) step 650 , a screening level 660 , a fragment shading level 670 and a raster operations level 680 , In one embodiment, the input data includes 601 Commands that configure the processing units around the stages of the graphics processing pipeline 600 and to implement geometric primitives (eg, points, lines, triangles, squares, triangular stripes or bins, etc.) to be processed by the stages. The output data 602 may include pixel data (ie, color data) that is copied to a frame buffer or other type of surface data structure in memory.

The data assembly stage 610 receives the input data 601 which specify vertex data for higher-order surfaces, primitives, or the like. The data assembly stage 610 collects the vertex data in a temporary memory or queue, such as by receiving a command from the host processor that includes a pointer to a buffer in memory and reads the vertex data from the buffer. The vertex data is then sent to the vertex shading stage 620 transferred for processing.

The vertex shading level 620 Processes vertex data by performing a set of operations (ie, a vertex shader or program) once for each of the vertices. For example, vertices may be specified as a 4-coordinate vector (ie, <x, y, z, w>) associated with one or more vertex attributes (eg, color, texture coordinates, surface normals, etc.). The vertex shading level 620 can manipulate individual vertex attributes, such as position, color, texture coordinates, and the like. In other words, the vertex shading level performs 620 Operations on the vertex coordinates or other vertex attributes associated with a vertex. Such operations usually include lighting operations (ie, modifying color attributes for a vertex) and transform operations (ie, modifying coordinate space for a vertex). For example, vertices may be specified using coordinates in an object coordinate space that are transformed by multiplying the coordinates by a matrix that converts the coordinates from the object coordinate space to a world space or a Normalized Device Coordinates (NCD). Translated space. The vertex shading level 620 generates transformed vertex data that is sent to the primitive assembly stage 630 be transmitted.

The primitive assembly stage 630 collects vertices using the vertex shading level 620 and groups the vertices in geometric primitives for processing by the geometry shading stage 640 , For example, the primitive assembly stage 630 be configured to apply all three consecutive vertices as a geometric primitive (ie a triangle) for transmission to the geometry shading stage 640 to group. In some embodiments, specific vertices for successive geometric primitives may be reused (eg, two consecutive triangles in a triangle strip may share two vertices). The primitive assembly stage 630 transfers geometric primitives (ie a collection of mapped vertices) to the geometry shading stage 640 ,

The geometry shading level 640 processes geometric primitives by performing a set of operations (ie, a geometry shader or program) on the geometric primitives. Tessellation operations can generate one or more geometric primitives from each geometric primitive. In other words, the geometry shading level 640 each geometric primitive into a finer mesh of two or more geometric primitives for processing by the remainder of the graphics processing pipeline 600 divide. The geometry shading level 640 transfers geometric primitives to the viewport SCC stage 650 ,

In one embodiment, the graphics processing pipeline 600 work within a streaming multiprocessor and the vertex shading level 620 , the primitive compilation stage 630 , the geometry shading level 640 , the fragment shading level 670 and / or the associated hardware / software can sequentially perform processing operations. Once the sequential processing operations are completed in one embodiment, the viewport SCC stage 650 to use the data. In one embodiment, primitive data passing through one or more of the stages in the graphics processing pipeline 600 are written to a cache (eg, an L1 cache, a vertex cache, etc.). In this case, in one embodiment, the viewport SCC stage 650 access the data in the cache memory. In one embodiment, the viewport is SCC stage 650 and the screening level 660 implemented as solid state circuits.

The viewport SCC stage 650 performs viewport scaling, disambiguation and truncation of geometric primitives. Each surface that is rendered is assigned to an abstract camera position. The camera position represents a location of a viewer viewing the scene and defines a viewing stub that includes the objects of the scene. The viewing stub may include a viewing plane, a posterior plane, and four clip planes. Any geometric primitive that is completely out of the view stub may be discarded (ie discarded) because the geometric primitive will not contribute to the final rendered scene. Any geometric primitive that is within the view stub and partially out of the view stub may be truncated (ie, transformed into a new geometric primitive that is included within the view stub). Furthermore, geometric primitives may each be scaled based on a depth of the viewing stump. All potentially visible geometric primitives are then sent to the screening stage 660 transfer.

The screening level 660 converts the 3D geometric primitives into 2D fragments (eg capable of being used for display, etc.). The screening level 660 can be configured to use the vertices of the geometric primitives to set up a set of plane equations from which different attributes can be interpolated. The screening level 660 may also compute a coverage mask for a plurality of pixels indicating whether one or more scan locations for the pixel intersect the geometric primitive. In one embodiment, z-testing may also be performed to determine if the geometric primitive is obscured by other geometric primitives that have already been rasterized. The screening level 660 generates fragment data (ie, interpolated vertex attributes associated with a particular sample location for each covered pixel) sent to the fragment shading stage 670 be transmitted.

The fragment shading level 670 processes fragment data by performing a set of operations (ie, a fragment shader or a program) on each of the fragments. The fragment shading level 670 may generate pixel data (ie, color values) for the fragment, such as by performing illumination operations or sampling texture maps using interpolated texture coordinates for the fragment. The fragment shading level 670 generates pixel data that is sent to the raster operations stage 680 be transmitted.

The raster operations level 680 can perform various operations on the pixel data, such as alpha testing, stencil testing and blending the pixel data with other pixel data corresponding to other fragments associated with the pixel. When the raster operations stage 680 the processing of the pixel data (ie the output data 602 ), the pixel data may be written to a render target, such as a frame buffer, a color buffer, or the like.

It is recognized that one or more additional stages in the graphics processing pipeline 600 in addition to or instead of one or more of the steps described above. Different implementations of the abstract graphics processing pipeline may implement different stages. Further, one or more of the above-described stages of the graphics processing pipeline may be implemented in some embodiments (such as the geometry shading stage 640 ) be excluded. Other types of graphics processing pipelines are contemplated as being within the scope of the present disclosure. Furthermore, any of the stages of the graphics processing pipeline 600 one or more dedicated hardware units within a graphics processor, such as the PPU 200 to be implemented. Other stages of the graphics processing pipeline 600 can by programmable hardware units, such as the SM 340 the PPU 200 to be implemented.

The graphics processing pipeline 600 can be implemented through an application that is hosted by a host processor, such as a CPU 550 , is performed. In one embodiment, a device driver may implement an application programming interface (API) that defines various functions that may be used by an application to generate graphical data for display. The device driver is a software program that includes a plurality of instructions that govern the operation of the PPU 200 control. The API provides an abstraction to a programmer that allows a programmer to use specialized graphics hardware, such as the PPU 200 to generate the graphical data without requiring the programmer to set the specific instruction set for the PPU 200 must use. The application may include an API call to the device driver for the PPU 200 is forwarded. The device driver interprets the API call and performs various operations to respond to the API call. In some cases, the Device Drivers Perform operations by executing instructions on the CPU 550 carry out. In other cases, the device driver may perform operations, at least in part, by starting operations on the PPU 200 perform an input / output interface between the CPU 550 and the PPU 200 is used. In one embodiment, the device driver is configured to execute the graphics processing pipeline 600 using the hardware of the PPU 200 to implement.

Different programs can be within the PPU 200 be executed at the various stages of the graphics processing pipeline 600 to implement. For example, the device driver may have a kernel on the PPU 200 start at the vertex shading level 620 on a SM 340 (or multiple SMs 340 ). The device driver (or the one from the PPU 200 executed initial kernel) may also have other kernels on the PPU 200 start at other stages of the graphics processing pipeline 600 perform such as the geometry shading stage 640 and the fragment shading level 670 , Also, some of the stages of the graphics processing pipeline 600 be implemented on a fixed hardware unit, such as a rasterizer or a data assembler, within the PPU 200 is implemented. It is recognized that results from a kernel may be processed by one or more hard-function intervening hardware units before being sent from a succeeding kernel to an SM 340 are processed.

7 illustrates an exemplary system 700 in which the various architecture and / or functionality of the various preceding embodiments may be implemented. As shown, a system 700 provided, the at least one central processor 701 that is connected to a communication bus 702 connected is. The communication bus 702 may be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI Express, AGP (Accelerated Graphics Port), HyperTransport, or one or more other bus protocols or point-to-point communication protocols. The system 700 may also be a main memory 704 respectively. Control logic (software) and data are in main memory 704 which may take the form of a random access memory (RAM).

The system 700 also includes input devices 712 , a graphics processor 706 and an ad 708 That is, a conventional CRT (Cathode Ray Tube), an LCD (Liquid Crystal Display), an LED (Light Emitting Diode), a plasma display, or the like. User input may be via the input devices 712 For example, keyboard, mouse, touch-sensitive pad, microphone and the like can be received. In one embodiment, the graphics processor 706 a plurality of shading modules, a raster module, etc. have. Each of the foregoing modules may be arranged in a single semiconductor platform to form a graphical processing unit (GPU).

In the present specification, a single semiconductor platform may designate a single standalone semiconductor-based integrated circuit or chip. It should be noted that the term single semiconductor platform may also refer to multi-chip modules with increased interconnect structure, which simulate on-chip operation, and represent a significant improvement over the use of conventional CPU and bus implementation. Of course, the various modules may also be arranged separately or in various combinations of semiconductor platforms according to the needs of the user.

The system 700 can also have a secondary memory 710 include. The secondary storage 710 For example, a hard disk and / or a removable disk that may represent a floppy disk drive, a magnetic tape drive, a compact diskette drive, a digital versatile floppy disk (DVD) drive, a recorder, a universal serial bus (USB) flash memory. The removable storage device reads in and / or writes from a removable storage device in a known manner.

Computer programs or computer control logic algorithms may reside in main memory 704 and / or in the secondary memory 710 be saved. Such computer programs, when executed, put the system 700 able to perform various functions. The main memory 704 , the memory 710 and / or any other memory are possible examples of computer readable media.

In one embodiment, the architecture and / or functionality of the various previous figures may be related to the central processor 701 , the graphics processor 706 an integrated circuit (not shown) that performs at least part of the capabilities of both the central processor 701 as well as the graphics processor 706 has implemented with a chipset (that is, a group of integrated circuits designed to operate as a unit to perform related functions and sold as such, etc.) and / or with another integrated circuit for that matter become.

Furthermore, the architecture and / or functionality of the various preceding figures may also be implemented within a general computer system, a system of printed circuit boards, a gaming console system intended for entertainment purposes, within an application specific system, and / or any other desired system become. For example, the system can 700 take the form of a desktop computer, a laptop, a service provider computer, a workstation, game consoles, an embedded system, and / or any other type of logic. Furthermore, the system can 700 take the form of various other devices including, without limitation, personal digital assistant (PDA) device, mobile device device, television device device, etc.

Further, although not shown, the system may 700 be coupled to a network (eg, a telecommunications network, local area network (LAN), wireless network, wide area network (WAN) such as the Internet, peer-to-peer network, cable network, or the like) for communication purposes.

Claims (11)

Method, comprising: Marking a scene to be rendered; Rendering a G-buffer of the scene; Starting a ray tracing for the scene; during ray tracing, generating a beam differential by accessing the G buffer; Attaching the generated beam differential to a current beam; and Tracking the generated beam differential. Method according to Claim 1 where the G buffer is a screen size buffer created using a pixel shader. Method according to Claim 1 or 2 wherein one or more attributes are written to the G buffer for each pixel in the scene when rendering the G buffer of the scene. The method of claim 1, wherein generating the beam differential by accessing the G buffer comprises accessing entries in the G buffer for pixels to the right of the current pixel and to the left of the current pixel within the G buffer. The method of claim 1, wherein generating the beam differential by accessing the G buffer comprises accessing entries in the G buffer for pixels that are above the current pixel and / or below the current pixel within the G buffer. A method according to any one of the preceding claims, wherein G buffer entries are accessed for pixels closest to the current pixel, both horizontal and vertical. Method according to one of the preceding claims, wherein a distance t to a hit point in the G-buffer is stored. System comprising: a processor configured to: to mark a scene to be rendered; render a G-buffer of the scene; to start a ray tracing for the scene; during beam tracing, generating a beam differential by accessing the G buffer; attach the generated radiation differential to a current beam; and to track the generated radiation differential. System according to Claim 8 , which is further configured to perform a method as in any of Claims 2 to 7 , A computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising: Marking a scene to be rendered; Rendering a G-buffer of the scene; Starting a ray tracing for the scene; during ray tracing, generating a beam differential by accessing the G buffer; Attaching the generated beam differential to a current beam; and Tracking the generated beam differential. Computer-readable storage medium according to Claim 10 which, when executed by the processor, causes the processor to perform steps of a method as in Claims 2 to 7 mentioned.

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