DE102019008738A1 - IMAGE SENSORS WITH REDUCED NOISE - Google Patents

Abstract

An image sensor can include an array of pixels controlled by row control circuitry. Each pixel may include a photodiode for generating image signals and a charge storage structure coupled to a floating diffusion region and configured to generate and store extraneous light noise level signals. The image signals and the background light noise level signals can be read out in the same readout cycle using a common or separate readout circuit arrangement. Processing circuitry may selectively process the image signals based on the extraneous light noise level signals to generate image signals with reduced noise.

Description

BACKGROUND

This applies generally to imaging systems, and more particularly to imaging systems with global shutter functionality.

Modern electronic devices such as cell phones, cameras and computers often use digital image sensors. Imagers (i.e., image sensors) often include a two-dimensional array of image capture pixels. Each pixel typically includes a light sensor, such as a photodiode, that receives incident photons (light) and converts the photons into electrical signals.

Conventional image sensors are fabricated on a semiconductor substrate using a complementary metal oxide semiconductor (CMOS) technology or a charge-coupled device (CCD) technology. A rolling shutter or a global shutter can be used with CMOS image sensors. In CMOS image sensors with a global shutter, a storage node area is generally integrated into each pixel in order to store charge from the photodiode for reading out. In addition, global shutter pixels without an independent charge storage area can use floating diffusion for charge storage. Storage areas can collect unwanted stray light that falsifies the charge from the photodiode. This can increase noise in the pixels (e.g., increase sensitivity to stray light in the floating diffusion area and decrease global shutter efficiency), thereby reducing image quality.

Therefore, it would be desirable to be able to provide improved image sensors with global shutter functionality.

Figure list

• 1 10 is a diagram of an illustrative imaging system that may include an image sensor having image pixels operable in a global shutter mode, in accordance with some embodiments.
• 2nd 10 is a diagram of an illustrative pixel array and associated readout circuitry for reading out image signals from the pixel array, in accordance with some embodiments.
• 3rd 10 is a diagram of an illustrative image pixel operable in a global shutter mode, according to embodiments.
• 4th 10 is a diagram of an illustrative image pixel having a charge storage area that stores a stray light reference voltage, also referred to as noise, in accordance with some embodiments.
• 5A and 5B FIG. 10 is an illustrative timing diagram for operating image pixels of the device shown in FIG 4th type shown in a global shutter mode, according to some embodiments.
• 6 10 is a diagram of an illustrative image pixel that includes a charge storage area that stores a noise reference voltage and that is coupled to an additional storage area, in accordance with some embodiments.
• 7 FIG. 10 is an illustrative timing diagram for operating image pixels of the FIG 6 shown type in a global shutter mode according to some embodiments.
• 8th 10 is a diagram of an illustrative image pixel that includes a charge storage area that stores a noise reference voltage and that is coupled to a floating diffusion area, in accordance with some embodiments.
• 9 FIG. 10 is an illustrative timing diagram for operating image pixels of the FIG 8th shown type in a global shutter mode according to some embodiments.

DETAILED DESCRIPTION

Electronic devices, such as digital cameras, computers, cell phones, and other electronic devices, include image sensors that capture incoming image light to take an image. The image sensors can include arrays of imaging pixels. The pixels in the image sensors can include photosensitive elements, such as photodiodes, that convert the incoming image light into image signals. Image sensors can have any number of pixels (e.g. hundreds or thousands or more). For example, a typical image sensor can have hundreds of thousands or millions of pixels (e.g., megapixels). Image sensors may include control circuitry such as circuitry for operating the imaging pixels and readout circuitry for reading out image signals corresponding to the electrical charge generated by the photosensitive elements.

1 FIG. 12 is a diagram of an illustrative imaging system that uses an image sensor with a global shutter function. In an imaging system 10th from 1 can be a portable electronic device, such as a camera, cellular phone, video camera, or other imaging device, that captures digital image data. A camera module 12th can be used to convert incoming light into digital image data. The camera module 12th can be one or more lenses 14 and one or more corresponding image sensors 16 lock in. The image sensor 16 can be an integrated image sensor circuit with an array of image pixels 30th be. The image pixels 30th can each include a shutter to control when charge is picked up by the image pixel.

During imaging operations, the lens 14 Light from a scene onto an image pixel array in the image sensor 16 focus. The image sensor 16 can be control circuitry, such as storage and processing circuitry 18th , provide appropriate digital image data.

The circuit arrangement 18th may include one or more integrated circuits (e.g., image processing circuits, microprocessors, memory devices such as random access memory and non-volatile memory, etc.) and may be implemented using components developed by the camera module 12th are present separately and / or part of the camera module 12th form (e.g. circuits that form part of an integrated circuit, the image sensors 16 includes, or an integrated circuit within the module 12th that the image sensors 16 assigned). Image data from the camera module 12th can be recorded using the processing circuitry 18th processed and / or saved. Processed image data can, if desired, be provided to external equipment (e.g., a computer or other device) using wired and / or wireless communication paths provided with the processing circuitry 18th are coupled. The processing circuitry 18th can be used to operate the image sensors 16 to control.

As in 2nd shown, the image sensor 16 a pixel array 19th , the image sensor pixel 30th contains arranged in rows and columns (sometimes referred to herein as image pixels or pixels) and control and processing circuitry 23 lock in. The array 19th can, for example, hundreds or thousands of rows and columns of image sensor pixels 30th contain. The control circuitry 23 can with a line control circuitry 25th and image readout circuitry 27 (sometimes referred to as column control circuitry, readout circuitry, processing circuitry, or column decoder circuitry). The line control circuitry 25th can get row addresses from the control circuitry 23 received and the pixels 30th via line control paths 29 appropriate line control signals such as reset, line selection, charge transfer, double conversion gain and readout control signals. One or more conductive lines, such as column lines 31 , can with any column of pixels 30th in the array 19th be coupled. The column lines 31 can be used to read out image signals from the pixels 30th and for supplying bias signals (e.g. bias currents or biases) to the pixels 30th be used. If desired, a pixel row can be in the array during pixel readout operations 19th using the line control circuitry 25th are selected and image signals through the image pixels 30th can be generated in this pixel row along the column lines 31 be read out.

The image readout circuitry 27 can image signals (e.g. analog, by the pixel 30th generated pixel values) via the column lines 31 receive. The image readout circuitry 27 may include sample-and-hold circuitry for sampling and temporarily storing from the array 19th read out image signals, amplifier circuitry, analog-to-digital conversion (ADC) circuitry, bias circuitry, column memory, latch circuitry for selectively activating or deactivating the column circuitry, or other circuitry including one or more columns of Pixels in the array 19th to operate the pixels 30th and for reading out image signals from the pixels 30th are coupled. The ADC circuitry in the readout circuitry 27 can get analog pixel values from the array 19th received, convert to corresponding digital pixel values (sometimes referred to as digital image data or digital pixel data). The image readout circuitry 27 can digital pixel data for pixels in one or more pixel columns of the control and processing circuitry 23 and / or the processor 18th ( 1 ) respectively.

If desired, the image pixels 30th include more than one photosensitive area to generate charge in response to the image light. Photosensitive areas within the image pixels 30th can be in rows and columns on the array 19th to be ordered. The pixel array 19th can be provided with a filter array that multiple (color) filter elements (each corresponding to a corresponding pixel), which allows a single image sensor to capture samples of light of different colors or sets of wavelengths. Image sensor pixels, like the image pixels in the array 19th For example, can be provided with a color filter array that includes red, green, and blue filter elements, which allows a single image sensor to sample from using the corresponding red, green, and blue image sensor pixels im arranged in a Bayer mosaic pattern red, green and blue (RGB) light.

The Bayer mosaic pattern consists of a repeating unit cell of two times two image pixels, with two green image pixels (under filter elements that allow green light to pass through) diagonally opposite each other and next to a red image pixel (under a filter element that lets red light pass through) diagonally opposite a blue image pixel (under a filter element that transmits blue light). In another suitable example, the green pixels in a Bayer pattern can be replaced by broadband image pixels with broadband color filter elements (e.g. transparent color filter elements, yellow color filter elements, etc.). In yet another example, one of the green pixels in a Bayer pattern can be replaced with infrared (IR) image pixels formed under IR color filter elements, and / or the remaining red, green, and blue image pixels can also be sensitive to IR Be light (e.g., they can be formed under filter elements that pass IR light in addition to the light of their respective colors). These examples are illustrative only and generally filter elements can be of any desired color and / or wavelength and in any desired pattern over any desired number of image pixels 30th be formed.

Additionally, separate microlenses can be placed over each image pixel 30th are formed (e.g. with light or color filter elements between the microlenses and image pixels 30th are arranged). The microlenses can form an array of microlenses, which are the array of light filter elements and the array of image sensor pixels 30th overlap. Each microlens can direct light from an imaging system lens onto a corresponding image pixel 30th or several image pixels 30th , if desired, focus.

The image sensor 16 can be one or more arrays 19th of image pixels 30th lock in. The image pixels 30th can be formed in a semiconductor substrate using complementary metal oxide semiconductor (CMOS) technology or charge coupled device (CCD) technology or any other suitable photosensitive device technology. With the image pixels 30th can be frontside illumination (FSI) image pixels or backside illumination (BSI) image pixels. If desired, the image sensor 16 include an integrated circuit package or other structure in which a plurality of substrate layers or chips of an integrated circuit are stacked vertically with respect to each other. In this scenario, one or more of the circuit arrangements 23 , 25th and 27 vertically above or below the array 19th inside the image sensor 16 be stacked. If desired, the lines 31 and 29 vertical conductive via structures (e.g. silicon vias or TSVs (through-silicon vias)) and / or horizontal connecting lines are formed in this scenario.

3rd Figure 11 is a circuit diagram of an illustrative image pixel 30th . As in 3rd shown, the pixel closes 30th a photosensitive element like the photodiode 20 , a. A positive supply voltage VAA can be connected to a positive voltage supply connection 22 are fed. Incoming light can come from the photodiode 20 to be collected. In certain embodiments, a color filter structure may be included and incoming light may pass through the color filter structure before it is in the photodiode 20 is collected. The photodiode 20 can generate a charge (e.g., electrons) in response to receiving incident photons. How much charge from the photodiode 20 collected depends on the intensity of the incident light and the exposure time (or integration time).

Before an image is captured, a reset transistor 26 be turned on to the charge storage structure 28 (sometimes referred to as a floating diffusion region or FD) to reset the voltage VAA. That in the floating diffusion area 28 stored reset voltage levels can be read out using charge readout circuitry. The charge readout circuitry can be a source follower transistor 40 and a row selection transistor 42 lock in. The reset level signal can be stored and then used in a readout scheme with correlated double scanning with an image level signal.

The pixel 30th can be an AB (anti-blooming) reset transistor, such as an AB transistor 32 , lock in. If the reset transistor 32 is turned on, the photodiode 20 can be reset to the supply voltage VAA (e.g. by connecting VAA to the photodiode 20 via the reset transistor 32 ). If the AB transistor 32 is turned off, it can be the photodiode 20 be enabled to accumulate photo-generated charge.

The pixel 30th can use a transfer transistor 38 lock in. The transfer transistor 38 can be turned on to charge from the photodiode 20 to a floating diffusion area 28 transferred to. The floating diffusion area 28 may be a doped semiconductor region (e.g., a region in a silicon substrate that has been doped by ion implantation, impurity diffusion, or other doping process).

As an example, the AB transistor 32 before or after generating and reading out the reset level signal (e.g. switched on and then switched off) in order to accumulate the charge on the photodiode 20 to start. After a suitable integration period, the transfer transistor 38 to be turned on to the accumulated charge to the floating diffusion area 28 transferred to. The accumulated charge can then be made using the charge readout circuitry (e.g. transistors 40 and 42 ) can be read out.

The row selection transistor 42 may have a gate controlled by a row select signal. When the row select signal is activated, the transistor 42 turned on and a corresponding signal Vout (e.g., an output signal with a magnitude proportional to the amount of charge at the floating diffusion node 28 is) is directed to the pixel output path. This is done both for the reset level signal reading and for the image level signal reading.

In a typical image pixel array configuration, numerous rows and columns are the pixels 30th available. Each column of pixels 30th can be assigned to a column readout path (e.g. each image pixel can 30th in a column via an associated row selection transistor 42 coupled to the pixel output path). The row selection signal can be activated in order to read the signal Vout from a selected image pixel into the column readout path. Image data Vout can be processed in the processing circuitry 18th be fed. The circuit arrangement of 3rd is illustrative only.

Using the pixel 30th in the above manner, however, undesirable stray light from in the floating diffusion region fails 28 in the pixel 30th to take into account and to protect stored distorted image signals. The unwanted stray light causes noise in the floating diffusion area 28 in the pixel 30th is introduced. In order to manage and take into account the noise introduced, an image pixel, such as an image pixel 30 ' in 4th brought in.

As in 4th shown, the pixel 30 ' in 4th have some components that match those in the pixel 30th in 3rd are similar, and the description of these components is omitted to prevent the present embodiments from appearing unnecessarily obscure. Of elements in 4th with reference numerals similar to those in the elements in 3rd can be assumed to serve similar functions, to operate in a similar manner, etc., unless otherwise described below.

The pixel 30 ' can also have a dual conversion gain transistor 60 , a charge storage structure 62 and a capacitor 64 lock in. The transistor 60 can the charge storage structure 62 with the floating diffusion area 28 couple. The condenser 64 can between the charge storage structure 62 and the positive voltage supply 22 (e.g. a power supply rail). Thus the capacitor 64 help charge at the storage node of the charge storage structure 62 to hold (e.g. voltage VAA from the memory structure 62 disconnect). As an example, the charge storage structure 62 a capacitor, a storage diode, a storage node, a storage gate, a storage loading structure with a storage area in a manner similar to the floating diffusion area 28 , etc. If desired, the charge storage structure 62 have a storage capacity that is larger than that of the floating diffusion region 28 (for example, two times larger, three times larger, five times larger, ten times larger, etc.).

In some embodiments, the charge storage structure 62 the storage capacity of the floating diffusion area 28 expand when saving image charge (e.g. by activating the transistor 60 when the charge is in the floating diffusion area 28 is stored above a potential barrier of the transistor 60 lies and flows over to the storage structure 62 , etc.). As an example, the charge storage structure 62 the storage capacity of the floating diffusion area 28 in a low conversion gain (LCG) mode, and the floating diffusion range 28 , but not the charge storage structure 62 , can be used to store image charge in a high conversion gate (HCG) mode.

Instead of or in addition to these functionalities (e.g. instead of an LCG mode and / or in addition to an HCG mode), the charge storage structure can 62 configured to detect an interference or stray light reference voltage and save. The stray light reference voltage level can be a lot of unwanted stray light that covers the floating diffusion area 28 achieved, represent and / or correspond to this. To the unwanted stray light that affects the floating diffusion area 28 reached to represent more precisely and / or to correspond more precisely to it, the charge storage structure 62 in an environment similar to that of the diffusion area 28 placed and / or in a manner similar to the diffusion area 28 can be provided (e.g. adjacent to the diffusion region 28 in a pixel layout, in the same part as the diffusion area 28 , in a similar optical environment, depth, size, shape, materials, etc.).

By monitoring and storing a reference voltage level (e.g. using the memory structure 62 ), which corresponds to the stray light, which is undesirably caused by the floating diffusion area 28 the pixel can be captured 30 ' estimate and take into account the noise in an image signal. As an example, that in the memory structure 62 stored reference voltage for subsequent readout using the charge readout circuitry in the pixel 30 ' in the floating diffusion area 28 are transmitted, similar to what happens to generate the reset level signal and the image level signal. The read noise reference signal can then be subtracted from the image level signal to take into account any noise contamination in the image level signal. This can be done similarly for the reset level signal if desired.

In addition, the read noise reference signal can be scaled before being subtracted as desired to represent the actual amount of noise in the image level signal. As an example, in some embodiments, the memory structure 62 , which stores the noise reference voltage level, is twice the noise sensitivity as the floating diffusion range 28 exhibit. Thus, the noise reference signal read out can be halved (or scaled in some other way to account for the difference in sensitivity between the floating diffusion region 28 and the memory structure 62 to be considered) before it is subtracted from the image level signal. As another example, the floating diffusion area 28 and the memory structure 62 are reset to a pixel reference voltage at different times, and the image voltage level may be subjected to a different amount of noise than the noise reference voltage level over two different time periods. The read-out noise reference signal can thus be scaled according to these time differences. These scaling and subtraction operations can be performed using digital processing (or analog processing, if desired) from the column readout circuitry and / or digital signal processing circuitry, if appropriate.

5A and 5B FIG. 4 shows an illustrative timing diagram for operating an image sensor with an array of image pixels of FIG 4th type described (e.g. image pixel 30 ' ) in a noise detection mode. In particular, during a period T1 the transistors 26 and 60 (which receive the control signals RST <n> and DCG <n>, respectively) in the pixels 30 ' from row n are activated to the floating diffusion area 28 and the memory structure 62 reset to a reset level voltage in these pixels. The reset level voltage can also change during the period T1 are read out using the respective charge readout circuitry in these pixels (pixels of line n) to generate reset level signals SHR <n>. During a period T2 similar floating diffusion area / charge storage area reset and reset voltage readout operations can take place for another row of pixels (pixels in row n + 1). The charge storage area reset and quiescent voltage readout operations can take place sequentially row by row across all rows in the pixel array (e.g., in a row-by-row operation).

After that, global operation can begin in overlap or before a section of the preceding line-by-line operation. As an example, global operation may be driving the transistors on or off 32 and 38 using global control signals AB and TX in pixels of different lines (e.g. in all pixels) during a period T3 lock in. If desired, the transistor 32 without the transistor 38 can be controlled.

After the period T3 an integration period can occur (e.g. during a period T4 , a period that is different from an end of the period T3 until the end of a period T5 extends). The respective photodiodes can be used during the integration period 20 accumulate charge in each active pixel in response to incident light. In a time span T5 a global signal TX can be activated to determine the accumulated charge on the photodiodes 20 to the corresponding floating diffusion areas 28 transferred to. Line-by-line (read) operations can subsequently take place. If desired, global operations can overlap some of the line-by-line operations to extend the duration of the integration period.

With a period T6 can the charge readout circuitry (e.g. source follower transistors 40 and row selection transistors 42 ) in pixels from line n are activated to generate image level signals SHS <n>. Then, during a period T7 the control signal RST <n> for pixels in line n are activated by appropriate transistors 26 to activate the floating diffusion area 28 reset and so remove the previously detected photodiode signal and any detected stray light noise. After a suitable period of time, the control signal DCG <n> for pixels in line n can be activated by corresponding transistors 60 to activate a spurious noise level voltage to the floating diffusion area 28 transferred to. The noise level voltage can also be read out using charge readout circuitry to produce a noise level signal Calib <n>. Similar operations as in the periods T6 and T7 can in T8 and T9 for pixels on another line (e.g. line <n + 1>). The image signal and noise level readout operations can take place sequentially line by line across all lines in the pixel array (e.g., in a line-by-line operation).

Digital processing circuitry can perform linear combinations of (e.g., scale and subtract operations on) corresponding image level signals and the noise level signals to produce reduced noise image level signals.

While in 4th the transistor 60 and the transistor 26 are shown in parallel, this is only illustrative. If desired, the transistor 60 along a common path between the voltage connection 22 and the floating diffusion area 28 in series with the transistor 26 and other additional circuitry (e.g., transistors, capacitors, switches, etc.) may be coupled to the common path. While some of the embodiments described herein relate to a five transistor pixel configuration, this is also illustrative only. If desired, a charge storage structure that can be operated to store a reference noise voltage level, such as structure 62 in 4th , are implemented in any suitable pixel, such as a pixel that can be operated in a global shutter mode and has more than five transistors, less than five transistors, or other structures (e.g. diodes, transistors, memory structures, etc.) in addition to the pixel configuration of 4th having. The features described herein may analogously describe the pixel configurations mentioned above.

In some embodiments, the charge storage structure 62 directly with the pixel (column) readout circuitry and bypass charge readout circuitry in pixels 30 ' in 4th be coupled. If desired, the charge storage structure 62 have and be coupled to a separate set of readout circuitry (e.g., different from the transistors 40 and 42 distinguish that have no connection to the floating diffusion area 28 etc.).

In some embodiments, the spurious noise level signal may be adjusted by a gain and / or an offset before subtracting it from the image level signal. In some embodiments, (digital) processing circuitry can only subtract the spurious noise level signal if the image level signal is greater than the spurious noise level signal. In some embodiments, the (digital) processing circuitry may only subtract the stray noise level signal from the image level signal when the stray noise level signal is above a (predetermined) given threshold (e.g., to avoid adding noise via the subtraction operation). In some embodiments, the (digital) processing circuitry may only subtract the spurious noise level signal from the image level signal if the image level signal is less than a saturated amount (e.g., to avoid desaturation of bright objects). These subtraction criteria can be applied to any suitable noise reference memory circuit.

In some embodiments, an image sensor can have pixels 30 ' use the difference between the spurious noise level signal and the image level signal (generated in the photodiode) as a means for monitoring and detecting moving objects. Thus, the control circuitry may be operable to perform object detection operations based on a comparison between the stray light level signal and the image level signal.

In some embodiments, the low conversion gain storage node (e.g., capacitor) can be used as a global shutter efficiency monitor. Thus, the storage node with low conversion gain can also be operated in an operating mode with high conversion gain (e.g. if the storage node with high conversion gain stores charge generated by the photodiode for the storage node with high conversion gain). The signal stored in the low conversion gain storage node can be used to locate a noise signal within the signal received in the storage node with high conversion gain is stored to subtract away. As an example, the subtraction operation can be performed in part by a digital scaler. This can be particularly helpful if the picture is a "low-light" picture and the interference signal is high (e.g. bright).

As in connection with the pixel configuration of 4th described, the charge storage area 62 in 4th may be formed from memory diodes and / or other structures and may be implemented in a different configuration with respect to the rest of the pixel circuitry. As an example shows 6 a pixel (e.g., similarly herein as the pixel 30 ' is called) that the memory diode 62 (sometimes referred to herein as a reference diode) that includes the floating diffusion region 28 through a memory diode 82 (sometimes referred to herein as a charge storage area or structure). The memory diode 62 can be a pinned diode (e.g. with an associated pinning voltage). If desired, the memory diode 82 implemented as a memory gate or other memory structure.

As in 6 shown, the pixel 30 ' in 6 some components have that of the pixel 30 ' in 4th are similar, and the description of these components is omitted to prevent the present embodiments from appearing unnecessarily obscure. Of elements in 6 with reference numerals similar to those in the elements in 4th may be assumed to serve similar functions, operate in a similar manner, etc., unless otherwise described herein.

In this configuration for the pixel 30 ' can the memory diode 82 between the photodiode 20 and the floating diffusion area 28 be inserted. Two transistors 80 and 82 can use the photodiode 20 with the memory diode 82 couple or can the memory diode 82 with the floating diffusion area 28 couple. The memory diode 62 can between transistors 86 and 88 be inserted. The transistor 86 can the power supply connector 22 with the memory diode 62 couple, creating a reset path for the memory diode 62 provided. The transistor 88 can the memory diode 62 with the memory diode 82 couple.

The memory diode 62 can similarly generate and store a stray light signal and the stray light signal through the transistor 88 , the storage diode 82 and the transistor 84 to the floating diffusion area 28 transfer. Once the stray light signal is in the floating diffusion range 28 it can be made using the transistors 40 and 42 (or other separate read-out transistors). The photodiode 20 can generate image signals and the image signal through the transistor 80 , the storage diode 82 and the transistor 84 to the floating diffusion area 28 transfer. Once the image signal is in the floating diffusion area 28 it can be made using the transistors 40 and 42 be read out.

While it is described that the memory diode 62 serves as a stray light noise store, this is only illustrative. If desired, the memory diode 62 be implemented in such a way that it serves other functions. As an example, the memory diode 62 used in one mode of operation to store stray light noise, and in another mode of operation the memory diode 62 are used to generate and store image signals that form individual images.

7 FIG. 5 shows an illustrative timing diagram for operating an image sensor with an array of image pixels of the type shown in FIG 6 type described (e.g. image pixel 30 ' ) in a noise detection mode. Similar to what is in the 5A and 5B is shown, the control circuitry (e.g., the row control circuitry 25th in 2nd ) global control signals AB1 activate (e.g. controlling the transistors 32 over all active pixels 30 ' or over all pixels 30 ' ) to the photodiodes 20 in a time span T10 reset. If the control signal FROM 1 is deactivated, a charging integration time can begin. The charging integration time can be at the end of a period T11 end up. During the period T11 the control circuitry can provide a control signal TX1 globally activate (control of the transistors 80 ) to integrated charge from the photodiodes 20 to the memory diode 82 transferred to. During a period T12 the control circuitry can provide a control signal STARTING AT 2 globally activate (control of the transistors 86 ) to the storage diode 62 reset. If the control signal STARTING AT 2 is deactivated, the memory diode 62 start to accumulate charge based on noise.

After an appropriate period of time, the control circuitry may activate control signals to sequentially read lines across pixels 30 ' to start away. In a time span T14 can be a control signal TX2 that the transistors 84 controls for a given row of pixels (row n), activated to those in the memory diode 82 stored image signals (transmitted during the period T11 ) to the floating diffusion area 28 transferred to. This image signal can be read out using readout circuitry (e.g., the control circuitry can be a Control signal RS activate). If desired, the image signal can be read out using a correlated double sampling (CDS) scheme. In this scenario, before the period T14 (e.g. during the period T13 ) the control circuit arrangement can provide a control signal RST activate that the transistors 26 for row n controls the floating diffusion area 28 reset. The reset level signal and the image signal can be read out in a CDS scheme.

In a time span T15 the control circuitry can provide a control signal TX3 activate that the transistors 88 for line n controls to spurious noise signals to the memory diode 82 transferred to. Subsequently and / or simultaneously, the control circuit arrangement can during a period T16 the control signal TX2 for the line n activate to read stray light signals to the floating diffusion area 28 transferred to. Similar to the image signals, the stray light signals can be read out in a CDS scheme. In this scenario, the control circuitry can control the signal RST for line n before the period T16 activate (e.g. during the period T16 ). During the timing of 17th illustrates that activation for the control signal RST synchronized with the activation for the control signal TX3 is illustrative only. If desired, these activations can only partially overlap in time or not overlap.

During periods T17 to T20 surgery can be analogous to surgery during periods T13 to T14 for line n take place for another line (e.g. line <n + 1>). After the period T20 similar operations can take place on yet another line. This continuous readout scheme can take place until all image signals and background noise level signals have been read out from all lines.

As another example shows 8th a pixel (e.g., herein similarly as a pixel 30 ' is called), which is a memory diode 62 includes that with the floating diffusion area 28 is coupled. The pixel 30 ' in 8th can have some components that match those in pixels 30 ' in 6 are similar, and the description of these components is omitted to prevent the present embodiments from appearing unnecessarily obscure. Of elements in 8th with reference numerals similar to those in the elements in 6 may be assumed to serve similar functions, operate in a similar manner, etc., unless otherwise described herein.

As in 8th shown, the transistor 88 in 8th the memory diode 62 directly with the floating diffusion area 28 couple instead of the transistor 88 the memory diode 62 with the memory diode 82 (as in 6 ) couples. In addition, due to this configuration, the memory diode 62 an unpinned diode (or a pinned diode similar to the diode 62 in 6 ) be.

9 FIG. 5 shows an illustrative timing diagram for operating an image sensor with an array of image pixels of the type shown in FIG 8th type described (e.g. image pixel 30 ' ) in a noise detection mode. The control circuitry can handle the signals AB1 , STARTING AT 2 and TX1 globally during periods T21 , T22 and T23 activate. Different from in 7 the control signal is activated STARTING AT 2 before activation of the control signal TX1 . However, this is only illustrative. If desired, the activation of the control signal STARTING AT 2 also on the activation of the control signal TX1 follow or overlap with this.

After the period T23 the control circuitry can control the pixels 30th control in order to carry out the read operation one after the other line by line. In a time span T25 the control circuitry can control the control signal TX3 for a given row of pixels 30th (e.g. for line n) to activate stray light signals for reading in the floating diffusion area 28 transferred to. In the case of a CDS readout scheme, the control signal RST for row n during a period T24 to be activated.

In a time span T27 the control circuitry can control the control signal TX2 for line n activate to image light signals for reading in the floating diffusion area 28 transferred to. In the case of a CDS readout scheme, the control signal RST for row n during the period T26 to be activated.

During periods T28 to T31 surgery can be analogous to surgery during periods T24 to T27 for line n take place for another line (e.g. line <n + 1>). After the period T31 similar operations can take place on yet another line. This continuous readout scheme can take place until all image signals and background noise level signals have been read out from all lines.

Various embodiments have been described that illustrate systems and methods for generating image signals with reduced noise.

In particular, an image sensor can include an array of image sensor pixels arranged in columns and rows. Each pixel in the array can be a photosensitive element that has a the first path coupled to and operable to generate an image level signal using global shutter operations and include a charge storage structure coupled to the floating diffusion region via a second path that differs from the first path and is operable to generate a stray noise level signal using global shutter operations. The image sensor can also include an additional charge storage structure.

The control circuitry may be operable to perform read operations on the stray light level operation on the stray light level signal line by line (to perform read operations for image level signals and stray noise level signals for a given line prior to performing read out operations for image level signals and stray noise level signals for a subsequent line perform). In other words, the read-out operations can be carried out line by line on sets of the image signals and the stray light signals, each set corresponding to the image signals and the stray light signals for one line in the lines.

The processing circuitry may be operable to selectively perform a subtraction operation based on the image level signal and the spurious noise level signal (e.g., a linear combination operation, such as subtracting a scaled version of the spurious noise level signal from the image level signal to produce a reduced noise signal to form a frame, perform). As examples, the subtraction operation can be performed based on whether the stray noise level signal is greater than a threshold level, whether the image level signal is less than a threshold level, etc.

As an example, the charge storage structure may be a memory diode coupled to the floating diffusion region via a first transistor, the floating diffusion region may be coupled to a voltage supply connection via a second transistor, and the memory diode may be decoupled from the voltage supply connection . The floating diffusion region can be inserted between the photosensitive element and the memory diode. The memory diode may be operable to store a low conversion gain signal in a low conversion gain operating mode.

In some embodiments, the photosensitive element may be coupled to the readout circuitry via a first path and the charge storage structure may be coupled to the readout circuitry via a second path that is different from the first path and is operable to generate a stray light signal. The readout circuitry may include a first set of transistors coupled to the photosensitive element and operable to read the image signal and a second set of transistors different from the first set coupled to the charge storage structure and operable to read out the stray light signal. If desired, the second set of transistors can be coupled to corresponding charge storage areas in two or more image pixels and shared between them.

The control circuitry may be operable to activate a first global control signal to cause the image pixels to begin generating the image signal and to control the image pixels to begin generating the stray light signal. The control circuitry may be operable to activate a second global control signal that controls a transistor to transfer the image signal to a charge storage area. The control circuitry may be operable to transmit the stray light signal line by line to the charge storage area. As examples, the control circuitry may be operable to activate a set of control signals line by line or a third global control signal to control the image pixels to begin generating the stray light signal.

In some embodiments with an image pixel having an additional charge storage structure disposed between the photosensitive element and the floating diffusion region, the image pixel may include a first transistor that couples the photosensitive element to the additional charge storage region, a second transistor that couples the charge storage area to the additional charge storage area, and a third transistor that couples the additional charge storage area to the floating diffusion area.

In one embodiment, an image sensor may include an array of image pixels. An image pixel in the array may include a photosensitive element coupled to a floating diffusion region via a first path and operable to generate an image level signal using global shutter operations. The image pixel may further include a charge storage structure coupled to the floating diffusion region via a second path and operable to generate a noise level signal using global shutter operations. The first path can be from the second path be separated. The image sensor may further include control circuitry operable to perform a readout operation on the image level signal and a readout operation on the stray light noise level signal.

According to another embodiment, the image sensor may further include processing circuitry that is operable to selectively perform a subtraction operation based on the image level signal and the noise level signal.

In another embodiment, the processing circuitry may be operable to perform the subtraction operation based on whether the stray noise level signal is greater than a threshold level or based on whether the image level signal is less than a threshold level.

In another embodiment, the processing circuitry may be operable to subtract a modified version of the stray noise level signal from the image level signal to produce a reduced noise signal to form a frame.

According to another embodiment, the charge storage structure can be a storage diode which is coupled to the floating diffusion region via a first transistor. The floating diffusion region can be coupled to a voltage supply connection via a second transistor. The memory diode can be decoupled from the voltage supply connection.

According to another embodiment, the memory diode can be operable to store a signal with low conversion gain in an operating mode with low conversion gain.

According to another embodiment, the image pixel can further include an additional charge storage structure that is inserted between the photosensitive element and the floating diffusion region.

According to another embodiment, the floating diffusion region can be inserted between the photosensitive element and the memory diode.

According to another embodiment, the array of image pixels can be arranged in rows and columns. The control circuitry may be operable to perform the read out operations for image level signals and noise level signals for a given line prior to performing read out operations for image level signals and noise level signals for a subsequent line.

According to another embodiment, the control circuit arrangement can be operable to carry out motion detection based on a comparison between the image level signal and the background noise level signal.

According to one embodiment, an image sensor can include image pixels arranged in rows and columns. Each image pixel in the image pixels may include a photosensitive element coupled to readout circuitry via a first path and operable to generate an image signal. Each image pixel may further include a charge storage structure coupled to the readout circuitry via a second path and operable to generate a stray light signal. The first path can be separated from the second path. The image sensor may further include control circuitry operable to activate a first global control signal to cause the image pixels to begin generating the image signal, to control the image pixels to begin generating the stray light signal, and to read out operations line by line Perform line on sets of image signals and stray light signals, each set corresponding to the image signals and stray light signals for one line in the lines.

According to another embodiment, each image pixel may further include a transistor that couples the photosensitive area to a charge storage area. The control circuitry may be operable to activate a second global control signal that controls the transistor to transfer the image signal to the charge storage region.

According to another embodiment, the control circuit arrangement can be operable to transmit the stray light signal line by line to the charge storage area.

According to another embodiment, the control circuitry may be operable to activate a set of control signals line by line to control the image pixels to begin generating the stray light signal.

In another embodiment, the control circuitry may be operable to activate a third global control signal to control the image signals to begin generating the stray light signal.

In another embodiment, the readout circuitry may include a first set of transistors coupled to the photosensitive element and operable to read the image signal, and may further include a second set of transistors coupled to the charge storage structure and operable to read out the stray light signal. The first set of transistors may differ from the second set of transistors.

According to another embodiment, the second set of transistors can be coupled to corresponding charge storage areas in two or more image pixels and can be shared by them.

In one embodiment, an image sensor may include an array of image pixels. An image pixel in the array may include a photosensitive element coupled to a floating diffusion region and operable to generate an image level signal, a charge storage structure coupled to the floating diffusion region and operable to provide a noise level signal and include an additional charge storage structure interposed between the photosensitive element and the floating diffusion region. The image sensor may further include control circuitry operable to activate control signals across the array to begin generating the image level signal and begin generating the stray noise level signal, and read out operations on the image level signal and the stray noise level signal line by line across the array.

According to another embodiment, the image pixel may further comprise a first transistor, which couples the photosensitive element to the additional charge storage area, a second transistor, which couples the charge storage area to the additional charge storage area, and a third transistor, which couples the additional charge storage area to the floating diffusion Include area.

According to another embodiment, the image sensor may further include processing circuitry that is operable to perform a linear combination operation based on the image level signal and that stray noise level signal.

The foregoing is merely illustrative of the principles of this invention, and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.

Claims (11)

Image sensor, comprising: an array of image pixels, an image pixel in the array comprising a photosensitive element coupled to a floating diffusion region via a first path and operable to generate an image level signal using global shutter operations, and a charge storage structure includes that is coupled to the floating diffusion region via a second path and is operable to generate a stray noise level signal using global shutter operations, the first path being separate from the second path; and control circuitry operable to perform a readout operation on the image level signal and a readout operation on the noise level signal. Image sensor after Claim 1 , further comprising: processing circuitry operable to selectively perform a subtraction operation based on the image level signal and the noise level signal. Image sensor after Claim 2 wherein the processing circuitry is operable to perform the subtraction operation based on whether the stray noise level signal is greater than a threshold level or based on whether the image level signal is less than a threshold level. Image sensor after Claim 2 wherein the processing circuitry is operable to subtract a modified version of the stray noise level signal from the image level signal to produce a reduced noise signal to form a frame. Image sensor after Claim 1 , wherein the charge storage structure comprises a storage diode which is coupled to the floating diffusion region via a first transistor, the floating diffusion region is coupled to a voltage supply connection via a second transistor and the storage diode is decoupled from the voltage supply connection. Image sensor after Claim 1 wherein the control circuitry is operable to perform motion detection based on a comparison between the image level signal and the spurious noise level signal. Image sensor, comprising: image pixels arranged in rows and columns, each image pixel among the image pixels including a photosensitive element coupled to a readout circuitry via a first path and operable to generate an image signal and a charge storage structure associated with the readout circuitry via a second path is coupled and operable to generate a stray light signal, the first path being separate from the second path; and control circuitry operable to activate a first global control signal for the image pixels to begin generating the image signal, to control the image pixels to begin generating the stray light signal, and read out operations line by line on sets of the Perform image signals and the stray light signals, each set corresponding to the image signals and stray light signals for one line in the lines. Image sensor after Claim 7 , wherein each image pixel comprises a transistor coupling the photosensitive region to a charge storage region, the control circuitry is operable to activate a second global control signal to control the transistor to transmit the image signal to the charge storage region and the control circuitry is operable to to transmit the stray light signal line by line to the charge storage area. Image sensor after Claim 7 wherein the readout circuitry includes a first set of transistors coupled to the photosensitive element and operable to read out the image signal, and a second set of transistors coupled to the charge storage structure operable to read out the stray light signal, and the first Set of transistors is different from the second set of transistors. Image sensor, comprising: an array of image pixels, an image pixel in the array being a photosensitive element which is coupled to a floating diffusion region and is operable, to generate an image level signal, a charge storage structure coupled to the floating diffusion region and operable to generate a stray noise level signal, and an additional charge storage structure interposed between the photosensitive element and the floating diffusion region ; and control circuitry operable to activate control signals across the array to begin generating the image level signal and begin generating the stray noise level signal, and Read operations on the image level signal and the noise level signal line by line across the array. Image sensor after Claim 10 The image pixel includes a first transistor that couples the photosensitive element to the additional charge storage area, a second transistor that couples the charge storage area to the additional charge storage area, and a third transistor that couples the additional charge storage area to the floating diffusion area wherein the image sensor further comprises: processing circuitry operable to perform a linear combination operation based on the image level signal and that stray noise level signal.

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