DE102018201410B3 - Demodulation method for C8PSK coding - Google Patents

Abstract

A method is proposed for reconstructing data coded according to C8PSK-HART®, which are transmitted from a transmitter to a receiver by means of a correspondingly modulated analog signal (2). The proposed method is characterized by a low hardware cost and a simple implementation.

Description

The invention relates to a method for reconstructing C8PSK encoded data according to claim 1. Furthermore, the invention relates to a corresponding integrated circuit according to claim 6, a computer program according to claim 7 and a storage medium according to claim 8.

Coherent 8-way Phase Shift Keying (C8PSK) data transmission is especially used in the telecommunications industry. C8PSK creates a balance between fast communication and low energy consumption and low resource consumption. C8PSK is used in particular for two-wire field devices.

As a further development of the established Highway Addressable Remote Transducer (HART®) standard used for building industrial fieldbuses, the C8PSK-HART® standard was created to transmit data eight times faster, ie at 9600 bps. In each case, 3 bits are combined into one symbol and used according to the PSK (PSK phase shift keying phase shift keying) method to modulate a 3200 Hz carrier with eight different phase states. The resulting bandwidth is about 900-2500Hz in the case of the FSK method, and 800-5600Hz in the case of the C8PSK method.

Frequently, (analog) input / output modules in automation systems communicate, for example, with transducers or actuators that send coded data in accordance with the C8PSK-HART® standard. For the I / O module to capture content of this encoded data, the data must first be decoded.

It is known that this special HART modem modules are used, which are either coupled to the (analog) input / output modules or even parts of the input-output modules. The use of the (integrated or external) HART modem modules is associated with a considerable amount of material and requires a relatively complex implementation.

In the publication US 2004/0252725 A1 the processing of an 8PSK signal is disclosed. In this case, a shift register is filled with 8PSK signal, a sum of the first half of the shift register and a sum derived from the second half, from which in turn a difference value is formed.

Transmission of analogue signals modulated according to the C8PSK-HART® standard using special HART modem modules is described in the publication DE 203 80 325 U1 disclosed.

The invention has for its object to provide a method for reconstructing C8PSK encoded data that can be performed without a HART® modem with relatively simple implementation.

This object is achieved by a method for reconstructing C8PSK coded data, which are transmitted by means of a correspondingly modulated analog signal from a transmitter to a receiver, according to claim 1.

In addition, the object is achieved by an integrated circuit, preferably an FPGA, which is designed and provided to carry out the method according to the invention, according to claim 6.

In addition, the object is achieved by a computer program with program code instructions that can be executed by a computer and / or an integrated circuit for implementing the method according to the invention.

In addition, the object is achieved by a storage medium having a computer program and / or an integrated circuit executable computer program according to claim 8.

Advantageous developments emerge from the dependent claims.

1. a) Das Analogsignal wird mittels eines Analog-Digital-Wandlers abgetastet und quantisiert, woraus ein Digitalsignal resultiert. Dabei weist der Analog-Digital-Wandler einen bestimmten Wandlungstakt auf.
2. b) Das Digitalsignal wird anschließend mittels eines Digitalfilters gefiltert. Dabei handelt es sich insbesondere um einen Bandpassfilter.
3. c) Ein Schieberegister wird darauffolgend mit dem gefilterten Digitalsignal in einem bestimmten Schiebetakt gefüllt, wobei der Schiebetakt dem Wandlungstakt des Analog-Digital-Wandlers entspricht.
4. d) Ein Summenwert aller in dem Schieberegister befindlichen Digitalwerte des Digitalsignals wird mittels eines Empfangsautomaten ermittelt.
5. e) Ermittlung jeweils eines Summenwerts eines ersten und eines zweiten Teils der in dem Schieberegister befindlichen Digitalwerte des Digitalsignals mittels des Empfangsautomaten;
6. f) Ein Differenzwert des in dem Verfahrensschritt e) ermittelten Summenwerts wird mittels des Empfangsautomaten ermittelt.
7. g) Eine Differenz der Beträge des in dem Verfahrensschritten d) ermittelten Summenwerts und des in dem Verfahrensschritt f) ermittelten Differenzwerts wird mittels des Empfangsautomaten ermittelt;
8. h) Ein Vorzeichenbit des in dem Verfahrensschritten d) ermittelten Summenwerts und des in dem Verfahrensschritt f) ermittelten Differenzwerts wird mittels des Empfangsautomaten ermittelt.
9. i) Ein durch eine dreistellige Binärzahl repräsentiertes Symbols wird mittels des Empfangsautoamten ermittelt, dahingehend, dass eine erste Stelle der Binärzahl dem in dem Verfahrensschritt h) ermittelten Vorzeichenbit des in dem Verfahrensschritt d) ermittelten Summenwerts (A) entspricht, und dass eine zweite Stelle der Binärzahl dem in dem Verfahrensschritt h) ermittelten Vorzeichenbit des in dem Verfahrensschritt d) ermittelten Differenzwerts (B) entspricht, und dass eine dritte Stelle der Binärzahl einen Wert Eins aufweist, falls der in dem Verfahrensschritt g) ermittelte Differenzwert einen Wert größer Null aufweist, und die einen Wert Null aufweist, falls der in dem Verfahrensschritt g) ermittelte Betrag einen Wert kleiner oder gleich Null ist.
10. j) Die Verfahrensschritte a) bis i) werden wiederholt, um eine Mehrzahl an Symbolen zu ermitteln.
11. k) Die ermittelten Symbole werden zu dekodierten Daten zusammengefügt.

In a method for reconstructing data coded according to C8PSK-HART®, which are transmitted from a transmitter to a receiver by means of a correspondingly modulated analog signal, the following method steps are carried out according to the invention:

1. a) The analog signal is sampled and quantized by means of an analog-to-digital converter, resulting in a digital signal. In this case, the analog-to-digital converter has a specific conversion clock.
2. b) The digital signal is then filtered by means of a digital filter. This is in particular a bandpass filter.
3. c) A shift register is subsequently filled with the filtered digital signal in a given shift clock, the shift clock corresponding to the conversion clock of the analog-to-digital converter.
4. d) A sum value of all in the Shift register located digital values of the digital signal is determined by means of a reception machine.
5. e) determining in each case a sum value of a first and a second part of the digital values of the digital signal in the shift register by means of the reception automaton;
6. f) A difference value of the sum value determined in method step e) is determined by means of the reception machine.
7. g) A difference between the amounts of the sum value determined in method step d) and the difference value determined in method step f) is determined by means of the reception machine;
8. h) A sign bit of the sum value determined in method step d) and of the difference value determined in method step f) is determined by means of the reception machine.
9. i) A symbol represented by a three-digit binary number is determined by means of the receive car, to the effect that a first digit of the binary number corresponds to the sign bit of the sum value (A) determined in method step h), and that a second digit of the Binary number corresponds to the sign bit determined in method step h) of the difference value (B) determined in method step d), and that a third position of the binary number has a value one, if the difference value determined in method step g) has a value greater than zero, and which has a value of zero, if the value determined in method step g) is a value less than or equal to zero.
10. j) The method steps a) to i) are repeated to determine a plurality of symbols.
11. k) The determined symbols are combined into decoded data.

The analog signal is a C8PSK-HART® standard modulated signal that transmits encoded data from a transmitter to a receiver. The transmitter may be, for example, a transmitter or an actuator. The receiver may be, for example, an input / output module. The sampling and quantization of the analog signal take place by means of per se known methods and devices.

The generated digital signal is then filtered by a digital filter to eliminate unwanted noise on the digital signal. This may preferably be a bandpass filter that filters out unwanted high and low frequencies on the digital signal.

The filtered digital signal is written to the shift register in a next step. The shift register can be, for example 16 - or 32 -stufig, without, however, to be limited. In this case, a shift register is understood to mean a logical switching mechanism which comprises a plurality of series-connected flip-flop vectors which shift their memory contents (each 1 bit, the bit width corresponds to a resolution of the digital signal) by a flip-flop at each shift clock. The shift clock corresponds to the conversion clock of the analog-to-digital converter in order to be able to push the converted analog signal through the shift register without delay.

• - Summenwert aller in dem Schieberegister befindlichen Digitalwerte
• - Summenwerte einer ersten Hälfte und einer zweiten Hälfte der in dem Schieberegister befindlichen Digitalwerte
• - Differenzwert der beiden Summenwerte der ersten und zweiten Hälfte des Schieberegisters
• - Betrag eines Differenzwerts der Beträge des zuvor ermittelten Summenwerts aller in dem Schieberegister befindlichen Digitalwerte und des zuvor ermittelten Differenzwerts der beiden (Teil-)Summenwerte
• - Vorzeichenbits des Summenwerts aller in dem Schieberegister befindlichen Digitalwerte und des zuvor ermittelten Differenzwerts der beiden (Teil-)Summenwerte
• - Ermittlung eines durch eine dreistellige Binärzahl repräsentierten Symbols, wobei die drei Stellen der Binärzahlen folgendermaßen berechnet werden:
  • ○ Stelle 1: Vorzeichenbit des Summenwerts aller in dem Schieberegister befindlichen Digitalwerte
  • ○ Stelle 2: Vorzeichenbit des Differenzwerts der beiden Summenwerte der ersten und zweiten Hälfte des Schieberegisters
  • ○ Stelle 3: Differenzwert aus Beträgen des Summenwerts und des Differenzwerts (vgl. Stellen 1 und 2): Falls größer Null, dann Stelle 3 == 1, falls kleiner oder gleich Null, dann Stelle 3 == 0

By means of a reception machine, the following calculations are carried out:

• - Sum of all digital values in the shift register
• Sum values of a first half and a second half of the digital values in the shift register
• - Difference value of the two summation values of the first and second half of the shift register
• - Amount of a difference value of the amounts of the previously determined sum value of all in the shift register digital values and the previously determined difference value of the two (sub) total values
• Sign bits of the sum value of all the digital values in the shift register and of the previously determined difference value of the two (partial) summation values
• Determination of a symbol represented by a three-digit binary number, the three digits of the binary numbers being calculated as follows:
  • ○ place 1 : Sign bit of the sum value of all digital values in the shift register
  • ○ place 2 : Sign bit of the difference value of the two summation values of the first and second half of the shift register
  • ○ place 3 : Difference value from the sum value and the difference value (see points 1 and 2 ): If greater than zero, then digit 3 == 1, if less than or equal to zero, then digit 3 == 0

In this context, a reception machine is understood to mean a control unit which assumes the states corresponding to the calculation steps and from this generates the control signals required for the respective calculation step. These may be, for example, clock or write signals for the shift register or the control of multiplexers for connecting the respective digital signals to be summed with an adder switch network.

The calculation of the three digit binary number is done with each conversion clock to obtain the necessary plurality of symbols needed for a partial or complete reconstruction of the original data to be transmitted.

The entire process can be performed on an integrated circuit, which is preferably an FPGA. This is inventively designed and provided to carry out the previously described inventive method. For this he has, among other things, an analog-to-digital converter, a shift register and a reception machine. Preferably, it additionally comprises a digital filter.

By means of the reception machine, a recognition of a symbol clock on the digital signal generated from the analog signal preferably takes place. The symbol clock may be used to effectively determine a time sequence of the symbols transmitted by the converted analog signal. In other words, a recognition by the receiving machine is synchronized with a time clock of the successive symbols. In this case, it is particularly preferred to search for a repeating sequence of specific symbols which is used for an effective fine adjustment of the symbol clock adopted by the receiving machine. For example, repeated recognition of a sequence of symbols "2" and "6" may be used to precisely determine the symbol clock. Optionally, the symbol clock can be readjusted over a respective symbol age on a symbol clock edge. For example, if the symbol age is zero, the assumed symbol clock is slightly extended, for example, if the symbol age is three, the symbol clock is slightly shortened.

The three-digit binary number (symbol value) determined from a content of the shift register represents the phase position of the full-wave fragment currently contained in the shift register. If a pure 3200Hz sinusoidal signal was sampled at n * 8 samples per full wave (where n equals an arbitrary natural number) and every sample is written to the shift register (for n = 4 this would correspond to a sampling frequency of 102400Hz), then the process described here would provide the same symbol value for every n consecutive samples. The transition from one symbol to the next symbol is referred to as a symbol edge. At this point, each begins a new phase section. The number of sample clocks after a symbol change is called a symbol age.

In a preferred embodiment of the method according to the invention, the conversion clock and the shift clock are in terms of magnitude between one kilohertz and one megahertz, preferably between 100 kilohertz and 250 kilohertz. As a result, the method can be used particularly easily for decoding data coded according to the C8PSK-HART® standard.

The analog-to-digital converter, the digital filter, the shift register and / or the reception machine are preferably implemented as an integrated circuit, preferably an FPGA, in order to enable flexible use of the method without a fixed hardware connection.

The object is further achieved by a computer program having program code instructions executable by a computer and / or an integrated circuit. The computer-implemented, inventive method provides a valuable and powerful support in the encrypted data transmission in the context of industrial facilities.

• 1 ein Blockschaltbild eines erfindungsgemäßen, integrierten Schaltkreises gemäß einer ersten Ausführungsform; und
• 2 ein Blockschaltbild eines erfindungsgemäßen, integrierten Schaltkreises gemäß einer zweiten Ausführungsform.

The above-described characteristics, features, and advantages of this invention, as well as the manner in which they will be achieved, will become clearer and more clearly understood in connection with the following description of the embodiments, which will be described in detail in conjunction with the drawings. Show it:

• 1 a block diagram of an integrated circuit according to the invention according to a first embodiment; and
• 2 a block diagram of an integrated circuit according to the invention according to a second embodiment.

In 1 is a block diagram of an integrated circuit 1 shown for carrying out the method according to the invention. A correspondingly modulated analog signal 2 , which transmits encoded data according to the C8PSK-HART® standard, is provided by an analog-to-digital converter 3 sampled and quantified. A sampling rate or a conversion clock is 102.4 kHz, which corresponds to an integer multiple of the carrier frequency used in the C8PSK-HART® in the amount of 3.2 kHz. Other integer multiples of 3.2 kHz are also usable.

That from the sampling and quantification by the analog-to-digital converter 3 resulting digital signal 5 is then using a bandpass filter 4 filtered to remove unwanted low or high frequencies. The resulting filtered digital signal 6 gets into a shift register 7 written, which consists of 16 levels. The shift clock of the shift register 7 corresponds to the conversion clock of the analog-to-digital converter 3 ,

By means of a receiving machine, not shown, a sum A of all in the shift register 7 located digital values of the filtered digital signal 6 that has a sign bit AVZ features. In addition, two partial sum values are determined, each of a sum of one half (ie, eight values) of those in the shift register 7 located digital values of the filtered digital signal 6 correspond. From these two partial sums, a difference value B is then determined by subtraction, which is another sign bit BVZ having.

The receiving machine uses the previously calculated values to determine a three-digit binary number that corresponds to a symbol 8th corresponds to the decoded data. The three-digit binary number has a first digit BZ1 , a second job BZ2 and a third place BZ3 on.

The first place BZ1 the binary number corresponds to the sign bit AVZ Sum value A. The second place BZ2 the binary number corresponds to the sign bit VZB the difference value B.

The third place BZ3 The binary number is determined from a comparison of the amounts of the sum value A and the difference value B. If the magnitude of the sum value A is greater than the magnitude of the difference value B, then the value of the third digit BZ3 One. If the magnitude of the sum value A is less than or equal to the magnitude of the difference value B, the value of the third digit is BZ3 Zero.

This process is repeated for each sampling cycle. To detect the symbol clock of the transmitter during the "preamble" phase at the beginning of the telegram, the changing appearance of the symbols 6 and 2 at intervals of n * 8 samples (that is the duration of a 3.2kHz full wave) searched.

This process is repeated until all necessary symbols have been received. To detect a symbol clock, ie a time interval between two transmitted symbols, a recognition of repetitive symbols is used, which have the values "2" and "6".

This detection is provided in the C8PSK-HART® as a synchronization method, which is why the data encoded by this standard all have the said symbol sequence at the beginning of a transmission. By means of the reception machine, the received symbols are finally assembled again to the original data bytes.

In 2 is a 32-stage shift register 7 shown. In general, the symbol recognition can be used especially for more noisy or disturbed analog signals 2 improve when a number of stages of the shift register 7 is increased. The determination of the symbols follows the same procedure, which is why only the minor differences are explained here for reasons of clarity. The sum value A is again a summation of all values in the shift register 7 determined, with one half of the shift register 7 positively into the sum and the other half negative. In a corresponding manner, the difference value B is also determined. The first 16 stages of the shift register 7 are therefore used exactly to calculate the values A and B, as previously described 1 described. The second 16 levels are each weighted by a negative sign, which in an overall view, the negative signs "out" again. It is the use of the 32-stage shift register 7 therefore a use according to the invention.

The advantage of the method according to the invention is that no explicit HART modem components have to be used. The hardware cost is therefore significantly reduced compared to the previously known methods or integrated circuits. In addition, under certain circumstances, the method according to the invention can only be realized by applying a new firmware to the integrated circuit.

Although the invention has been further illustrated and described in detail by the preferred embodiment, the invention is not limited by the disclosed examples, and other variations can be derived therefrom by those skilled in the art without departing from the scope of the invention.

Claims (8)

A method of reconstructing C8PSK-HART® encoded data transmitted from a transmitter to a receiver by means of a correspondingly modulated analog signal (2), comprising: a) sampling and quantizing the analog signal (2) using an analog-to-digital converter ( 3), resulting in a digital signal (5) results, wherein the analog-to-digital converter (3) has a certain conversion clock; b) filtering the digital signal (5) by means of a digital filter (4); c) filling a shift register (7) with the filtered digital signal (6) in a specific shift clock, the shift clock corresponding to the conversion clock of the analog-to-digital converter (3); d) Determining a sum value (A) of all the digital values of the shift in the shift register (7) filtered digital signal (6) by means of a reception machine; e) determining in each case a sum value of a first half and a second half of the digital values of the filtered digital signal (6) located in the shift register (7) by means of the reception automaton; f) determining a difference value (B) of the two sum value determined in method step e) by means of the reception machine; g) determination of a difference of the amounts of the sum value (A) determined in method step d) and of the difference value (B) determined in method step f) by means of the reception machine; h) determination of a sign bit (VZA) of the sum value (A) determined in method step d) and of a sign bit (VZB) of the difference value (B) determined in method step f) by means of the reception machine; i) determination of a symbol (8) represented by a three-digit binary number by means of the reception automat, in such a way that a first digit (BZ1) of the binary number corresponds to the sign bit (VZA) of the sign (VZA) determined in method step d). and that a second position (BZ2) of the binary number corresponds to the sign bit (VZB) of the difference value (B) determined in method step d), and that a third position (BZ3) of the binary number has a value of one if the difference value determined in method step g) has a value greater than zero and has a value of zero if the value determined in method step g) is less than or equal to zero; j) repeating the method steps a) to i) to determine a plurality of symbols (8); k) combining the determined symbols (8) into decoded data. Method according to Claim 1 in which by means of the reception automaton a recognition of a symbol clock takes place on the filtered digital signal (6) generated from the analog signal (2). Method according to Claim 2 in which, as part of the recognition of the symbol clock, the filtered digital signal (6) is searched for a repeating sequence of certain symbols (8) used for a fine adjustment of the symbol clock. Method according to one of the preceding claims, in which the conversion clock and the shift clock amount lie between one kilohertz and one megahertz. Method according to one of the preceding claims, in which the analog-to-digital converter (3), the digital filter (4), the shift register (7) and / or the reception machine are implemented as an integrated circuit (1). Integrated circuit (1) designed and provided for carrying out the method according to one of Claims 1 to 5 wherein the integrated circuit (1) comprises at least one analog-to-digital converter (3), a shift register (7) and a reception machine. A computer program comprising program code instructions executable by a computer and / or an integrated circuit (1) for implementing the method according to any one of Claims 1 to 5 , Storage medium having a computer program executable by a computer and / or integrated circuit (1) Claim 7 ,

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