DE102018130452A1 - A concept for converting a thermometer-coded input signal - Google Patents

Abstract

Examples relate to conversion circuitry, means for conversion, a conversion method, a delta-sigma modulator, a delta-sigma modulation means, a digital-to-analog conversion circuit, a digital-to-analog conversion means, a mobile device , a communication device and a base station transceiver. The conversion circuit arrangement is suitable for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values. The output signal is effective for n digital-to-analog converter units of a digital-to-analog conversion circuit. The conversion circuit arrangement is designed to generate the output signal based on a plurality of pair-wise comparisons between first binary values and second binary values of the n binary values. An offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values.

Description

Territory

Examples relate to conversion circuitry, means for conversion, a conversion method, a delta-sigma modulator, a delta-sigma modulation means, a digital-to-analog conversion circuit, a digital-to-analog conversion means, a mobile device , a communication device and a base station transceiver.

background

Analog-to-digital conversion of analog signals is an area of research and development. A group of circuits that are suitable for the analog-to-digital conversion of analog signals are delta-sigma modulators. Delta sigma modulators include a quantizer for sampling the analog signal and a digital-to-analog converter circuit for providing a feedback signal to the quantizer.

Figure list

• 1a zeigt ein Blockdiagramm eines Beispiels einer Umwandlungsschaltungsanordnung, ein Beispiel einer Digital-zu-Analog-Wandlungsschaltung, umfassend die Umwandlungsschaltungsanordnung, und ein Beispiel eines Delta-Sigma-Modulators, umfassend die Digital-zu-Analog-Wandlungsschaltung umfassend die Umwandlungsschaltungsanordnung;
• 1b zeigt ein Blockdiagramm eines Beispiels einer Umwandlungsschaltungsanordnung und ein Beispiel eines Delta-Sigma-Modulators, umfassend die Umwandlungsschaltungsanordnung;
• 1c zeigt ein Flussdiagramm eines Beispiels eines Umwandlungsverfahrens;
• 2 zeigt ein Blockdiagramm eines Beispiels einer mobilen Vorrichtung oder einer Kommunikationsvorrichtung, umfassend einen Delta-Sigma-Modulator mit einer Umwandlungsschaltungsanordnung, und ein Beispiel eines Basisstationssendeempfängers, umfassend einen Delta-Sigma-Modulator mit einer Umwandlungsschaltungsanordnung;
• 3a zeigt ein vereinfachtes schematisches Diagramm eines Multi-Bit-Sigma-Delta-Modulator-basierten Analog-zu-Digital-Wandlers;
• 3b zeigt ein vereinfachtes schematisches Diagramm eines Multi-Bit-differenziellen Digital-zu-Analog-Wandlers;
• 3c zeigt ein beispielhaftes Schaltschema eines Multi-Bit-differenziellen Digital-zu-Analog-Wandlers, getrieben durch einen monotonen ADC (z.B. Flash-ADC);
• 3d zeigt ein vereinfachtes schematisches Diagramm eines Multi-Bit-differenziellen Digital-zu-Analog-Wandlers mit einer Dumping-Schaltungsanordnung;
• 3e zeigt ein beispielhaftes Dumping-Schaltschema eines Multi-Bit-differenziellen Digital-zu-Analog-Wandlers, getrieben durch einen monotonen ADC (z.B. Flash-ADC);
• 4a zeigt ein Beispiel eines Schaltschemas für einen 4-Bit-Multi-Bit-differenziellen Digital-zu-Analog-Wandler, getrieben durch einen Analog-zu-Digital-Wandler vom Typ eines spannungsgesteuerten Oszillators; und
• 4b zeigt ein beispielhaftes Dumping-Schaltschema eines Multi-Bit-differenziellen Digital-zu-Analog-Wandlers, getrieben durch einen Analog-zu-Digital-Wandler vom Typ eines spannungsgesteuerten Oszillators.

Some examples of devices and / or methods are described below by way of example only and with reference to the accompanying figures, in which:

• 1a FIG. 12 shows a block diagram of an example of conversion circuitry, an example of a digital-to-analog conversion circuit comprising the conversion circuitry, and an example of a delta-sigma modulator comprising the digital-to-analog conversion circuit comprising the conversion circuitry;
• 1b Figure 12 shows a block diagram of an example of conversion circuitry and an example of a delta sigma modulator comprising the conversion circuitry;
• 1c 11 shows a flowchart of an example of a conversion method;
• 2nd Figure 3 shows a block diagram of an example of a mobile device or a communication device comprising a delta sigma modulator with conversion circuitry and an example of a base station transceiver comprising a delta sigma modulator with conversion circuitry;
• 3a shows a simplified schematic diagram of a multi-bit sigma-delta modulator-based analog-to-digital converter;
• 3b shows a simplified schematic diagram of a multi-bit differential digital-to-analog converter;
• 3c shows an exemplary circuit diagram of a multi-bit differential digital-to-analog converter, driven by a monotonous ADC (eg flash ADC);
• 3d shows a simplified schematic diagram of a multi-bit differential digital-to-analog converter with a dumping circuit arrangement;
• 3e shows an exemplary dumping schematic of a multi-bit differential digital-to-analog converter, driven by a monotonous one ADC (eg flash ADC);
• 4a FIG. 3 shows an example of a circuit diagram for a 4-bit multi-bit differential digital-to-analog converter, driven by an analog-to-digital converter of the voltage-controlled oscillator type; FIG. and
• 4b shows an exemplary dumping circuit diagram of a multi-bit differential digital-to-analog converter, driven by an analog-to-digital converter of the voltage-controlled oscillator type.

Detailed description

Various examples will now be described in more detail with reference to the accompanying drawings, in which some examples are shown. In the figures, the strengths of lines, layers and / or regions may be exaggerated for clarity.

Accordingly, while other examples of various modifications and alternative forms are suitable, some specific examples thereof are shown in the figures and are described in detail below. However, this detailed description does not limit further examples to the particular forms described. Other examples may cover all modifications, equivalents, and alternatives that fall within the scope of the disclosure. The same or similar reference numerals refer to the same or similar elements throughout the description of the figures, which when compared with one another can be implemented identically or in a modified form while providing the same or a similar function.

It is understood that when an element is referred to as “connected” or “coupled” to another element, the elements can be connected or coupled directly, or via one or more intermediate elements. When combining two elements A and B using an "or" , it is to be understood that all possible combinations are disclosed, ie only A, only B and A and B, unless this is explicitly or implicitly stated otherwise. An alternative wording for the same combinations is "at least one of A and B" or "A and / or B". The same applies mutatis mutandis to combinations of more than two elements.

The terminology used herein for the purpose of describing certain examples is not intended to be limiting of other examples. If a singular form, e.g. For example, "a, a," and "the, that," is used and the use of only a single element is neither explicitly nor implicitly defined as mandatory, other examples can also use plural elements to implement the same function. Similarly, if a function is described below as being implemented using multiple elements, other examples may implement the same function using a single element or processing entity. It is further understood that the terms “comprises”, “comprising”, “has” and / or “having” in use specify the presence of the specified features, integers, steps, operations, processes, actions, elements and / or components thereof , but do not exclude the presence or addition of one or more other characteristics, integers, steps, operations, processes, actions, elements, components and / or a group thereof.

Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their usual meaning of the area to which the examples belong.

In many circuits, delta-sigma modulators (or sigma-delta modulators) can be used to sample analog signals. Such delta-sigma modulators include a quantizer and a digital-to-analog converter that is used to provide a feedback signal to the input of the modulator. The digital-to-analog converter often receives thermometer-encoded input from the quantizer based on which the feedback signal is generated. The digital-to-analog converter can include a plurality of digital-to-analog conversion units that are controlled by the thermometer-coded input. In order to achieve a low-noise feedback signal, a dumping process can be used by the digital-to-analog converter: If, based on the signal provided by the quantizer, two digital-to-analog conversion units could cancel each other out these units are deactivated (eg “dumped from the feedback signal”) and thus may not contribute to the signal noise. For some quantizers, the thermometer-encoded signal provided by the quantizer always starts at the same position (e.g., if the signal provided by the quantizer has a logical sequence of n binary values, the thermometer-encoded signal can be a sequence of k instances of a first value (eg 1 or high) and a sequence of nk sequences of a second value (e.g. 0 or low), following the sequence of k instances of the first value, the sequence of k instances of the first value (always) in position 1 the logical sequence begins). Thus, to determine whether digital-to-analog conversion units should be dumped, fixed paired comparisons can be used, e.g., by comparing signal components that are at symmetrical positions within the logical sequence of binary values (e.g., as in 3e shown) are positioned.

With other quantizers, e.g. quantizers, which are based on a voltage controlled oscillator ( VCO ; voltage controlled oscillator), the starting position of the sequences can shift depending on the signals previously generated by the quantizer. With such an input signal, comparisons of symmetrical positions within the logical sequence of binary values may not result in all pairs of digital-to-analog conversion units that can be mutually dumped. The concept is related to the 3a to 3e shown in more detail.

At least some examples may provide conversion circuitry or means for converting that is adapted to provide a signal (eg, an output signal) for digital-to-analog conversion units of a digital-to-analog converter based on a thermometer-coded input signal with a thermometer code with a variable starting position.

1a and 1b show examples of conversion circuitry 10th or a means of converting 10th for a digital-to-analog conversion circuit 100 or for a digital-to-analog conversion medium 100 . 1a shows the digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 comprising the conversion circuitry 10th or the means to convert 10th and n digital-to-analog converter units 20th . Alternatively, the conversion circuitry 10th or the means to convert 10th separately from the digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 be like in 1b is shown. 1a and 1b also show a delta-sigma modulator 1000 or a delta sigma Modulation means 1000 comprising the digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 and / or the conversion circuitry 10th or the means to convert 10th . The components of the means for conversion 10th , the digital-to-analog conversion medium 100 and / or the delta-sigma modulation means 1000 are defined as component means that correspond to the respective structural components of the conversion circuitry 10th , the digital-to-analog conversion circuit 100 and / or the delta-sigma modulator 1000 correspond.

The conversion circuitry 10th or the means to convert 10th is suitable for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with ternary n values. The output signal is effective (ie suitable) for the n digital-to-analog converter units 20th a digital-to-analog conversion circuit 100 . The conversion circuitry 10th is configured to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values. An offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values.

Using a fixed offset can allow using a dumping process with a thermometer encoded input signal having a variable starting point of the thermometer code. This may allow noise to be reduced in such circuits since digital-to-analog conversion units, which may otherwise contribute to signal noise, can be dumped from the generation of the signal.

The conversion circuit is designed to determine the output signal based on the thermometer-coded input signal. For example, the thermometer-coded input signal can comprise n input signal components. The n input signal components can be assigned to the logical sequence of n binary values, e.g. a logical first input signal component of the input signal may correspond (e.g., be assigned) to a first binary value of the logical sequence of n binary values, a logical second input signal component of the input signal may correspond (e.g., be assigned) to a second binary value of the logical sequence of n binary values. Each signal component can take one of two values, e.g. a first value or a second value, which represents a binary value of the logical sequence of n binary values.

For example, the first value 1 (or "high" or "positive"), and the second value can 0 or -1 (or "neutral", "mass", "low" or "negative"). Alternatively, the first value 0 or -1 can be and the second value 1 be.

The thermometer encoded input signal includes a thermometer code. The thermometer code can be distributed over the logical sequence of binary values. The thermometer code can be represented by a sequence of instances of the first value, for example by a sequence of 1s or “high” values. The remaining binary values or signal components of the input signal can include the second value. Within the logical sequence of signal components, subsequent signal components can have the same value, except at the position or positions within the logical sequence at which the thermometer code changes (eg from high to low, from low to high, from 1 to 0 or from 0 to 1 ). With some thermometer-coded input signals there can be zero transitions, e.g. if the entire logical sequence of binary values has the same value (e.g. 0 or 1 , high or low). There may be a transition with some thermometer-coded input signals, for example, if the thermometer code begins at the first position of the logical sequence or if the thermometer code ends at the last position of the logical sequence. With some thermometer-coded input signals, there can be two transitions, for example if the thermometer code comprises at least a first value and if the first and the last binary value of the logical sequence of binary values both have the first value (and are part of the thermometer code) or both the have second value. The thermometer code can wrap binary values at the end of the logical sequence.

For example, the thermometer-coded input signal can be a thermometer-coded input signal with a variable starting position of the thermometer code. This may allow using the conversion circuitry and / or the means for converting with an input signal generated by an analog-to-digital converter based on a voltage controlled oscillator. For example, the thermometer code can have a variable start position. The thermometer code can be a rotating thermometer code. The thermometer-coded input signal can be a thermometer-coded input signal with a rotating thermometer code. For example, the thermometer code may not necessarily start at the first logical position of the logical sequence of binary values. For example, the starting position of the thermometer code within the logical sequence of binary values may depend on at least one previous state of the input signal. For example, the start position of the thermometer code within the logical sequence of binary values can correspond to a position within the logical sequence of binary values that follows an end position of a previous thermometer code within a (directly) previous state of the input signal.

In at least some examples, as in 1b is shown includes the conversion circuitry 10th one or more entrances 12 or input means 12 which are designed to receive the input signal from a quantizer, which is based on a voltage-controlled oscillator. Such quantizers can be used for high-resolution oversampling ADCs because they allow an additional order of noise shaping. An entrance 12 or input means 12 may correspond to an interface for receiving information which may be in digital (bit) values according to a specified code, within a module, between modules or between modules of different entities.

The output signal comprises n ternary values. Each ternary value of the n ternary values of the output signal can correspond to and / or be assigned to a digital-to-analog converter unit of the n digital-to-analog converter units. For example, a ternary value of the output signal can be coupled (eg electronically connected) to a digital-to-analog conversion unit of the n digital-to-analog converter units to which it is assigned, for example via an output 14 or a starting agent 14 . Each binary value of the n binary values of the thermometer-coded input signal can correspond to and / or be assigned to a digital-to-analog converter unit of the n digital-to-analog conversion units and / or a ternary value of the n ternary values of the output signal. For example, a logical first binary value of the thermometer-coded input signal may correspond to or be associated with a logical first ternary value of the output signal, and may correspond to a logical first digital-to-analog conversion unit of the n digital-to-analog conversion units or be assigned to the same.

The n ternary values can correspond, for example, to a positive value, a negative value and a neutral value. The neutral value can be used to “dump” one digital-to-analog converter unit of the n digital-to-analog converter units. The output signal is effective (ie suitable) for n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 . For example, the output signal may be effective / suitable for controlling the n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 be.

In some examples, the conversion circuitry may be configured to generate a differential output signal. The signal previously referred to as the output signal can be a first polarity component of the differential output signal. The conversion circuit arrangement can be designed to generate a second polarity component of the output signal. The conversion circuit arrangement can be designed to generate the second polarity component inversely to the first polarity component of the differential output signal. For example, both the first polarity component and the second polarity component can comprise n ternary values. For each positive value of the first polarity component, the second polarity component can include a negative value at the corresponding position within the second polarity component. For each negative value of the first polarity component, the second polarity component can comprise a positive value at the corresponding position within the second polarity component. For each neutral value of the first polarity component, the second polarity component can comprise a neutral value at the corresponding position within the second polarity component.

Alternatively, the differential signal can be generated by the digital-to-analog conversion units based on a single output signal (eg the output signal). For example, the n digital-to-analog conversion units can be n differential digital-to-analog conversion units. Each digital-to-analog conversion unit of the n digital-to-analog conversion units can be designed to obtain a ternary value (for example a signal component of the output signal corresponding to the ternary value) from the conversion circuit arrangement. The n digital-to-analog conversion units can each be designed to provide a positive voltage or a positive current on a first output connection (for example a “p” output connection for a first polarity component of a differential output signal) of the digital-to-analog conversion unit and provide a negative voltage or current on a second output terminal (eg, an "n" output terminal for a second polarity component of the differential output signal) of the digital-to-analog conversion unit when the ternary value is a positive value. The n digital-to-analog conversion units can each be configured to provide a negative voltage or a negative current on the first output connection of the digital-to-analog conversion unit and a positive voltage or a positive current on the second output connection of the digital-to-analog conversion unit, if the ternary Value is a negative value. The n digital-to-analog conversion units can each be designed to provide a ground or common mode voltage or a zero current via both the first and the second connection if the ternary value is a neutral value.

In at least some examples, the output signal includes either positive or negative values. The output signal may not include both positive and negative values. The output signal may also include zero or more neutral values.

For example, the output signal may possibly be provided to the n digital-to-analog conversion units of the digital-to-analog conversion circuit. As in 1b is shown, the conversion circuitry 10th one or more outputs 14 or starting means 14 comprise, which are designed to the output signal of the n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 to provide. An exit, for example the exit 14 or the starting agent 14 can correspond to an interface for sending information which can be represented by digital (bit) values according to a specified code or protocol, within a module, between modules, or between modules of different entities. For example, the digital-to-analog conversion circuit 100 a digital-to-analog conversion circuit 100 of the delta-sigma modulator 1000 be.

The conversion circuitry 10th is configured to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values. For example, the plurality of pairwise comparisons can determine whether a first binary value is different / different from the second binary value, for example whether the first binary value is a logical 1 value (eg a “high” value) and the second binary value is a logical one 0 or logical -1 value (eg a "low" value) or whether the second binary value is a logical 1 value (eg a "high" value) and the first binary value is a logical 0- or logical -1- Value (eg a "low" value), eg to determine whether the first binary value and the second binary value would cancel each other out. If this is the case, a neutral value can be generated for the output signal, for example in order to effect dumping of one or both of the digital-to-analog conversion units in accordance with the first and / or the second binary value.

For example, the n binary values can be represented by a first value and a second value. The conversion circuitry 10th can be designed to determine whether the first binary value and the second binary value are odd values, for example whether the first binary value is a logical 1 value (eg a “high” value) and the second binary value is a logical 0- or a logical -1 value (eg a "low" value), or whether the second binary value is a logical 1 value (eg a "high" value) and the first binary value is a logical 0 or logical -1 value (eg a "low" value).

The conversion circuitry 10th may be configured to generate a neutral value for the ternary value of the n ternary values that corresponds to the first binary value or the second binary value if the first binary value and the second binary value are unequal values.

For example, n can be an even number. The n digital-to-analog conversion units can comprise an even number of digital-to-analog conversion units. The offset between the first binary value and the second binary value can be n / 2. For example, if the n digital-to-analog conversion units 16 The offset can correspond to digital-to-analog conversion units 8th be. For example, n / 2 comparisons can be carried out in pairs. The conversion circuitry may be configured to generate a neutral value for the ternary value of the n ternary values that corresponds to the first binary value and the second binary value if the first binary value and the second binary value are unequal values. Since all n binary values can be compared with only n / 2 comparisons if n is an even number, these comparisons can be sufficient and both digital-to-analog conversion units that correspond to the first and second binary values can be dumped ( for example, their corresponding ternary values can be set to the neutral value).

Alternatively, n can be an odd number. The offset between the first binary value and the second binary value can be the ceiling function of n / 2. For example, if the n digital-to-analog conversion units 15 Digital-to-analog conversion units (as in 4A and 4b shown), the offset can 8th be. The plurality of pair-wise comparisons can correspond to n pair-wise comparisons. This can be necessary to carry out pairwise comparisons on all binary values. The conversion circuitry 10th can be designed to have a neutral value for the ternary value of the n generate ternary values that correspond to either the first binary value or the second binary value if the first binary value and the second binary value are unequal values.

The conversion circuitry may be configured to generate a positive or negative value for the ternary value of the n ternary values that corresponds to (either) the first binary value or the second binary value if the second binary value are equal values, e.g. a positive value if both have the first value and a negative value if both have the second value. If n is even, the conversion circuitry may be configured to generate a positive or negative value for the ternary value of the n ternary values corresponding to the first binary value and the second binary value if the second binary value are equal values, e.g. a positive value if both have the first value and a negative value if both have the second value. If the first and second binary values are the same (e.g. they do not cancel each other out), the ternary values of the n ternary values can reflect the binary values of the n binary values corresponding to the ternary values.

The offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values. For example, the offset can be a logically static offset for the plurality of pairwise comparisons. For example, the logical sequence of the thermometer-coded input signal can provide an enumeration of the positions / components of the thermometer-coded input signal. The conversion circuitry 10th or the means for converting can be designed to select the first and second binary for pairwise comparison based on the offset, for example based on the enumeration of the positions / components of the thermometer-coded input signal. For example, if n = 15, the offset can be 8th be. The logical first binary value within the logical sequence of binary values can be compared in pairs with the logical ninth binary value within the logical sequence of binary values, the logical second binary values can be compared in pairs with the logical tenth binary value, etc.

The offset between the first binary value and the second binary value can wrap n binary values at the end of the logical sequence. This may allow using the conversion circuitry and / or means for converting with an input signal generated by a quantizer based on a voltage controlled oscillator. For example, if n = 15, the offset can be 8th be. The logical seventh binary value can be compared in pairs with the logical fifteenth binary value and the logical eighth binary value can be compared in pairs with the logical first binary value.

In at least some examples, the offset between the first binary value and the second binary value may be the ceiling function of n / 2. This can enable identification of suitable digital-to-analog conversion units that can be dumped.

For example, n can be an odd number. The plurality of pairwise comparisons can correspond to n pairwise comparisons. The n pairwise comparisons can be carried out in parallel. This can avoid introducing delays in the generation of the output signal. For example, the conversion circuitry may comprise n parallel comparison circuits for the plurality of pairwise comparisons, e.g. n XOR (eXclusive OR; exclusive OR) -based or XNOR (eXclusive Negative OR; exclusive negative OR) -based comparison circuits.

Alternatively, n can be an even number. The offset between the first binary value and the second binary value can be n / 2. This can allow dumping of both digital-to-analog conversion units that are assigned to compared binary values. The majority of pair-wise comparisons may correspond to n / 2 pair-wise comparisons. The n / 2 pair-wise comparisons can be carried out in parallel. This can avoid introducing delays in the generation of the output signal. For example, the conversion circuitry can (only) n / 2 parallel comparison circuits for the plurality of pairwise comparisons, e.g. n / 2 XOR-based or XNOR-based comparison circuits. Since only n / 2 pair comparisons may be used, the circuitry required for the comparisons can be reduced.

1a and 1b also show a delta-sigma modulator 1000 or a delta-sigma modulation means 1000 comprising the conversion circuitry 10th or the means to convert 10th . The output signal may be effective (ie suitable) for n digital-to-analog converter units 20th a digital-to-analog conversion circuit 100 of the delta-sigma modulator 1000 or the delta-sigma modulation means 1000 . Inside the delta sigma modulator 1000 the conversion circuitry may be used to convert the digital to analog converter of the delta-sigma modulator through the (VCO-based) quantizer to convert provided signal.

In at least some examples, as further described in 1b is shown includes the delta-sigma modulator 1000 a quantizer 30th , which is based on a voltage controlled oscillator, or a quantizer 30th , which is based on a voltage controlled oscillator. The quantizer 30th which is based on a voltage controlled oscillator or the quantization means 30th , which is based on a voltage controlled oscillator, can be configured to the conversion circuitry 10th to provide the input signal. The quantizer 30th , which is based on a voltage controlled oscillator, can be used by the quantizer 30th , which is based on a voltage-controlled oscillator, or be implemented by the same. As further in 1b is shown, the delta-sigma modulator 1000 or the delta-sigma modulation means 1000 a digital-to-analog converter circuit 100 or a digital-to-analog conversion means 100 include. The digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 can the conversion circuitry 10th or the means to convert 10th include. Alternatively, the digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 separately from the conversion circuitry 10th or the means to convert 10th be. The digital-to-analog conversion circuit 100 can the n digital-to-analog converter units 20th include. The conversion circuitry 10th or the means to convert 10th can be designed to the n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 to provide the output signal.

In at least some examples, as in 1a is shown includes the digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 the n digital-to-analog converter units 20th and the conversion circuitry 10th or the means to convert 10th . The conversion circuitry 10th or the means to convert 10th can be designed to the n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 or the digital-to-analog conversion means 100 to provide the output signal.

In examples, the conversion circuitry 10th or the means to convert 10th using one or more circuit gates, one or more transistors, one or more conversion units, one or more means for conversion, one or more processing units, any means for processing such as a processor, a computer or a programmable hardware component that are effective with appropriately adapted software. In other words, the described function of the conversion circuitry 10th or the means to convert 10th can also be implemented in software that then runs on one or more programmable hardware components. Such hardware components can include a general-purpose processor, a digital signal processor (DSP), a microcontroller, etc.

More details and aspects are mentioned in connection with the examples described above or below. In the 1a or 1b Examples shown may include one or more optional additional features corresponding to one or more aspects associated with the proposed concept or one or more above or below (e.g. 1c to 4b ) described examples are mentioned.

1c shows a flowchart of a conversion process. The conversion method is suitable for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values. The output signal is effective (ie suitable) for n digital-to-analog converter units 20th of a digital-to-analog conversion medium 100 or a digital-to-analog converter 100 . The conversion process involves creating 120 of the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values. An offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values.

The method may further include other features, such as in connection with the conversion circuitry or the means for converting 1a or 1b is shown.

For example, like in 1c is shown, the conversion method can be obtained 110 the input signal from a quantization means based on a voltage controlled oscillator or a quantizer based on a voltage controlled oscillator. The conversion process can provide 130 the output signal to n digital-to-analog converter units 20th of the digital-to-analog conversion means 100 include.

In at least some examples, the n binary values are a first value and a represents the second value. The conversion process can determine 122 include whether the first binary value and the second binary value are unequal values. The conversion process can generate 124 a neutral value for the ternary value of the n ternary values that corresponds to the first binary value or the second binary value if the first binary value and the second binary value are unequal values.

For example, n can be an even number. The offset between the first binary value and the second binary value can be n / 2. n / 2 pair comparisons can be made. The method may include performing the plurality of pair-wise comparisons, such as the n / 2 pair-wise comparisons. The conversion process can generate 124 a neutral value for the ternary value of the n ternary values that corresponds to the first binary value and the second binary value if the first binary value and the second binary value are unequal values.

Alternatively, n can be an odd number. The offset between the first binary value and the second binary value can be the ceiling function of n / 2. The plurality of pair-wise comparisons can correspond to n pair-wise comparisons. The conversion process can generate 124 include a neutral value for the ternary value of the n ternary values that corresponds to either the first binary value or the second binary value if the first binary value and the second binary value are unequal values.

More details and aspects are mentioned in connection with the examples described above or below. This in 1c The example shown may include one or more optional additional features corresponding to one or more aspects associated with the proposed concept or one or more of the foregoing (e.g. 1A or 1b ) or below (e.g. 2nd to 4b ) described examples are mentioned.

2nd FIG. 4 shows a block diagram of an example of a mobile device, communication device or mobile terminal device 200 comprising a delta-sigma modulator 1000 or a delta-sigma modulation means 1000 and / or a base station transceiver 250 comprising a delta-sigma modulator 1000 or a delta-sigma modulation means 1000 . The delta sigma modulator 1000 or the delta-sigma modulation means 1000 can be similar to the delta sigma modulator 1000 or the delta-sigma modulation means 1000 be implemented in conjunction with the 1a to 1c is described. Such a mobile device, communication device or mobile terminal device 200 and / or a base station transceiver 250 may use a delta-sigma modulator with a VCO-based quantizer and a dumping-based digital-to-analog converter that has both an additional order of noise shaping provided by the VCO-based quantizer and one can provide additional low-noise operation that is made possible by the dumping process.

More details and aspects are mentioned in connection with the examples described above or below. This in 2nd The example shown may include one or more optional additional features corresponding to one or more aspects associated with the proposed concept or one or more of the foregoing (e.g. 1a to 1c ) or below (e.g. 3a to 4b ) described examples may be mentioned.

At least some examples can be a dumping concept for fully differential DACs (digital-to-analog converter; digital-to-analog converter, for example the digital-to-analog conversion circuit or the digital-to-analog conversion means) for a rotating thermometer - Provide code input signal format (e.g. the thermometer-coded input signal).

At least some examples can refer to a multi-bit sigma-delta modulator (e.g. the delta-sigma modulator 1000 and / or the delta-sigma modulation means 1000 ) -based analog-to-digital converter ( ADC , 3a ) Respectively. 3a shows a simplified principle of a multi-bit sigma-delta modulator-based ADC . The converter includes a loop filter 302 , a multi-bit ADC 304 and a multi-bit DAC 306 . The n-bit ADC can have a relatively low resolution (eg 1 to about 6 bits) and can be implemented by a flash-type ADC. The connection 305 between the ADC and the DAC can be realized in a thermometer code representation of 2 ^N lines instead of in a binary, weighted format. This thermometer code representation can be used to drive the DAC cells within the n-bit DAC, ie each of the ADC digital output lines drives one of the DAC cells.

The multi-bit differential DAC ( 3b ) comprises a number M of identical DAC slices (for example the n digital-to-analog conversion units). 3b shows a simplified schematic diagram of a multi-bit differential DAC . The output signals I _p 310 and In 312 of (all) of the disks can be connected. Depending on the digital input code of the DAC will a certain number of I _{cell_p} 314 Cells and I _{cell_n} 316 Cells with positive output I _p 310 connected. The opposite number of I _{cell_p} cells and I _{cell_n} Cells is with the negative output I _n 312 connected. The switches 318 can be used to select whether I _{cell_p} 314 Cells and / or I _{cell_n} 316 are connected to the outputs.

3c shows an exemplary circuit diagram of a multi-bit differential DAC (for example, the digital-to-analog conversion circuit 100 ) by a monotonous ADC (e.g. flash ADC) is driven, e.g. driven by a thermometer code type ADC. 3c can show an example of the circuit diagram for a 4-bit DAC for all possible input code combinations. In the first column 320 the input code is shown. The columns 2nd to 16 322 show the individual input signal components for the DAC cells 1 to 15 . The last column 324 shows the sum of the addition of the signal components for DAC cells 1 to 15 . For the maximum code of 15 (designated by reference numerals 326 ) all positive current sources are connected to the positive output. The sum of the currents is 15 . For a code of 14 (designated by reference numerals 328 ) are only 14 positive power sources and 1 negative power source connected to the positive output. Therefore, one of the positive currents is compensated by a negative current, which too 13 effective positive currents at the output leads, and so on. For a given digital input signal, the selected DAC cells can always be the same, ie only dependent on the digital code. Regardless of the input code, (all) DAC cells can be connected and can add noise to the output.

To avoid this, a dumping process, as in 3d shown can be used. 3d shows a simplified schematic diagram of a multi-bit differential DAC with dumping circuitry. The output signals I _p 330 and In 332 of (all) of the disks can be connected. Depending on the digital input code of the DAC will a certain number of I _{cell_p} 334 Cells and I _{cell_n} 336 Cells with positive output I _p 330 and the negative outcome I _n 332 connected. The switches 338 can be used to select whether I _{cell_p} 334 Cells and / or I _{cell_n} 336 are connected to the outputs. Here cells from which currents are compensated are separated in pairs from the DAC output nodes and dumped to a common mode voltage. In this way, the current sources that contribute to the output current can produce noise at the output.

The corresponding circuit diagram is in 3e shown. 3e shows an exemplary dumping circuit diagram of a multi-bit differential DAC by a monotonous ADC (e.g. flash ADC) is driven, e.g. driven by a thermometer code type ADC. In the first column 340 the input code is shown. The columns 2nd to 16 342 show the individual input signal components for the DAC cells 1 to 15 . The last column 344 shows the sum of the addition of the signal components for DAC cells 1 to 15 . For the maximum code of 15 (as with reference numerals 346 all positive current sources can be connected to the positive output. The sum of the currents is 15 . For a code of 14 (as with reference numerals 348 may be just 13 positive current sources connected to the positive output. A positive and a negative power source (shown in the columns 2nd and 16 ) can be dumped. The resulting output current is still 13 , as with the conventional circuit diagram. Dumping can be done by pairwise comparison of fixed cell pairs [ Cell1 , Cell15 ], [ Cell2 , Cell1l4 ], ...., [ Cell7 , Cell9 ] be performed. If these cells drive the opposite current, they can be dumped. In the example in 3e 7 comparisons may be necessary.

In at least some examples VCO (Voltage-Controlled Oscillators) -based quantizers (e.g. the quantizer 30th , which is based on a voltage controlled oscillator) can be used in multi-bit sigma-delta modulators, since this can allow an additional order of noise shaping, which can increase the resolution of the modulator. The output format of the VCO quantizer-based ADC (eg the thermometer-coded input signal) can also have thermometer codes, but the thermometer code may not have a fixed starting point. The starting point can depend on the previous starting value.

For a given digital input signal, the DAC cells selected may not always be the same and the known dumping scheme may not work.

At least some examples can use knowledge of signal properties of the VCO-based ADC output code to combine this information and create a dumping scheme that fits this code. This can enable the DAC noise reduction of the dumping concept to be used in combination with VCO-based ADCs.

4a Fig. 12 may show a conventional circuit diagram of a multi-bit differential DAC driven by a VCO-type ADC. 4a Fig. 4 may show an example of the circuit diagram for a 4-bit multi-bit differential digital-to-analog converter driven by an analog-to-digital converter of the type one voltage controlled oscillator for all possible input code combinations. In the first column 400 the input code is shown. The columns 2nd to 16 402 show the individual input signal components for the DAC cells 1 to 15 . The last column 404 shows the sum of the addition of the signal components for the DAC cells 1 to 15 . For the maximum code of 15 (Reference number 406 ) all positive current sources are connected to the positive output. The sum of the currents is 15 . For a code of 14 (Reference number 408 ) are only 14 positive power sources and 1 negative power source connected to the positive output. Therefore 1 of positive currents compensated for by a negative current, leading to only 13 effective currents at the output leads, and so on.

In contrast to 3c Where the selected DAC cells were identical for a given input code, only the number of selected DAC cells may now be identical, but the position of the cells may depend on the last input code. The connected DAC cells can start at the next position compared to the previously selected cells. This pointer can rotate down from celll5 to celll in this example and continue from cell15, and so on. The example shows an example of selected cells to decrease the DAC input code from 15 on 0 .

Fortunately, the "ones" and the "minus ones" in this representation are still consecutive when you assume a pointer rotation of Cell15 to Cell0 going out. This property can be used for the efficient generation of dumping codes for this signal representation.

4b shows an exemplary dumping circuit diagram of a multi-bit differential DAC, which by a VCO-type ADC (eg the delta-sigma modulator 1000 ) is driven. The circuit diagram of at least some examples can be found in 4b be shown. In the first column 410 the input code is shown. The columns 2nd to 16 412 show the individual input signal components for the DAC cells 1 to 15 . The last column 414 shows the sum of the addition of the signal components for DAC cells 1 to 15 .

• Wenn sich Celll und Cell9 aufheben ((Cell1=1 Cell9=-1) ODER (Cell1=-1 Cell9=1))) wird Cell1 gedumpt.
• Wenn sich Cell2 und Cell10 aufheben ((Cell2=1 Cell10=-1) ODER (Cell2=-1 Cell10=1))) wird Cell2 gedumpt. ...
• Wenn sich Cell7 und Celll5 aufheben ((Cell7=1 Cell15=-1) ODER (Cell7=-1 Cell15=1)) ) wird Cell7 gedumpt.
• Wenn sich Cell8 und Cell1 aufheben ((Cell8=1 Cell1 =-1) ODER (Cell8=-1 Cell1=1))) wird Cell8 gedumpt. ...
• Wenn sich Celll5 und Cell8 aufheben ((Cell15=1 Cel18=-1) ODER (Cell15=-1 Cell8=1)) ) wird Cell15 gedumpt.

In the example, every time 15 Operations are performed (e.g. by the conversion circuitry 10th ) to find out which of the cells can be dumped. The logical operation of at least some examples is the following:

• If Celll and Cell9 cancel ((Cell1 = 1 Cell9 = -1) OR (Cell1 = -1 Cell9 = 1))) Cell1 dumped.
• If Cell2 and Cell10 cancel ((Cell2 = 1 Cell10 = -1) OR (Cell2 = -1 Cell10 = 1))) Cell2 dumped. ...
• If Cell7 and Celll5 cancel ((Cell7 = 1 Cell15 = -1) OR (Cell7 = -1 Cell15 = 1))) Cell7 dumped.
• If Cell8 and Cell1 cancel ((Cell8 = 1 Cell1 = -1) OR (Cell8 = -1 Cell1 = 1))) Cell8 dumped. ...
• If Celll5 and Cell8 cancel ((Cell15 = 1 Cel18 = -1) OR (Cell15 = -1 Cell8 = 1))) Cell15 dumped.

Dumping can be done by pair-wise comparison (e.g. the majority of pair-wise comparisons) of fixed cell pairs (e.g. the first and second binary values) with a constant offset (e.g. the offset between the first binary value and the second binary value) by fast XOR logic gates can be realized.

• Wenn sich Cell1 und Cell9 aufheben ((Cell1=1 Cell9=-1) ODER (Cell1=-1 Cell9=1)) ) werden Cell1 und Cell9 gedumpt.
• Wenn sich Cell2 und Cell10 aufheben ((Cell2=1 Cell10=-1) ODER (Cell2=-1 Cell10=1)) ) werden Cell2 und Cell10 gedumpt. ...
• Wenn sich Cell8 und Cell16 aufheben ((Cell8=1 Cell16=-1) ODER (Cell8=-l Cell16=1)) ) werden Cell8 und Cell16 gedumpt.

In the event that the DAC is based ADC If the number of cells is even, the logic can be further simplified. In this case, two DAC cells can be dumped for each XOR operation. For example, for a 16 cell DAC, this can lead to the following logic:

• If Cell1 and Cell9 cancel ((Cell1 = 1 Cell9 = -1) OR (Cell1 = -1 Cell9 = 1))) Cell1 and Cell9 dumped.
• If Cell2 and Cell10 cancel ((Cell2 = 1 Cell10 = -1) OR (Cell2 = -1 Cell10 = 1))) Cell2 and Cell10 dumped. ...
• If Cell8 and Cell16 cancel ((Cell8 = 1 Cell16 = -1) OR (Cell8 = -l Cell16 = 1))) Cell8 and Cell16 dumped.

In the example, every time 8th Operations are performed.

Further details and aspects of the examples are provided in connection with the proposed concept or one or more preceding ones (e.g. 1a to 2 B ) mentioned examples mentioned. The examples may have one or more additional optional features that correspond to one or more aspects of the proposed concept or one or more examples described above or below.

The aspects and features mentioned and described together with one or more of the previously detailed examples and figures can also be combined with one or more of the other examples to replace a same feature of the other example or to change the feature into the other Introduce example in addition.

Example 1 relates to conversion circuitry 10th for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values, the output signal being effective (ie suitable) for n digital-to-analog converter units 20th a digital-to-analog conversion circuit 100 , wherein the conversion circuitry 10th is configured to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, an offset between a first binary value and a second binary value for the plurality of pairwise comparisons based on the logical sequence of n binary values.

ist.In Example 2, the subject matter of Example 1 or any of the examples described herein may further include that the offset between the first binary value and the second binary value is the ceiling function $\frac{n}{\mathrm{2nd}}$

is.

In Example 3, the subject matter according to any of the preceding examples or any of the examples described herein may further include n being an odd number, the plurality of paired comparisons corresponding to n paired comparisons, the n paired comparisons being made in parallel.

ist.In example 4, the subject matter of example 2 or any of the examples described herein may further include n being an even number and the offset between the first binary value and the second binary value $\frac{n}{\mathrm{2nd}}$

is.

paarweisen Vergleichen entspricht, wobei die $\frac{n}{2}$

paarweisen Vergleiche parallel durchgeführt werden.In Example 5, the subject matter of Example 4 or any of the examples described herein may further include the plurality of pairwise comparisons $\frac{n}{\mathrm{2nd}}$

matches in pairs, with the $\frac{n}{\mathrm{2nd}}$

pairwise comparisons are carried out in parallel.

In Example 6, the article according to any one of Examples 1 to 5 or any of the examples described herein may further include the n ternary values corresponding to a positive value, a negative value, and a neutral value.

In Example 7, the subject matter of Example 6 or any of the examples described herein may further include that the n binary values are represented by a first value and a second value, with the conversion circuitry 10th is configured to determine whether the first binary value and the second binary value are unequal values, the conversion circuitry 10th is configured to generate a neutral value for the ternary value of the n ternary values, corresponding to the first binary value or the second binary value, if the first binary value and the second binary value are unequal values.

ist, wobei $\frac{n}{2}$

paarweise Vergleiche durchgeführt werden, wobei die Umwandlungsschaltungsanordnung 10 ausgebildet ist, um einen neutralen Wert für den ternären Wert der n ternären Werte, entsprechend dem ersten binären Wert und dem zweiten binären Wert, zu erzeugen, falls der erste binäre Wert und der zweite binäre Wert ungleiche Werte sind.In Example 8, the subject matter of Example 7 or any of the examples described herein may further include n being an even number and the offset between the first binary value and the second binary value $\frac{n}{\mathrm{2nd}}$

is where $\frac{n}{\mathrm{2nd}}$

pairwise comparisons are made using the conversion circuitry 10th is configured to generate a neutral value for the ternary value of the n ternary values, corresponding to the first binary value and the second binary value, if the first binary value and the second binary value are unequal values.

ist, wobei die Mehrzahl von paarweisen Vergleichen n paarweisen Vergleichen entspricht, wobei die Umwandlungsschaltungsanordnung 10 ausgebildet ist, um einen neutralen Wert für den ternären Wert der n ternären Werte, entsprechend entweder dem ersten binären Wert oder dem zweiten binären Wert, zu erzeugen, falls der erste binäre Wert und der zweite binäre Wert ungleiche Werte sind.In Example 9, the article of Example 7 or any of the examples described herein may further include n being an odd number, and wherein the offset between the first binary value and the second binary value is the ceiling function of $\frac{n}{\mathrm{2nd}}$

where the plurality of paired comparisons correspond to n paired comparisons, the conversion circuitry 10th is configured to generate a neutral value for the ternary value of the n ternary values, corresponding to either the first binary value or the second binary value, if the first binary value and the second binary value are unequal values.

In Example 10, the subject matter of any one of Examples 1 through 9 or any of the examples described herein may further include the thermometer encoded input signal being a thermometer encoded input signal having a variable starting position of the thermometer code.

In Example 11, the subject matter of any one of Examples 1 through 10, or any of the examples described herein, may further include the offset between the first binary value and the second binary value at the end of the logical sequence of n binary values.

In Example 12, the subject matter of any one of Examples 1 through 11 or any of the examples described herein may further include the conversion circuitry 10th one or more entrances 12 which are designed to receive the input signal from a quantizer, which is based on a voltage-controlled oscillator.

In Example 13, the subject matter according to any one of Examples 1 to 12 or any of the examples described herein may further include the conversion circuitry 10th one or more outputs 14 comprises, which are designed to the output signal of the n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 to provide.

In Example 14, the subject matter of any of Examples 1 to 13 or any of the examples described herein may further include that the output signal be effective / suitable for n digital-to-analog converter units 20th a digital-to-analog conversion circuit 100 of a delta sigma modulator 1000 is.

Example 15 relates to a delta-sigma modulator 1000 comprising the conversion circuitry 10th according to one of Examples 1 to 14 or according to any of the examples described herein.

In Example 16, the article of Example 15 or any of the examples described herein may further include a quantizer 30th , which is based on a voltage-controlled oscillator, wherein the quantizer, which is based on a voltage-controlled oscillator, is designed to the conversion circuitry 10th to provide the input signal.

In Example 17, the article according to one of Examples 15 or 16, or any of the examples described herein, may further include a digital-to-analog conversion circuit 100 comprise, wherein the digital-to-analog conversion circuit 100 n Digital-to-analog converter units 20th comprises, the conversion circuitry 10th is formed to the output signal to the n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 to provide.

Example 18 relates to a digital-to-analog conversion circuit 100 comprising n digital-to-analog converter units 20th and the conversion circuitry 10th according to any one of Examples 1 to 15, wherein the conversion circuitry 10th is formed to the output signal of the n digital-to-analog converter units 20th the digital-to-analog conversion circuit 100 to provide.

Example 19 relates to a mobile device comprising the delta-sigma modulator 1000 according to one of Examples 15 to 17 or according to any of the examples described herein.

Example 20 relates to a communication device comprising the delta-sigma modulator 1000 according to one of Examples 15 to 17 or according to any of the examples described herein.

Example 21 relates to a base station transceiver comprising the delta sigma modulator 1000 according to one of Examples 15 to 17 or according to any of the examples described herein.

Example 22 relates to a converting agent 10th , suitable for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values, the output signal being effective for n digital-to-analog converter units 20th of a digital-to-analog conversion medium 100 , being the means to convert 10th is configured to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, an offset between a first binary value and a second binary value for the plurality of pairwise comparisons based on the logical sequence of n binary values, is the same.

ist.In example 23, the subject matter of example 22 or any of the examples described herein may further include that the offset between the first binary value and the second binary value is the ceiling function of $\frac{n}{\mathrm{2nd}}$

is.

In Example 24, the subject matter of either of Examples 22 or 23, or any of the examples described herein, may further include n being an odd number, the plurality of paired comparisons corresponding to n paired comparisons, the n paired comparisons being made in parallel.

ist. In Example 25, the subject matter of Example 24 or any of the examples described herein may further include n being an even number and the offset between the first binary value and the second binary value $\frac{n}{\mathrm{2nd}}$

is.

paarweisen Vergleichen entspricht, wobei die $\frac{n}{2}$

paarweisen Vergleiche parallel durchgeführt werden.In example 26, the subject matter of example 25 or any of the examples described herein may further include the plurality of paired comparisons $\frac{n}{\mathrm{2nd}}$

matches in pairs, with the $\frac{n}{\mathrm{2nd}}$

pairwise comparisons are carried out in parallel.

In Example 27, the article according to any one of Examples 22 to 26 or any of the examples described herein may further include the n ternary values corresponding to a positive value, a negative value, and a neutral value.

In example 28, the article of example 27 or any of the examples described herein may further include the n binary values being represented by a first value and a second value, the means for converting 10th is configured to determine whether the first binary value and the second binary value are unequal values, the means for converting 10th is configured to generate a neutral value for the ternary value of the n ternary values, corresponding to the first binary value or the second binary value, if the first binary value and the second binary value are unequal values.

ist, wobei $\frac{n}{2}$

paarweise Vergleiche durchgeführt werden, wobei das Mittel zum Umwandeln 10 ausgebildet ist zum Erzeugen eines neutralen Werts für den ternären Wert der n ternären Werte, entsprechend dem ersten binären Wert und dem zweiten binären Wert, falls der erste binäre Wert und der zweite binäre Wert ungleiche Werte sind.In example 29, the subject matter of example 28 or any of the examples described herein may further include n being an even number and the offset between the first binary value and the second binary value $\frac{n}{\mathrm{2nd}}$

is where $\frac{n}{\mathrm{2nd}}$

pairwise comparisons are made using the means to convert 10th is configured to generate a neutral value for the ternary value of the n ternary values, corresponding to the first binary value and the second binary value, if the first binary value and the second binary value are unequal values.

ist, wobei die Mehrzahl von paarweisen Vergleichen n paarweisen Vergleichen entspricht, wobei das Mittel zum Umwandeln (10) ausgebildet ist zum Erzeugen eines neutralen Werts für den ternären Wert der n ternären Werte, entsprechend entweder dem ersten binären Wert oder dem zweiten binären Wert, falls der erste binäre Wert und der zweite binäre Wert ungleiche Werte sind.In example 30, the article of example 28 or any of the examples described herein may further include n being an odd number, and wherein the offset between the first binary value and the second binary value is the ceiling function of $\frac{n}{\mathrm{2nd}}$

where the plurality of pair-wise comparisons correspond to n pair-wise comparisons, the means for converting ( 10th ) is configured to generate a neutral value for the ternary value of the n ternary values, corresponding to either the first binary value or the second binary value, if the first binary value and the second binary value are unequal values.

In Example 31, the article according to any one of Examples 22 to 30 or any of the examples described herein may further include the thermometer encoded input signal being a thermometer encoded input signal having a variable starting position of the thermometer code.

In Example 32, the subject matter of any one of Examples 22-31 or any of the examples described herein may further include the offset between the first binary value and the second binary value at the end of the logical sequence of n binary values.

In Example 33, the article according to any one of Examples 22 to 32 or any of the examples described herein may further comprise the agent for converting 10th one or more input means 12 which are designed to receive the input signal from a quantizer, which is based on a voltage-controlled oscillator.

In Example 34, the article according to any one of Examples 22 to 33 or any of the examples described herein may further comprise the agent for converting 10th one or more starting materials 12 comprises, which are designed to provide the output signal to the n digital-to-analog converter units 20th of the digital-to-analog conversion means 100 .

In Example 35, the subject matter of any one of Examples 22 to 34 or any of the examples described herein may further include that the output signal is effective for n digital-to-analog converter units 20th of a digital-to-analog conversion medium 100 a delta-sigma modulation means 1000 is.

Example 36 relates to a delta-sigma modulation means 1000 comprising the means for converting 10th according to one of Examples 22 to 35 or according to any of the examples described herein.

In Example 37, the article of Example 36 further includes a quantizer 30th based on a voltage controlled oscillator, the quantizing means based on a voltage controlled oscillator being configured to convert the means 10th to provide the input signal.

In Example 38, the subject matter according to either of Examples 36 or 37 further includes digital-to-analog conversion means 100 , wherein the digital-to-analog conversion means 100 n Digital-to-analog converter units 20th comprises, the means for converting 10th is formed to the output signal to the n digital-to-analog converter units 20th of the digital-to-analog conversion means 100 to provide.

Example 39 relates to a digital-to-analog conversion means 100 comprising n digital-to-analog converter units 20th and the means to convert 10th according to any one of Examples 22 to 35, wherein the converting agent 10th is formed to the output signal of the n digital-to-analog converter units 20th of the digital-to-analog conversion means 100 to provide.

Example 40 relates to a mobile device comprising the delta-sigma modulation means 1000 according to any one of Examples 36 to 38 or any of the Examples described herein.

Example 41 relates to a communication device comprising the delta-sigma modulation means 1000 according to any one of Examples 36 to 38 or any of the Examples described herein.

Example 42 relates to a base station transceiver comprising the delta-sigma modulation means 1000 according to any one of Examples 36 to 38 or any of the Examples described herein.

Example 43 relates to a conversion method suitable for converting a thermometer-coded input signal having a logical sequence of n binary values to an output signal having n ternary values, the output signal being effective for n digital-to-analog converter units 20th of a digital-to-analog conversion medium 100 wherein the conversion method comprises generating the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, an offset between a first binary value and a second binary value for the plurality of pairwise comparisons based on the logical sequence of n binary values.

ist.In example 44, the article of example 43 or any of the examples described herein may further include that the offset between the first binary value and the second binary value is the ceiling function of $\frac{n}{\mathrm{2nd}}$

is.

In Example 45, the subject matter of any of Examples 43 or 44, or any of the examples described herein, may further include n being an odd number, the plurality of paired comparisons corresponding to n paired comparisons, the n paired comparisons being made in parallel.

ist.In example 46, the subject matter of example 45 or any of the examples described herein may further include n being an even number and the offset between the first binary value and the second binary value $\frac{n}{\mathrm{2nd}}$

is.

paarweisen Vergleichen entspricht, wobei die $\frac{n}{2}$

paarweisen Vergleiche parallel durchgeführt werden.In Example 47, the subject matter of Example 46 or any of the examples described herein may further include the plurality of paired comparisons $\frac{n}{\mathrm{2nd}}$

matches in pairs, with the $\frac{n}{\mathrm{2nd}}$

pairwise comparisons are carried out in parallel.

In Example 48, the article according to any of Examples 43 to 47 or any of the examples described herein may further include the n ternary values corresponding to a positive value, a negative value, and a neutral value.

In Example 49, the subject matter of Example 48 or any of the examples described herein may further include that the n binary values are represented by a first value and a second value, the conversion method comprising determining 122 whether the first binary value and the second binary value are unequal values, the conversion method includes generating 124 a neutral value for the ternary value of the n ternary values, corresponding to the first binary value or the second binary value if the first binary value and the second binary value are unequal values.

ist, wobei $\frac{n}{2}$

paarweise Vergleiche durchgeführt werden, das Umwandlungsverfahren umfassend ein Erzeugen 124 eines neutralen Werts für den ternären Wert der n ternären Werte, entsprechend dem ersten binären Wert und dem zweiten binären Wert, falls der erste binäre Wert und der zweite binäre Wert ungleiche Werte sind.In Example 50, the article can be according to Example 7 or any of the present described examples further include that n is an even number, and wherein the offset between the first binary value and the second binary value $\frac{n}{\mathrm{2nd}}$

is where $\frac{n}{\mathrm{2nd}}$

comparisons are made in pairs, the conversion process comprising generating 124 a neutral value for the ternary value of the n ternary values, corresponding to the first binary value and the second binary value if the first binary value and the second binary value are unequal values.

ist, wobei die Mehrzahl von paarweisen Vergleichen n paarweisen Vergleichen entspricht, das Umwandlungsverfahren umfassend ein Erzeugen 124 eines neutralen Werts für den ternären Wert der n ternären Werte, entsprechend entweder dem ersten binären Wert oder dem zweiten binären Wert, falls der erste binäre Wert und der zweite binäre Wert ungleiche Werte sind.In Example 51, the article of Example 48 or any of the examples described herein may further include n being an odd number, and wherein the offset between the first binary value and the second binary value is the ceiling function of $\frac{n}{\mathrm{2nd}}$

where the plurality of pairwise comparisons correspond to n pairwise comparisons, the conversion method comprising generating 124 a neutral value for the ternary value of the n ternary values, corresponding to either the first binary value or the second binary value if the first binary value and the second binary value are unequal values.

In Example 52, the article according to any of Examples 43 to 51 or any of the examples described herein may further include the thermometer encoded input signal being a thermometer encoded input signal having a variable starting position of the thermometer code.

In Example 53, the subject matter of any of Examples 43 to 52 or any of the examples described herein may further include the offset between the first binary value and the second binary value at the end of the logical sequence of n binary values.

In Example 54, the article according to any one of Examples 43 to 53 or any of the examples described herein may further include the conversion process receiving 110 of the input signal from a quantization means based on a voltage controlled oscillator.

In Example 55, the article according to any one of Examples 43 to 54 or any of the examples described herein may further include that the conversion process provide 130 of the output signal to the n digital-to-analog converter units 20th of the digital-to-analog conversion means 100 includes.

In Example 56, the subject matter according to any of Examples 43 to 55 or any of the examples described herein may further include that the output signal is effective for n digital-to-analog converter units 20th of a digital-to-analog conversion medium 100 a delta-sigma modulation means 1000 is.

Examples may also be, or refer to, a computer program having program code for executing one or more of the preceding methods when the computer program is executed on a computer or processor. Steps, operations, or processes of various methods described above can be performed by programmed computers or processors. Examples may also cover program storage devices, such as digital data storage media, that are machine, processor, or computer readable and encode machine-executable, processor-executable, or computer-executable programs of instructions. The instructions perform or cause some or all of the steps in the previously described procedures. The program storage devices may e.g. B. digital storage, magnetic storage media such as magnetic disks and tapes, hard drives or optically readable digital data storage media include or be. Other examples can also include computers, processors or control units which are programmed to carry out the steps of the methods described above, or (field) programmable logic arrays ((F) PLAs; (Field) Programmable Logic Arrays) or (field) programmable Gate Arrays ((F) PGA; (Field) Programmable Gate Arrays) that are programmed to perform the steps of the previously described methods.

The description and drawings only illustrate the principles of the disclosure. Furthermore, all of the examples listed here are intended to serve expressly for illustrative purposes only in order to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor (s) for the further development of the technology. All statements here about principles, aspects and examples of the disclosure, as well as concrete examples thereof, are intended to include their equivalents.

A function block called "means for ..." that performs a specific function can refer to a circuit that is designed to perform a specific function. Thus, a "means for something" can be implemented as a "means trained for or suitable for something", e.g. B. a device or a circuit which is designed for or suitable for the respective task.

Functions of various elements shown in the figures, including each function block referred to as "means", "means for providing a signal", "means for generating a signal", etc., may be in the form of dedicated hardware, e.g. B "of a signal provider", "a signal processing unit", "a processor", "a controller" etc. as well as hardware capable of executing software in connection with associated software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some or all of which can be shared. However, the term “processor” or “controller” is by no means limited to hardware that is capable of executing software only, but can be digital signal processor (DSP) hardware, network processor, application-specific integrated circuit (ASIC) Field programmable gate array (FPGA), read-only memory (ROM) for storing software, random access memory (RAM) and non-volatile memory (storage). Other hardware, conventional and / or custom, can also be included.

For example, a block diagram may represent a detailed circuit diagram that implements the principles of the disclosure. Similarly, a flowchart, flowchart, state transition diagram, pseudocode, and the like may represent various processes, operations, or steps that are, for example, substantially represented in computer readable medium and thus performed by a computer or processor, whether or not such Computer or processor is shown explicitly. Methods disclosed in the description or in the claims can be implemented by an apparatus having means for performing each of the respective steps of these methods.

It is understood that the disclosure of several acts, processes, operations, steps or functions disclosed in the description or claims should not be interpreted as being in the specific order unless this is explicitly or implicitly otherwise, e.g. B. for technical reasons. Therefore, by disclosing multiple steps or functions, these are not limited to any particular order unless these steps or functions are not interchangeable for technical reasons. Furthermore, in some examples, a single action, function, process, operation, or step may include and / or be broken down into multiple sub-actions, functions, processes, operations, or steps. Such sub-steps can be included and can be part of the disclosure of this single step, unless they are explicitly excluded.

Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it should be noted that although a dependent claim may refer to a particular combination in the claims with one or more other claims, other examples may also be a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are explicitly suggested here unless it is stated that a particular combination is not intended. Features of a claim are also intended to be included for any other independent claim, even if that claim is not directly dependent on the independent claim.

Claims (23)

A conversion circuit arrangement (10) for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values, the output signal being effective for n digital-to-analog converter units (20) of a digital-to-digital Analog conversion circuit (100), wherein the conversion circuitry (10) is configured to generate the output signal based on a plurality of pair-wise comparisons between first binary values and second binary values of the n binary values, wherein an offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values. The conversion circuitry (10) according to Claim 1 , the offset between the first binary value and the second binary value being the ceiling function of $\frac{n}{\mathrm{2nd}}$

is. The conversion circuitry (10) according to any one of the preceding claims, wherein n is an odd number, wherein the plurality of pairwise comparisons correspond to n pairwise comparisons, the n pairwise comparisons being carried out in parallel. The conversion circuitry (10) according to Claim 2 , where n is an even number, and where the offset between the first binary value and the second binary $\frac{n}{\mathrm{2nd}}$

is. The conversion circuitry (10) according to Claim 4 , with the majority of pairwise comparisons $\frac{n}{\mathrm{2nd}}$

matches in pairs, with the $\frac{n}{\mathrm{2nd}}$

pairwise comparisons are carried out in parallel. The conversion circuitry (10) according to one of the Claims 1 to 5 , where the n ternary values correspond to a positive value, a negative value and a neutral value. The conversion circuitry (10) according to Claim 6 , wherein the n binary values are represented by a first value and a second value, the conversion circuit arrangement (10) being designed to determine whether the first binary value and the second binary value are unequal values, the conversion circuit arrangement (10) is configured to generate a neutral value for the ternary value of the n ternary values, corresponding to the first binary value or the second binary value, if the first binary value and the second binary value are unequal values. The conversion circuitry (10) according to Claim 7 , where n is an even number, and where the offset between the first binary value and the second binary value $\frac{n}{\mathrm{2nd}}$

is where $\frac{n}{\mathrm{2nd}}$

comparisons are carried out in pairs, the conversion circuitry (10) being designed to generate a neutral value for the ternary value of the n ternary values, corresponding to the first binary value and the second binary value, if the first binary value and the second binary value Value are unequal values. The conversion circuitry (10) according to Claim 7 , where n is an odd number, and where the offset between the first binary value and the second binary value is the ceiling function of $\frac{n}{\mathrm{2nd}}$

wherein the plurality of pair-wise comparisons correspond to n pair-wise comparisons, the conversion circuitry (10) being designed to generate a neutral value for the ternary value of the n ternary values, corresponding to either the first binary value or the second binary value, if the first binary value and the second binary value are unequal values. The conversion circuitry (10) according to one of the Claims 1 to 9 , wherein the thermometer-coded input signal is a thermometer-coded input signal with a variable starting position of the thermometer code. The conversion circuitry (10) according to one of the Claims 1 to 10th , the offset between the first binary value and the second binary value at the end of the logical sequence breaking n binary values. The conversion circuitry (10) according to one of the Claims 1 to 11 wherein the conversion circuitry (10) includes one or more inputs (12) configured to receive the input signal from a quantizer based on a voltage controlled oscillator. The conversion circuitry (10) according to one of the Claims 1 to 12 , wherein the conversion circuit arrangement (10) comprises one or more outputs (14) which are designed to provide the output signal to the n digital-to-analog converter units (20) of the digital-to-analog conversion circuit (100). The conversion circuitry (10) according to one of the Claims 1 to 13 , wherein the output signal for n digital-to-analog converter units (20) of a digital-to-analog conversion circuit (100) of a delta-sigma modulator (1000) is effective. A delta sigma modulator (1000) comprising the conversion circuitry (10) according to one of the Claims 1 to 14 . The delta sigma modulator (1000) according to Claim 15 , further comprising a quantizer (30) based on a voltage controlled oscillator, the quantizer based on a voltage controlled oscillator being configured to provide the input signal to the conversion circuitry (10). The delta-sigma modulator (1000) according to one of the Claims 15 or 16 , further comprising a digital-to-analog conversion circuit (100), the digital-to-analog conversion circuit (100) comprising n digital-to-analog converter units (20), wherein the conversion circuit arrangement (10) is designed to provide the output signal to the n digital-to-analog converter units (20) of the digital-to-analog conversion circuit (100). A digital-to-analog conversion circuit (100) comprising n digital-to-analog conversion units (20) and the conversion circuit arrangement (10) according to one of the Claims 1 to 14 , wherein the conversion circuit arrangement (10) is designed to provide the output signal to the n digital-to-analog converter units (20) of the digital-to-analog conversion circuit (100). A mobile device comprising the delta sigma modulator (1000) according to one of the Claims 15 to 17th . A communication device comprising the delta sigma modulator (1000) according to one of the Claims 15 to 17th . A base station transceiver comprising the delta sigma modulator (1000) according to one of the Claims 15 to 17th . A converting means (10) adapted to convert a thermometer-coded input signal having a logical sequence of n binary values to an output signal having n ternary values, the output signal being effective for n digital-to-analog converter units (20) of a digital -to-analog conversion means (100), the means for converting (10) being designed to generate the output signal based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, wherein an offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values. A conversion method suitable for converting a thermometer-coded input signal with a logical sequence of n binary values into an output signal with n ternary values, the output signal being effective for n digital-to-analog converter units (20) of a digital-to-analog Conversion means (100), wherein the conversion method comprises generating the output signal (120) based on a plurality of pairwise comparisons between first binary values and second binary values of the n binary values, wherein an offset between a first binary value and a second binary value is the same for the plurality of pairwise comparisons based on the logical sequence of n binary values.

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