DE102018125786A1 - Encrypted system memory management - Google Patents

Abstract

In one example, an encrypted memory management system includes a processor for storing a first MAC based on data stored in system memory in response to a write to system memory. The processor may also detect a read corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and the second MAC with a correction operation recalculating, wherein the correction process includes an XOR operation based on the data retrieved from the system memory and a replacement value for a system memory device. Further, the processor may decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC and transmit the decrypted data to a cache, thereby correcting memory errors.

Description

Cross-reference to related applications

The present application is a continuation-in-part of US patent application Ser. No. 14 / 998,054 entitled "Memory Integrity with Error Detection and Correction" filed on December 24, 2015, the contents of which are incorporated by reference as if fully set forth herein.

Technical area

This disclosure generally relates to managing data stored in a memory, and more particularly, but not exclusively, managing encrypted data stored in memory.

background

Computers can store data in a hierarchical manner, transferring data between a larger storage device and smaller cache memory devices. In some examples, the data may be stored in an encrypted format in storage devices and non-encrypted in smaller on-chip cache devices. In some examples, Error Correction Code (ECC) memory techniques may be used to detect errors in the data stored in memory devices. The ECC storage techniques may be deterministic and reversible, but not cryptographic.

list of figures

• 1 veranschaulicht ein Blockdiagramm einer Rechenvorrichtung, die verschlüsselte Daten verwalten kann;
• 2 veranschaulicht ein Blockdiagramm eines Dual-In-Line-Speichermoduls;
• 3 veranschaulicht ein Prozessflussdiagramm zum Verwalten verschlüsselter Daten;
• 4 veranschaulicht ein Prozessflussdiagramm zum Verwalten verschlüsselter Daten;
• 5A und 5B veranschaulichen Beispiele für Datenstrukturen zum Speichern verschlüsselter Daten;
• 6 ist ein Prozessflussdiagramm zum Verwalten verschlüsselter Daten basierend auf einem Entropieniveau der Daten;
• 7 ist eine Beispiel-Pipeline zum Verwalten verschlüsselter Daten;
• 8 ist ein Prozessflussdiagramm zum Verwalten verschlüsselter Daten;
• 9 ist ein Prozessflussdiagramm zum Verwalten verschlüsselter Daten basierend auf einem Korrekturwert als ein zweiter MAC-Wert;
• 10A und 10B sind Beispiele für Techniken zum Verwalten verschlüsselter Daten mit einem Blockkorrekturwert als ein zweiter MAC; und
• 11 ist ein Beispiel für ein greifbares nichtflüchtiges computerlesbares Medium zum Verwalten verschlüsselter Daten.

The following detailed description may be better understood with reference to the accompanying drawings, which include specific examples of numerous features of the disclosed subject matter.

• 1 Figure 12 illustrates a block diagram of a computing device that can manage encrypted data;
• 2 illustrates a block diagram of a dual-in-line memory module;
• 3 illustrates a process flow diagram for managing encrypted data;
• 4 illustrates a process flow diagram for managing encrypted data;
• 5A and 5B illustrate examples of data structures for storing encrypted data;
• 6 FIG. 10 is a process flow diagram for managing encrypted data based on an entropy level of the data; FIG.
• 7 is an example pipeline for managing encrypted data;
• 8th is a process flow diagram for managing encrypted data;
• 9 FIG. 10 is a process flow diagram for managing encrypted data based on a correction value as a second MAC value; FIG.
• 10A and 10B Examples of techniques for managing encrypted data having a block correction value as a second MAC; and
• 11 is an example of a tangible non-transitory computer-readable medium for managing encrypted data.

In some cases, the same numbers are used throughout the disclosure and the drawings to refer to like components and features. Numbers in the 100 series refer to features originally in 1 were found; Numbers in the 200 series refer to features originally in 2 were found; and so on.

Description of the embodiments

Error Correcting Code (ECC) memory may include using additional integrated circuits or physical memory chips or chips to correct erroneous data, which may increase system cost. In addition, ECC storage techniques may not be cryptographic. Techniques described herein provide cryptographically secure ECC techniques while maintaining error correction capabilities to provide high performance memory that can mitigate random bit errors, memory-based integrated circuit errors, and harmful adversaries. A memory-based integrated circuit, also referred to herein as a device, may include any suitable hardware or logic chip for storing a predetermined number of bits in a memory device. The techniques described herein are cryptographically secure and perform the task of both error correction and memory integrity, including Multi-Key Total Memory Encryption (MKTME) support, repetition prevention, and cryptographically strong data corruption detection even by a physical adversary , In addition, the techniques described herein may not require the use of additional ECC memory and accordingly reduce memory costs.

The techniques described herein involve the use of a cryptographically strong message authentication code (MAC) or hash message authentication code (HMAC) to replace ECC detection mechanisms with a statistical trial-and-error approach. In some examples, device correction codes are unrolled to test one device of memory at a time versus the secure hash, which can identify the memory device that contains errors and whose bits are flipped (up to a completely failed device). Unrolling, as referred to herein, may include performing an XOR operation or any other suitable logic operation on data stored in integrated circuits in a memory device. In some examples, heuristics, when combined with Total Memory Encryption (TME), can help identify potentially faulty plaintext blocks assuming their entropy is given, because errors that Change the secret code text stored in the memory, lead to random plain texts when decrypted. Alternatively, compression may be used to encrypt detection codes (eg, Reed-Solomon) within data cache lines, to identify / locate bad memory locations, and to reduce the cost / amount of physical memory used to store them Codes is needed.

In some embodiments, a computing device may store a first message authentication code (MAC) based on system data stored in system memory in response to a write to system memory. A MAC, as referred to herein, may include any suitable message authentication code involving a cryptographic hash function and a secret cryptographic key. In some embodiments, the computing device may also detect a read corresponding to the data stored in the system memory and calculate a second MAC based on the data stored in the system memory. The computing device may also determine that the second MAC does not match the first stored MAC and then recalculate the second MAC to a correction process, the correction process performing an XOR operation based on the data stored in the system memory and a system memory device replacement value includes. Further, the computing device may decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC and transmit the decrypted data to a cache.

In some embodiments, a computing device may also store an encrypted first block correction value based on plaintext data to be stored in system memory in response to a write to system memory. In addition, the computing device may detect a read corresponding to the data stored in the system memory and calculate a second block correction value based on the data stored in the system memory, wherein the second block correction value is calculated based on an XOR operation that is the plaintext of the System memory includes stored encrypted data. In some embodiments, the computing device may determine that the second block correction value does not match a decrypted first block correction value and then recalculate the second block correction value to a correction operation, the correction process performing an XOR operation based on data decrypted in the system memory and a replacement value for the data System memory comprises a device. Furthermore, the computing device may store the data stored in the system memory in response to the Detecting that the recalculated second block correction value matches the first block correction value, decrypts, and transmits the decrypted data to a cache.

The techniques described herein may prevent reconstruction of data stored in the memory to provide correct ECC code and provide memory protection against random errors and failures. In addition, the techniques described herein make it possible to detect attempts to corrupt a memory by injecting data from one tenant to another tenant in a cross-domain domain attack or by flipping physical bits in a rowhammer attack or other physical manipulation of a storage device. Because the techniques described herein are cryptographically nondeterministic to an adversary, no deterministic manipulation of the memory data by an adversary is possible, such as for detection.

Reference in the specification to "one embodiment" of the disclosed subject matter means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosed subject matter , Accordingly, the phrase "in one embodiment" may appear at different locations throughout the description, but the phrase may not necessarily refer to the same embodiment.

1 Fig. 10 is a block diagram of an example of a host computing device that can manage encrypted data. The host computing device 100 may be, for example, a mobile phone, a laptop computer, a desktop computer or a tablet computer. The host computing device 100 can be a processor 102 which is adapted to execute stored instructions and a memory device 104 that stores commands by the processor 102 executable include. The processor 102 may be a single-core processor, a multi-core processor, a compute cluster, or any number of other configurations. The storage device 104 may include random access memory, read only memory, flash memory, or any other suitable memory system. The commands by the processor 102 can be used to implement a method that can transmit encrypted image data.

The processor 102 can also through the system interconnect 106 (eg PCI®, PCI-Express®, NuBus, etc.) with a display interface 108 linked, which is adapted to the host computing device 100 with a display device 110 connect to. The display device 110 may include a display screen that includes a built-in component of the host computing device 100 is. The display device 110 may also include, but is not limited to, a computer monitor, television, or projector connected externally to the host computing device 100 connected is. The display device 110 may include light emitting diodes (LEDs) and micro LEDs, among others.

In addition, a network interface controller (also referred to herein as a NIC (Network Interface Controller)) may be used. 112 be configured to the host computing device 100 through the system interconnect 106 to connect to a network (not shown). The network (not shown) may be, inter alia, a cellular network, a wireless network, a wide area network (WAN), a local area network (LAN), or the Internet.

The processor 102 can through a system interconnect 106 with an input / output (I / O) device interface 114 which is adapted to the rake host device 100 with one or more I / O devices 116 connect to. The I / O devices 116 For example, they may include a keyboard and a pointing device, wherein the pointing device may include, but is not limited to, a touch pad or a touch screen. The I / O devices 116 can be built-in components of the host computing device 100 his or her devices may be external to the host computing device 100 are connected.

In some embodiments, the processor 102 also through the system interconnect 106 with any storage device 118 which may include a hard disk, an optical drive, a USB flash drive, a solid state drive or other nonvolatile memory, an array of drives, or any combination thereof. In some embodiments, the storage device 118 include any suitable applications and stored data.

In some embodiments, the processor 102 include any suitable number of logic modules provided by a memory controller 119 are executable. In some examples, the memory controller 119 (or a memory management unit) logic on the processor 102 Using the external system storage device 104 interacts. The memory controller 119 can with the external memory 104 for read / write operations to transmit or receive data to compute / manage the MACs, error correction codes, encryption / decryption and the like. In some examples, a MAC administrator may 120 store a first message authentication code (MAC) in system memory based on data stored in the system memory in response to a write. A MAC, as referred to herein, may include any suitable message authentication code involving a cryptographic hash function and a secret cryptographic key. In some embodiments, the MAC manager 120 also detect a read corresponding to the data stored in the system memory and calculate a second MAC based on the data stored in the system memory. The MAC administrator 120 may also determine that the second MAC does not match the first MAC, and then recalculate the second MAC to a correction process, the correction process including an XOR operation based on the data stored in the system memory and a system memory device replacement value. Furthermore, a decryption manager 122 decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC. In some embodiments, a data transmitter 124 the decrypted data to a cache 126 that is on a processor 102 or any other suitable cache or storage device. For some examples, the cache is located 126 (or a cache hierarchy) between the processor 102 and the memory controller 119 , In some embodiments, the processor may be 102 , the cache 126 and the memory controller 119 on the same physical chip / die or enclosure.

Alternatively, the MAC administrator 120 in some embodiments, storing an encrypted first correction value based on information stored in the system memory in the system memory in response to a write. In addition, the MAC administrator 120 also detect a read corresponding to the data stored in the system memory and calculate a second block correction value based on the data stored in the system memory, wherein the second block correction value calculated based on an XOR operation comprises plaintext data stored in the system memory. In some embodiments, the MAC manager 120 determining that the second block correction value does not match a decrypted first block correction value and recalculating the second block correction value with a correction process, the correction process comprising an XOR operation based on decrypted data stored in the system memory and a system memory device replacement value. Furthermore, the decryption manager 122 the data stored in the system memory is decrypted and the data transmitter is capable of decoding in response to detecting that the recalculated second block correction value matches the first block correction value 124 transfer the decrypted data to the cache.

It is understood that the block diagram 1 should not specify that the host computing device 100 all in 1 should contain components shown. Instead, the host computing device 100 less or additional components in 1 not illustrated (eg, additional memory components, embedded controllers, additional modules, additional network interfaces, etc.). Furthermore, any of the functionalities of the MAC administrator 120 , the decryption manager 122 and the data sender 124 partially or completely in hardware and / or in the processor 102 be implemented. For example, the functionality may include, but is not limited to, an application specific integrated circuit, logic implemented in an embedded controller, or one in the processor 102 implemented logic implemented. In some embodiments, the functionalities of the MAC manager 120 , the decryption manager 122 and the data sender 124 implemented with logic, the logic as referred to herein including any suitable hardware (eg, but not limited to, a processor), software (e.g., an application among others), firmware, or any suitable combination of hardware, Software and firmware may include.

2 illustrates a block diagram of a dual-in-line memory module (DIMM). In 2 can the DIMM 200 These include SIMM, SO-DIMM, NVDIMM, VLPDIMM, DDR-DIMM, DDR2-DIMM, DDR3-DIMM, DDR4-DIMM or DDR5-DIMM. The DIMM 200 may include any number of devices or integrated circuits or chips. For example, there are eight devices for storing data in two memory groups 202 and 204 of the DIMM 200 shown. In some examples, an error-related device may become 206 near the storage groups 202 and 204 can and can be the fault-related device 206 save a MAC value. In some examples, the DIMM may 200 also additional devices on a back side (not shown) of the DIMM 200 include. The back of the DIMM 200 may also include storage groups and an error related device for storing a device correction value. The fault-related device 206 and the fault-related device on the back of the DIMM 200 may provide additional memory for storing detection and correction codes.

It is understood that the block diagram 2 should not specify that the DIMM 200 all in 2 should contain components shown. Instead, the DIMM can 200 less or additional components in 2 not illustrated (eg, additional memory components, embedded controllers, additional sensors, additional interfaces, etc.).

3 illustrates a process flow diagram for managing encrypted data. This in 3 illustrated method 300 may be with any suitable computing component or device, such as the computing device 100 out 1 to be implemented.

At block 302 can be a MAC administrator 120 compute and store a first MAC based on data stored in system memory in response to a write to system memory. For example, the MAC administrator 120 detect a write to the system memory and, among other things, use any suitable cryptographic MAC function with a second key to generate a MAC based on the data stored in the memory. In some embodiments, the data stored in the memory may include any suitable secret code text encrypted using any suitable encryption technique. The result of the logic operation over blocks of the device data may be stored as a device data block correction value.

At block 304 can the MAC administrator 120 detect a read corresponding to the data stored in the system memory. For example, the MAC administrator 120 detect an attempt to execute a command based on the encrypted data stored in the system memory.

At block 306 can the MAC administrator 120 calculate a second MAC based on the encrypted data retrieved from system memory. The MAC administrator 120 can use the same MAC function used in the write as well as use the same key to produce a matching MAC.

At block 308 can the MAC administrator 120 determine that the second MAC does not match the first MAC. For example, the MAC administrator 120 as part of a write operation, detect whether bits of data stored in the memory have flipped since the data was stored in the memory. In some examples, the flipped bits in the memory may represent data that has been corrupted by a malicious attempt to manipulate the data stored in the memory.

At block 310 can the MAC administrator 120 Recalculate the second MAC with a correction process, wherein the correction process includes an XOR operation based on the device data blocks retrieved from the system memory and a system memory excluded device data block substitute value. In one example, a substitute value (also referred to herein as an unrolled correction value) may repair erroneous data stored in a device of a memory. As a simplified example, a hypothetical 16-bit cache line may consist of four 4-bit integrated circuits or device data blocks and a 4-bit MAC such as 1010 (block1), 0100 (block2), 1101 (block3), 1011 (Block4) and 0010 (MAC). The MAC value may be based on a coded secure hash of device data blocks 1 - 4 be calculated. The correction value may be a combination of the devices 1 - 4 based on a logical XOR operation, resulting in a value of 1000. The MAC value may also be included in the XOR process resulting in a 1010 Device Block Correction Value (BC). In some examples, the correction value may be used to reconstruct any of the missing device data blocks, including the MAC device with XOR operations, assuming that the other devices are error free. For example, a substitution data block may be for a faulty device 1 based on a logical XOR operation of the correction value, the MAC value and the values of device data blocks 2 - 4 be calculated. In addition, the second MAC value may be calculated based on an encoded secure hash operation that represents the replacement correction value for the device 1 with the values of the device data blocks 2 - 4 and the stored first MAC value combined. This second calculated MAC value should match the first stored MAC value if the faulty device data has been repaired by using the Substitute value were substituted. The substitute value should then be used instead of the erroneous device data block. Otherwise, the calculated second MAC value will most likely not match the first stored MAC value.

At block 312 can the decryption manager 122 decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC. At block 314 can the data transmitter 124 transmit the decrypted data to a cache.

In some embodiments, the process flow diagram is intended to be 3 do not specify that the procedures of the procedure 300 are to be executed in any particular order or that all of the procedures of the procedure 300 in any case should be included. In addition, the process can 300 include any suitable number of additional operations. For example, the techniques may be applied here to correct a block or integrated circuit of any suitable size. In some examples, there may be a trade-off between block correction value size and the number of correction attempts used to correct a defective data block. As shown below, the cache line may be represented as a set of N device data blocks B [0], ... B [N-1] of size S. In some embodiments, any suitable cryptographically secure hash function may be used as a MAC function, including, but not limited to, a SHA-3 based MAC. In some examples, a MAC function accepts any suitable secret key and a number of data blocks as input, as illustrated by equation 1 below: $$MAC=SHA3\left(ScHlüssel.B\left[0\right]\Vert ...\Vert \left[N-1\right]\right)$$

In some embodiments, the key may be selected based on metadata or key identifiers that are part of a memory address. In some examples, alternative MAC functions may include the memory address of the data line in memory as part of the hashed data. In addition, in some examples, the MAC function may be provided with any suitable alternative cryptographically secure hash function, such as, but not limited to, SHA. 1 or SHA- 2 , be calculated.

In some examples, the device block correction value (BC) may be calculated as an XOR operation: $$BC=MAC\oplus B\left[0\right]\oplus ...\oplus B\left[N-1\right]$$

In some examples, data returned from a memory read is B '[0]... B' [N-1], which may be B [0]... B [N-1] if it is there was no mistake. If a MAC does not match, a repair value (RV) may be calculated with an XOR operation in which one of the device data blocks B '[i] from the set of B' [0] to B '[N-1] is extracted from the equation is omitted: $$RV=BC\oplus MAC\oplus B\text{'}\left[0\right]\oplus ...\oplus B\text{'}\left[N-1\right]$$

As discussed above, an attempt to repair each device and verify the MAC in a correction process for all device data may include: $$MAC\text{'}=SHA3\left(ScHlüssel.B\text{'}\left[0\right]\Vert ...\Vert \left(B\text{'}\left[\text{i}\right]SubstitutRV\right)\Vert ...\Vert B\text{'}\left[N-1\right]\right)$$

In some examples, the MAC function may be implemented with any suitable alternative cryptographically secure hash function, such as, but not limited to, SHA. 1 or SHA- 2 , be calculated. If MAC 'matches the MAC, then the repaired value may be returned instead of the failed device data block. Otherwise, a return error may be provided.

Alternatively, the repair value RV for each device without XOR operations may be calculated in terms of the data block of this device with data blocks of the other device. In this example, the RV may replace a device data block during a repair attempt. In some examples, S = 32 and N = 16. However, S and N may be any suitable values. For an example For example, if S = 1 and N = 512, each bit can be flipped and the MAC can then be verified for each bit flip. In this example, the BC may not be saved.

4 illustrates a process flow diagram for managing encrypted data. This in 4 illustrated method 400 can with any suitable computing component or device, such as the computing device 100 out 1 to be implemented.

At block 402 can be a MAC administrator 120 calculate a MAC. In some examples, the MAC is calculated in response to a read as discussed above. The MAC administrator 120 may compute the MAC with a coded secure hash based on encrypted data stored in any suitable number of integrated circuits or devices that comprise a cache line of data.

At block 404 can the MAC administrator 120 determine if the computed MAC matches a stored MAC. If the calculated MAC matches a stored MAC, the process flow continues at block 406 where an error is corrected (or never existed), data is decrypted and sent to a cache device. If the calculated MAC does not match a stored MAC, the process flow moves to block 408 where each of the integrated circuits or each of the memory devices is tested.

If each of the integrated circuits or each of the devices that comprise a cache line of data are tested, but the first and second MACs never match, then the process moves to block 410 where an uncorrectable error is reported. If not each of the integrated circuits or each of the devices that comprise a cache line of data has been tested, the process flow continues at block 412 continued. At block 412 can the MAC administrator 120 skip a next integrated circuit or device data block in an XOR calculation and substitute an unrolled or XOR repair value (RV) to calculate a MAC value. The process flow returns to block 402 back.

In some examples, the techniques may be used here with a MAC size of any suitable length. For example, two additional integrated circuits or memory devices may be used to store two 32-bit values if the MAC value 64 Bit has. The two 32-bit MAC values can be combined with a logical OR operation. In some embodiments, two MAC values may be calculated in response to a read, and the results of the two MAC values may be concatenated to produce a 64-bit MAC value.

In some embodiments, the techniques herein may use one attempt per integrated circuit or device of a memory DIMM that includes a cache line of data to correct for single bit errors or multiple bit errors within a single device or integrated circuit. In some examples, the techniques may also correct for multiple single bit errors across multiple devices or multiple integrated circuits. For example, if there is one bit error in each of two separate devices, the fully unrolled or XORed correction value may indicate that two bits have flipped. In some embodiments, the MAC may be tested by flipping the various combinations of bits in each device data block. For example, for 8 DDR5 devices, two bit positions per device data block can be flipped over n devices. Similarly, sixty-four MAC tests can identify that both of the devices contain individual single-bit errors.

In some examples, if a fully unrolled or XORed correction value has a large number of flip bits, then the error is likely to be a complete device failure. Device failures can exist over a number of memory reads, but use fewer attempts to fix. For example, adding only 22 * 8 additional clocks for SHA3 encryption may be the worst case for DDR5 memory and these operations can be done in parallel. In some examples, SHA3 encryption takes less clock cycles than AES-XTS encryption, so integrity does not add any performance overhead to memory reads beyond encryption when the MAC is computed over the secret code text and computed in parallel with the decryption on a memory read.

The process flow diagram 4 should not specify that the procedures of the procedure 400 be executed in any particular order or all of the procedures of the method 400 in any case should be included. In addition, the process can 400 include any suitable number of additional operations.

5A and 5B Examples of data structures for storing encrypted data. In some examples, each device may 502A include any suitable number of bits. For example, any device 502A including a 16-bit value, 32-bit value or 64-bit value. In some embodiments, any number of devices may be equal in size to an encryption key or encryption block. For example, devices 502A . 504A . 506A and 508A if its size 32 Bit is equal to a block size of AES encrypted data. In some embodiments, a correction value 510A generated by a result of an XOR operation based on a previously stored MAC value 512A and encrypted data values stored in device data blocks 502A . 504A . 506A . 508A and the like are stored, and equally the entire remainder of the 514A shown contributes to the cache line of data.

In 5B can device data blocks 502B . 504B . 506B . 508B and 510B store encrypted data in a memory. In some examples, a substitute value 512B for the device data block 504B based on an XOR operation of the device data blocks 502B . 506B . 508B and all others as 510B shown device data blocks, a MAC 514B and a correction value 516B generated. For example, if the stored MAC 514B fails, the calculated MAC 518B the data line (the combined device data blocks), the substitute value 512B with an XOR operation (also referred to herein as unrolling) based on the MAC value 514B , the correction value 516B and each of the device data blocks excluding the one device data block being tested. For example, a device data block 504B be excluded from the XOR sequence to determine if the device data block 504B contains erroneous bits if the resulting substitute value is used instead of the device data block 504B is used and the recalculated second MAC matches the stored first MAC.

6 FIG. 12 illustrates a process flow diagram for managing encrypted data based on an entropy level of the data. This in 6 illustrated method 600 may be with any suitable computing component or device, such as the computing device 102 out 1 to be implemented. The procedure 600 can use heuristics to locate which device or which part of a storage device is likely to fail. For example, if a decrypted AES block shows a random plaintext, then probably one of the device data blocks contributing to that AES block has failed.

At block 602 can the MAC administrator 120 detect that a calculated MAC does not match a stored MAC value. At block 604 can the MAC administrator 120 decrypt a number of blocks of data in a stored memory. In some embodiments, the number of decrypted device data blocks is equal to a length of an encryption key. For example, four device data blocks each storing thirty-two bits may be decrypted for a one hundred twenty-eight-bit encryption block. In some examples, a size of the block corresponds to a size of input or output of a block secret code. For example, a block secret code, such as AES128, may use a 128-bit key to encrypt / decrypt a 128-bit block size of data. Alternatively, a block secret code, such as AES256, may use a 256-bit key to encrypt / decrypt the equally sized 128-bit block of data.

At block 606 can the MAC administrator 120 determine whether the plaintext of the decrypted data block has an entropy that is below a threshold. For example, if the number of 0-bits and 1-bits in the plaintext are approximately equal or equal in distribution, the entropy is above a threshold due to the random nature of the data. Accordingly, the method 600 Ignore plain text data with a low entropy or select the highest entropy blocks for replacement tests first. In one example, a decrypted block having multiple 8-bits of zeros in byte aligned positions may not be considered random or faulty, so those devices that comprise the block may be eliminated from the process of identifying a faulty data block with errors. In other examples, decrypted plaintexts having repeating values or values similar to other decrypted blocks are considered to have lower entropy and may be skipped first in the replacement value tests because they are unlikely to be the source of memory corruption.

If the plaintext of the decrypted data has an entropy that is above a threshold, the process flow moves to block 608 continued. At block 608 can the MAC administrator 120 determine if each block of data is corrected by replacing the device data block with a correction value as described above with respect to 3 was discussed. If the plaintext of the decrypted data has an entropy below a threshold, the process flow moves to block 610 Continue by testing a subsequent number of blocks of data before going to block 602 of the process flowchart returns. The MAC manager may also recalculate the second MAC after substituting each device data block with a replacement value for the decrypted block of highest entropy.

In some embodiments, compression for data may also be used to capture Reed-Solomon codes or similar ECC error detection codes within the data cache lines. If these codes are duplicated over multiple blocks, they can also be used to precisely identify the bit error locations without requiring trial-and-error. Likewise, the compression of the data line may allow the MAC value to be stored in the space released by compression, thereby reducing the need for additional memory to hold the MAC values. Further, if there is a device failure or an adhesion failure, it is likely to have multiple memory readings to aligned memory locations corresponding to the same device. This means that several adjacent readings will experience the same point of failure. This will help to fix the error correction on the most likely device for adhesive failure, again reducing trial-and-error.

The process flow diagram 6 should not specify that the procedures of the procedure 600 are to be executed in any particular order or that all of the procedures of the procedure 600 in any case should be included. In addition, the process can 500 include any suitable number of additional operations.

7 FIG. 10 illustrates a pipelining technique for computing a MAC. In some embodiments, a MAC computation pipeline may be used for speculatively repaired device data blocks instead of a sequential MAC computation for each repair attempt. For example, the cache line in a full pipeline design ( 1 Stage / clock cycle) at each clock cycle i = 0 ... 15 with "fixed" device i are sent to the MAC generation pipeline, so that the MAC values are calculated in parallel. In one example, assuming a SHA 3 22-cycle latency pipeline, the results of total latency would be a best case of 22 cycles, a worst case of 47 cycles, and an average of 29 cycles. In some examples, a SHA-3 pipeline may have a partial pipeline structure to meet throughput, ie, accept a cache line every four cycles. In some embodiments, repairing the device storing a MAC value does not require recalculation of the MAC value over cache line data because the data remains unchanged in a repair attempt. Instead, the process may involve performing XOR operations to generate a "repaired" MAC and attempting to match the repaired MAC with the MAC generated from the read raw data. In some examples, this repair attempt may be performed first before attempting to repair any device data block, which may have a latency of at least 22 cycles due to a MAC recalculation.

In example 700 off 7 For example, a complete pipeline SHA-3 engine consists of 22 identical concatenated stages, each having a set of state registers and combinational logic for a keccak function. The input can be delivered to each stage and the last stage provides the output. To increase the utilization of this pipeline, a loop of pipeline stages K 702 may input 702 pass any of the pipeline stages through the inputs in0 ... in21704. The output for certain input data is fetched after 22 cycles from the corresponding output out0 ... out21 706.

This loop design allows multiple input cache lines to be loaded in the same cycle and processed in parallel rather than offset by one cycle. This is useful when calculating MACs to repair a device data block. At best, if the pipeline is empty, the "repaired" cache lines can be loaded in parallel to determine which device was faulty, thereby reducing latency. In some examples, unused inputs may be used to compute MACs for other data responses that arrive from the memory. This improves latency and throughput for memory-intensive workloads with frequent DRAM errors. A hardware arbiter can be used to keep track of the MAC calculations that are in-line and to multiplex input data into the appropriate stages. This approach can also be applied to a partial pipeline Design, in which each stage applies multiple rounds of a keccak function to the current state until a transfer to the next level. Each of these stages may have an external input and output as described above to maximize utilization of each stage.

8th illustrates a process flow diagram for managing encrypted data. This in 8th illustrated method 800 may be with any suitable computing component or device, such as the computing device 102 out 1 to be implemented.

At block 802 can the MAC administrator 120 store an encrypted first block correction value and a first MAC value based on data stored in system memory in the system memory in response to a write. The first block correction value comprises the XOR of the plaintext of each block of data in a data line written in the memory. In addition, the MAC manager may calculate an additional MAC value for the encrypted data in the data line and store the additional MAC value in the memory. At block 804 can the MAC administrator 120 detect a read corresponding to the data stored in the system memory.

At block 806 can the MAC administrator 120 calculate a second block correction value based on the data stored in the system memory. In some examples, the second block correction value may be calculated based on an XOR operation that includes plaintext data or decrypted data of each block of a data line stored in the system memory. In some examples, the second block correction value may be generated in response to a read.

At block 808 can the MAC administrator 120 determine that the second block correction value does not match a decrypted first stored block correction value. In this case, the MAC administrator 120 retrieve the additional stored MAC value from the memory and calculate a second MAC of the data line stored in the memory. If the stored MAC matches the second calculated MAC, then it is determined that the block correction code is in an error state and the data can be decrypted and sent to the cache. If the stored MAC does not match the second calculated MAC at block 810 can match, the MAC administrator 120 at block 812 Recalculate the second block correction value with a correction operation. In some embodiments, the correction process includes an XOR operation based on the decrypted data blocks stored in the system memory and a replacement value for a device data block or integrated circuit of the system memory is determined by omitting the device data block and using the remaining block correction value instead of the decrypted device data block text. The substitute value is then encrypted with a secret key (used to encrypt the device data blocks) and the second MAC is recalculated using the remaining encrypted blocks and the encrypted substitute value.

At block 814 can the decryption manager 122 decrypt the data stored in the system memory comprising a cache line in response to detecting that the recalculated second MAC value matches the first stored MAC value. At block 816 can the data transmitter 124 transmit the decrypted data to a cache.

The process flow diagram 8th should not specify that the procedures of the procedure 800 are to be executed in any particular order or that all of the procedures of the procedure 800 in any case should be included. In addition, the process can 800 include any suitable number of additional operations. In the process 800 For example, the block correction code itself may surely detect (in a non-falsible manner) that the data has at least one error. The additional MAC value can be used to determine when any errors are corrected or corrected. If there is no error, the additional stored MAC value will not be retrieved. In some embodiments, the additional MAC value may be stored in a separate memory location, accordingly removing the need for additional devices on a storage device, such as a DIMM, for the MAC. Some embodiments may completely eliminate the additional stored MAC value by using the entropy of each decrypted block of data to determine which device / block is in an error state and the substitute value instead of the decrypted block of highest data Entropy, as in 6 illustrates is used. Similarly, data compression techniques can be used to allow a MAC to fit into a space that is freed by compressing the data line.

9 is a process flow diagram for managing encrypted data. In some embodiments, the method 900 Transforming each device data block before calculating the error correction code. One transformation is to use a small block size secret code (eg, SIMON, SPECK, PRINCE, among others) in which the block size matches the device size to encrypt each device one at a time with a secret key before XORing each one resulting secret code text is performed. Some embodiments may include a tweak, for example, using XTS (XEX-based tweak codebook mode with secret code text steal) or other tweak modes, the tweak comprising the address of the device data block to provide memory location / location dependent secret code text to create. Which key is used to encrypt / decrypt the data line can also be selected by additional address bits or other cacheable metadata that indicates which key from a set of keys to use.

Accordingly, even the correction code is secure. For example, an encryption of any device having a secret code with a small block size may be used as input to the XOR function to compute the XOR-executed correction code. An attacker would need to know this secret function output to ensure that all device data blocks are unrolled to zero. Therefore, both the MAC and the correction codes work together, improving the security of the block.

At block 902 can the MAC administrator 120 calculate a MAC, decrypt data, and decrypt a block correction value in response to a read. In some examples, the block correction value is stored in an encrypted format from a previous write. In some embodiments, the MAC may be computed based on the encrypted data that was stored in memory prior to decryption.

At block 904 can the MAC administrator 120 determine whether the decrypted block correction value matches an XOR result based on the plaintext data or decrypted data. If the block correction value matches the XOR plaintext data blocks, the process flow moves to block 906 and the decrypted data is sent to a cache. If the block correction value does not match the XOR plaintext data blocks, the process flow moves to block 908 continued.

At block 908 can the MAC administrator 120 determine if the computed MAC matches a stored MAC. If the calculated MAC matches a stored MAC, the process flow continues at block 906 by sending decrypted data to a cache device. If the calculated MAC does not match a stored MAC, the process flow moves to block 910 continued. At block 910 can the MAC administrator 120 skip to a next device data block in an XOR calculation, substitute the decrypted block correction value for a decrypted device data block, re-encrypt the substitute value, and recalculate a MAC over the remaining encrypted device data blocks and the encrypted substitute value before going to block 908 returns. Therefore, in order for a bad cache line to pass the integrity test, an attacker not only has to fake the MAC but also falsify the block correction value that is generated using a secret key. Therefore, this effectively becomes a solution with two MACs, especially if a stronger (larger) MAC is needed than it can fit in the device data block of the error detection code. With increasing DRAM device densities, the above scheme is also effective in reducing ECC memory costs, because the MAC is stored separately in a separate (e.g., software assigned) memory or as a table structure in a memory (table represented by the Memory address indexed associated with each table entry) can be stored. The additional ECC chip / device on the DIMM for the ECC error detection code and / or MAC can therefore be eliminated. Meanwhile, the dedicated memory may be used for the MAC if the device correction fails at a match. The MAC is used to determine which of the correction values were successful or whether the correction device was the failing part because the MAC matches the uncorrected data line value. Finally, techniques such as compression can be used to embed the MAC within the data line (if compressible) using MAC lookup only for data cache lines that do not compress. This can also reduce the amount of dedicated memory needed and reduce the number of memory lookups when memory errors are corrected.

10A and 10B illustrate techniques for managing encrypted data with a block correction value and a second MAC 10A can in a memory write the encrypted data 1002A used to be a MAC 1004A to calculate, which is stored separately. also can be a decrypted version of the data or plain text data 1006A combined with an XOR operation to produce an XOR-executed plaintext 1008A to generate a correction value 1010A is. The correction value 1010A can be in an encrypted format 1012A stored as an encrypted block correction value.

In 10B In a memory read, all device data blocks for a memory line are decrypted. The plaintext of each device block is then XORed together with the decrypted block correction value 1010B compared. Every device of data 1002B can be decrypted before the plaintext 1004B an XOR operation to get an XOR-executed plaintext 1006B to create. In some examples, the encrypted block correction value 1008B be decrypted to a decrypted block correction value 1010B to generate that with the XOR-executed plaintext 1006B is compared. In some examples, if the decrypted value of 1010B and 1006B does not match the XOR-executed plaintext 1006B an XOR operation with the decrypted block correction value 1010B be subjected to one device / block at a time by the 1006B Calculation is omitted. The resulting block correction value is then encrypted to produce the data block value of the original encrypted failed device. This value is then substituted for the data block of the omitted device and the MAC is recalculated and compared with the separately stored MAC until the data block of the failed device is identified and corrected. In some examples, even if the MAC exists, the block correction value should unroll or generate a null value as a result of an XOR operation as the blocks / devices are transformed and subjected to an XOR operation with the original block correction value.

In some embodiments, techniques described herein may also provide replay protection even when multiple keys (MKTME) have been used to encrypt the data to AES XTS. For example, the MAC administrator 120 periodically provide the MAC values with a unique key as a new key, the MAC being recalculated using the MKTME AES XTS secret code text and a unique MAC key. The addition of a new key may coincide with a memory refresh in which the memory is read, the MAC is calculated with an old key, compared with the old stored MAC for the same memory line and, if these values match, the MAC is recalculated with the new key before the new MAC is written back to memory. In some examples, techniques may use a construct, such as ICV, which is equal to an HMACrk (Ck) XOR AESk (address). This construct makes it possible to refresh a key rk for the HMAC. This independently combines the MAC via the data secret code text (Ck) from a particular domain key (k) and a key-dependent test using the tweak (XTS tweak that uses the address).

In this example, if an adversary or unauthorized user re-loads content from another key domain for the same memory address, the HMAC will correctly compute over the secret code text, but the address-based tweak using the current key domain key k will not match on a memory read. The MAC administrator 120 may compute the old HMAC (using the previous update key rk) via the secret code text data cache line, XOR the data cache line contents from the stored ICV, and perform an XOR operation on it with the new one Perform HMAC using the refreshed key.

In some embodiments, the MAC manager 120 use an alternative construct to provide a MAC with a new key. For example, the MAC administrator 120 use the construct ICV equal to HMACrk (Ck) -XOR-HMACk (address). This construct provides secret code text error detection, is scalable via key domain error detection, and can refresh to limit replay without additional MAC keys.

In another embodiment, the MAC manager 120 use the construct ICV, which is equal to ENCRYPTrk (SHA3 (Ck, TWEAKk)), to add new keys to MAC values. Here, ENCRYPT may be a small-block secret code (eg, SIMON, among others) having the same size as the truncated SHA3-HMAC (eg, 32-bit or 64-bit, etc.) with the HMAC with the refresh key rk is encrypted. The HMAC also includes an XTS-based tweak (eg, an AES encrypted memory address based on the data encryption key) in addition to the secret code text based on the data encryption key k. This allows the ICV to both prevent cross-domain attacks and bind to the memory address / location where the data is physically stored. The tweak can be the same as it used to encrypt the XTS Data is used to produce Ck, but a different tweak offset can be used exclusively for this operation (eg, based on an extended address value to produce an additional unique tweak value from the tweaks that are used to encrypt the Data-line used). Likewise, other cryptographic key derivation techniques may be used in place of the tweak to produce a data encryption key dependent HMAC. In some examples, the TWEAKk based on the data encryption key k is effectively a key derivation function that causes the SHA3 hash algorithm to issue a MAC that can then be truncated. The advantage of using the tweak with the encryption key is that it eliminates the need to store separate keys for computing the MAC. Instead, the encryption key may be reused by a key derivation function that encrypts the memory address (padding) for the encrypted data line (Ck) using the encryption key k. Likewise, any secure hash function can be used instead of SHA3, and any key derivation function can be used instead of the TWEAK.

A replay / version tree can also be used with this construct. Here, the embedded MACs are the ECC memory MACs, as previously described. The MAC of the replay tree may include a parent counter value for the cache line. A root counter / nonce (or counter / nonces for multiple memory areas) may also be embedded in the hardware on which the. The first level in the tree in memory contains a cache line with a set of counter / nonce values and the MAC in the ECC memory. This MAC is calculated over all counter values that comprise the cache line and the associated root counter / nonce stored on the die. Each counter / nonce value on the line is a parent for the next level of the tree. The next level of the tree is a line with counter / nonce values, again with the MAC in the ECC memory hashing all counter / nonce values in the line and a single parent nonce / counter from the previous line in the tree. The last level / leaves of the tree consist of the data line and its MAC in the ECC memory, as previously described, the one difference being that the MAC is also hashed over the parent counter / nonce value. In this way, replay can be prevented because each time data is written to memory, the root counter and all counter values in the branch of the counter / nonce tree leading to the updated data line are increased / updated and all affected MACs in the ECC memory are recalculated. In a memory read, the MACs for the branch of the tree associated with the read data line are verified by verifying that the counter / nonce values are correct / unmodified. The MAC values can be calculated with a different secret key than the key used to encrypt the data lines and the MAC calculated via the AES-XTS secret code text of the data line, thereby allowing that different data is encrypted with different keys, such as MKTME.

In some embodiments, the ECC / integrity values may also be stored in separate memory locations so that they do not require the addition of physical / physical ECC memory / ECC DIMMs. Additional memory read / write operations will be used to retrieve the ECC / integrity values from the separate memory locations in this case. For example, the ECC correction field may be extended to both correct a memory and to be an HMAC for detecting errors. Using entropy tests to validate which device is likely to be in an error state eliminates the need to store any other values, saving half of the ECC memory overhead and reducing costs.

11 FIG. 12 illustrates a block diagram of a non-transitory computer-readable medium for managing encrypted data. FIG. The tangible nonvolatile computer-readable medium 1100 can through a processor 1102 via a computer interconnect 1104 be accessed. Furthermore, the tangible non-transitory computer-readable medium 1100 a code for instructing the processor 1102 to carry out the operations of the present method.

The various software components discussed herein may be stored on the tangible non-transitory computer-readable medium 1100, as in FIG 11 is specified. For example, a MAC administrator 1106 store a first message authentication code (MAC) in system memory based on data stored in the system memory in response to a write. In some embodiments, the MAC manager 1106 also detect a read corresponding to the data stored in the system memory and calculate a second MAC based on the data stored in the system memory. The MAC administrator 1106 may also determine that the second MAC does not match the first MAC, and the second MAC with a correction process recalculating, wherein the correction process comprises an XOR operation based on the data stored in the system memory and a replacement value for a system memory device. Furthermore, a decryption manager 1108 decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC. In some embodiments, a data transmitter 1110 the decrypted data to a cache residing on a processor 102 or any other suitable cache or storage device.

Alternatively, the MAC administrator 1106 in some embodiments, storing an encrypted first block correction value based on information stored in the system memory in the system memory in response to a write. In addition, the MAC administrator 1106 also detect a read corresponding to the data stored in the system memory and calculate a second block correction value based on the data stored in the system memory, wherein the second block correction value calculated based on an XOR operation includes plaintext data stored in the system memory. In some embodiments, the MAC manager 1106 determining that the second block correction value does not match a decrypted first block correction value and recalculating the second block correction value with a correction operation, the correction process comprising an XOR operation based on encrypted data stored in the system memory and a system memory device replacement value. Furthermore, the decryption manager 1108 the data stored in the system memory is decrypted and the data transmitter is capable of decoding in response to detecting that the recalculated second block correction value matches the first block correction value 1110 transmit the decrypted data to a cache.

It is understood that any suitable number of in 11 shown software components in the tangible, non-transitory computer-readable medium 1100 may be included. Furthermore, any number of in 11 not shown additional software components within the tangible non-transitory computer-readable medium 1100 be included depending on the particular application.

EXAMPLE 1

In some examples, an encrypted memory management system includes a processor for storing a first message authentication code (MAC) based on data stored in system memory in response to a write to system memory. The processor may also detect a read corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, and determine that the second MAC does not match the first MAC. Further, the processor may also recalculate the second MAC subsequent to a correction process, wherein the correction process includes an XOR operation based on the data retrieved from the system memory and a replacement value for a system memory device. In addition, the processor may decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC and transmit the decrypted data to a cache.

Alternatively, or in addition, the recalculate correction process includes the second MAC for a plurality of system memory devices. Alternatively, or in addition, the processor is configured to perform the XOR operation for each of the plurality of devices, wherein the XOR operation is based on the replacement value and the data stored in each of the plurality of device-only devices. Alternatively, or in addition, the processor is configured to generate an uncorrectable error in response to detecting that the recalculated second MAC for each device of the system memory does not match the first MAC. Alternatively, or in addition, the processor is configured to decrypt a block of the data stored in the system memory, wherein a size of the block corresponds to a size of an input or output of a block secret code, to determine that an entropy of a plaintext in the decrypted block of the data is above a threshold level, and to execute the correction command on each device in the system memory storing a portion of the block of data. Alternatively, or additionally, the processor includes logic to execute the correction instruction in a parallel pipeline, the parallel pipeline comprising generating the second MAC with the substitute value for each device of the system memory. Alternatively or additionally, the processor is configured to generate a block correction value. Alternatively, or in addition, the processor is configured to provide the first MAC and the second MAC with a new key in response to a lapse of a predetermined period of time.

EXAMPLE 2

In one embodiment, a system for managing encrypted data includes a processor for storing an encrypted first block correction value based on data stored in system memory in response to a write to the system memory. The processor may also detect a read corresponding to the data stored in the system memory and calculate a second block correction value based on the data stored in the system memory, wherein the second block correction value calculated based on an XOR operation is stored in the system memory Plain text data includes. In addition, the processor may determine that the second block correction value does not match a decrypted first block correction value, determine that a stored first MAC value does not match a calculated second MAC, and recalculate the second block correction value with a correction operation, wherein the correction operation is an XOR. A process based on decrypted data stored in the system memory and a system memory device replacement value. Further, the processor may decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first block correction value and transmit the decrypted data to a cache device.

Alternatively, or in addition, the processor is configured to generate a first MAC based on an XOR process that includes secret code text data stored in the system memory. Alternatively or additionally, the processor is configured to decrypt the data stored in the system memory and the first block correction value. Alternatively or additionally, the system includes a single device in the system memory for storing the first block correction value.

EXAMPLE 3

In one example, a method for managing encrypted memory includes storing a first message authentication code (MAC) based on data stored in system memory in response to a write to system memory. The method may also include detecting a read corresponding to the data stored in the system memory, calculating a second MAC based on the data retrieved from the system memory, and determining that the second MAC does not match the first MAC. In addition, the method may include recalculating the second MAC subsequent to a correction process, the correction process including an XOR operation based on the data retrieved from the system memory and a system memory device replacement value. Furthermore, the method may include decrypting the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC and transmitting the decrypted data to a cache.

Alternatively, or in addition, the correction process includes recalculating the second MAC for a plurality of system memory devices. Alternatively, or additionally, the method includes executing the XOR operation for each of the plurality of devices, wherein the XOR process is based on the substitute value and the data stored in each of the plurality of device-only devices. Alternatively, or additionally, the method includes generating an uncorrectable error in response to the detecting that the recalculated second MAC for each device of the system memory does not match the first MAC. Alternatively, or additionally, the method includes decrypting a block of the data stored in the system memory, wherein a size of the block corresponds to a size of an input or output of a block secret code, determining that an entropy of a plaintext in the decrypted block of the data is above a threshold level, and performing the correction command on each device in the system memory that stores a portion of the block of data. Alternatively, or additionally, the method includes executing the correction instruction in a parallel pipeline, the parallel pipeline comprising generating the second MAC with the substitute value for each device of the system memory. Alternatively, or additionally, the method includes generating a block correction value. Alternatively or additionally, the method includes providing the first MAC and the second MAC with a new key or re-encrypting it based on a new key in response to a lapse of a predetermined period of time.

EXAMPLE 4

In one embodiment, a method for managing encrypted data includes storing an encrypted first block correction value based on data stored in system memory in response to a write to the system memory. The method may also include detecting a read corresponding to the data stored in the system memory and calculating a second block correction value based on the data stored in the system memory, wherein the second block correction value calculated based on an XOR operation is in the system memory stored plaintext data. In addition, the method may determine that the second block correction value does not match a decrypted first block correction value, determine that a stored first MAC value does not match a calculated second MAC, and recalculate the second block correction value with a correction operation, wherein the correction process is an XOR Operation based on decrypted data stored in the system memory and a replacement value for a system memory device. Furthermore, the method may include decrypting the data stored in the system memory in response to detecting that the recalculated second MAC matches the first block correction value and transmitting the decrypted data to a cache device.

Alternatively, or in addition, the method may include generating a first MAC based on an XOR process that includes secret code text data stored in the system memory. Alternatively, or in addition, the method may include decrypting the data stored in the system memory and the first block correction value. Alternatively, or in addition, the method may include using a single device in the system memory to store the first block correction value.

EXAMPLE 5

In one embodiment, a non-transitory computer readable medium for managing encrypted memory includes a plurality of instructions that, in response to execution by a processor, cause the processor to generate a first message authentication code (MAC) based on data stored in system memory in response to a write to the computer System memory stores. The processor may also detect a read corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, and determine that the second MAC does not match the first MAC. Further, the processor may also recalculate the second MAC subsequent to a correction process, wherein the correction process includes an XOR operation based on the data retrieved from the system memory and a replacement value for a system memory device. In addition, the processor may decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC and transmit the decrypted data to a cache.

Alternatively, or in addition, the correction process includes recalculating the second MAC for a plurality of system memory devices. Alternatively, or in addition, the processor is configured to perform the XOR operation for each of the plurality of devices, wherein the XOR operation is based on the replacement value and the data stored in each of the plurality of device-only devices. Alternatively, or in addition, the processor is configured to generate an uncorrectable error in response to detecting that the recalculated second MAC for each device of the system memory does not match the first MAC. Alternatively, or in addition, the processor is configured to decrypt a block of the data stored in the system memory, wherein a size of the block corresponds to a size of an input or output of a block secret code, to determine that an entropy of a plaintext in the decrypted block of the data is above a threshold level, and to execute the correction command on each device in the system memory storing a portion of the block of data. Alternatively, or additionally, the processor includes logic to execute the correction instruction in a parallel pipeline, the parallel pipeline comprising generating the second MAC with the substitute value for each device of the system memory. Alternatively or additionally, the processor is configured to generate a block correction value. Alternatively, or in addition, the processor is configured to provide the first MAC and the second MAC with a new key in response to a lapse of a predetermined period of time.

EXAMPLE 6

In one embodiment, a non-transitory computer-readable medium for managing encrypted memory includes a plurality of instructions that cause the processor to store an encrypted first block correction value based on system-stored data in system memory in response to a write to system memory , The processor may also detect a read corresponding to the data stored in the system memory and calculate a second block correction value based on the data stored in the system memory, wherein the second block correction value calculated based on an XOR operation is stored in the system memory Plain text data includes. In addition, the processor may determine that the second block correction value does not match a decrypted first block correction value, determine that a stored first MAC value does not match a calculated second MAC, and recalculate the second block correction value with a correction operation, wherein the correction process is an XOR. A process based on decrypted data stored in the system memory and a system memory device replacement value. Further, the processor may decrypt the data stored in the system memory in response to detecting that the recalculated second MAC matches the first block correction value and transmit the decrypted data to a cache device.

Alternatively, or in addition, the processor is configured to generate a first MAC based on an XOR process that includes secret code text data stored in the system memory. Alternatively or additionally, the processor is configured to decrypt the data stored in the system memory and the first block correction value. Alternatively or additionally, the system includes a single device in the system memory for storing the first block correction value.

Although one embodiment of the disclosed subject matter is described with reference to block and flow diagrams in FIG 1-11 One of ordinary skill in the art will readily recognize that many other methods for implementing the disclosed subject matter may alternatively be used. For example, the order of execution of the blocks in flowcharts may be changed and / or some of the blocks in described block / flow diagrams may be changed, eliminated or combined.

In the foregoing description, various aspects of the disclosed subject matter have been described. For purposes of explanation, specific numbers, systems, and configurations have been set forth in order to provide a thorough understanding of the subject matter. However, it will be apparent to those skilled in the art, with the aid of this disclosure, that the subject matter can be practiced without these specific details. In other instances, well-known features, components or modules have been omitted, simplified, combined or subdivided so as not to obscure the disclosed subject matter.

Various embodiments of the disclosed subject matter may be implemented in hardware, firmware, software, or a combination thereof, and may be by reference to or in connection with program code, such as instructions, functions, procedures, data structures, logic, application programs, design presentations, or simulation, emulation and fabricating a design that, when accessed by a machine, causes the machine to perform tasks, define low-level abstract data types or hardware contexts, or produce a result.

Program code may represent hardware using a hardware description language or other functional description language that essentially provides a model of how a designed hardware functions as expected. Program code may be assembly or machine language or hardware definition languages, or data that may be compiled and / or interpreted. Further, it is common in the art to speak of software in a form or other as an act or effect a result. Such terms are merely a shorthand way of indicating execution of program code by a processing system that causes a processor to perform an action or produce a result.

Program code may be stored in, for example, volatile and / or nonvolatile memory, such as storage devices and / or an associated machine-readable or machine-accessible medium, including a solid state memory, hard disks, floppy disks, optical storage, tapes, flash memory, memory sticks , digital video discs, digital versatile discs (DVDs), etc., as well as more exotic media, such as machine-accessible biological condition preservation storage. A machine-readable medium may include any tangible mechanism for storing, transmitting, or receiving information in a form readable by a machine such as antennas, optical fibers, communication interfaces, and so on. Program code may be transmitted in the form of packets, serial data, parallel data, etc., and may be used in a compressed or encrypted format.

Program code may be implemented in programs executing on programmable machines, such as mobile or stationary computers, personal digital assistants, set-top boxes, cell phones and pagers, and other electronic devices, each having a processor, a volatile, and / or nonvolatile memory readable by the processor, including at least one input device and / or one or more output devices. Program code may be applied to the data input using the input device to perform the described embodiments and generate output information. The output information may be applied to one or more output devices. One of ordinary skill in the art will understand that embodiments of the disclosed subject matter may be implemented with various computer system configurations, including multiple processor or multi-core processor systems, minicomputers, mainframe computers, and ubiquitous or miniature computers or processors that may be embedded in virtually any device. Embodiments of the disclosed subject matter may also be practiced in distributed computing environments where tasks may be performed by remote processing devices that are linked by a communications network.

Although operations may be described as a sequential process, some of the operations may in fact be performed in parallel, concurrently, and / or in a distributed environment and with program code stored locally and / or remotely for access by single or multiple processor machines. Additionally, in some embodiments, the order of operations may be resorted without departing from the idea of the disclosed subject matter. Program code can be used by or in conjunction with embedded controllers.

Although the disclosed subject matter has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments as well as other embodiments of the subject that will be apparent to those skilled in the art to which the disclosed subject matter pertains are considered to be within the scope of the disclosed subject matter.

Claims (23)

A system for managing an encrypted memory, comprising: means for storing a first message authentication code (MAC) based on data stored in system memory in response to a write to system memory; means for detecting a read corresponding to the data stored in the system memory; means for calculating a second MAC based on the data retrieved from the system memory; means for determining that the second MAC does not match the first MAC; a means for recalculating the second MAC subsequent to a correction operation, the correction process comprising an XOR operation based on the data retrieved from the system memory and a replacement value for a system memory device; means for decrypting the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC; and means for transmitting the decrypted data to a cache. System after Claim 1 wherein the correction process comprises means for recalculating the second MAC for a plurality of system memory devices. System after Claim 2 comprising means for performing the XOR operation for each of the plurality of devices, wherein the XOR operation is based on the substitute value and the data stored in each of the plurality of device-only devices. System after Claim 1 or 2 in that means for generating an uncorrectable error in response to detecting that the recalculated second MAC for each device of the system memory does not match the first MAC comprises. System after Claim 1 or 2 method comprising: means for decrypting a block of the data stored in the system memory, a size of the block corresponding to a size of an input or output of a block secret code; means for determining that entropy of a plaintext in the decrypted block of the data is above a threshold level; and means for performing the correction command on each device in the system memory storing a portion of the block of data. System after Claim 1 or 2 comprising means for executing the correction instruction in a parallel pipeline, the parallel pipeline comprising generating the second MAC with the substitute value for each device of the system memory. System after Claim 1 or 2 comprising means for generating a block correction value. System after Claim 1 comprising means for providing the first MAC and the second MAC in response to a lapse of a predetermined time period with a new key. System after Claim 8 comprising means for providing the first MAC and the second MAC with a new key based on a memory refresh rate, wherein the providing with a new key comprises: means for detecting a second read operation; means for comparing the first MAC with a previously stored key; means for recalculating the first MAC with a new key; and means for storing the first MAC encrypted with the new key in the system memory. An encrypted data management system comprising: a processor designed to: Storing an encrypted first block correction value based on data stored in a system memory in response to a write to the system memory; Detecting a read corresponding to the data stored in the system memory; Calculating a second block correction value based on the data stored in the system memory, the second block correction value calculated based on an XOR operation comprising plaintext data stored in the system memory; Determining that the second block correction value does not match a decrypted first block correction value; Determining that a stored first MAC value does not match a calculated second MAC; Recalculating the second block correction value with a correction operation, the correction process comprising an XOR operation based on decrypted data stored in the system memory and a system memory device replacement value; Decrypting the data stored in the system memory in response to detecting that the recalculated second MAC value matches the first block correction value; and Transmitting the decrypted data to a cache device. System after Claim 10 wherein the processor is configured to generate the first MAC based on an XOR process comprising secret code text data stored in the system memory. System after Claim 10 wherein the processor is configured to decrypt the data stored in the system memory and the first block correction value. System after Claim 10 . 11 or 12 wherein the system comprises a single device in the system memory for storing the first block correction value. A method of managing an encrypted memory, comprising: storing a first message authentication code (MAC) based on data stored in system memory in response to a write to the system memory; Detecting a read corresponding to the data stored in the system memory; Calculating a second MAC based on the data retrieved from the system memory; Determining that the second MAC does not match the first MAC; Recalculating the second MAC subsequent to a correction process, the correction process including an XOR operation based on the data retrieved from the system memory and a replacement value for a system memory device; Decrypting the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC; and transmitting the decrypted data to a cache. Method according to Claim 14 wherein the correction process comprises recalculating the second MAC for a plurality of system memory devices. Method according to Claim 15 , which comprises performing the XOR operation on each of the plurality of devices, wherein the XOR operation is based on the substitute value and the data stored in each of the plurality of device-only devices. Method according to Claim 14 or 15 , generating an uncorrectable error in response to detecting that the recalculated second MAC for each device of the system memory does not match the first MAC. Method according to Claim 14 or 15 method comprising: decrypting a block of the data stored in the system memory, wherein a size of the block corresponds to a size of an input or output of a block secret code; Determining that an entropy of a plaintext in the decrypted block of the data is above a threshold level; and performing the correction command on each device in the system memory that stores a portion of the block of data. Method according to Claim 14 or 15 that comprises providing the first MAC and the second MAC with a new key or re-encrypting it based on a new key in response to a lapse of a predetermined period of time. A non-transitory computer-readable medium for managing an encrypted memory that includes a plurality of instructions that, in response to execution by a processor, cause the processor to: Storing a first message authentication code (MAC) based on data stored in system memory in response to a write to system memory; Detecting a read corresponding to the data stored in the system memory; Calculating a second MAC based on the data retrieved from the system memory; Determining that the second MAC does not match the first MAC; Recalculating the second MAC subsequent to a correction process, the correction process including an XOR operation based on the data retrieved from the system memory and a replacement value for a system memory device; Decrypting the data stored in the system memory in response to detecting that the recalculated second MAC matches the first MAC; and Transmitting the decrypted data to a cache. Non-volatile computer readable medium after Claim 20 wherein the correction process comprises recalculating the second MAC for a plurality of system memory devices. Non-volatile computer readable medium after Claim 21 wherein the processor is configured to perform the XOR operation for each of the plurality of devices, wherein the XOR operation is based on the substitute value and the data stored in each of the plurality of device-only devices. Non-volatile computer readable medium after Claim 20 or 21 wherein the processor is configured to generate an uncorrectable error in response to detecting that the recalculated second MAC for each device of the system memory does not match the first MAC.

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