DE102018124815A1 - FIN field effect transistor device and method - Google Patents

Abstract

One method includes forming a first fin protruding above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; and forming a second spacer layer over the first spacer layer. The method further includes performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and sidewalls of the first fin in the PMOS region; and epitaxially growing a first source / drain material over the first fin in the PMOS region, wherein the first source / drain material extends along the top surface and sidewalls of the first fin in the PMOS region

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the priority of the provisional U.S. Patent Application No. 62 / 592,871 filed on Nov. 30, 2017, entitled "Fin Field-Effect Transistor Device and Method", the application of which is hereby incorporated by reference.

GENERAL PRIOR ART

The semiconductor industry has experienced rapid growth due to constant improvement in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density has consisted of repeated reductions in the minimum element size that allows more components to be integrated in a given area.

Fin Field Effect Transistor (FinFET) devices are commonly used in integrated circuits. FinFET devices have a three-dimensional structure that includes a semiconductor fin protruding from a substrate. A gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device settles around the semiconductor fin. In a triple gate FinFET device, the gate structure is laid around three sides of the semiconductor fin, forming conductive channels on three sides of the semiconductor fin.

list of figures

• 1 veranschaulicht einen FinFET in einer perspektivischen Ansicht in Übereinstimmung mit einigen Ausführungsformen.
• Die 2, 3A, 3B, 4A bis 4C, 5A bis 5F, 6A bis 6C, 7A bis 7C, 8A bis 8C, 9A bis 9C, 10A bis 10C, 11A bis 11C, 12A bis 12C und 13 bis 16 sind diverse Ansichten (zum Beispiel Draufsichten, Querschnittansichten) eines FinFET-Bauteils bei diversen Fertigungsstufen in Übereinstimmung mit einigen Ausführungsformen.
• 17 veranschaulicht ein Ablaufdiagramm eines Verfahrens zum Bilden eines Halbleiterbauteils.

Aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying figures. It is emphasized that various elements are not drawn to scale in accordance with industry standard practice. Namely, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of the discussion.

• 1 FIG. 12 illustrates a FinFET in a perspective view in accordance with some embodiments. FIG.
• The 2 . 3A . 3B . 4A to 4C . 5A to 5F . 6A to 6C . 7A to 7C . 8A to 8C . 9A to 9C . 10A to 10C . 11A to 11C . 12A to 12C and 13 to 16 FIGS. 10 are various views (eg, plan views, cross-sectional views) of a FinFET device at various stages of fabrication in accordance with some embodiments.
• 17 FIG. 12 illustrates a flowchart of a method of forming a semiconductor device. FIG.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are just examples, of course, and they are not intended to be limiting. Forming a first feature over or on a second feature in the following description, for example, may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are interposed between the first and second features second feature may be formed so that the first and the second feature may not be in direct contact.

Further, spatial reference terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to facilitate the description of the relationship of one feature or feature to one or more other features or features to describe how they are illustrated in the figures. The spatial terms may be intended to include different orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or to other orientations), and the spatial reference descriptors used herein will be interpreted accordingly.

1 illustrates an example of a FinFET 30 in a perspective view. The FinFET 30 has substrate 50 and a Finn 64 that over the substrate 50 protrudes, up. The substrate 50 has isolation areas 62 on, and the Finn 64 protrudes above and between adjacent isolation areas 62 in front. A gate dielectric 66 lies along sidewalls and over an upper surface of the fin 64 , and a gate 68 is above the gate dielectric 66 , Source / drain regions 80 lie in the fin on opposite sides of the gate 68 , 1 further illustrates reference cross sections used in later figures. The cross section BB extends along a longitudinal axis of the gate 68 of the FinFET 30 , The cross section AA is perpendicular to the cross section BB and runs along a longitudinal axis of the fin 64 and in one direction, for example, a current flow between the Source / drain regions 80 , The cross section CC is parallel to the cross section BB and passes over a source / drain region 80 of the FinFET 30. Subsequent figures refer to these reference cross sections for clarity.

The 2 . 3A . 3B . 4A to 4C . 5A to 5F . 6A to 6C . 7A to 7C . 8A to 8C . 9A to 9C . 10A to 10C . 11A to 11C . 12A to 12C and 13 to 16 are various views (eg, plan views, cross-sectional views) of a FinFET device 100 at various stages of manufacture in accordance with one embodiment. The FinFET device 100 is the FinFET 30 in 1 similar, but with several Finns.

2 illustrates a plan view of a substrate 50 which is used to fabricate the FinFET device 100 is used. The substrate 50 may be a semiconductor substrate such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like doped (for example, with a P-type or N-type dopant ) or undotated. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) oxide layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically on a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor substrate 50 Silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof.

As in 2 illustrates the substrate 50 a first section in an area 200 and a second section in an area 300 on. The first section of the substrate 50 in that area 200 can be used to form N-type devices, such as N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), and the second portion of the substrate 50 in that area 300 can be used to form P-type devices such as P-type MOSFETs. The area 200 may thus be an NMOS region of the substrate 50 be called, and the area 300 may be a PMOS region of the substrate 50 to be named. In other embodiments, P-type devices (or N-type devices) will both be in the range 200 as well as in the field 300 educated.

3A illustrates the substrate 50 in 2 with an upper portion of the substrate 50 in that area 300 by a semiconductor material 50A is replaced. 3B FIG. 12 illustrates a cross-sectional view of the structure in FIG 3A along the cross section DD ,

With reference to the 3A and 3B becomes a section of the substrate 50 in that area 300 with the semiconductor material 50A as with a semiconductor epitaxial material suitable for forming a corresponding device type (eg, a P-type device device) in the region 300 is suitable replaced. The semiconductor material 50A For example, it may be or include epitaxially grown silicon germanium. For forming the semiconductor material 50A For example, a mask layer (not shown), which may be a photosensitive layer, such as a photoresist, over the substrate 50 using chemical vapor deposition (CVD), physical vapor deposition (PVD), spin coating, or other suitable deposition method. The mask layer is then patterned using, for example, photolithography and / or patterning techniques. The structured mask layer covers the area 200 , but sets the area 300 free. An exposed section of the substrate 50 in that area 300 is then removed by a convenient etch process, such as Reactive Ion Etch (RIE), Neutral Beam Etching (NBE), or a combination thereof, around a depression (not shown) in the region 300 to build.

Thereafter, an epitaxy is performed to the semiconductor material 50A in the wells of the area 300 grow up. The epitaxially grown semiconductor material 50A can be doped in situ during growth, which may obviate the need for prior and subsequent implantation, although in situ and implant doping can be shared. After epitaxy, the masking layer may be removed by a convenient removal process, such as etching or plasma ashing. A planarization process, such as chemical mechanical polishing (CMP), may then be performed to form the top surface of the semiconductor material 50A with the upper surface of the substrate 50 match. 3B shows a cut surface 63 between the semiconductor material 50A and the substrate 50 that, as in 3B illustrated, may or may not be a straight line.

Optionally, another patterned mask layer (not shown) may be formed around the region 300 cover while the area 200 is exposed, and an exposed portion of the substrate 50 in that area 200 can be removed and with an epitaxially grown semiconductor material 50B , this in 3B dashed lines, to be replaced. A cut surface 63 ' can be between the semiconductor material 50B (if it is formed) and the substrate 50 be formed. The semiconductor material 50B For example, an epitaxial semiconductor material that is capable of forming a corresponding device type (eg, an N-type device) in the region 200 is suitable, be or include. The semiconductor material 50B For example, it may be or include epitaxially grown silicon carbide.

In other embodiments, the semiconductor material replaces 50B (For example, an epitaxial semiconductor material) a portion of the substrate 50 in that area 200 , and a portion of the substrate 50 in that area 300 can be optional with the semiconductor material 50A (For example, an epitaxial semiconductor material) are replaced. In yet other embodiments, the epitaxial semiconductor materials described above (for example 50A and 50B ), so that the processing in the 3A and 3B is illustrated, can be omitted. The following discussion uses an embodiment configuration for the substrate 50 in which the semiconductor material 50A in that area 300 is formed, and the semiconductor material 50B in that area 200 is not formed, it being understood that the processing illustrated in the present disclosure can also be applied to other substrate configurations such as those described. In the following discussion becomes substrate 51 used to on the substrate 50 and the semiconductor materials 50A / 50B if they are made to reference.

The semiconductor materials 50A or 50B (For example, epitaxial semiconductor materials) may have a lattice constant which is greater than, substantially equal to or less than the lattice constant of the substrate 50 , The lattice constant of the semiconductor materials 50A or 50B is determined by the material (s) selected from the conductivity types (eg, N-type or P-type) of the resulting FinFETs. Further, it may be advantageous to epitaxially grow a material in an NMOS region that is different than the material in a PMOS region. In various embodiments, the semiconductor materials (for example 50A . 50B ) Silicon germanium, silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, an II-VI compound semiconductor or the like. For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Then, as in the 4A to 4C illustrates, the substrate becomes 51 structured to semiconductor fins 64 (also called Finns) to form. 4A illustrates a top view of the FinFET device 100 after the Finns 64 were formed. The 4B and 4C illustrate cross-sectional views of the FinFET device 100 in 4A each along cross sections FF and EE , As in 4A illustrated, includes each fin 64 a section 64A in that area 200 and a section 64B in that area 300 , The section 64A and the section 64B can be formed in a same processing step (for example, a same patterning process), details of which are described below with reference to FIGS 4B and 4C are described.

With reference to the 4B and 4C becomes the substrate 51 structured using lithography and etching techniques, for example. For example, a mask layer, such as a pad oxide layer (not shown) and an overlying pad nitride layer (not shown), is deposited over the substrate 51 educated. The pad oxide layer may be a thin film comprising silicon oxide formed using, for example, a thermal oxidation process. The pat oxide layer may act as an adhesive layer between the substrate 51 and the overlying pad nitride layer act. In some embodiments, the pad nitride layer is formed of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, or the like, or a combination thereof, and may be formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (plasma Enhanced Chemical Vapor Deposition - PECVD) can be formed as examples.

The mask layer may be patterned using photolithography techniques. In general, photolithography techniques employ a photoresist (not shown) which is deposited, irradiated (exposed), and developed to remove a portion of the photoresist. The remaining photoresist protects the underlying material, as in this example the mask layer, before subsequent processing steps, such as etching. In this example, the photoresist is used to pattern the pad oxide layer and the pad nitride layer to form a patterned mask 58 to build. As in the 4B and 4C illustrates the structured mask 58 structured pad oxide 52 and structured pad nitride 56 on.

The textured mask 58 is subsequently used to the substrate 51 to structure around trenches 61 to form, thereby semiconductor fines 64 between adjacent trenches, as in the 4B and 4C to be defined. Every semiconductor fin 64 has a section 64A (please refer 4A) in that area 200 (for example in an NMOS area) and a section 64B (please refer 4A) in that area 300 (for example in a PMOS area). The section 64A can be used to form, for example, an N-type FinFET, and the section 64B can be used to form, for example, a P-type FinFET. At the following meeting, the section 64A the Finnish man 64 fin 64A be called, and the section 64B the Finnish man 64 can a Finn 64B to be named.

In some embodiments, the semiconductor fins become 64 by etching trenches in the substrate 51 for example, using Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or a combination thereof. The etching can be anisotropic. In some embodiments, the trenches may be strips (in plan view) spaced parallel and closely spaced from one another. In some embodiments, the trenches may be continuous and the semiconductor fins 64 surround.

Finns 64 can be structured by any convenient method. Finns 64 For example, they can be patterned using one or more photolithographic processes, including double structuring or multiple structuring processes. In general, dual structuring or multiple structuring processes combine photolithography and self-aligned processes that allow structures to be created that, for example, have distances smaller than those that can otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

As mentioned, an upper portion of the substrate becomes 50 in that area 300 through the semiconductor material 50A replaced. Depending on where the bottom of the trenches 61 to the cut surface 63 between the semiconductor material 50A and the substrate 50 (For example, at the interface 63 , above the cut surface 63 or below the cut surface 63 ), the Finns can 64B thus having one or more materials. In the example of 4C The bottom of the trenches extends 61 under the cut surface 63 , and the Finn 64B thus has a first section over the cut surface 63 made of the semiconductor material 50A (For example, silicon germanium) is formed, and a second section below the cut surface 63 made of the material (for example silicon) of the substrate 50 is formed. The Finn 64A is completely made of the material (for example silicon) of the substrate 50 in the illustrated example of 4B educated. In other embodiments, the bottom of the trenches extends 61 above or at the cut surface 63 , and the Finn 64B is therefore completely made of the semiconductor material 50A (for example, silicon germanium) formed, and the fin 64A is completely made of the material (for example silicon) of the substrate 50 educated.

Variations in the structure and method of education of the Finns 64 are possible and are considered to be fully within the scope of the present disclosure. Although the 4A to 4C making two Finns 64 illustrate, more or less than two fins can be formed. As another example, the Finns 64 by etching the substrate 50 to form a first plurality of fins (at least portions of which are removed and replaced in subsequent processing), forming an insulating material around the first plurality of fins, removing portions (for example, portions in the region 300 ) of the first plurality of fins for forming recesses in the insulating material, and epitaxially growing semiconductor material (s) in the recesses to form the fins 64 be formed.

As in the 5A to 5F illustrated, then isolation areas 62 above the substrate 50 and on opposite sides of the fins 64 formed, and dummy gate structures 75 (for example 75A and 75B ) are about the Finns 64 educated. 5A is a plan view of the FinFET device 100 , and the 5B and 5C FIG. 15 are cross-sectional views of the FinFET device. FIG 100 in 5A in each case along cross sections FF and EE , The 5D and 5E FIG. 15 are cross-sectional views of the FinFET device. FIG 100 in 5A in each case along cross sections HH and GG , and 5F is a cross-sectional view of the FinFET device 100 in 5A along the cross section II.

With reference to the 5B and 5C become isolation areas 62 by filling the trenches 61 formed with an insulating material and deepening of the insulating material. The insulation material 54 may be an oxide, such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g. CVD-based material deposition in a remote plasma system and post-curing may be formed to make it convert to another material such as an oxide), the like, or a combination thereof. Other insulation materials and / or formation processes may be used. A planarization process, such as a CMP, can remove excess insulating material and an upper surface of the insulating material and upper surfaces of the semiconductor fins 64 form coplanar (not shown). The textured mask 58 (please refer 4B and 4C) can be removed through the CMP process.

In some embodiments, the isolation areas 62 a liner, for example a liner oxide (not shown) at the interface between the isolation regions 62 and the substrate 50 / the Finns 64 on. In some embodiments, the liner oxide is formed to provide crystalline imperfections at the interface between the substrate 50 and the isolation areas 62 to reduce. Similarly, the liner oxide can also be used to eliminate crystalline defects at the interface between the semiconductor fins 64 and reduce the isolation areas. The liner oxide (for example, silicon oxide) may be a thermal oxide obtained by thermal oxidation of a surface layer of the substrate 50 and / or the Finns 64 although any convenient method can be used to form the liner oxide.

Thereafter, the insulation material is recessed to isolation areas 62 such as shallow trench isolation (STI) regions. The insulating material is recessed such that the upper portions of the semiconductor fins 64A / 64B between adjacent isolation areas 62 protrude. The upper surfaces of the isolation areas 62 may have a flat surface (as illustrated), a convex surface, a concave surface (such as a dishing), or a combination thereof. The upper surfaces of the isolation areas 62 may be formed flat, convex and / or concave by proper etching. The isolation areas 62 can be recessed using an acceptable etch process, such as that with respect to the material of the isolation regions 62 is selective. For example, chemical oxide removal using a CERTAS® etch or Applied Material SICONI tool or dilute hydrofluoric acid (dHF) may be used.

The 5A to 5C illustrate forming a dummy gate structure 75 over the semiconductor fins 64 , The dummy gate structure 75 has a gate dielectric in some embodiments 66 and a gate 68 on. To form the dummy gate structure 75 becomes a dielectric layer on the semiconductor fins 64 (for example 64A and 64B ) and the isolation areas 62 educated. The dielectric layer may be, for example, silicon oxide, silicon nitride, multiple layers thereof, or the like, and may be deposited (as illustrated) or grown thermally according to acceptable techniques (not shown). The dielectric layer formation methods may include Molecular Beam Deposition (MBD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and the like.

A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized by, for example, a CMP. The mask layer may over the gate layer 60 be deposited. The gate layer may be formed of polysilicon, for example, although other materials may be used. The mask layer may be formed of silicon nitride or the like, for example.

After the layers (eg, the dielectric layer, the gate layer, and the mask layer) have been formed, the mask layer may be patterned using acceptable photolithography and etching techniques to form a mask 70 to build. The structuring of the mask 70 is then transferred to the gate layer and the dielectric layer by an acceptable etching technique, to each gate 68 and the gate dielectric 66 to form, and the gate 68 and the gate dielectric 66 cover respective channel regions of the semiconductor fins in some embodiments 64 from. In other embodiments, the patterning of the mask 70 transferred to the gate layer to the gate 68 but not transferred to the dielectric layer. In other words, in some embodiments, the dielectric layer is not removed from the mask 70 structured, in which case the dielectric layer is the gate dielectric 66 or the dielectric layer 66 can be called. The following discussion uses the example where the dielectric layer is not covered by the mask 70 However, the concept of the present disclosure also applies to embodiments in which the dielectric Layer of the mask 70 is structured. The gate 68 may be a longitudinal direction substantially perpendicular to the longitudinal direction of the respective semiconductor fins 64 respectively. As in 5A illustrates the gate structure 75A over the Finn 64A in area 200 formed, and the gate structure 75B will be over the Finn 64B in that area 300 educated.

The 5D and 5E 12 illustrate cross-sectional views of the FinFET device 100 of FIG 5A each along a cross section HH and GG , The gate structures 75A and 75B may not be visible in this section. In the example of 5E the cut surface extends 63 farther from an upper main surface 50U of the substrate 50 as an upper surface 62U the isolation areas 62 ,

5F illustrates a cross-sectional view of the FinFET device 100 the 5A along the cross section II , As in 5F illustrates the gate structure 75A over the Finn 64A in that area 200 formed, and the gate structure 75B will be over the Finn 64B in that area 300 educated.

The 6A to 6C . 7A to 7C . 8A to 8C . 9A to 9C . 10A to 10C . 11A to 11C and 12A to 12C illustrate further processing of the FinFET device 100 that in the 5A to 5F is shown. In particular, they illustrate 6A . 7A . 8A . 9A . 10A . 11A and 12A Cross-sectional views of the FinFET device 100 along the cross section II (please refer 5A) at various stages of production. The 6B . 7B . 8B . 9B . 10B . 11B and 12B illustrate the corresponding cross-sectional views of the FinFET device 100 along the cross section HH (please refer 5A) , and the 6C . 7C . 8C . 9C . 10C . 11C and 12C illustrate the corresponding cross-sectional views of the FinFET device 100 along the cross section GG (please refer 5A) ,

Then, as in the 6A to 6C illustrates a first spacer layer 86 and a second spacer layer 84 one after the other over the structure, which in the 5A to 5F is illustrated formed. The first spacer layer 86 and the second spacer layer 84 can be made in shape. In some embodiments, the first spacer layer comprises 86 low-K dielectric material and can therefore be called a low-kappa spacer layer. The first spacer layer 86 may be formed of a suitable material such as silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN) or silicon carbonitride (SiCN). A strength of the first spacer layer 86 may be in a range between about 2 nm to about 5 nm. In some embodiments, the second spacer layer comprises a nitride-rich dielectric material. The second spacer layer 84 may be formed of a suitable material, such as silicon nitride (SiN) or silicon carbonitride (SiCN). A strength of the second spacer layer 84 may be in a range between about 3 nm to about 5 nm. Any suitable deposition method, such as PVD, CVD and ALD, may be used to form the first spacer layer 86 and the second spacer layer 84 to build.

In accordance with some embodiments, a first material of the first spacer layer becomes 86 from a second material of the second spacer layer 84 differently selected to etch selectivity between the first spacer layer 86 and the second spacer layer 84 upon subsequent processing. If the second spacer layer 84 For example, SiN is formed, the first spacer layer 86 SiOC, SiOCN or SiCN are formed. As another example, if the second spacer layer 84 For example, SiCN is formed, the first spacer layer 86 be formed from SiOC or SiOCN.

Then, as in the 7A to 7C 1, a mask layer, which may be a photosensitive layer such as a photoresist, is formed over the structure shown in FIGS 6A to 6C is formed using CVD, PVD, spin coating, or other suitable deposition method. The mask layer is then patterned using, for example, photolithography and / or patterning techniques to form a patterned mask 88 to build. The textured mask 88 covers the area 200 but sets the area 300 as in the 7A to 7C Illustrates, free. The textured mask 88 thus shields the area 200 from the subsequent etching processes described with reference to FIGS 8A to 8C and 9A to 9C are described from.

Then, as in the 8A to 8C 1, an etching process is performed to form portions of the second spacer layer 84 in that area 300 to remove. In some embodiments, the process is to remove portions of the second spacer layer 84 is used, an anisotropic etching process, such as a dry etching process. A plasma etching process using carbon monoxide (CO), tetrafluoromethane (CF ₄ ), oxygen (O ₂ ), ozone (O ₃ ), or combinations thereof may be performed to remove the exposed second spacer layer 84 in that area 300 (for example, a PMOS area). In some embodiments, the plasma etching process has a high etch selectivity (has, for example, a higher Etch rate) for the second spacer layer 84 over the first spacer layer 86 on. In some embodiments, the plasma (eg, CF ₄ plasma) used in the plasma etching process reacts with the second spacer layer 84 to the second spacer layer 84 to remove. In some embodiments, the anisotropic etch process removes the second spacer layer 84 over an upper surface and side walls of the fins 64B (please refer 8C) so that the first spacer layer 86 above the upper surface and the side walls of the fins 64B is exposed. The anisotropic etching process may also include upper portions of the first spacer layer 86 in that area 300 remove. As in 8A illustrates, the etching process removes portions of the second spacer layer 84 and portions of the first spacer layer 86 over the top surface of the gate structure 75B (for example, over the mask 70 ), leaving the mask 70 is exposed. In addition, the first spacer layer 86 above the upper surface of the fins 64B diluted (see 8A) or removed (not shown).

Due to the anisotropy of the plasma etching process (for example, DC bias is used) and / or due to the by-product (for example, polymer) attached to the sidewalls of the gate structure 75B is formed during the plasma etching process, remain portions of the second spacer layer 84 (for example 84R ) along the sidewalls of the gate structure 75B (for example, due to the protection provided by the by-product of the plasma etching process) after the plasma etching process, as in FIG 8A illustrated. The remaining sections 84R the second spacer layer 84 along the sidewalls of the gate structure 75B advantageously protect portions of the first spacer layer 86 that between the remaining sections 84R and the gate structure 75B are arranged, before a subsequent etching process, so that the portions of the first spacer layer 86 between the remaining sections 84R and the gate structure 75B remain after the subsequent etching process to act as a gate spacer of the gate structure 75B to serve.

In an exemplary embodiment, the anisotropic etch process is a plasma etch process that includes a first plasma etch followed by a second plasma etch. The first plasma etching step is carried out using tetrafluoromethane (CF ₄ ), and the second plasma etching step is performed using oxygen (FIG. 02 ). In some embodiments, the first plasma etching step may produce byproducts such as polymer, where the polymer is the top surface and the sidewalls of the gate structure 75B covering, and therefore advantageously damage (for example, etching the side walls of the gate structure) to the gate structure 75B reduced or prevented during the first plasma etching step. After the first plasma etching step, the O 2 plasma used in the second plasma etching step removes the by-product generated by the first plasma etching step.

In some embodiments, the first plasma etching step and the second plasma etching step of the plasma etching process are performed at a same temperature and under a same pressure. In some embodiments, a temperature of the plasma etching process is in a range between about 30 ° C to about 65 ° C, and a pressure of the plasma etching process is in a range between about 4 millitorr (mTorr) to about 50 mTorr. A CF ₄ flow rate in the first plasma etching step may range between about 100 standard cubic centimeters per minute (sccm) to about 200 sccm. An O ₂ flow rate in the second plasma etching step may be in a range between about 100 sccm to about 200 sccm. Carrier gas, such as nitrogen, argon or the like, can be used to carry the plasma. Each cycle of the first plasma etching step may be performed for a duration in a range between about 5 seconds and about 15 seconds. Each cycle of the second plasma etching step may be performed for a duration in a range between about 5 seconds and about 15 seconds. The number of cycles in the first plasma etching step and the second plasma etching step may be, for example, the thickness of the spacer layer (for example 84 ), which is to be removed.

Then, as in the 9A to 9C illustrates another etching process is performed to sections of the first spacer layer 86 in that area 300 to remove. In some embodiments, the other etching process is to remove the first spacer layer 86 is used, a wet etching process, for example, a chemical etching process using an etchant. The etchant may have a high etch selectivity (eg, a higher etch rate) for the first spacer layer 86 compared to the second spacer layer 84 respectively. The first spacer layer 86 thus, without essentially the second spacer layer 84 (for example 84R ) to be removed. A wet etching process which includes, for example, dilute hydrofluoric acid (dHF), hydrogen peroxide (H ₂ O ₂ ), ozone (O ₃ ), phosphoric acid (H ₃ PO ₄ ), a standard (STD) purification fluid (which is a deionized Water (DIW), ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ )) or combinations thereof, may be carried out to remove the exposed first spacer layer 86 in that area 300 to remove. In some embodiments, the wet etching process removes the exposed first spacer layer 86 in that area 300 completely, leaving a top surface 64BU the Finns 64B and the side walls of the Finns 64B (For example, the side walls of the Finns 64B above the upper surface 62U the isolation areas 62 ) are exposed after the wet etching process, as in 9C illustrated. It should be noted that due to the remaining section 84R the second spacer layer 84 Sections of the first spacer layer 86 along the sidewalls of the gate structure 75B remain after the wet etching process.

In some embodiments, the wet etching process includes a first step, a second step, a third step, and a fourth step that are performed sequentially. In other words, the second step of the wet etching process is performed after the first step of the wet etching process, the third step of the wet etching process is performed after the second step of the wet etching process, and the fourth step of the wet etching process is performed after the third step of the wet etching process. Specifically, the first step is carried out using a mixture using hydrogen peroxide (H ₂ O ₂ ) and ozone (O ₃ ), the second step is carried out using dilute hydrofluoric acid (dHF), the third step is carried out using phosphoric acid (H ₃ PO ₄ ), and the fourth step is carried out using the STD cleaning fluid, which is a mixture comprising deionized water (DIW), ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). By performing the first step of the second step, the third step, and the fourth step as described above, the removing process of the first spacer layer may be performed 86 be precisely controlled.

Then, as in the 10A to 10C illustrates epitaxial source / drain regions 80B over the exposed upper surface 64BU (please refer 9C) and the exposed sidewalls of the Finns 64B using appropriate methods such as Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), selective epitaxial growth (SEG), the like or a combination thereof. The epitaxial source / drain regions 80B may have surfaces that overlie respective top surfaces of the fins 64B are elevated, and may have facets. As in 10C illustrates, the source / drain regions unite 80B the neighboring Finns 64B to form a continuous epitaxial source / drain region 80B to build. After the epitaxial source / drain regions 80B Shaped, becomes the textured mask 88 using a convenient process, such as ashing away.

Although that in the 10A to 10C not illustrated in the Finns 64B lightly doped drain (Light Doped Drain - LDD) regions are formed before the epitaxial source / drain regions 80B be formed. LDD regions can be formed by a plasma doping process. The plasma doping process may have a corresponding type of contaminants, such as P-type impurities (for P-type devices), in the fins 64B implant to form the LDD areas. The textured mask 88 For example, the area 200 (For example, an NMOS region) while shielding P-type impurities in the LDD areas of the fins 64B be implanted.

In some embodiments, the resulting FinFET is in the range 300 a P-type FinFET, the source / drain regions 80B include SiGe and a P-type impurity such as boron or indium. The epitaxial source / drain regions 80B can be implanted with dopants followed by annealing. The source / drain regions 80B may have an impurity (for example dopant) concentration in a range of about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . In some embodiments, the epitaxial source / drain regions 80B be doped in situ during growth.

The epitaxial source / drain regions 80B be directly on the exposed upper surface 64BU (please refer 9C) and on the exposed side walls of the Finns 64B educated. This is from the process of forming the epitaxial source / drain regions 80A referring to the below with reference to the 11A to 11C is discussed, different. The epitaxial source / drain regions 80B formed by the processing in the present disclosure are called a cladding epitaxial structure.

Due to the multi-layered structure (for example, first spacer layer 86 and the second spacer layer 84 ) for the spacer layers and because of the specific etching process (for example, dry etching followed by wet etching, as discussed above) which is disclosed, the first spacer layer becomes 86 and the second spacer layer 84 above the upper surface and the side walls of the fins 64B completely removed. As a result, the epitaxial source / drain regions 80B have a larger volume, resulting in improved device performance, such as lower drain-induced barrier loss (DIBL), higher ON current I _on , lower contact resistance for subsequently formed source / drain Contacts, and improved component reliability as examples. In addition, damage to the gate structure 75B and the Finns 64B reduced. For example, a fin top loss is reduced, damaging (eg, etching) the sidewalls of the fins 64B is reduced, and the critical dimension (CD) of the Finns 64B is better controlled. As another example, there are portions of the first spacer layer 86 and the second spacer layer 84 (for example 84R ) on the sidewalls of the gate structure 75B remain after the above-disclosed etching process, damage to the gate structure 75B reduces or prevents, and the strength of the gate structure 75B is well controlled. Furthermore, the structure and method disclosed herein reduce the loading effect between inner portions (eg, portions between adjacent fins 64B ) of the isolation areas 62 and outer sections (for example, sections that are not between adjacent fins 64B lie) of the isolation areas. By using the multilayered structure for the spacer layer and the specific etching process disclosed herein, a distance between an upper surface of the inner portions of the isolation regions 62 and an upper surface of the outer portions of the isolation regions 62 be reduced from 25 nm to 5 nm.

Below are in the 11A to 11C the second spacer layer 84 in that area 200 and the remaining section 84R the second spacer layer 84 in that area 300 using a convenient process, such as an etching process. A suitable etchant such as phosphoric acid (H ₃ PO ₄ ) can be used for the etching process. Subsequently, the first spacer layer 86 in that area 200 using, for example, an isotropic etch process to remove portions of the first spacer layer 86 over the top surface of the gate structure 75A and above the upper surface of the fins 64A structured. A patterned mask layer (not shown), such as a patterned photoresist, may be used to cover the area 300 cover during the first distance range 86 in that area 200 is structured. The patterned mask layer is then removed using a convenient method such as ashing. After structuring the first spacer layer 86 As described above, remaining portions of the first spacer layer become 86 (please refer 11A) like those along the sidewalls of the gate structures 75A and 75B , as the gate spacers (for example, low-K-gate spacers) of the corresponding gate structure used. The sections of the first spacer layer 86 along the sidewalls of the gate structures 75A and 75B can thus down spacers 86 to be named.

Then, although not illustrated, LDD regions can be found in the fins 64A are formed before the epitaxial source / drain regions 80A be formed. LDD regions can be formed by a plasma doping process. The plasma doping process may have a corresponding type of contaminants, such as N-type impurities (for N-type devices) in the fins 64A implant to form the LDD areas. For example, some patterned masking layer (not shown) may be formed around the area 300 shield (for example, a PMOS region) while N-type impurities in the LDD regions of the fins 64A be implanted. The patterned masking layer can be removed after the LDD regions have been formed.

Then become epitaxial source / drain regions 80A in the Finns 64A educated. The epitaxial source / drain regions 80A can be done by etching the fins 64A (For example, etching the LDD regions within the fins 64A) for forming wells, and epitaxially growing a material in the well, using appropriate methods such as organometallic metalorganic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (LPE) VPE), selective epitaxial growth (SEG), the like, or a combination thereof.

As in 11A illustrates gaps 87 (for example, white space) between the source / drain regions 80B and the spacers 86 the gate structure 75B due to the removal of the remaining sections 84R (please refer 10A) the second spacer layer 84 be formed. The epitaxial source / drain regions 80B for example, from the spacers 86 through gaps 87 be spaced. The width of the gaps 87 can be determined by the width of the remaining sections 84R the second spacer layer 84 to be determined. The width of the gaps 87 may be between about 0 nm and 3 nm, for example, although other dimensions are possible. In contrast, the epitaxial source / drain region is affected 80A the spacers 86 the gate structure 75A physically, and thus, in some embodiments, there is no gap between the epitaxial source / drain region 80A and the spacers of the gate structure 75A , In some embodiments, there is a gap between the epitaxial source / drain regions 80B and the gate structure 75B greater than a distance between the epitaxial source / drain regions 80A and the gate structure 75A ,

As in the 11B illustrates, deepens the etching of the LDD regions within the fins 64A an upper surface 64AU the Finns 64A , The etching of the LDD region within the fins 64A can also be sections of the dielectric layer 66 that over the top surface 64AU is arranged as in 11B 4, although in other embodiments, the etching of the LDD region within the fins is removed 64A the dielectric layer 66 not removed. In the illustrated embodiment of the 11B lies the recessed upper surface 64AU above the upper surface 62U the isolation areas 62 , In other embodiments, the recessed upper surface of the fins may be 64A under (see for example 64AU ") or flush with (see for example 64AU ' ) of the upper surface 62U the isolation areas 62 lie. As in the 11B and 11C illustrates an upper surface extends 64BU the Finns 64B further from the upper surface 62U the isolation areas 62 away as the recessed upper surface 64AU / 64AU ' / 64AU " the Finns 64A , In some embodiments, the top surface 64BU is about 18 nm to about 23 nm higher (extending farther from the top surface, for example) 62U away) than the recessed upper surface 64AU / 64AU ' / 64AU " ,

With reference to 11B grows as a result of the etching of the LDD regions within the fins 64A a subsection of the epitaxial source / drain regions 80A in the recess between the first spacer layer 86 first. Once the well is filled, upper portions of the epitaxial source / drain regions become 80A over the Finn 64A formed and can combine to form continuous source / drain regions 80A to build. In some embodiments, a bottommost surface contacts 80AL the epitaxial source / drain regions 80A the recessed upper surface 64AU / 64AU / 64AU " the Finnish man 64A , as in 11B illustrated. In contrast, a bottom surface 80BL of the epitaxial source / drain regions 80B under the upper surface 64BU the Finnish man 64B , as in 11C illustrates lie. In some embodiments, the bottom surface is located 80AL the epitaxial source / drain regions 80A deeper (for example closer to the upper main surface 50U of the substrate 50 ) as the lowest surface 80BL the epitaxial source / drain regions 80B ,

As in the 11A and 11B illustrates, the epitaxial source / drain regions 80A having over respective surfaces of the fins 64A have raised surfaces (for example, over the non-recessed portions of the fins 64A raised) and can have facets. The source / drain regions 80A the neighboring Finns 64A can combine to form a continuous epitaxial source / drain region 80A to build. In some embodiments, the resulting FinFET is in the range 200 an N-type FinFET, and source / drain regions 80A include silicon carbide (SiC), silicon phosphorus (SiP), phosphorus doped silicon carbon (SiCP), or the like.

The epitaxial source / drain regions 80A can be implanted with dopants followed by annealing. The source / drain regions 80A may have an impurity (for example dopant) concentration in a range of about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . In some embodiments, the epitaxial source / drain regions may be doped in situ during growth.

As in the 12A to 12C illustrates, then a contact etch stop layer (CESL) 105 (for example, formatted) over the structure that in the 11A to 11C is formed and thereafter a first interface dielectric (ILD) is formed. 90 over the CESL 105 educated. The CESL may comprise any suitable material, such as TiN, and may be formed by any convenient method, such as PVD, CVD, or the like. In some embodiments, the first ILD 90 formed from a dielectric material such as silicon oxide, phosphorous glass (PSG), boron doped silicon glass (BSG), and undoped silicate glass (USG) or the like, and may be formed by any convenient method, such as CVD, PECVD or FCVD. A planarization process, such as a CMP process, may be performed to the top surface of the first ILD 90 planarize, leaving the top surface of the first ILD 90 with the upper surface of the gate 68 is at the same level. The mask 70 (please refer 11A) , Sections of the first spacer layer 86 and sections of CESL 105 over the upper surface of the gate 68 can be removed through the CMP process. Thus, in some embodiments, after the CMP process, in some embodiments, the top surface of the gate is 86 exposed. In the example of 12B and 12C There is an air gap between the epitaxial source / drain region 80A (or 80B ) and the underlying isolation areas 62 ,

The 13 to 16 illustrate cross-sectional views of the FinFET device 100 in further processing steps along the cross-section II , As in 13 1, a gate-load process (occasionally replacement gate process) is performed. In a gate-load process, the gate 68 and the gate dielectric 66 (please refer 12A) are considered as dummy structures and are removed and having an active gate (also called a spare gate) and an active gate Replaced gate dielectric. In some embodiments, the active gate is a metal gate.

With reference to 13 become the gate 68 and the gate dielectric 66 directly under the gate 68 at one or more etching steps, so that recesses (not shown) between respective spacer layers 86 be formed. The pits are formed by subsequently forming a gate dielectric layer 96 , a barrier layer 94 , a germ layer 92 and a gate electrode 98 filled in the wells.

In some embodiments, the gate dielectric layer becomes 96 formally formed in the depressions. The gate dielectric layer 96 may have silicon dioxide. The silica may be formed by convenient oxidation and / or deposition techniques. In some embodiments, the gate dielectric layer is 96 a high-K dielectric layer such as hafnium oxide (HfO ₂ ). Alternatively, the high-K dielectric layer may comprise other high-K dielectrics, such as TiO ₂ , HfZrO, Ta ₂ O ₃ , HfSiO ₄ , ZrO ₂ , ZrSiO _2, combinations thereof, or other suitable material. The high-K dielectric layer may be formed by ALD, PVD, CVD or other suitable methods.

Then a barrier layer 94 conformally over the gate dielectric layer 96 educated. The barrier layer 94 may prevent or reduce outdiffusion of the material of a subsequently formed gate electrode (for example, 98). The barrier layer 94 may include a conductive material such as titanium nitride, although other materials such as tantalum nitride, titanium, tantalum or the like may alternatively be used. The barrier layer may be formed using a CVD process, such as plasma-enhanced CVD (PECVD). Other alternative processes, such as sputtering or metal organic chemical vapor deposition (MOCVD), ALD, may alternatively be used.

Then a germ layer 92 conformally over the dielectric barrier 94 educated. The seed layer may include copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof and may be atomic layer deposition (ALD), sputtering, physical vapor deposition (Physical Vapor Deposition - PVD) or the like are deposited. In some embodiments, the seed layer is a metal layer that comprises a single layer or a composite layer that includes a plurality of sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer.

Then, a conductive material is formed over the seed layer to fill the recesses to the gate electrode 98 to build. The conductive material may include tungsten, although other useful materials such as aluminum, copper, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys thereof, combinations thereof, and the like may alternatively be employed. The conductive material may be formed by electroplating, PVD, CVD or any convenient deposition method. A planarization process, such as a CMP, may be performed to cover excess portions of the gate dielectric layer 96 , the barrier layer 94 , the germ layer 92 and the gate electrode 98 For example, remove excess sections above the top surface of the first ILD 90 are arranged. The remaining portions of the gate dielectric layer 96 , the barrier layer 94 , the germ layer 92 and the gate electrode 98 in the depressions form the replacement gates 97 of the FinFET device 100 ,

Then, referring to 14 a second ILD 95 over the first ILD 90 deposited. In one embodiment, the second is ILD 95 a flowable film formed by a flowable CVD process. In some embodiments, the second ILD becomes 95 is formed of a dielectric material such as PSG, BSG, BPSG, USG or the like, and may be deposited by any convenient method such as CVD and PECVD. contact openings 91 and 93 for contact plugs 102 (please refer 16 ) be through the first ILD 90 and / or the second ILD 95 educated. The contact opening 91 for example, by the second ILD 95 formed and sets the replacement gate 97 free while the contact openings 93 through the first ILD 90 and the second ILD 95 be formed and source / drain areas 80A / 80B uncover.

Then be in 15 silicide 82 in the source / drain regions 80A / 80B formed, and a barrier layer 104 is over the silicide areas 82 and the second ILD 95 educated. In some embodiments, the silicide areas become 82 by depositing over the source / drain regions 80A / 80B of a metal capable of reacting with semiconductor materials (for example, silicon, germanium) to form silicide or germanide regions. The metal may be nickel, cobalt, titanium, tantalum, platinum, tungsten or other precious metals, other refractory metals, rare earth metals or their alloys. A thermal annealing process is then performed such that the deposited metal is in contact with the source / drain regions 80A / 80B reacts to Silicide regions 82 to build. After the thermal annealing process, metal that has not reacted is removed.

The barrier layer 104 is formatted over the silicide areas 82 and the second ILD 95 formed and covers sidewalls and grounds of contact openings 91 / 93 , The barrier layer 104 may comprise an electrically conductive material such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or the like, and may be formed using a CVD process such as plasma enhanced CVD (PECVD). Other alternative processes, such as sputtering or metalorganic chemical vapor deposition (MOCVD), Physical Vapor Deposition (PVD) atomic layer deposition (ALD) may alternatively be used.

Then it will be in 16 a germ layer 109 above the barrier layer 104 formed, and an electrically conductive material 110 becomes over the germ layer 109 educated. The germ layer 109 may be deposited by PVD, ALD or CVD and may be formed from tungsten, copper or copper alloys, although other convenient methods and materials may alternatively be used.

Once the germ layer 109 was formed, the conductive material 110 on the germ layer 109 be formed to the contact openings 91 / 93 to fill. The conductive material 110 For example, tungsten may include, although other useful materials such as aluminum, copper, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys thereof, combinations thereof, and the like may alternatively be employed. Any convenient deposition method, such as PVD, CVD, ALD, electroplating (e.g., electroplating), and reflow, may be used to form the conductive material 110 be used.

Once the contact openings 91 / 93 could be filled, excess barrier layer 104 , Germ layer 109 and excess conductive material 110 outside the contact openings 91 / 93 by a planarization process, such as CMP, although any convenient removal process can be used. contact plugs 102 are therefore in the contact openings 91 / 93 educated. Although contact plugs 102 over the source / drain regions 80A / 80B and over the replacement gate 97 in a same cross section in 16 Illustrated are the contact plugs 102 in different cross sections in the FinFET device 100 his.

17 FIG. 12 illustrates a flowchart of a method of forming a semiconductor device in accordance with some embodiments. You have to understand that in 17 The execution method shown is only one example of many possible execution methods. One of ordinary skill in the art would recognize many variations, alternatives and changes. Various steps, like in 17 can be added, removed, replaced, rearranged, and repeated, for example.

With reference to 17 becomes at step 1010 a first fin projecting above a substrate, the first fin having a PMOS region and an NMOS region. At step 1020 For example, a first gate structure is formed over the first fin in the PMOS region. At step 1030 a first spacer layer is formed over the first fin and the first gate structure. At step 1040 a second spacer layer is formed over the first spacer layer. At step 1050 For example, a first etching process is performed to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region. At step 1060 For example, a second etching process is performed to remove the first spacer layer from the top surface and sidewalls of the first fin in the PMOS region. At step 1070 For example, a first source / drain material is epitaxially grown over the first fin in the PMOS region, with the first source / drain material extending along the top surface and sidewalls of the first fin in the PMOS region.

Embodiments can achieve advantages. The disclosed multi-layered spacer structure with the first spacer layer 86 and the second spacer layer structure 84 together with the disclosed etching process (for example, dry etching followed by wet etching) removes the spacer layers (for example 84 and 86 ) from the top surface and side walls of the fins 64B while portions of the spacer layers on the sidewalls of the gate structure 75B to be kept. The mantle epitaxy structure (for example 80B ) becomes on the upper surface and the side walls of the Finns 65B formed with a large volume, resulting in improved device performance, such as lower drain-induced blocking loss (DIBL), higher ON current I _on , lower contact resistance, and improved device reliability. In addition, damage to the gate structure 75B and the Finns 64B which results in better control of the profile of the formed FinFET device. Furthermore, the charging effect becomes between inner portions of the isolation areas 62 and outer sections of the isolation areas 62 reduced. Another advantage is improved PMOS channel stress due to the cladding Epitaxial structure enabled by the present disclosure.

In an embodiment, a method comprises forming a first fin projecting above a substrate, the first fin having a PMOS region; forming a first gate structure over the first fin in the PMOS region; forming a first spacer layer over the first fin and the first gate structure; forming a second spacer layer over the first spacer layer; performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and sidewalls of the first fin in the PMOS region; and epitaxially growing a first source / drain over the first fin in the PMOS region, wherein the first source / drain extends along the top surface and sidewalls of the first fin in the PMOS region. In one embodiment, the first spacer layer and the second spacer layer are formed of different materials. In one embodiment, performing the first etching process includes performing an anisotropic etch process. In one embodiment, after performing the first etching process, the first spacer layer over the top surface and the sidewalls of the first fin is exposed in the PMOS region, and a remaining portion of the second spacer layer extends along sidewalls of the first gate structure and first spacer layer is between the remaining portion of the second spacer layer and the first gate structure. In one embodiment, the second etch process exposes the top surface and sidewalls of the first fin in the PMOS region. In one embodiment, performing the first etching process comprises performing a plasma etching process, the plasma etching process comprising a first plasma etching step and a second plasma etching step, wherein the first plasma etching step is performed using tetrafluoromethane (CF ₄ ) , and the second plasma etching step is performed using oxygen (O ₂ ). In one embodiment, performing the second etching process includes performing a chemical etching process, wherein the chemical etching process comprises a first step, a second step, a third step, and a fourth step performed sequentially. In one embodiment, the first step is performed using a mixture that uses hydrogen peroxide (H ₂ O ₂ ) and ozone (O ₃ ), the second step is performed using dilute hydrofluoric acid (dHF), the third step is using phosphoric acid (H ₃ PO ₄ ), and the fourth step is carried out using the STD cleaning fluid, which is a mixture comprising deionized water (DIW), ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). In one embodiment, the first fin further comprises an NMOS region, the method further comprising forming a second gate structure over the first fin in the NMOS region, wherein the first spacer layer and the second spacer layer are over the second gate structure forming a patterned mask layer to cover the NMOS region prior to performing the first etching process; and removing the patterned mask layer after epitaxially growing the first source / drain material. In one embodiment, after the epitaxial growth of the first source / drain material, the method further comprises removing remaining portions of the second spacer layer in the PMOS region and the NMOS region; and epitaxially growing a second source / drain over the first fin in the NMOS region. In an embodiment, epitaxially growing the second source / drain material comprises removing a portion of the first spacer layer to expose an upper surface of the first fin in the NMOS region; deepening the upper surface of the first fin in the NMOS region; and epitaxially growing the second source / drain material over the recessed top surface of the first fin in the NMOS region.

In an embodiment, a method includes forming a fin projecting above a substrate, the fin having a PMOS region and an NMOS region; forming a first gate over the fin in the PMOS region; forming a second gate over the fin in the NMOS region; forming a first spacer layer over the fin, the first gate and the second gate; forming a second spacer layer different from the first spacer layer over the first spacer layer; forming a patterned mask layer to cover the NMOS region while leaving the PMOS region exposed; and after forming the patterned mask layer, performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the fin in the PMOS region, thereby exposing the top surface and side walls of the fin in the PMOS region; and epitaxially growing a first semiconductor material along the top surface and the sidewalls of the fin in the PMOS area. In one embodiment, the first spacer layer is formed using a material selected from the group consisting essentially of silicon oxycarbide, silicon oxycarbonitride, and silicon carbonitride, and wherein the second spacer layer is formed using a material selected from the group consisting of which consists essentially of silicon nitride and silicon carbonitride. In one embodiment, the first etching process includes a dry etching process, and the second etching process includes a wet etching process. In one embodiment, performing the first etching process includes performing a plasma etching process using carbon monoxide, tetrafluoromethane, oxygen, or ozone. In one embodiment, after the epitaxial growth of the first semiconductor material, the method further comprises removing the patterned mask layer; deepening a top surface of the fin in the NMOS region; and epitaxially growing a second semiconductor material over the recessed upper surface of the fin in the NMOS region.

In one embodiment, a semiconductor device includes a fin projecting above a substrate, the fin having a first portion and a second portion, wherein the first portion is in a PMOS region and the second portion is in an NMOS region ; a first gate structure over the first portion of the fin in the PMOS region; a second gate structure over the second portion of the fin in the NMOS region; first epitaxial source / drain regions on opposite sides of the first gate structure and over the first portion of the fin, the first epitaxial source / drain regions being in the PMOS region and extending along a first top surface and first sidewalls extend the first portion of the fin; and second epitaxial source / drain regions on opposite sides of the second gate structure and over the second portion of the fin, wherein the second epitaxial source / drain regions in the NMOS region and over a second top surface of the second region Finn are in the NMOS range. In one embodiment, a bottom surface of the second epitaxial source / drain regions contacts the second top surface of the second portion of the fin in the NMOS region. In one embodiment, the semiconductor device further includes first spacers on opposite sidewalls of the second portion of the fin in the NMOS region, and opposite sidewalls of the first portion of the fin in the PMOS region are free of first spacers. In one embodiment, the first upper surface of the first portion of the fin extends farther from the substrate than the second upper surface of the second portion of the fin.

The above outlines the features of several embodiments such that those skilled in the art will better understand the aspects of the present disclosure. One skilled in the art should appreciate that he may readily use the present disclosure as a basis for designing or changing other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. One skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that it can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 62592871 [0001]

Claims (20)

A method comprising: Forming a first fin protruding over a substrate, the first fin having a PMOS region; Forming a first gate structure over the first fin in the PMOS region; Forming a first spacer layer over the first fin and the first gate structure; Forming a second spacer layer over the first spacer layer; Performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the first fin in the PMOS region; Performing a second etching process to remove the first spacer layer from the top surface and sidewalls of the first fin in the PMOS region; and epitaxially growing a first source / drain material over the first fin in the PMOS region, the first source / drain material extending along the top surface and sidewalls of the first fin in the PMOS region. Method according to Claim 1 wherein the first spacer layer and the second spacer layer are formed of different materials. Method according to Claim 1 or 2 wherein performing the first etching process comprises performing an anisotropic etch process. Method according to Claim 3 wherein, after performing the first etching process, the first spacer layer is exposed over the top surface and sidewalls of the first fin in the PMOS region, and a remaining portion of the second spacer layer extends along sidewalls of the first gate structure, and wherein the first spacer layer is between the remaining portion of the second spacer layer and the first gate structure. The method of any one of the preceding claims, wherein performing the second etching process exposes the top surface and sidewalls of the first fin in the PMOS region. The method of claim 1, wherein performing the first etching process comprises performing a plasma etching process, the plasma etching process comprising a first plasma etching step and a second plasma etching step, the first plasma etching step using tetrafluoromethane. CF ₄ ), and the second plasma etching step is carried out using oxygen (O ₂ ). The method of claim 1, wherein performing the second etching process comprises performing a chemical etching process, wherein the chemical etching process comprises a first step, a second step, a third step and a fourth step performed sequentially. Method according to Claim 7 wherein the first step is carried out using a mixture using hydrogen peroxide (H ₂ O ₂ ) and ozone (O ₃ ), the second step is carried out using dilute hydrofluoric acid (dHF), the third step using phosphoric acid (H ₃ PO ₄ ), and the fourth step is carried out using a mixture comprising deionized water (DIW), ammonium hydroxide (NH ₄ OH) and hydrogen peroxide (H ₂ O ₂ ). The method of any one of the preceding claims, wherein the first fin further has an NMOS region, the method further comprising: Forming a second gate structure over the first fin in the NMOS region, wherein the first spacer layer and the second spacer layer are formed over the second gate structure; Forming a patterned mask layer to cover the NMOS region before performing the first etching process; and Removing the patterned mask after epitaxially growing the first source / drain material. Method according to Claim 9 , further comprising: after epitaxially growing the first source / drain material, removing remaining portions of the second spacer layer in the PMOS region, and in the NMOS region; and epitaxially growing a second source / drain over the first fin in the NMOS region. Method according to Claim 10 wherein the epitaxial growth of the second source / drain material comprises: removing a portion of the first spacer layer to expose an upper surface of the first fin in the NMOS region; Deepening the upper surface of the first fin in the NMOS region; and epitaxially growing the second source / drain material over the recessed first surface of the first fin in the NMOS region. A method comprising: Forming a fin protruding over a substrate, the fin having a PMOS region and an NMOS region; Forming a first gate structure over the fin in the PMOS region; Forming a second gate structure over the fin in the NMOS region; Forming a first spacer layer over the fin, the first gate and the second gate; Forming a second spacer layer different from the first spacer layer over the first spacer layer; Forming a patterned mask layer to cover the NMOS region while leaving the PMOS region exposed; and after forming the patterned mask layer, performing a first etching process to remove the second spacer layer from a top surface and sidewalls of the fin in the PMOS region; Performing a second etching process to remove the first spacer layer from the top surface and the sidewalls of the fin in the PMOS region, thereby exposing the top surface and sidewalls of the fin in the PMOS region; and epitaxially growing a first semiconductor material along the top surface and sidewalls of the fin in the PMOS region. Method according to Claim 12 wherein the first spacer layer is formed using a material selected from the group consisting essentially of silicon oxycarbide, silicon oxycarbonitride and silicon carbonitride, and wherein the second spacer layer is formed using a material selected from the group consisting of consists essentially of silicon nitride and silicon carbonitride. Method according to Claim 12 or 13 wherein the first etching process comprises a dry etching process, and the second etching process comprises a wet etching process. Method according to one of the preceding Claims 12 to 14 wherein performing the first etching process comprises performing a plasma etching process using carbon monoxide, tetrafluoromethane, oxygen or ozone. Method according to one of the preceding Claims 12 to 15 further comprising: after the epitaxial growth of the first semiconductor material, removing the patterned masking layer; Deepening an upper surface of the fin in the NMOS region; and epitaxially growing a second semiconductor material over the recessed first surface of the fin in the NMOS region. Semiconductor device comprising: a fin protruding over a substrate, the fin having a first portion and a second portion, the first portion being in a PMOS region and the second portion being in an NMOS region; a first gate structure over the first portion of the fin in the PMOS region; a second gate structure over the second portion of the fin in the NMOS region; first epitaxial source / drain regions on opposite sides of the first gate structure and over the first portion of the fin, the first epitaxial source / drain regions being in the PMOS region and extending along a first top surface and first sidewalls extend the first portion of the fin; and second epitaxial source / drain regions on opposite sides of the second gate structure and over the second portion of the fin, the second epitaxial source / drain regions in the NMOS region and over a second upper surface of the second portion of the fin in the NMOS range. Semiconductor device according to Claim 17 wherein a bottom surface of the second epitaxial source / drain regions contacts the second top surface of the second portion of the fin in the NMOS region. Semiconductor device according to Claim 17 or 18 further comprising first spacers on opposite sidewalls of the second portion of the fin in the NMOS region, and opposite sidewalls of the first portion of the fin in the PMOS region are free of first spacers. Semiconductor device according to one of the preceding Claims 17 to 19 wherein the first upper surface of the first portion of the fin extends farther from the substrate than the second upper surface of the second portion of the fin.

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