DE102018123485B4 - Method for separating a semiconductor component with a pn junction - Google Patents

Abstract

Method for separating a semiconductor component (1a, 1b) with a pn junction (4a, 4b), with the method steps:
A. Providing a semiconductor component (1a, 1b) which has at least one emitter (2a, 2b) and at least one base (3a, 3b), with a pn junction between emitter (2a, 2b) and base (3a, 3b) (4a, 4b) is formed,
B. Separating the semiconductor component (1a, 1b) into at least two sub-elements on at least one separating surface (T),
characterized,
that after method step B, a separating surface passivation layer (6a, 6b) is arranged on the separating surface (T), which is formed with stationary charges with a surface charge density in the amount greater than or equal to 10 ¹² cm ^-2 ,
that the interface passivation layer (6a, 6b) is formed as an aluminum oxide layer, as a silicon nitride layer or as a silicon oxynitride layer and
that the interface passivation layer (6a, 6b) is formed to cover the entire interface (T).

Description

The invention relates to a method for separating a semiconductor component with a pn junction according to claim 1.

• Fotovoltaische Module werden heute üblicherweise aus Silizium-Solarzellen mit einer Kantenlänge von ca. 156 mm hergestellt. Die Verschaltung erfolgt durch elektrisch leitende Verbindungen mittels leitenden Elementen - meist sogenannten Zellverbindern -, die jeweils Solarzellen alternierend auf Vorder- und Rückseite verbinden. Ein Nachteil dieser Verschaltung ist, dass der hohe Strom (bis ca. 10 A) der einzelnen Solarzellen eine sehr hohe Leitfähigkeit und somit hohe Leitungsquerschnitte der Zellverbinder voraussetzen.

In the production of semiconductor components, it is often desirable to separate (separate) a plurality of semiconductor components produced on a substrate by separating the substrate at at least one separating surface so that the semiconductor components are separated. Such a separation is necessary in the manufacture of computing processors, since a large number of computing processors are typically manufactured on a silicon wafer. In addition, the separation of photovoltaic solar cells is increasingly used:

• Today, photovoltaic modules are usually made from silicon solar cells with an edge length of approx. 156 mm. The interconnection takes place through electrically conductive connections using conductive elements - mostly so-called cell connectors - which alternately connect solar cells on the front and back. A disadvantage of this interconnection is that the high current (up to approx. 10 A) of the individual solar cells requires very high conductivity and thus high cable cross-sections of the cell connectors.

A known possibility of avoiding this disadvantage is to provide two or more solar cells on a silicon wafer in order to reduce the current per solar cell proportionally. These are only separated at the end of the processing in order to be able to produce as long as possible using the large starting wafers and thus to keep productivity high and to be able to use established production equipment.

If the solar cells continue to be electrically connected by means of cell connectors as described above, space remains between the solar cells that is not photovoltaically active and therefore leads to a reduction in the module efficiency.

A known method of circumventing this disadvantage is the so-called shingling of the solar cells, in which the upper side of one end of one solar cell is electrically connected directly to the lower side of the next cell. For this purpose, the external contacts are made on the front and back on the opposite edges of the solar cells. Since there are usually no very highly conductive contact elements in the solar cell in order to minimize shading, and the distances through which the current in the contact fingers must flow to the external external contacts are very large for the shingle concept based on large conventional solar cells, the After processing the solar cells, silicon wafers are cut into narrow strips, so that several photovoltaic solar cells with a typically rectangular shape can be realized in order to minimize power losses in the finger contacts of the solar cell when interlocking.

The separation of the semiconductor components produced on a substrate, in particular a silicon wafer, leads to an increase in the ratio of circumference to area and thus to an increase in area-normalized power losses through edge recombination. Investigations have shown (J. Dicker, "Analysis and simulation of highly efficient silicon solar cell structures for industrial production techniques", dissertation, University of Konstanz, 2003) that in particular the area in which a pn transition to a separation surface was carried out , leads to a loss of performance. One reason for this is in particular the edge recombination in the quasi-neutral areas of the emitter and base and, as described above, in particular in the space charge zone. In addition, the separation of the separated semiconductor components at the generated edges leads to a significant increase in the recombination rate itself. This influence is particularly relevant if the semiconductor component has a high electronic quality on the other surfaces, in particular a lower recombination rate due to passivation layers or other passivation mechanisms.

There is therefore a need to separate semiconductor components without significantly reducing the electronic quality of the semiconductor component through the separation surface, in particular through recombination effects at the separation surface.

It is known that in silicon solar cells, a silicon dioxide layer that grows natively on the interface reduces the negative influence at low illuminance levels ( M. Hermle, J. Dicker, W. Warta, SW Glunz and G. Willeke, “Analysis of edge recombination for high-efficiency solar cells at low illumination densities”, 2003, pp. 1009-1012 .). In the case of silicon solar cells under standard lighting, however, only a slight improvement is achieved as a result.

US 9 087 934 B2 describes a solar cell with a horizontal passivation layer.

DE 10 2009 026 410 A1 describes a two-stage laser process for separating solar cells.

In SZE, SM: Physics of Semiconductor Devices, 2nd edition, Singapore: John Wiley & Sons, Inc., 1981, p. 380 stationary charges on a semiconductor interface are described.

The present invention is therefore based on the object of providing a method for separating a semiconductor component in which a negative influence of the separating surface on the electronic quality is reduced.

This object is achieved by a method according to claim 1. Advantageous embodiments can be found in the dependent claims.

A semiconductor component produced by means of the method according to the invention preferably has a front side and an opposite rear side as well as side surfaces. Furthermore, the semiconductor component has at least one emitter and at least one base, a pn junction being formed between the emitter and the base. The emitter extends parallel to the front and / or rear. The semiconductor component can thus be designed as a photovoltaic solar cell or transistor, for example. The emitter can be designed in a manner known per se. In particular, emitters produced by means of diffusion and / or implantation as well as hetero emitters and epitaxially produced emitters are within the scope of the invention.

Furthermore, at least one side surface is a separation surface on which a separation surface passivation layer is arranged. The interface passivation layer has stationary charges with a surface charge density in an amount greater than or equal to 10 ¹² cm ^-2 . The surface charge density can thus be electrically positive or negative. Is the magnitude of the surface charge density of greater than or equal to 10 ¹² cm ^-2, ie at a greater positive charge equal to 10 ¹² cm ^-2 and at a negative charge less than or equal -1 × 10 ¹² cm ^-2.

The invention is based on the knowledge that the negative effects which occur at a separating surface can be reduced particularly efficiently by a separating surface passivation layer with a surface charge density of ≥ 10 ¹² cm ^-2 . It is true that passivation layers are known per se in semiconductor components and in particular in photovoltaic solar cells, which reduce the surface recombination speed of charge carriers. Investigations by the applicant show, however, that the negative effects on the interface are reduced particularly efficiently by the interface passivation layer described above. This is primarily due to the fact that stationary charges in the interface passivation layer prevent charge carriers in the semiconductor component, in particular a silicon layer of the semiconductor component, from reaching the interface. In the case of a silicon layer in particular, these are kept from the separating surface up to a depth of about 20 nm into the silicon. This has the advantage that near-surface damage to the separation surface caused by the separation process can be tolerated up to a depth of approximately 20 nm. Mechanical separation is usually not possible without damaging several atomic layers on the surface of the semiconductor volume. However, it can be limited to a depth of less than 20 nm by choosing a suitable process. The method is therefore advantageously carried out in such a way that the separation takes place by means of one of the TLS, LIC or LDC methods explained below, since these methods have a comparatively small depth of damage.

The interface passivation layer advantageously covers at least the area in which the pn junction adjoins the interface or, if the pn junction does not reach the interface, in which an extension of the pn junction up to the interface meets the interface.

A particularly advantageous passivation of the separating surface is achieved in that, in an advantageous embodiment, the separating surface passivation layer extends over the entire separating surface.

Such a semiconductor component has the advantage that, due to the passivation of the separating surface by the separating surface passivation layer, the surface of the semiconductor component can be used efficiently and thus the emitter can reach up to the separating surface. In particular, previously known methods for avoiding negative influences of a separating surface, which have provided insulation by means of isolation trenches and / or spacing the pn junction by forming emitter windows from the separating surface, are not or at least not absolutely necessary. Although the positive effect can be increased in that the pn junction does not directly reach the interface, a slight spacing is sufficient for such an increase.

The pn junction is therefore advantageously less than 50 μm, in particular less than 20 μm, from the separating surface. In particular, it is advantageous that the pn junction adjoins the separating surface. This results in a simplified manufacturing process.

• - CVD (siehe nachfolgend);
• - ALD (siehe nachfolgend);
• - Drucktechnologien, insbesondere ein Druck mittels Siebdruck, Inkjet, Extrusion oder Dispenser;
• - Spray-Coating;
• - Aufbringen von Schichtmaterial mittels eines Mediums auf die Trennfläche;

According to the invention, the interface passivation layer is formed as an aluminum oxide layer, as a silicon nitride layer or as a silicon oxynitride layer. These layers can be produced in a manner known per se and provided with high surface charge densities. In particular, it is within the scope of the invention that Form the interface passivation layer with one of the following methods:

• - CVD (see below);
• - ALD (see below);
• - Printing technologies, in particular printing by means of screen printing, inkjet, extrusion or dispenser;
• - spray coating;
• - Application of layer material by means of a medium on the parting surface;

The semiconductor component can be designed as a transistor.

It is advantageous that the semiconductor component is designed as a photovoltaic solar cell. This is because, in the case of photovoltaic solar cells in particular, long lifetimes of minority charge carriers in the emitter and base are necessary for high efficiencies, so that the passivation of an interface is particularly relevant here.

The semiconductor component is therefore advantageously designed as a photovoltaic solar cell which has at least one silicon layer in which at least the base is formed. It is within the scope of the invention that both the emitter and the base are formed in the silicon layer. Arranging a separate layer, in particular a separate silicon layer, for forming the emitter on the base is also within the scope of the invention.

The semiconductor component is advantageously separated at the separating surface in such a way that a damage zone with a small depth is created. In particular, it is advantageous that the semiconductor component has a damage zone at the interface with a charge carrier lifetime at least in the base <1 μs, the damage zone having a thickness of <20 nm perpendicular to the interface. In particular, it is advantageous that the charge carrier life at least in the base in an area adjoining the damage zone has a charge carrier life of> 10 μs, as is usual with photovoltaic solar cells.

The method according to the invention for separating a semiconductor component with a pn junction has the following method steps: In method step A, a semiconductor component is provided which has at least one emitter and at least one base, a pn junction being formed between the emitter and the base.

In a method step B, the semiconductor component is separated into at least two sub-elements on at least one separating surface.

It is essential that, after method step B, a separation surface passivation layer is arranged on the separation surface, which is formed with a surface charge density with an amount greater than or equal to 10 ¹² cm ^-2 . This results in the advantages mentioned in the preceding description of the semiconductor component.

The interface passivation layer is designed to cover the entire interface in order to achieve the most efficient possible reduction in the negative influences of the interface on the electronic quality of the semiconductor component.

1. a) Verfahren einer Chipsäge ( W. P. Mulligan, A. Terao, D. D. Smith, P. J. Verlinden, and R. M. Swanson, „Development of chip-size silicon solar cells“, in Proceedings of the 28th IEEE Photovoltaic Specialists Conference, Anchorage, USA, 2000, pp. 158-163 );
2. b) Erzeugen eines Grabens mittels eines Lasers mit nachfolgendem mechanischen Brechen ( M. Oswald, M. Turek, J. Schneider, and S. Schönfelder, „Evaluation of silicon solar cell separation techniques for advanced module concepts“, in Proceedings of the 28th European Photovoltaic Solar Energy Conference and Exhibition, Paris, France, 2013, pp. 1807-1812 );
3. c) Thermal Laser Separation (TLS): M. Oswald, M. Turek, J. Schneider, and S. Schönfelder, „Evaluation of silicon solar cell separation techniques for advanced module concepts“, in Proceedings of the 28th European Photovoltaic Solar Energy Conference and Exhibition, Paris, France, 2013, pp. 1807-1812 ; S. Eiternick, F. Kaule, H.-U. Zühlke, T. Kießling, M. Grimm, S. Schoenfelder, and M. Turek, „High quality half-cell processing using thermal laser separation“, Energy Procedia, vol. 77, pp. 340-345, 2015 .
4. d) Laser induced Cutting (LIC): S. Weinhold, A. Gruner, R. Ebert, J. Schille, and H. Exner, „Study of fast laser induced cutting of silicon materials“, in Proc. SPIE 8967, Laser Applications in Microelectronic and Optoelectronic Manufacturing (LAMOM), San Francisco, USA, 2014, 89671J .

It is within the scope of the invention to perform the separation in method step B by separating the semiconductor component using a method known per se. The semiconductor component can thus be separated in method step B in a manner known per se, in particular by means of one or more of the methods described below:

1. a) Process of a chipsaw ( WP Mulligan, A. Terao, DD Smith, PJ Verlinden, and RM Swanson, “Development of chip-size silicon solar cells”, in Proceedings of the 28th IEEE Photovoltaic Specialists Conference, Anchorage, USA, 2000, pp. 158-163 );
2. b) Creating a trench by means of a laser with subsequent mechanical breaking ( M. Oswald, M. Turek, J. Schneider, and S. Schönfelder, "Evaluation of silicon solar cell separation techniques for advanced module concepts", in Proceedings of the 28th European Photovoltaic Solar Energy Conference and Exhibition, Paris, France, 2013, pp. 1807-1812 );
3. c) Thermal Laser Separation (TLS): M. Oswald, M. Turek, J. Schneider, and S. Schönfelder, "Evaluation of silicon solar cell separation techniques for advanced module concepts", in Proceedings of the 28th European Photovoltaic Solar Energy Conference and Exhibition, Paris, France, 2013, pp. 1807-1812 ; S. Eiternick, F. Kaule, H.-U. Zühlke, T. Kießling, M. Grimm, S. Schoenfelder, and M. Turek, “High quality half-cell processing using thermal laser separation”, Energy Procedia, vol. 77, pp. 340-345, 2015 .
4. d) Laser induced cutting (LIC): S. Weinhold, A. Gruner, R. Ebert, J. Schille, and H. Exner, “Study of fast laser induced cutting of silicon materials”, in Proc. SPIE 8967, Laser Applications in Microelectronic and Optoelectronic Manufacturing (LAMOM), San Francisco, USA, 2014, 89671J .

Investigations show that it is particularly advantageous to perform the separation in method step B using TLS or LIC. The TLS method is based on the fact that a short laser trench is generated by means of a first laser beam, which is then based on simultaneous heating (for example by means of a second laser beam) and cooling (for example by means of an air-water mixture) along the edge to be generated leads to a separation of the wafer in any direction by means of introduced thermomechanical stress. In this way, in particular, a separation surface is possible independently of the crystal orientation of the wafer to be separated. The LIC process is quite similar to the TLS process, with LIC not tracking the heating (for example by a laser beam). The LIC process is also known as the LDC process (Laser Direct Cleaving).

The method according to the invention has the particular advantage that the separation can take place after completion or at least largely completion of the semiconductor component. A passivating layer is therefore advantageously applied to a front and / or rear side of the semiconductor component before method step B. In particular, it is advantageous that, prior to method step B, one or more metallic contacting structures for supplying and / or removing charge carriers have been applied to a front and / or rear side of the semiconductor component.

In order to improve the passivation quality of the interface passivation layer, it is advantageous that, after the interface passivation layer has been applied, a temperature treatment of the interface passivation layer takes place, in particular heating to a temperature greater than or equal to 150 ° C. for a period of at least 1 min.

To improve the passivation quality, it can also be advantageous to do this in a defined atmosphere, in particular in a hydrogen-containing atmosphere.

The temperature treatment can take place globally in that the entire semiconductor component is heated. In an advantageous embodiment, the temperature treatment of the interface passivation layer takes place by means of successive local heating, in particular by means of a laser. In this case, local partial areas of the interface passivation layer are consequently heated one after the other, particularly preferably, as mentioned above, in a hydrogen-containing atmosphere.

As described above, the method according to the invention can be used particularly advantageously for separating photovoltaic solar cells. The semiconductor component is therefore preferably in the form of a photovoltaic solar cell; in particular, at least the base is preferably formed in a silicon layer.

In a further advantageous embodiment, the interface passivation layer is additionally formed on at least the front or at least the rear of the semiconductor component. This has the advantage that the interface passivation layer can additionally be used with a further function on the front and / or rear. Particularly when the semiconductor component is designed as a photovoltaic solar cell, applying the interface passivation layer to the side facing the incident radiation when the solar cell is used, in particular the front side, as a further optical layer can lead to an increase in the coupling of light in the solar module. In the method according to the invention, therefore, the interface passivation layer is preferably also formed on the front and / or rear side of the semiconductor component, in particular while the interface passivation layer is being produced on the interface.

In particular, it is advantageous that, as described above, a passivating layer is applied to at least one side of the semiconductor component and the interface passivation layer is applied to the passivating layer and to the interface to be passivated. In particular, it is advantageous to also design the passivating layer as a charge carrier barrier layer. This avoids the formation of stationary charges in the interface passivation layer on the surface in which the interface passivation layer covers the charge carrier barrier layer. This is due to the fact that the charge carrier barrier layer acts as a tunnel barrier, no charge carriers from the semiconductor can penetrate into the interface passivation layer and thus the interface passivation layer cannot form stationary charges. The charge carrier barrier layer is advantageously designed as a dielectric layer, in particular as a silicon nitride layer, silicon oxynitride layer or aluminum oxide layer.

A further advantage of the present method is that the interface does not necessarily have to be parallel to a preferred direction in which a semiconductor substrate of the semiconductor component has the weakest bonds. In the case of monocrystalline silicon wafers, a break line typically occurs in a 45 ° direction to an edge of the silicon wafer when broken, since fewer bonds exist in this direction due to the crystal orientation. The present proceedings however, enables separation surfaces at any angles, in particular separation surfaces parallel to an edge of the silicon wafer.

The separation area is therefore preferably parallel to an edge of the semiconductor component, in particular a silicon wafer of the semiconductor component.

• 1 zwei Ausführungsbeispiele von Halbleiterbauelementen sowie Teilschritte zweier Ausführungsbeispiele erfindungsgemäßer Verfahren und
• 2 eine Draufsicht von oben auf einen Halbleiterwafer zur Verdeutlichung der Position der Trennflächen.

Further advantageous features and embodiments of the present invention are explained below with reference to embodiments and the figures. It shows:

• 1 two exemplary embodiments of semiconductor components and sub-steps of two exemplary embodiments of the method according to the invention and
• 2 a plan view from above of a semiconductor wafer to illustrate the position of the separation surfaces.

The figures show schematic representations that are not true to scale. In particular, the widths and thicknesses of the individual layers do not correspond to the actual conditions for better representation.

In 1 two exemplary embodiments A and B are shown, each with partial steps of an exemplary embodiment of a method according to the invention. In 1a , iii is correspondingly a first embodiment of a semiconductor component and in 1b , iii a second embodiment of a semiconductor component is shown.

Photovoltaic solar cells as semiconductor components are explained below as exemplary embodiments. Likewise, in a modification of the exemplary embodiments, the illustrated semiconductor components can be embodied as transistors.

• In einem Verfahrensschritt A wird das Halbleiterbauelement 1a bereitgestellt.
• Dieses weist vorliegend einen mittels Diffusion aus der Gasphase ausgebildeten Emitter 2a des n-Dotierungstyps und entsprechend eine Basis 3a auf, welche mit einem Dotierstoff des p-Dotierungstyps dotiert ist. Entsprechend bildet sich zwischen Emitter 2a und Basis 3a ein pn-Übergang 4a aus. Emitter und Basis wurden in einem Siliziumwafer ausgebildet. Weiterhin wurden zusätzliche, an sich bekannte Komponenten einer Solarzelle bereits erzeugt: Dies umfasst Passivierungsschichten an der oben liegenden Vorderseite sowie an der unten liegenden Rückseite, Metallisierungsstrukturen an Vorder- und Rückseite zum Abführen von Ladungsträgern sowie Antireflexschichten an der Vorder- und gegebenenfalls Rückseite zum Erhöhen der Lichtabsorption. In einer Abwandlung des Ausführungsbeispiels wird der Emitter mittels Diffusion aus einer vorab aufgebrachten Dotierschicht oder mittels Implantation ausgebildet. Ebenso können die Dotiertypen von Emitter und Basis vertauscht sein.

Using the in 1a The first exemplary embodiment of a method according to the invention is explained:

• In a method step A, the semiconductor component 1a provided.
• In the present case, this has an emitter formed by diffusion from the gas phase 2a of the n-type doping and correspondingly a base 3a which is doped with a dopant of the p-doping type. Correspondingly forms between the emitter 2a and base 3a a pn junction 4a. The emitter and base were formed in a silicon wafer. Furthermore, additional, per se known components of a solar cell have already been produced: This includes passivation layers on the top front and on the bottom rear, metallization structures on the front and back to remove charge carriers and anti-reflective layers on the front and, if necessary, back to increase the Light absorption. In a modification of the exemplary embodiment, the emitter is formed by means of diffusion from a previously applied doping layer or by means of implantation. The doping types of emitter and base can also be interchanged.

Subsequently, in a method step B, a separation at the separation surface is carried out by means of the above-described TLS method T carried out. The interface T stands perpendicular to the drawing surface in 1 and thus penetrates the base 3a as well as emitters 2a .

The TLS method is carried out starting from the rear side, that is to say, first of all, a laser is used to create an initial trench on the lower rear side in the area in which the dividing line T the back cuts, trained. The initial trench begins at an edge of the semiconductor component. The initial trench does not extend over the entire width of the semiconductor component. Typical initial trenches have a length in the range from 200 μm to 4 mm, typically less than 2 mm. Then, as described above, the semiconductor component is separated by means of simultaneous heating and cooling. In a modification of the exemplary embodiment, the TLS method is carried out starting from the front, so that the solar cell does not have to be rotated in the process.

The result is in 1a , ii shown: Two mirror-inverted symmetrical semiconductor components are thus produced, each of which has a pn junction 4a that is connected to the interface T adjoins.

After process step B, the separation area T an interface passivation layer 6a educated. The training takes place by means of industrial chemical vapor deposition (English: Chemical Vapor Deposition, CVD) or, in a modification, by means of atomic layer deposition (ALD).

The interface passivation layer 6a thus extends over the entire interface T . The interface passivation layer is an aluminum oxide layer with a surface charge density in the amount 10 ¹² cm ^-2 , in the present case -3 × 10 ¹² cm ^-2 at the interface with the interface T and has a thickness of a few atomic layers over a few nm up to several 10 nm, in this case 6 nm.

• Das Halbleiterbauelement 1b weist ebenfalls einen Emitter 2b sowie eine Basis 3b auf, sodass sich zwischen Emitter und Basis ein pn-Übergang 4b ausbildet. Zwischen den Verfahrensschritten A und B wie zuvor beschrieben, das heißt insbesondere vor dem Auftrennen, erfolgt jedoch in einem Verfahrensschritt B0 das Ausbilden eines Querleitungsvermeidungsbereiches 5b. Wie in 1b, i ersichtlich wird mittels Laserablation ein als Trenngraben ausgebildeter Querleitungsvermeidungsbereich 5b ausgebildet, welcher den Emitter 2b und auch den pn-Übergang 4b vollständig durchdringt. Hierdurch wird eine Querleitung von Ladungsträgern durch den Emitter zu der Trennfläche T vermieden und somit ein die elektronische Güte des Halbleiterbauelementes verringernder negativer Einfluss der Trennfläche zusätzlich verringert.

In 1b a second embodiment of a method according to the invention is shown. To avoid repetition, only the main differences are discussed below:

• The semiconductor component 1b also has an emitter 2 B as well as a base 3b so that a pn junction 4b is formed between the emitter and the base. Between method steps A and B as described above, that is to say in particular before the disconnection, however, a cross-line avoidance area is formed in a method step B0 5b . As in 1b, i By means of laser ablation, a cross-conduction avoidance area designed as a separating trench can be seen 5b formed, which the emitter 2 B and also completely penetrates the pn junction 4b. This creates a transverse conduction of charge carriers through the emitter to the interface T avoided and thus a negative influence of the interface that reduces the electronic quality of the semiconductor component is additionally reduced.

As in 1b , 2ii As can be seen, analogously to the first exemplary embodiment, the semiconductor component is then separated at the separating surface T . In this exemplary embodiment, the separation takes place by means of the LIC method described above.

As in 1b , 3iii As can be seen, the interface passivation layer is then applied 6b . In the present case, this is formed as an aluminum oxide layer with a surface ^{charge density greater than or equal to 10 12} cm ^-2 , in this case approximately -3x10 ¹² cm ^-2 at the interface with the base and emitter and has a thickness of a few atomic layers over a few nm up to several tens nm, in the present case 6 nm. The interface passivation layer 6b was generated using ALD. As a result, formation takes place not only on the parting surface T , but also on the walls of the cross-line avoidance area designed as a separating trench 5b .

In 1 For the sake of better illustration, only one separating surface is shown in each case.

When separating photovoltaic solar cells, for example to form modules according to the shingling technique mentioned at the outset, a plurality of solar cells are usually separated starting from a silicon wafer.

In 2 is a schematic plan view from above of a silicon wafer in which photovoltaic solar cells have been formed. At several, in this case four, dividing surfaces T one of the methods described above is carried out, so that five semiconductor components are present after separation.

List of reference symbols

1a, 1b

Semiconductor component

2a, 2b

Emitter

3a, 3b

Base

4a, 4b

pn junction

5b

Cross line avoidance area

6a, 6b

Interface passivation layer

T

Parting surface

Claims (8)

Method for separating a semiconductor component (1a, 1b) with a pn junction (4a, 4b), with the following steps: A. Providing a semiconductor component (1a, 1b) which has at least one emitter (2a, 2b) and at least one base ( 3a, 3b), a pn junction (4a, 4b) being formed between the emitter (2a, 2b) and the base (3a, 3b), B. Separating the semiconductor component (1a, 1b) into at least two sub-elements on at least one Separation surface (T), characterized in that, according to method step B, a separation surface passivation layer (6a, 6b) is arranged on the separation surface (T), which is formed with stationary charges with a surface charge density greater than or equal to 10 ¹² cm ^-2 that the separation surface passivation layer (6a, 6b) is formed as an aluminum oxide layer, as a silicon nitride layer or as a silicon oxynitride layer and that the interface passivation layer (6a, 6b) is formed to cover the entire interface (T). Method according to a Claim 1 , characterized in that in process step B the separation takes place by means of thermal laser separation. Method according to one of the Claims 1 to 2 , characterized in that a passivating layer is applied to a front and / or a rear side of the semiconductor component (1a, 1b) before method step B, in particular that before method step B to a front and / or a rear side of the semiconductor component (1a, 1b) one or more metallic contacting structures are applied. Method according to one of the Claims 1 to 3 , characterized in that after Application of the interface passivation layer (6a, 6b), a temperature treatment of the interface passivation layer (6a, 6b) takes place, in particular heating to a temperature greater than or equal to 150 ° C. for a period of at least 1 min. Procedure according to Claim 4 , characterized in that the temperature treatment takes place by means of successive local heating, in particular by means of a laser. Procedure according to Claim 4 and 5 , characterized in that the temperature treatment is carried out within a hydrogen-containing atmosphere, in particular a hydrogen atmosphere or a hydrogen / nitrogen atmosphere. Method according to one of the preceding Claims 1 to 6th , characterized in that the interface passivation layer is additionally applied to at least one side of the front or rear of the semiconductor component, preferably to the front. Method according to one of the Claims 1 to 6th , characterized in that the semiconductor component (1a, 1b) is formed as a photovoltaic solar cell, in particular that at least the base (3a, 3b) is formed in a silicon layer.

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