DE102018116540A1 - Adaptive use of multiple power supplies in communication systems - Google Patents

Abstract

Systems and techniques for adaptively using multiple power supplies in a communication system are disclosed herein. For example, in some embodiments, a slave device may include: an upstream transceiver for coupling to an upstream link of a bus of a communications system; and circuitry for coupling to the bus's upstream link and to a local power supply, the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the bus's upstream link to the supply the slave device is used with power.

Description

Reference to related application

The present application claims priority of the provisional U.S. Patent Application No. 62 / 532,658 , filed on 14.7.2017 entitled "HYBRID POWER ARRANGEMENTS IN COMMUNICATION SYSTEMS" and the non-provisional U.S. Patent Application No. 16 / 020,812 filed on 27.6.2018 entitled "ADAPTIVE USE OF MULTIPLE POWER SUPPLIES IN COMMUNICATION SYSTEMS". These priority applications are hereby incorporated by reference in their entirety.

State of the art

With decreasing size of electronic components and increasing performance expectations, more components are being incorporated into previously uninstrumented or less instrumented devices. In some cases, the communication infrastructure used to exchange signals between these components (e.g., in a vehicle) has required thick and heavy bundles of cables.

list of figures

• 1 ist eine Blockdarstellung eines beispielhaften Zweidraht-Kommunikationssystems gemäß verschiedenen Ausführungsformen.
• 2 ist eine Blockdarstellung eines Knoten-Sendeempfängers, der in einem Knoten des Systems von 1 enthalten sein kann, gemäß verschiedenen Ausführungsformen.
• 3 ist eine Darstellung eines Teils eines zur Kommunikation in dem System von 1 verwendeten Synchronisations-Steuerrahmens gemäß verschiedenen Ausführungsformen.
• 4 ist eine Darstellung eines zur Kommunikation in dem System von 1 verwendeten Superrahmens gemäß verschiedenen Ausführungsformen.
• 5 zeigt beispielhafte Formate für einen Synchronisations-Steuerrahmen in verschiedenen Betriebsarten des Systems von 1 gemäß verschiedenen Ausführungsformen.
• 6 zeigt beispielhafte Formate für einen Synchronisations-Antwortrahmen in verschiedenen Betriebsarten des Systems von 1 gemäß verschiedenen Ausführungsformen.
• 7 ist eine Blockdarstellung verschiedener Komponenten der Busprotokollschaltungstechnik von 2 gemäß verschiedenen Ausführungsformen.
• 8-11 zeigen Beispiele für Informationsaustausch auf einem Zweidrahtbus gemäß verschiedenen Ausführungsformen der hier beschriebenen Busprotokolle.
• 12 zeigt eine Ringtopologie für den Zweidrahtbus und ein unidirektionales Kommunikationsschema darauf gemäß verschiedenen Ausführungsformen.
• 13 zeigt schematisch eine Vorrichtung, die in dem System von 1 als Knoten oder Host dienen kann, gemäß verschiedenen Ausführungsformen.
• 14-16 zeigen Anordnungen zur adaptiven Verwendung mehrerer Leistungsversorgungen in dem System von 1 gemäß verschiedenen Ausführungsformen.

Embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. To facilitate the present description, like reference numerals designate like structural elements. In the figures of the accompanying drawings, embodiments are shown by way of example and not by way of limitation.

• 1 FIG. 10 is a block diagram of an exemplary two-wire communication system according to various embodiments. FIG.
• 2 FIG. 12 is a block diagram of a node transceiver operating in a node of the system of FIG 1 may be included, according to various embodiments.
• 3 is a representation of a part of a communication in the system of 1 used synchronization control frame according to various embodiments.
• 4 is a representation of one for communication in the system of 1 used superframes according to various embodiments.
• 5 shows exemplary formats for a synchronization control frame in various modes of the system 1 according to various embodiments.
• 6 shows exemplary formats for a synchronization response frame in various modes of the system 1 according to various embodiments.
• 7 FIG. 14 is a block diagram of various components of the bus protocol circuitry of FIG 2 according to various embodiments.
• 8-11 show examples of information exchange on a two-wire bus according to various embodiments of the bus protocols described herein.
• 12 FIG. 12 shows a ring topology for the two-wire bus and a unidirectional communication scheme thereon according to various embodiments. FIG.
• 13 schematically shows a device that in the system of 1 can serve as a node or host, according to various embodiments.
• 14-16 show arrangements for the adaptive use of multiple power supplies in the system of 1 according to various embodiments.

Detailed description

Disclosed herein are systems and techniques for powering a slave device in a communication system using an adaptive combination of a local power supply and power derived from the communication bus. In some previous systems, a slave device may be configured to be powered only by a dedicated local power supply (eg, a battery, voltage regulator, or other power source), or may be configured to be powered only by power is extracted from a bias on the signal upstream part of a communication bus (eg, by filtering the voltage from this upstream signal part by a low-pass-filter (LPF) network). In some such prior systems, when the power supply to a locally powered slave device is interrupted or fails (eg, due to a collision or other impact due to power regulator failure, electrical failure, other mechanical damage, part failure, etc.) locally powered-up slave device will no longer be able to communicate over the communication bus (eg, the slave device will no longer respond to upstream or downstream devices) and any slave devices will be downstream of this locally powered slave device also cut off from communication.

Various of the systems and techniques disclosed herein allow a locally powered slave device to extract power from the communication bus when the local power supply is no longer sufficient (herein referred to as a "hybrid power" arrangement, as an "adaptive use" arrangement) multiple power supplies "or as an" adaptive power supply "arrangement). Some of the systems and techniques disclosed herein are compatible with line diagnostics that can be performed by the communication system when a locally powered slave device can "switch" to extracting power from the communication bus without a fault or other performance penalty. Trigger flag. Some of the systems and techniques disclosed herein also allow slave devices located downstream of a locally powered slave device to extract power from the communication bus in the event of a local power failure of the locally powered slave device.

The following detailed description refers to the accompanying drawings, which form a part hereof, wherein like reference numerals refer to like parts throughout, and in which is shown by way of illustration embodiments which may be practiced. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description is therefore not to be construed in a limiting sense.

Various operations may be described as multiple discrete steps or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, it should not be inferred from the order of description that these operations are necessarily order-dependent. In particular, these operations can not be performed in the presentation order. Described operations may be performed in a different order than the described embodiment. In additional embodiments, various additional operations may be performed and / or operations described may be omitted.

For the purposes of the present disclosure, the term "A and / or B" means (A), (B) or (A and B). For the purposes of the present disclosure, the term "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A , B and C).

Various components may be mentioned or illustrated herein in singular form (e.g., a "processor", a "peripheral device", etc.), but this is for convenience of discussion only, and each element mentioned in the singular may have multiple such elements in accordance with the present teachings.

The description uses the terms "in one embodiment" or "in embodiments", which may each refer to one or more of the same or different embodiments. Furthermore, as used to refer to embodiments of the present disclosure, the terms "having," "containing," "having," and the like are synonymous. As used herein, the term "circuitry" may refer to an application specific integrated circuit (ASIC), an electronic circuit and an optical circuit, a processor (shared, dedicated or grouped) and / or memory (shared, dedicated or grouped) including or execute a plurality of software or firmware programs, a combinatorial logic circuit, and / or other suitable hardware that provides, or is part of, the described functionality. A master node may also be referred to herein as a master "device"; Similarly, a slave node may also be referred to herein as a slave "device". As used herein, a "unipolar device" may be a device that allows power flow substantially freely in one direction but severely impedes power flow in the opposite direction.

1 FIG. 10 is a block diagram of an exemplary half duplex two-wire communication system. FIG 100 according to various embodiments. The system 100 has a host 110 , a master node 102 and at least one slave node 104 on. In 1 are three slave nodes ( 0 . 1 and 2 ). The illustration of three slave nodes 104 in 1 is merely exemplary, and the system 100 can have one, two or more slave nodes as desired 104 exhibit.

The master node 102 can via a two-wire bus 106 with the slave node 104 communicate. The bus 106 can use different two-wire bus connections between adjacent nodes on the bus 106 to connect the nodes on the bus 106 in the daisy-chain method. For example, as in 1 represented the bus 106 one the master node 102 with the slave node 0 coupling connection, one the slave node 0 with the slave node 1 coupling connection and one the slave node 1 with the slave node 2 have coupling connection. In some embodiments, the connections of the bus 106 each from a single twisted pair (eg a non-shielded twisted pair) are formed. In some embodiments, the connections of the bus 106 each formed of a coaxial cable (where, for example, the core provides the "positive" line and the shield provides the "negative" line or vice versa).

The host 110 may have a processor that is the master node 102 programmed and as the origin and receiver of various on the bus 106 transmitted useful signals acts. In particular, the host can 110 the master of I2S communication (Inter-Integrated Circuit Sound) being on the bus 106 can take place. The host 110 may be via an I2S / Time Division Multiplexing (TDM) bus and / or an I / C (Inter-Integrated Circuit) bus to the master node 102 communicate. In some embodiments, the master node 102 a transceiver (eg, the node transceiver 120 hereinafter referred to with reference to 2 be discussed), which is in a housing of the host 110 located. The master node 102 can by the host 110 can be programmable via the I2C bus for configuration and readback and can be adapted to clock, synchronization and framing for all slave nodes 104 to create. In some embodiments, expansion of the I2C control bus may occur between the host 110 in the master node 102 in the over the bus 106 transmitted data streams are embedded, which is the host 110 direct access to registers and status information for the one or more slave nodes 104 allowed as well as communication from I2C to I2C over distances allows it to the host 110 to allow the peripheral devices 108 to control.

The master node 102 may include "downstream" signals (eg, data signals, power supply signals, etc.) from the master node 102 away on the bus 106 be transmitted) and "signal up" signals (eg in the direction of the master node 102 on the bus 106 to be transmitted). The master node 102 can be a clock signal for synchronous data transmission over the bus 106 provide. As used herein, "synchronous data" may include continuously streamed data (eg, audio signals) having a fixed time interval between two successive transmissions to / from the same node on the bus 106 exhibit. In some embodiments, this may be done by the master node 102 provided clock signal can be derived from an I2S input by the host 110 the master node 102 provided. A slave node 104 can be an addressable network connection point, which is a possible destination for downstream on the bus 106 or upstream on the bus 106 represents transmitted data frames. A slave node 104 may also represent a possible source of downstream or upstream data frames. The system 100 can transfer control information and other data in both directions via the bus 106 allow from one node to the next. One or more of the slave nodes 104 You can also go through the bus 106 transmitted signals are powered as will be discussed below. In some embodiments, according to any of the embodiments discussed herein, one or more of the slave nodes 104 to be able to adaptively between through the bus 106 provided power and power provided by a local power supply.

In particular, the master node 102 and the slave nodes 104 each a positive signal upstream terminal (referred to as "AP"), a negative signal upstream terminal (referred to as "ON"), a positive signal down terminal (referred to as "BP"), and a negative signal (referred to as "BN") downstream Have connection. The positive and negative downstream signal ports of a node may be coupled to the positive and negative signal upstream ports of the adjacent downstream node. As in 1 shown, the master node 102 have positive and negative signal upstream terminals, but these terminals do not need to be used; in other embodiments, the master node 102 have no positive and negative signal upstream connections. The last slave node 104 on the bus 106 (in 1 the slave node 2 ) can have positive and negative downstream terminals, but these terminals do not need to be used; in other embodiments, the last slave node 104 on the bus have no positive and negative downstream connections.

As will be discussed in detail below, the master node 102 periodically sending a synchronization control frame downstream, optionally together with data corresponding to one or more of the slave nodes 104 are determined. For example, the master node 102 every 1024 bits (representing a superframe) with a frequency of 48 kHz transmit a synchronization control frame, resulting in an effective bit rate on the bus 106 of 49.152 Mbps. Other rates may be supported, including, for example, 44.1 kHz. The synchronization control frame may be the slave node 104 allow to identify the beginning of each superframe, and can also do so in combination with physical layer coding / signaling to each slave node 104 allow his internal operating clock off the bus 106 derive. The synchronization control frame may have a preamble for signaling the synchronization start as well Have control fields that different addressing types (eg normal, broadcast, discovery), configuration information (eg writing in the register of the slave node 104 ), Transmission of I2C information, remote control of various GPIO (General Purpose Input / Output) pins to the slave node 104 and allow other services. A portion of the synchronization control frame following the preamble and payload data may be scrambled to reduce the likelihood that information in the synchronization control frame will be confused with a new preamble and to flatten the spectrum of related electromagnetic emissions.

The synchronization control frame can be between slave nodes 104 also optionally together with other data provided by the master node 102 but in addition or as an alternative to one or more upstream slave nodes 104 or from a slave node 104 himself can come) until he is the last slave node 104 (ie in 1 the slave node 2 reached by the master node 102 as the last slave node 104 has been configured or itself as the last slave node 104 has identified. Upon receipt of the synchronization control frame, the last slave node 104 transmit a synchronization response frame followed by any data it is allowed to transmit (eg, a 24-bit audio sample in a designated timeslot). The synchronization response frame may be upstream between slave nodes 104 (optionally together with data from downstream slave nodes 104 ), and based on the synchronization response frame, each slave node 104 be able to identify any time slot in which the slave node 104 to send.

In some embodiments, one or more of the slave nodes 104 in the system 100 with a peripheral device 108 be coupled and communicate with her. For example, a slave node 104 be adapted to data from the associated peripheral device 108 under the use of I2S Pulse density modulation (PDM), TDM and / or I2C protocols, as discussed below, to read and / or write data to them. Although "peripheral device 108" may be referred to singular herein, this is for ease of discussion only, and a single slave node 104 may be coupled to zero, one or more peripheral devices. Examples of peripheral devices included in the peripheral device 108 may include a DSP (Digital Signal Processor), a FPGA (Field Programmable Gate Array), an ASIC, an ADC (Analog to Digital Converter), a DAC (Digital to Analog Converter), a codec, a microphone, a microphone array , a speaker, an audio amplifier, a protocol analyzer, an accelerometer or other motion sensor, an ambient condition sensor (eg, a temperature, humidity, and / or gas sensor), a wired or wireless communication transceiver, a display device (eg, a touchscreen display) , a user interface component (eg, a button, dialer, or other control), camera (eg, a video camera), storage device, or any other suitable device that transmits and / or receives data. Several examples of various peripheral device configurations are discussed in detail here.

In some embodiments, the peripheral device 108 have any device designed for I2S communication (Inter-Integrated Circuit Sound); the peripheral device 108 can over the I2S protocol with the assigned slave node 104 communicate. In some embodiments, the peripheral device 108 have any device designed for I2C communication (Inter-Integrated Circuit); the peripheral device 108 can over the I2C protocol with the assigned slave node 104 communicate. In some embodiments, a slave node 104 with no peripheral device 108 be coupled.

A slave node 104 and its associated peripheral device 108 may be contained in separate housings and coupled by means of a wired or wireless communication link or may be contained in a common housing. For example, one may be used as a peripheral device 108 connected speaker with the hardware for an associated slave node 104 (eg, the following with reference to 2 discussed node transceiver 120 ) so that the hardware for the associated slave node 104 is contained in a housing having other speaker components. The same may apply to any type of peripheral device 108 be valid.

As discussed above, the host can 110 using multi-channel I2S and I2C communication protocols with the master node 102 communicate and control this. In particular, the host can 110 above I2S Data to a frame buffer (not shown) in the master node 102 transferred, and the master node 102 can read data from the frame buffer and the data on the bus 106 transfer. Analogously, the master node 102 over the bus 106 store received data in the frame buffer and then transfer the data via I2S to the host 110 transfer.

Every slave node 104 can have internal control registers that communicate through the master node 102 can be configured. In the following, a number of such registers will be discussed in detail. Every slave node 104 can receive downstream data and transmit the data further downstream. Every slave node 104 may receive and / or generate upstream data and / or transmit data upstream and / or add data to an upstream transaction.

Communication on the bus 106 can take place in periodic superframes. Each superframe may begin with a downstream synchronization control frame; in periods of downstream transmission (also referred to as "downstream"), upstream (also referred to as "upstream") and no transmission (the bus 106 not controlled); and terminate shortly before the transmission of another downstream synchronization control frame. The master node 102 can (by the host 110 ) with a number of downstream signal portions that go to one or more of the slave nodes 104 and a number of upstream signal portions transmitted by one or more of the slave nodes 104 are to be programmed. Every slave node 104 can (through the master node 102 ) with a number of the bus 106 down to be further transmitted downstream parts, a number of consumable signal downstream parts, a number of the bus 106 up further to be transmitted upstream parts and a number of signal upstream parts, in which the slave node 104 Data transmitted by the slave node 104 from the associated peripheral device 108 be received, programmed. Communication on the bus 106 will be referred to below with reference to 2-12 discussed in more detail.

Each of the master node 102 and the slave node 104 A transceiver can be used to manage communication between components of the system 100 exhibit. 2 is a block diagram of a node transceiver 120 which is in a node (eg the master node 102 or a slave node 104 ) of the system 100 from 1 may be included, according to various embodiments. In some embodiments, a node transceiver may 120 in each of the nodes of the system 100 may be included, and a control signal may be the node transceiver 120 via a master ( MSTR ) Pin to indicate whether the node transceiver 120 as master (eg when the MSTR pin is high) or as slave (eg when the MSTR pin is low).

The node transceiver 120 may include a signal uplink differential signaling (DS) transceiver 122 and a downstream DS transceiver 124 exhibit. The upstream DS transceiver 122 can with the above with respect to 1 be discussed positive and negative upstream signal terminals, and the downstream DS transceiver 124 can with the above with respect to 1 be coupled to positive and negative downstream signal connections. In some embodiments, the upstream DS transceiver may be 122 a low voltage DS (LVDS) transceiver and the downstream DS transceiver 124 be an LVDS transceiver. Every node in the system 100 can by bus 106 be AC coupled and data signals can be on the bus 106 (eg via the upstream DS transceiver 122 and / or the downstream DS transceiver 124 ) using a predetermined form of DS (eg LVDS or Multipoint LVDS (MLVDS) or similar signaling) with appropriate coding to provide timing information over the bus 106 (eg, differential Manchester coding, biphase marker coding, Manchester coding, non-return-to-zero, inverted (NRZI) encoding, or any other suitable coding).

The upstream DS transceiver 122 and the downstream DS transceiver 124 can with bus protocol circuitry 126 communicate and the bus protocol circuitry 126 can be used alongside other components with a phase-locked loop ( PLL ) 128 and voltage regulator circuit technology 130 communicate. If the node transceiver 120 can be powered up, the voltage regulator circuit technology 130 put a signal "power supply good" that the PLL 128 used as startup reset.

As mentioned above, one or more of the slave nodes 104 in the system 100 simultaneously with data over the bus 106 received transmitted power. For power distribution (which is optional because some of the slave nodes 104 can be designed to be powered only locally), the master node 102 a DC bias on the bus connection between the master node 102 and the slave node 0 (for example, by connecting one of the down-signal terminals to one voltage source provided by one voltage regulator and the other downstream signal to ground). The DC bias may be a predetermined voltage, such as 5V, 8V, the voltage of a car battery, or a higher voltage. Each successive slave node 104 can selectively change its upstream bus connection to power (eg using the voltage regulator circuitry 130 ) to regain. This power can be used to power the slave node 104 itself (and optionally one or more with the slave node 104 coupled peripheral devices 108 ) be used. A slave node 104 can also selectively downlink the bus for the next slave node 104 subsequently biasing either with the recovered power from the upstream bus connection or from a local power supply. For example, the slave node 0 the DC bias on the upstream bus connection 106 use to power for the slave node 0 itself and / or for one or more associated peripheral devices 108 regain and / or the slave node 0 can output power from its upstream bus connection 106 regain its signal downlink bus connection 106 pretension.

Thus, in some embodiments, each node in the system may 100 provide power to the following downstream node via a downstream bus connection. The energization of nodes can be performed in a sequenced manner. For example, after discovering and configuring the slave node 0 over the bus 106 the master node 102 the slave node 0 instruct, its downstream bus connection 106 Provide power to the slave node 1 Provide power; After the slave node 1 discovered and configured, the master node 102 the slave node 1 instruct, its downstream bus connection 106 Provide power to the slave node 2 Provide power (and so on for additional slave nodes 104 by bus 106 coupled). In some embodiments, one or more of the slave nodes 104 be powered locally instead of being powered from its upstream bus connection or in addition to it. In some such embodiments, the local power source may be for a given slave node 104 used to provide power to one or more downstream slave nodes. A slave node 104 may also be able to adaptively between through the bus according to any of the embodiments discussed herein 106 provided power and power provided by a local power supply.

In some embodiments, the upstream filter circuitry technique 132 between the upstream DS transceiver 122 and the voltage regulator circuit technology 130 be arranged and the downstream filter circuit technology 131 between the downstream DS transceiver 124 and the voltage regulator circuit technology 130 be arranged. As every connection of the bus 106 Can carry AC components (signal) and DC components (power), the upstream filter circuit technique 132 and the downstream filter circuit technique 131 the AC and DC components disconnect the AC components to the upstream DS transceiver 122 and the downstream DS transceiver 124 provide and the DC components of the voltage regulator circuit technology 130 provide. AC couplings on the line side of the upstream DS transceiver 122 and the downstream DS transceiver 124 isolate the transceivers 122 and 124 essentially from the DC component on the line to allow fast bidirectional communication. As discussed above, the DC component can be tapped for power and the upstream filter circuitry 132 and the downstream filter circuit technique 131 For example, a ferrite, a common mode choke or an inductor may be those of the voltage regulator circuitry 130 to reduce supplied AC component. In some embodiments, the upstream filter circuitry technique 132 in the upstream DS transceiver 122 , and / or the downstream filter circuitry 131 may in the downstream DS transceiver 124 be included; in other embodiments, the filter circuitry may be external to the transceivers 122 and 124 are located.

The node transceiver 120 can be a transceiver 127 for I2S, TDM and PDM communication between the node transceiver 120 and an external device 155 exhibit. Although the "external device 155 ' may be mentioned here in the singular, this is simply for ease of illustration, and multiple external devices may be via the I2S / TDM PDM transceiver 127 with the node transceiver 120 communicate. As is known in the art, the I2S protocol is used to carry PCM information (Pulse Code Modulation) (eg between audio chips on a printed circuit board ( PCB )). As used herein, "I2S / TDM" may refer to an expansion of the I2S stereo content ( 2 Channels) to multiple channels using TDM. As is known in the art, PDM may be used in sigma-delta converters, and in particular, the PDM format may represent an over sampled 1-bit sigma-delta ADC signal prior to decimation. The PDM format is often used as the output format for digital microphones. The I2S / TDM / PDM transceiver 127 may use the bus protocol circuitry 126 and pins for communication with the external device 155 are in communication. In 2 are six pins BCLK, SYNC, DTX [1: 0] and DRX [1: 0] shown; the BCLK pin can be used for an I2S bit clock, the SYNC pin for an I2S frame synchronization signal and the pins DTX [1: 0] and DRX [1: 0] are used to send and receive data channels. Although in 2 two send pins (DTX [1: 0]) and two receive pins (DRX [1: 0]) are shown, any desired number of receive and / or transmit pins can be used.

If the node transceiver 120 in the master node 102 is included, the external device 155 the host 110 and the I2S / TDM / PDM transceiver 127 can provide an I2S slave (in terms of BCLK and SYNC) that synchronizes with an I2S interface clock of the host 110 Data from the host 110 receive and data to the host 110 can send. In particular, an I2S frame synchronization signal on the SYNC pin may be input from the host 110 be received, and the PLL 128 can use this signal to generate clocks. If the node transceiver 120 in a slave node 104 is included, the external device 155 one or more peripheral devices 108 and the I2S / TDM / PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC), I2S communication with the peripheral device 108 can control. In particular, the I2S / TDM / PDM transceiver may 127 provide an I2S frame synchronization signal to the SYNC pin as output. Register in the node transceiver 120 can determine which and how many I2S and TDM channels as data slots over the bus 106 be transmitted. A register for the TDM mode (TDMMODE) in the node transceiver 120 can store a value of how many TDM channels will fit between consecutive SYNC pulses on a TDM transmit or receive pin. Together with the knowledge of the channel size, the node transceiver may 120 set the BCLK rate automatically to match the number of bits within the sample time (eg 48 kHz).

The node transceiver 120 can be a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157 exhibit. Although the "external device 157 ' may be mentioned here in the singular, this is for ease of illustration only, and there may be multiple external devices via the I2C transceiver 129 with the node transceiver 120 communicate. As is known in the art, the I2C protocol uses lines for the clock ( SCL ) and data ( SDA ) for providing data transfer. The I2C transceiver 129 can deal with the bus protocol circuitry 126 and pins for communication with the external device 157 are in communication. In 2 are four pins ADR1 . ADR2 . SDA and SCL shown; ADR1 and ADR2 may be used to modify the I2C addresses provided by the node transceiver 120 used when the node transceiver 120 acting as an I2C slave (eg if in the master node 102 is included), and SDA and SCL are used for serial data or serial clock signals from I2C. If the node transceiver 120 in the master node 102 is included, the external device 157 the host 110 and the I2C transceiver 129 can provide an I2C slave, the programming instructions from the host 110 can receive. In particular, a serial I2C clock signal may be input to the SCL pin as an input from the host 110 for register accesses. If the node transceiver 120 in a slave node 104 is included, the external device 157 a peripheral device 108 and the I2C transceiver 129 may provide an I2C master to allow the I2C transceiver to program one or more peripheral devices in accordance with instructions provided by the host 110 provided and over the bus 106 to the node transceiver 120 be transmitted. In particular, the I2C transceiver may 129 provide the serial I2C clock signal to the SCL pin as output.

The node transceiver 120 may be a pin for interrupt request (IRQ) in communication with the bus protocol circuitry 126 exhibit. If the node transceiver 120 in the master node 102 can be included, the bus protocol circuitry 126 via the I2C transceiver 129 event-driven interrupt requests towards the host 110 deploy via the IRQ pin. If the node transceiver 120 in a slave node 104 is included (eg, when the MSTR pin is low), the IRQ pin may serve as a GPIO pin with interrupt request capability.

The system 100 can work in any of a number of different modes. The nodes on the bus 106 can each have a register that indicates which mode is currently enabled. Below are descriptions of examples of different modes that can be implemented. In standby mode, bus activity is reduced to allow global power savings; the only traffic required is a minimum downstream preamble to the PLL every node (eg the PLL 128 ) synchronized. In standby mode, read and write operations are via the bus 106 unsupported. In a discovery mode, the master node 102 predetermined signals on the bus 106 send out and wait for appropriate answers to the topology of on the bus 106 distributed slave nodes 104 to map. In a normal mode, full register access can be slave nodes 104 and to these and access to and from peripheral devices 108 over the bus 106 be available. The normal mode can be global by the host 110 with or without synchronous signal upstream data and with or without synchronous signal downstream data.

3 Figure 12 is an illustration of a portion of one for communication in the system 100 used synchronization control frame 180 according to various embodiments. In particular, the synchronization control frame may 180 as discussed below for data clock recovery and PLL synchronization. Because communication over the bus 106 can take place in both directions, as mentioned above, communication can be time multiplexed into downstream parts and upstream parts. In a downstream signal, a synchronization control frame and downstream data may be sent from the master node 102 while in a signal upstream part, a synchronization response frame and upstream data from each of the slave nodes 104 to the master node 102 can be transmitted. The synchronization control frame 180 can be a preamble 182 and control data 184 exhibit. Every slave node 104 may be adapted to the preamble 182 of the received synchronization control frame 180 as a time base to dine PLL 128 to use. To facilitate this, a preamble follows 182 not the "rules" of valid control data 184 and thus can easily from the control data 184 be differentiated.

For example, in some embodiments, communication may be on the bus 106 using a clock-first, transition-at-zero-difference Manchester coding scheme. According to such a coding scheme, each bit time starts with one clock transition. If the data value is zero, the coded signal transitions again in the middle of the bit time. If the data value 1 is, the coded signal does not go over again. In the 5 presented preamble 182 may violate the encoding protocol (eg by having clock transitions that are not at the beginning of the bit times 5 . 7 and 8th take place), which means that the preamble 182 with no legal (eg correctly coded) pattern for the control data 184 can match. In addition, the preamble 182 not be reproduced by a legal pattern for the control data 184 taken and the bus 106 is forced high or low for a single bit time or for a multiple bit time period. In the 5 presented preamble 182 is merely illustrative and the synchronization control frame 180 can different preambles 182 in any suitable manner against the control data 184 used coding can violate.

The bus protocol circuitry 126 may include differential Manchester decoder circuitry resident on one of the bus 106 recovered clock runs and the synchronization control frame 180 detect a frame SYNC indicator for PLL 128 to send. In this way, the synchronization control frame 180 can be detected without using a system clock or faster oversampling clock. Consequently, the slave nodes 104 a PLL synchronization signal from the bus 106 received without a crystal clock source to the slave node 104 to require.

As mentioned above, communication can be on the bus 106 occur in periodic superframes. 4 is a representation of a superframe 190 according to various embodiments. As in 6 can show a superframe with a synchronization control frame 180 kick off. When the synchronization control frame 180 as a timing source for the PLL 128 is used, the frequency at which superframes are transmitted ("the superframe frequency") may be the same as the synchronization signal frequency. In some embodiments, where audio data is on the bus 106 The superframe frequency may be the same as the audio sampling frequency used in the system 100 is used (eg, either 48 kHz or 44.1 kHz), but any suitable superframe frequency can be used. Every super frame 190 can in periods of downstream transmission 192 , Periods of the upstream signal transmission 194 and periods without transfer 196 (eg if the bus 106 not controlled).

In 4 is the super frame 190 with an initial period of downstream transmission 192 and a later period of the upstream transmission 194 shown. The period of the downstream transmission 192 can be a synchronization control frame 180 and X Signal downstream data slots 198 have, wherein X can be zero. Essentially all the signals on the bus 106 can be line coded and one downstream from the master node 102 to the last slave node 104 (eg the slave node 104C) in the form of the synchronization preamble 182 in the synchronization control frame 180 as discussed above be forwarded synchronization signal. Downstream, synchronous TDM data can be stored in the X Signal downstream data slots 198 after the synchronization control frame 180 be included. The downstream data slots 198 can have the same width. As discussed above, the PLL 128 provide the tact that a node times out of Communication over the bus 106 used. In some embodiments, where the bus 106 can be used to transfer audio data, the PLL 128 at a multiple of the audio sampling frequency (eg, 1024 times the audio sampling frequency, resulting in 1024-bit clocks in each superframe).

The period of the upstream transmission 194 can be a synchronization response frame 197 and Y Signal upstream data slots 199 have, wherein Y can be zero. In some embodiments, each slave node 104 a portion of the downstream data slots 198 consume. The last slave node (eg slave node 2 in 1 ) can (after a predetermined response time stored in a register of the last slave node) with a synchronization response frame 197 reply. Synchronous upstream TDM data may pass through each slave node 104 in the upstream data slots 199 right after the synchronization response frame 197 to be added. The upstream data slots 199 can have the same width. A slave node 104 which is not the last slave node (eg the slave node 0 and 1 in 1 ), can receive the received synchronization response frame 197 with its own upstream signal response when reading one of its registers in the synchronization control frame 180 of the superframe 190 was requested or if a remote I2C read in the synchronization control frame 180 of the superframe 190 was requested.

As discussed above, the synchronization control frame may be 180 start every downstream transmission. In some embodiments, the synchronization control frame may 180 64 Bit length, but any other suitable length can be used. The synchronization control frame 180 can as mentioned above with a preamble 182 kick off. In some embodiments, when the synchronization control frame 180 through a slave node 104 to a downstream slave node 104 is transmitted further, the preamble 182 through the transmitted slave node 104 be generated instead of being transmitted further.

The control data 184 of the synchronization control frame 180 can have fields that are used to control transactions over the bus 106 used data. Examples of these fields are discussed below, and some embodiments are in 5 shown. In particular shows 5 exemplary formats for the synchronization control frame 180 in normal mode (I2C mode) and discovery mode according to various embodiments. In some embodiments, standby may have a completely different preamble 182 or a completely different synchronization control frame 180 be used so that the slave nodes 104 not the entire synchronization control frame 180 receive until a transition to normal mode is sent.

In some embodiments, the synchronization control frame may 180 have a count or CNT field. The CNT field may have any suitable amount (eg, 2 bits) and may be incremented (modulo the length of the field) from the value used in the previous superframe. A slave node 104 that receives a CNT value that is not expected may be programmed to return an interrupt.

In some embodiments, the synchronization control frame may 180 have a node addressing mode (NAM) field. The NAM field may be any suitable length (eg, 2 bits) and may be used to control access to registers of a slave node 104 over the bus 106 be used. In normal mode, based on the ID of the slave node 104 and the address of the register from registers of a slave node 104 read and / or these can be described. Broadcast transactions are writes made by each slave node 104 should be undertaken. In some embodiments, the NAM field may provide four node addressing modes, including "none" (eg, data is not at any particular slave node 104 addressed), "normal" (eg unicast of data to a specific slave node 104 specified in the address field discussed below), "broadcast" (to all slave nodes 104 addressed) and "discovery".

In some embodiments, the synchronization control frame may 180 have an I2C field. The I2C field may have any suitable length (eg, 1 bit) and may be used to indicate that the period of the downstream transmission 192 has an I2C transaction. The I2C field may indicate that the host 110 Has given instructions remotely to a peripheral device 108 access with respect to an associated slave node 104 acting as an I2C slave.

In some embodiments, the synchronization control frame may 180 have a node field. The node field may be any suitable length (eg 4 bits) and may be used to indicate which slave node is being addressed for normal and I2C access. In discovery mode, this field can be used to identify a newly discovered slave node 104 in a node ID register of the slave node 104 be programmed. Every slave node 104 in the system 100 can be assigned a unique ID be if the slave node 104 through the master node 102 is discovered as discussed below. In some embodiments, the master node has 102 no node id, while the master node 102 in other embodiments may have a node ID. In some embodiments, it is to the master node 102 on the bus 106 connected nodes 104 (eg the slave node 0 in 1 ) of the slave node 0 and each successive slave node 104 will have a number that 1 higher than the previous slave node. However, this is merely illustrative and any suitable slave node identification system may be used.

In some embodiments, the synchronization control frame may 180 have a read / write or RW field. The RW field may be any suitable length (eg, 1 bit) and may be used to control whether normal accesses are reads (eg, RW == 1) or writes (eg, RW == 0).

In some embodiments, the synchronization control frame may 180 have an address field. The address field may be any suitable length (eg 8 bits) and may be used to address specific registers of a slave node 104 by means of the bus 106 be used. For I2C transactions, the address field may be replaced with I2C control values such as START / STOP, WAIT, RW and DATA VLD. For discovery transactions, the address field may have a predetermined value (such as in 5 shown).

In some embodiments, the synchronization control frame may 180 have a data field. The data field can have any suitable length (eg 8 bits) and can be used for normal, I2C and broadcast writes. The one with 4 multiplied RESPCYCS value can be used to determine how many cycles of a newly discovered node between the start of receiving the synchronization control frame 180 and the start of transmitting the synchronization response frame 197 should allow a newly discovered node to pass. If the NAM field indicates discovery mode, the node address and data fields discussed below may be encoded as a RESPCYCS value which, when multiplied by a suitable optional multiplier (eg 4), the time in bits from the end of the synchronization control frame 180 until the start of the synchronization response frame 197 indicates. This can be a newly discovered slave node 104 determine the correct time slot for upstream transmission.

In some embodiments, the synchronization control frame may 180 a cyclic redundancy check field ( CRC ) exhibit. The CRC field may be any suitable length (eg, 16 bits) and may be used to transmit a CRC value for the control data 184 of the synchronization control frame 180 after the preamble 182 be used. In some embodiments, the CRC according to the error detection scheme CCITT-CRC.

In some embodiments, at least a portion of the synchronization control frame 180 between the preamble 182 and scrambling the CRC field to lessen the likelihood that a sequence of bits in that interval will be periodic with the preamble 182 matches (and thus by the slave node 104 wrong for the start of a new superframe 190 can be held), as well as to reduce electromagnetic emissions as mentioned above. In some such embodiments, the CNT field of the synchronization control frame 180 be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Various embodiments of the system described herein 100 can omit the Verwphan.

Other techniques can be used to ensure that the preamble 182 uniquely by the slave nodes 104 can be identified, or to reduce the likelihood that the preamble 182 at another location in the synchronization control frame 180 in addition to or instead of techniques such as scrambling and / or error coding as discussed above. For example, a longer synchronization sequence may be used to reduce the likelihood that a particular encoding of the remainder of the synchronization control frame 180 agrees with her. Additionally or alternatively, the remainder of the synchronization control frame may be structured such that it can not occur synchronization sequence, such as by placing fixed values. " 0 "Or" 1 "To appropriate bit.

The master node 102 can read and write requests to the slave nodes 104 send, including both for communication on the bus 106 specific requirements as well as I2C requirements. For example, the master node 102 Read and write requests (specified using the RW field) to one or more designated slave nodes 104 (using the NAM and Node fields) and can indicate whether the request is a request for the slave node 104 specific to the bus 106 , an I2C request for the slave node 104 or An I2C requirement is that of an I2C-compatible peripheral device 108 to be forwarded to one or more 12C ports of the slave node 104 with the slave node 104 is coupled.

Now with respect to upstream communication, the synchronization response frame may 197 start each upstream transmission. In some embodiments, the synchronization response frame may 197 64 Bit length, but any other suitable length can be used. The synchronization response frame 197 may also have a preamble, as above with respect to the preamble 182 of the synchronization control frame 180 discussed, followed by the data part. At the end of a downstream transmission, the last slave node 104 on the bus 106 wait until the RESPCYCS counter has expired, and then transmit a synchronization response frame 197 start up the signal. When a normal read or write transaction to an upstream slave node 104 can have a slave node 104 its own synchronization response frame 197 and replace that received from downstream. If any slave node 104 no synchronization response frame at the expected time 197 from a downstream slave node 104 sees, generates the slave node 104 its own synchronization response frame 197 and starts transmitting it upstream.

The data part of the synchronization response frame 197 can have fields that contain data that provides response information to the master node 102 be transmitted back. Examples of these fields are discussed below, and in 6 some embodiments are shown. In particular shows 6 exemplary formats for the synchronization response frame 197 in normal mode (I2C mode) and discovery mode according to various embodiments.

In some embodiments, the synchronization response frame may 197 have a count or CNT field. The CNT field may be any suitable length (eg 2 bits) and may be used to transmit the value of the CNT field in the previously received synchronization control frame 180 be used.

In some embodiments, the synchronization response frame may 197 have an acknowledgment or ACK field. The ACK field may be any suitable length (eg, 2 bits) and may be a slave node 104 be inserted to one in the previous synchronization control frame 180 received command to confirm if this slave node 104 the synchronization response frame 197 generated. Exemplary indicators that can be transmitted in the ACK field would be Wait, Acknowledge, Not Acknowledge (NACK) and Retry. In some embodiments, the ACK field may be for transmitting an acknowledgment by a slave node 104 in that it has received it and processed a broadcast message (eg by transmitting a broadcast acknowledgment to the master node 102 ) be measured. In some such embodiments, a slave node 104 also specify if the slave node 104 Data (which could be used, for example, for on-demand uplink transmissions, such as non-TDM keypad or touch screen inputs, or for prioritized upstream communication, such as when the slave node 104 would like to report an error or emergency condition).

In some embodiments, the synchronization response frame may 197 have an I2C field. The I2C field may be any suitable length (eg, 1 bit) and may be used to transmit the value of the I2C field in the previously received synchronization control frame 180 be used.

In some embodiments, the synchronization response frame may 197 have a node field. The node field may be any suitable length (eg 4 bits) and may be used to transmit the ID of the slave node 104 containing the synchronization response frame 197 generated, used.

In some embodiments, the synchronization response frame may 197 have a data field. The data field may be of any suitable length (eg 8 bits) and its value may depend on the type of transaction and the ACK response of the slave node 104 containing the synchronization response frame 197 generated, depend. For discovery transactions, the data field may include the value of the RESPCYCS field in the previously received synchronization control frame 180 exhibit. If the ACK field indicates a NACK or if the synchronization response frame 197 responds to a broadcast transaction, the data field may have a broadcast acknowledgment (BA) indicator (in which the last slave node 104 indicate whether the broadcast message was received without error), a discovery error or DER indicator (indicating whether a newly discovered slave node 104 in a discovery transaction with an existing slave node 104 and a CRC error indicator (indicating whether a NACK was caused by a CRC error).

In some embodiments, the synchronization response frame may 197 a CRC field exhibit. The CRC field may be any suitable length (eg 16 bits) and may be used to transmit a CRC value for the part of the synchronization response frame 197 between the preamble and the CRC field.

In some embodiments, the synchronization response frame may 197 have an interrupt request or IRQ field. The IRQ field may be any suitable length (eg 1 bit) and may be used to indicate that an interrupt is from a slave node 104 was signaled.

In some embodiments, the synchronization response frame may 197 have an IRQ node or IRQNODE field. The IRQNODE field can be any suitable length (eg 4 bits) and can be used to identify the ID of the slave node 104 that signaled the interrupt presented by the IRQ field. In some embodiments, the slave node adds 104 to generate the IRQ field its own ID in the IRQNODE field.

In some embodiments, the synchronization response frame may 197 have a second CRC or CRC-4 field. The CRC-4 field can be any suitable length (eg, 4 bits) and can be used to transmit a CRC value for the IRQ and IRQNODE fields.

In some embodiments, the synchronization response frame may 197 an IRQ field, an IRQNODE field and a CRC-4 field as the last bits of the synchronization response frame 197 (eg the last 10 bits). As already discussed, these interrupt-related fields may have their own CRC protection in the form of CRC 4 (and thus are not protected by the previous CRC field). Every slave node 104 that is an interrupt to the master node 102 must enter its interrupt information in these fields. In some embodiments, a slave node 104 with a pending interrupt higher priority than any slave node 104 further down the signal, which also has a pending interrupt. The last slave node 104 on the bus 106 (eg the slave node 2 in 1 ) can always fill these interrupt fields. If the last slave node 104 has no pending interrupt, may be the last slave node 104 set the IRQ bit to 0, set the IRQNODE field to its node ID, and provide the correct CRC-4 value. For simplicity, a synchronization response frame will be used 197 which transmits an interrupt, here referred to as an "interrupt frame".

In some embodiments, at least a portion of the synchronization response frame 197 between the preamble 182 and scrambling the CRC field to reduce emissions. In some such embodiments, the CNT field of the synchronization response frame 197 be used by scrambling logic to ensure that the scrambled fields are scrambled differently from one superframe to the next. Various embodiments of the system described herein 100 can omit scrambling.

Other techniques can be used to ensure that the preamble 182 uniquely by the slave nodes 104 can be identified, or to reduce the likelihood that the preamble 182 elsewhere in the synchronization response frame 197 in addition to or instead of techniques such as scrambling and / or error coding as discussed above. For example, a longer synchronization sequence may be used to reduce the likelihood that a particular encoding of the remainder of the synchronization control frame 197 agrees with her. Additionally or alternatively, the remainder of the synchronization control frame may be structured such that it can not occur synchronization sequence, such as by placing fixed values. " 0 "Or" 1 "To appropriate bit.

7 Figure 4 is a block diagram of the bus protocol circuitry 126 from 2 according to various embodiments. The bus protocol circuitry 126 can control circuitry 154 for controlling the operation of the node transceiver 120 according to the protocol described here for the bus 106 exhibit. In particular, the control circuit technology 154 controlling the generation of synchronization frames for transmission (eg, synchronization control frames or synchronization response frames as discussed above), the processing of received synchronization frames, and the execution of control operations specified in the received synchronization control frame. The control circuit technology 154 may have programmable registers as discussed below. The control circuit technology 154 may generate and receive synchronization control frames appropriate to received messages (eg, associated with a synchronization control frame when the bus protocol circuitry technique 126 in a slave node 104 or from an I2C device, if the bus protocol circuitry 126 in a master node 102 is included) and set the framing to the different modes (eg, normal, discovery, standby, etc.).

If the node transceiver 120 Data for transfer on the bus 106 prepared, can preamble circuitry 156 be adapted to generate preambles for synchronization frames for transmission and to receive preambles from received synchronization frames. In some embodiments, a downstream synchronization control frame preamble may occur every 1024 bits through the master node 102 be sent. As discussed above, one or more slave nodes 104 synchronize with the downstream synchronization control frame preamble and generate preamble local phase aligned master clocks.

The CRC insertion circuit technique 158 may be configured to generate one or more CRCs for synchronization frames for transmission. Frame / Komprimierschaltungstechnik 160 may be configured to receive incoming data from the I2S / TDM / PDM transceiver 127 (eg from a transceiver 127 associated frame buffer) and / or the I2C transceiver 129 If necessary, compress the data and optionally generate parity check bits or error correction codes (ECC) for the data. A multiplexer (MUX) 162 may be a preamble from the preamble circuit technique 156 , Synchronization frames and multiplex data to a stream for transmission. In some embodiments, the transmission stream may be prior to transmission by scrambling circuitry 164 be scrambled.

For example, in some embodiments, the frame / compression circuitry technique 160 apply a floating-point compression scheme. In such an embodiment, the control circuitry 154 3 Bits to indicate how many repeated sign bits are in the number, followed by a sign bit and N-4-bit data, where N is the size of the over the bus 106 is to be transferred. The use of data compression may be through the master node 102 be configured if desired.

In some embodiments, the node transceiver may be included in the node transceiver 120 incoming receive stream through the descrambling circuitry 166 be descrambled. A demultiplexer (DEMUX) 168 can demultiplex the preamble, sync frame, and data from the receive stream. CRC Prüfschaltungstechnik 159 On the receive side, received synchronization frames can check for the correct CRC. When the CRC test circuit technology 159 a CRC error in an incoming synchronization control frame 180 identifies the control circuitry 154 be notified of the error and does not carry any control commands in the control data 184 of the synchronization control frame 180 out. When the CRC test circuit technology 159 a CRC error in an incoming synchronization response frame 197 identifies the control circuitry 154 be notified of the error and an interrupt for transmission to the host 110 in an interrupt frame. DeFrame / Dekomprimierschaltungstechnik 170 can accept receive data, check its parity if necessary, optionally perform error detection and correction (eg single error correction - double error detection (SECDED)), optionally decompress the data and transmit the received data to the I2S / TDMPPDM transceiver 127 (eg a transceiver 127 associated frame buffer) and / or the I2C transceiver 129 write.

As discussed above, upstream and downstream data may be on the bus 106 in TDM data slots in a superframe 190 be transmitted. The control circuit technology 154 may have registers that manage these data slots on the bus 106 for which a number of examples are discussed below. When the control circuitry 154 in a master node 102 can contain the values in these registers through the host 110 in the control circuit technology 154 be programmed. When the control circuitry 154 in a slave node 104 can contain the values in these registers through the master node 102 in the control circuit technology 154 be programmed.

In some embodiments, the control circuitry may 154 have a downstream slot or DNSLOTS register. If the node transceiver 120 in the master node 102 is included, this register may hold the value of the total number of downstream data slots. This register may also define the number of data slots required for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 in the master node 102 is used. In a slave node 104 For example, this register may define the number of data slots that are downstream to the next slave node 104 before or after the addition of locally generated downstream slots, as discussed in more detail below with reference to LDNSLOTS.

In some embodiments, the control circuitry may 154 have a local downstream slot or LDNSLOTS register. This register can be in the master node 102 be unused. In a slave node 104 This register can define the number of data slots that the slave node 104 use and will not transfer. As an alternative, this can be Registers define the number of slots that the slave node 104 to the downstream bus connection 106 can contribute.

In some embodiments, the control circuitry may 154 have an upstream slot or UPSLOTS register. In the master node 102 For example, this register may hold the value of the total number of upstream data slots. This register may also define the number of slots required for 12S TDM transmission by the I2S / TDM / PDM transceiver 127 in the master node 102 is used. In a slave node 104 For example, this register may define the number of data slots that are routed up the signal before the slave node 104 starts to add his own data.

In some embodiments, the control circuitry may 154 have a local upstream slot LUPSLOTS register. This register can be in the master node 102 be unused. In a slave node 104 This register can define the number of data slots that the slave node 104 to the data received from downstream, before being sent upstream. This register may also define the number of data slots required for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 in the slave node 104 is used.

In some embodiments, the control circuitry may 154 have a broadcast downstream slot or BCDNSLOTS register. This register can be in the master node 102 be unused. In a slave node 104 This register can define the number of broadcast data spikes. In some embodiments, broadcast data slots may always come at the beginning of the data field. The data in the broadcast data slots can be from multiple slave nodes 104 can be used and managed by all slave nodes 104 regardless of whether they are used or not.

In some embodiments, the control circuitry may 154 a slot format or SLOTSFMT register. This register may define the format of data for upstream and downstream transmissions. The data size for the I2S / TDM / PDM transceiver 127 can also be determined by this register. In some embodiments, valid data sizes 8th . 12 . 16 . 20 . 24 . 28 and 32 Bit up. This register may also have bits for enabling floating point compression for downstream and upstream traffic. When floating point compression is enabled, the I2S / TDM data size can be 4 bits larger than the data size over the bus 106 be. All nodes in the system 100 may have the same values for SLOTFMT when data slots are enabled, and the nodes may be programmed by a broadcast write so that all nodes are updated with the same value.

8-11 show examples of information exchange on the bus 106 according to various embodiments of the bus protocols described herein. In particular, show 8-11 Embodiments in which each slave node 104 with one or more speakers and / or one or more microphones as the peripheral device 108 is coupled. This is merely exemplary, as in accordance with the techniques described herein, any desired arrangement of the peripheral device 108 with any specific slave node 104 can be coupled.

First shows 8th Signaling and timing considerations for bidirectional communication on the bus 106 according to various embodiments. In the 8th pictured slave node 104 have different numbers of sensor / actuator elements, and thus different amounts of data can be sent to the different slave nodes 104 be sent or received by them. Specifically, the slave node 1 two elements, the slave node 4 four elements and the slave node 5 three elements on, so that through the master node 102 transmitted data two time slots for slave nodes 1 , four time slots for slave nodes 4 and three timeslots for slave nodes 5 exhibit. Similarly, the slave node 0 three elements, the slave node 2 three elements, the slave node 3 three elements, the slave node 6 an element and the slave node 7 four elements on, so that through these slave nodes 104 signal up-transmitted data have the appropriate number of time slots. It should be noted that there need not be a clear correlation between elements and time slots. For example, a microphone array with three microphones may be in the peripheral device 108 include a DSP that receives signals from the three microphones (and possibly also from the master node 102 or from other slave nodes 104 received information) to produce a single sample of data which, depending on the type of processing, could correspond to a single time slot or multiple timeslots.

In 8th transmits the master node 102 a synchronization control frame ( SCF ) followed by data for speakers connected to specific slave nodes 104 ( SD ) are coupled. Each successive slave node 104 directs the SCF and also forwards at least any for downstream slave nodes 104 certain data continues. A certain one Slave node 104 can forward all data or can for this slave node 104 remove certain data. If the last slave node 104 the SCF receives, transmits this slave node 104 the synchronization response frame ( SRF ), optionally followed by any data representing the slave node 104 may transfer. Each successive slave node 104 routes the SRF together with any data from downstream slave nodes 104 and optionally add data from one or more to the particular slave node 104 paired microphones ( MD ) one. In the example of 8th sends the master node 102 Data about the slave nodes 1 . 4 and 5 (in the 8th are shown as active speakers) and receive data from the slave nodes 7 . 6 . 3 . 2 and 0 (in the 8th are shown as microphone arrays).

9 Fig. 12 schematically shows the dynamic removal of data from a downstream transmission and insertion of data into an upstream communication from the point of view of the downstream DS transceiver 124 from, according to various embodiments. In 9 transfers as in 8th the master node 102 one SCF , followed by data for the slave nodes 1 . 4 and 5 ( SD ) in reverse order (eg data for the slave node 5 are followed by data for the slave node 4 which data is for the slave node 1 follow, etc.) (see the line labeled MASTER). If the slave node 1 receives this transmission, removes the slave node 1 his own data and directs only the SCF , followed by the data for the slave nodes 5 and 4 to the slave node 2 further. The slave nodes 2 and 3 forward the data unchanged (see the one with SLAVE 2 designated line), so that by the slave node 1 forwarded data through the slave node 4 be received (see the with SLAVE 3 designated line). The slave node 4 removes his own data and passes only the SCF , followed by the data for the slave node 5 to the slave node 5 Next, and the slave node 5 similarly removes its own data and passes only the SCF to the slave node 6 further. The slave node 6 directs the SCF to the slave node 7 continue (see the with SLAVE 6 designated line).

At this point, the slave node transmits 7 the SRF followed by its data, to the slave node 6 (see the with SLAVE 6 designated line). The slave node 6 directs the SRF together with the data from the slave node 7 and its own data to the slave node 5 Next, and the slave node 5 for his part manages the SRF along with the data from the slave nodes 7 and 6 to the slave node 4 further. The slave node 4 has no data to add, so he simply transfers the data to the slave node 3 redirects (see the with SLAVE 3 designated row) which stores the data together with its own data to the slave node 2 forwarded (see the one with SLAVE 2 designated line), which in turn supplies the data together with its own data to the slave node 1 forwards. The slave node 1 has no data to add, so he gets the data to the slave node 0 who forwards the data together with his own data. As a result, the master node receives 102 the SRF, followed by the data from the slave nodes 7 . 6 . 3 . 2 and 0 (see the ones with MAS TER designated line).

10 shows another example of the dynamic removal of data from a downstream transmission and insertion of data into an upstream communication from the point of view of the downstream DS transceiver 124 as seen in 9 although in 10 the slave nodes 104 both with sensors and actuators as the peripheral device 108 are coupled, so that the master node 102 Data downstream to all slave nodes 104 sends and data from all slave nodes 104 gets back. In addition, in 10 the data is ordered based on the node address for which it is intended or from which it originated. The one with " Y "Designated data slot can be used for a data integrity check or data correction.

11 shows another example of the dynamic removal of data from a downstream transmission and insertion of data into an upstream communication from the point of view of the downstream DS transceiver 124 as seen in 9 although in 11 the data is transmitted downstream and upstream in sequential order, rather than in reverse order. Buffering in each slave node 104 allows selective addition, removal and / or forwarding of data.

As discussed above, each slave node can 104 Remove data from downstream or upstream transmissions and / or add data to downstream or upstream transmissions. Thus, for example, the master node 102 to each of a number of slave nodes 104 transmit a separate sample of data and each such slave node 104 can remove its data sample and pass only certain data for downstream slaves. In contrast, a slave node 104 Data from a downstream slave node 104 receive and forward the data along with additional data. An advantage of transmitting as little information as necessary is reducing the amount of collective through the system 100 consumed power.

The system 100 can also broadcast broadcasts (and multicast transmissions) of the master node 102 to the slave nodes 104 specifically by configuring the downstream slot use of the slave nodes 104 , support. Every slave node 104 can process the broadcast transmission and send it to the next slave node 104 forward, although a particular slave node 104 "consume" the broadcast message (ie, not broadcast to the next slave node 104 forward) can.

The system 100 can also be uplink (eg from a particular slave node 104 to one or more other slave nodes 104 ) support. Such upstream communications may include unicast, multicast and / or broadcast upstream communications. With upstream addressing as discussed above with respect to downstream transmissions, a slave node may be discussed 104 based on the configuration of the upstream slot use of the slave nodes 104 determine whether or not to remove data from an upstream communication and / or an upstream communication to the next upstream slave node 104 to forward or not. Thus, for example, data may pass through a particular slave node 104 in addition to forwarding the data to the master node 102 or instead of one or more other slave nodes 104 be directed. Such slave-slave relationships can, for example, via the master node 102 be configured.

In various embodiments, the slave nodes 104 thus working as active / intelligent repeater nodes with the ability to selectively route, extract and add information. The slave nodes 104 can generally perform such functions without necessarily decoding / examining all data, since each slave node 104 knows the relevant timeslot (s) in which it receives / sends data, and therefore can remove data from or add data to a timeslot. Although the slave node 104 The slave nodes may not have to decode / examine all the data 104 typically re-timed the data they transmit / forward. This can be the robustness of the system 100 improve.

In some embodiments, the bus may 106 be designed for unidirectional communication in a ring topology. For example, shows 12 an arrangement 1200 from the master node 102 and four slave nodes 104 in a ring topology, showing signaling and timing considerations for unidirectional communication in the array 1200 according to various embodiments. In such embodiments, the node transceivers may 120 a receive-only transceiver (MASTER IN) and a transmit-only transceiver (MASTER OUT) instead of having two bidirectional transceivers for upstream and downstream communication. At the in 12 The data link layer synchronization scheme shown is transmitted by the master node 102 one SCF 180 , optionally "downstream" data 1202 for the three with different slave nodes 104 coupled speakers (the data for the various speakers may be arranged in any suitable order as described above with reference to FIG 8-11 and each successive slave node 104 directs the synchronization control frame 180 together with any "upstream" data from previous slave nodes 104 and "up-signal" data from itself to provide "up-signal" data 1204 (eg, the data from the eight different microphones may be arranged in any suitable order as described above with respect to FIG 8-11 discussed).

As described herein, data may be in any of a number of ways between elements of the system 100 be transmitted. In some embodiments, data may be part of a set of synchronous data slots by a slave node 104 (eg using the data slots 199 ) upstream or through a slave node 104 or a master node 102 (eg by using the data slots 198 ) are sent downstream. The volume of such data may be adjusted by changing the number of bits in a data slot or by including additional data slots. Data can also be obtained by inclusion in a synchronization control frame 180 or a synchronization response frame 197 in the system 100 be transmitted. Data transmitted in this way can provide I2C control data from the host 110 (with a response from a slave node 104 associated peripheral device 108 ); Access to registers of the slave nodes 104 (eg for discovery and configuration of slots and interfaces), write access from host 110 / master node 102 to a slave node 104 and read access from a slave node 104 on the host 110 / master node 102 can have; and event signaling via interrupts from a peripheral device 108 to the host 110 exhibit. In some embodiments, GPIO pins may be used to convey information to a slave node 104 to the master node 102 used (eg by the master node 102 the GPIO pins over I2C or by a node transceiver 120 a slave node 104 an interrupt is generated at an interrupt request pin). For example, in some such embodiments, a host 110 information about I2C to master node 102 send and the master node 102 can then send this information to the slave via the GPIO pins. Any of the types of data discussed here, as well as they over the bus 106 can be transmitted using any one or more of these communication paths. Other types of data and data communication techniques in the system 100 can be revealed here.

Embodiments of the present disclosure may be implemented using any suitable hardware and / or software for configuration as desired to a system. 13 schematically shows a device 1300 that in the system 100 as host or node (eg host 110 , Master node 102 or slave node 104 ), according to various embodiments. In 13 are a number of components than in the device 1300 but any one or more of these components may be omitted or duplicated as appropriate for the application.

In addition, in various embodiments, the device 1300 one or more of the in 13 components not shown, but the device 1300 may include interface circuitry for coupling to the one or more components. For example, the device may 1300 no display device 1306 but may include display device interface circuitry (eg, a connector and driver circuitry) to which a display device 1306 can be coupled. In another set of examples, the device may 1300 no audio input device 1324 or audio output device 1308 but may include audio input or output device interface circuitry (eg, connectors and supporting circuitry) to which an audio input device 1324 or audio output device 1308 can be coupled.

The device 1300 may be the node transceiver 120 according to any of the embodiments disclosed herein, for communication on the bus 106 to manage when the device 1300 by bus 106 is coupled. The device 1300 may be a processing device 1302 (eg, one or more processing devices) included in the node transceiver 120 contained or from the node transceiver 120 can be separated. As used herein, the term "processing device" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data stored in registers and / or memory can be stored. The processing device 1302 may include one or more DSPs, ASICs, CPUs, GPUs, crypto processors, or any other suitable processing device. The device 1300 can a memory 1304 which may itself comprise one or more memory devices, such as volatile memory (eg, dynamic random access memory (DRAM)), nonvolatile memory (eg, read only memory (ROM)), flash memory, semiconductor memory, and / or a hard disk.

In some embodiments, the memory may 1304 for storing a working copy and a permanent copy of programming instructions to cause the device 1300 Any of the techniques disclosed herein may be used. In some embodiments, machine-accessible media (including non-transitory computer-readable storage media), methods, systems, and apparatus for carrying out the techniques described above are illustrative examples of embodiments disclosed herein for communication over a two-wire bus. For example, on a computer readable medium (eg the memory 1304 ) Instructions that are stored by one or more of the processing devices operating in the processing device 1302 are included, execute, cause the device 1300 performs any of the techniques disclosed herein.

In some embodiments, the device may 1300 another communication chip 1312 (eg one or more other communication chips). For example, the communication chip 1312 for managing wireless communication for transferring data to and from the device 1300 be educated. The term "wireless" and its derivatives can be used herein to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data through a non-solid medium using modulated electromagnetic radiation. It does not follow from the expression that the associated devices do not include wires, although in some embodiments this could be the case.

The communication chip 1312 may implement any of a number of wireless standards or protocols, including, but not limited to, IEEE (IEEE 802.11 Family) standards, IEEE 802.16 standards (eg, IEEE 802.16 Supplement from 2005), the LTE Project (Long Term Evolution) together with any additions, updates and / or revisions (eg the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, an abbreviation for Worldwide Interoperability for Microwave Access, a product quality mark, conformance and interoperability testing for the IEEE 802.16 standards consist. The one or more communication chips 1312 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), or Evolved HSPA (E-HSPA) or LTE. The one or more communication chips 1312 may operate in accordance with EDGE (Enhanced Data for GSM Evolution), GERAN (GSM EDGE Radio Access Network), UTRAN (Universal Terrestrial Radio Access Network) or E-UTRAN (Evolved UTRAN). The one or more communication chips 1312 may be in accordance with CDMA (Code Division Multiple Access), TDMA (Time Division Multiple Access), DECT (Digital Enhanced Cordless Telecommunications), EV-DO (Evolution-Data Optimized) and derivatives thereof as well as any other wireless protocols known as 3G, 4G, 5G and beyond, work. The communication chip 1312 may work in other embodiments according to other wireless protocols. The device 1300 can an antenna 1322 to facilitate wireless communication and / or to receive other wireless communications (such as AM or FM radio broadcasts).

In some embodiments, the communication chip 1312 wired communication using a protocol other than the protocol described here for the bus 106 manage. Wired communication may include electrical, optical, or any other suitable communication protocol. Examples of wired communication protocols passing through the communication chip 1312 Ethernet, CAN (Controller Area Network), I2C , MOST (Media-Oriented Systems Transport) or any other suitable wired communication protocol.

As already mentioned, the communication chip 1312 have multiple communication chips. For example, a first communication chip 1312 Short-range wireless communication such as WiFi or Bluetooth may be dedicated, and a second communication chip 1312 may be dedicated to longer range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or others. In some embodiments, a first communication chip 1312 dedicated to wireless communication, and a second communication chip 1312 can be dedicated to wired communication.

The device 1300 can battery / power supply circuit technology 1314 exhibit. The battery / power supply circuitry 1314 may include one or more energy storage devices (eg, batteries or capacitors) and / or circuitry for coupling components of the device 1300 with one of the device 1300 separate power source (eg, mains power, voltage provided by a car battery, etc.). For example, the battery / power supply circuitry may 1314 the above with respect to 2 discussed upstream filter circuit technique 132 and downstream filter circuitry 131 and could be due to the bias on the bus 106 getting charged. The battery / power supply circuitry 1314 may be any of the support circuitry discussed below 320 or 321 exhibit.

The device 1300 can be a display device 1306 (or corresponding interface circuitry as discussed above). The display device 1306 can have any visual indicators, such as a heads-up display, a computer monitor, a projector, a touch-screen display, a liquid crystal display ( LCD ), a light-emitting diode display or a flat display.

The device 1300 may be an audio output device 1308 (or corresponding interface circuitry, as discussed above). The audio output device 1308 may include a device that generates an audible indicator, such as speakers, headsets or earphones.

The device 1300 may be an audio input device 1324 (or corresponding interface circuitry, as discussed above). The audio input device 1324 may include any device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (eg, instruments with a Musical Instrument Digital Interface (MIDI) output).

The device 1300 may include a Global Positioning System (GPS) device 1318 (or equivalent interface circuitry, as discussed above). The GPS device 1318 can be in communication with a satellite based system and can be a location the device 1300 as is known in the art.

The device 1300 may be another output device 1310 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1310 would be an audio codec, a video codec, a printer, a wired or wireless transmitter to provide information to other devices, or an additional storage device. In addition, any suitable peripheral devices discussed herein may be used 108 in the other output device 1310 be included.

The device 1300 can be another input device 1320 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1320 An accelerometer, a gyroscope, an imaging device, a keyboard, a cursor control device such as a mouse, pen, touch pad, bar code reader, QR code reader (Quick Response), or RFID (Radio Frequency Identification) reader. In addition, any of the sensors or peripheral devices discussed herein may be used 108 in the other input device 1320 be included.

Any suitable one of the above with respect to the device 1300 described display, input, output, communication or memory devices can be used as the peripheral device 108 in the system 100 serve. Alternatively, or in addition, suitable ones may be those of the above with respect to the device 1300 described display, input, output, communication or memory devices in a host (eg the host 110 ) or a node (eg a master node 102 or a slave node 104 ).

14-16 show various systems and techniques for adaptive power supply in the system 100 from 1 , These systems and techniques may be used with any of the embodiments of the system disclosed herein 100 including any of the embodiments of the master node 102 and the slave node 104 , Even though 14-16 an adaptively powered slave device coupled directly to a master device is for illustrative purposes only, and the adaptively powered slave may be located downstream of one or more other slave devices (which itself is locally powered, from the bus 106 powered or adaptively powered according to any of the present embodiments). Certain with respect to various of the embodiments of 14-16 discussed circuits and operational details can be applied to other of the embodiments of 14-16 be applied, but need not be repeated for more expedient representation. Diodes are considered to be in different of the 14-16 However, any suitable unipolar device may be used instead of or in addition to a diode. The in any of 14-16 Voltage regulators shown can be provided by any suitable power supplies (eg batteries).

14-16 For example, adaptive power supply arrangements that allow a slave device to begin to power from the upstream bus 106 extract if a local power supply fails. In these arrangements, there are two alternative power supply paths for a transceiver. "Switching" from the local power supply to that through the bus 106 The "phantom power supply" provided may allow the slave device to communicate upstream and downstream in the system 100 and may allow for possible remote diagnostics of the fault in the slave device. Further, additional downstream slave devices may be powered and discovered. In this way, despite the degradation of an upstream slave device, downstream slave devices may still be available to the rest of the system 100 be available. In some embodiments, after a local power supply has failed and a slave transceiver has begun to use bus power, the slave transceiver may resume operation using the local power supply as soon as it becomes available again (eg, as soon as the voltage provided by the local power supply exceeds the bus bias, as discussed below). This switching between power sources can be done without having the slave device through the rest of the system 100 must be rediscovered and without interruption of communication in the system 100 ,

In particular, show 14-16 adaptive power supply arrangements permitting a slave device selectively through a local power supply or bias on the bus 106 be powered without triggering line diagnostics error. For example, if a slave device is power off the bus 106 can monitor line diagnostics in the transceivers for a "short to ground" line fault. If an error is detected, communication may be in the system 100 be compromised. The adaptive power supply arrangements disclosed herein can provide high DC impedance back to a Provide system ground return path that isolates the signal upstream devices sufficiently from the local ground of the slave device to avoid false "short to ground" line faults. In addition, the adaptive power supply arrangements disclosed herein may be structured such that the local ground return for a particular slave device is the preferred path for any bias provided, thereby breaking the control that the signal uplink conventionally exerts over the loop current during startup and discovery can be, and the risk of high inrush currents and the possibility of a collapse of the upstream signal bus voltage is reduced.

At the in 14 In the illustrated embodiment, a master transceiver and a slave transceiver may each have their own support circuitry 320 respectively. 321 exhibit. The support circuit technique 320 for the master transceiver, among other components one (by the associated voltage regulator ( ORDEA ), low-pass filter networks ( LPF ) and high-pass filter networks ( HPF ) exhibit. The LPF and HPF the support circuit technique 320 may be part of upstream signal filtering technique 132 / downstream filtering circuitry 131 be discussed above. In some embodiments, any of the LPF disclosed herein may optionally include ferrite beads (or similar inductive elements) and capacitors. The bus 106 can couple the master transceiver and the slave transceiver communicatively. The bus 106 may include a bias voltage (eg, a DC voltage) provided by the master power supply (eg, by means of a diode as shown). The support circuit technique 321 for the slave transceiver can be a (by the associated voltage regulator ( ORDEA ), low pass filter networks and high pass filter networks. The LPF and HPF the support circuit technique 321 may be part of the upstream filter circuitry 132 / downstream filter circuitry 131 be discussed above.

The support circuit technique 321 may also include circuitry to achieve the adaptive power supply functionality described above. In particular shows 14 one between the bus 106 (as shown the "negative" line of the bus 106 ) and grounded diode to "prevent" the ground from being "seen" by the line diagnostics (thus avoiding a "short to ground" fault). The use of the diode 303 can allow for the freedom of control that the line diagnostics in the upstream node (eg, the master node in 14 ) needed to work correctly.

14 also has two "high-side" diodes 301 and 302 on, the power supply for the slave transceiver from the power source (the bias on the bus 106 or the local power supply) having a higher potential. The support circuit technique 321 can also switch-on control circuitry 322 to control the rate at which power is supplied to the slave transceiver when the power source is from the local power supply to the bus 106 switches. In the embodiment of 14 may be the power-up control circuitry 322 a transistor 307 (eg as shown PFET , one NFET or another switching device of any polarity), with which a filter (with resistors 304 and 306 and a capacitor 309 , arranged in an RC network) is coupled. The values of the elements in the filter can be selected to provide a desired on-time of the signal passing through the bus 106 provided power supply, whereby the risk of excessive inrush currents is reduced. The support circuit technique 321 can be between the diode 302 and the diode 303 have another filter that the resistance 305 and the capacitor 308 having.

Any of the components of the support circuitry 320 or 321 can take any suitable value. In some embodiments, the resistance 306 have a resistance between 40 kilohms and 200 kilohms (eg 100 kilohms). In some embodiments, the resistance 304 have a resistance between 5 kilohms and 50 kilohms (eg 10 kilohms). In some embodiments, the capacitor may be 309 have a capacity between 20 nanofarads and 50 nanofarads (eg 33 nanofarads). In some embodiments, the turn-on control circuitry technique 322 one PFET 307 can, the resistance 306 a 100 kilohm resistor and the resistor 304 be a 10 kilohm resistor. In some embodiments, the turn-on control circuitry technique 322 has an NFET, the resistance 306 can be a 100 kilohm resistor and can be the resistor 304 be an 80 kilohm resistor. In some embodiments, the bias on the bus 106 (provided by the power supply of the master transceiver) is between 4 volts and 8 volts (eg, 7 volts). In some embodiments, the through the voltage provided local slave power supply be greater than 4 volts (eg 8 volts). In some embodiments, the voltage provided by the local slave power supply may be greater than the bias on the bus 106 be; if this condition is met, the slave transceiver can be powered by its local power supply, and if this condition is not met, the slave transceiver can be biased onto the bus 106 be supplied.

There may be any suitable components in the support circuitry 320 or 321 be used. For example, as mentioned above, any of the diodes may be provided by another unipolar device. In some embodiments, the diodes may be low-leakage diodes or opto-diodes. In some embodiments, the diodes may have a leakage of less than 1 microampere.

15-16 show extensions of the arrangement of 14 which enable additional slave devices downstream of the adaptively powered slave device. These arrangements allow the supply of downstream slave devices with power through the bus 106 no interruption, regardless of whether the adaptively powered slave device is locally powered by the bus 106 or switch between the two. One or more of the downstream slave devices may themselves be adaptively powered by any of the techniques disclosed herein.

In 15 and 16 is the "B-side" of the backup circuitry 321 including LPF and HPF connected to a signal downstream segment of the bus 106 are shown. The support circuitry has one between the local power supply of the slave device and the "positive" line of the downstream bus segment 106 switched diode 311 on.

The embodiment of 15 has one between the voltage input of the slave transceiver and the output terminal of the diode 311 switched diode 310 on. The diode 310 Interruption of the power (not shown) to additional downlink slave devices while the adaptively powered slave device transitions between different power sources can prevent interruption of communication with the additional downlink slave devices without rediscovery.

The embodiment of 16 has one between the input terminal of the diode 301 and the output terminal of the diode 311 switched diode 313 on. Like the ones above with regard to 15 discussed diode 310 can the diode 313 Interrupting the supply of additional downstream downstream slave devices (not shown) while the adaptively powered slave device transitions, reduces, or prevents different power sources, allowing continued communication with the additional downlink slave devices without rediscovery. The embodiment of 16 can reduce the voltage drop across nodes in the system 100 occurs, and may allow the voltage input of the adaptively powered slave transceiver to see the same voltage as the bias applied to the next downstream slave device.

The following paragraphs give examples of various embodiments disclosed herein.

Example 1 is a slave device capable of adaptively using multiple power supplies, comprising: an upstream transceiver for coupling to an upstream link of a bus of a communications system; and circuitry for coupling to the bus's upstream link and to a local power supply, the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the bus's upstream link to the supply the slave device is used with power.

Example 2 includes the subject matter of Example 1, and further provides that the circuitry for switching from providing the local power supply to power the slave device with power to provide bus power provided by the signal's uplink to power the slave device. A power device is when a voltage provided by the local power supply falls below a bias of the bus's uplink.

Example 3 includes the subject matter of any of Examples 1-2 and further provides that the circuitry includes a unipolar device for coupling between the upstream signal of the bus and a reference ground.

Example 4 includes the subject matter of Example 3 and further contemplates that the unipolar device limits power flow from the signal's uplink to the reference ground.

Example 5 comprises the subject matter of any one of Examples 1-4 and further provides that the Circuitry includes a filter for controlling a turn-on time when the circuitry switches to providing bus power provided by the signal's uplink to supply the slave device.

Example 6 includes the subject matter of any of Examples 1-5, and further provides that the circuitry further includes switching from providing bus power provided by the upstream connection of the bus to powering the slave device with power to provide the local power supply Serving the slave device with power is used.

Example 7 includes the subject matter of Example 6 and further provides that the circuitry for switching provision of power supplied by the upstream connection of the bus to power the slave device with power to provide the local power supply to power the slave device is used when a bias of the signal up-link of the bus falls below a voltage provided by the local power supply.

Example 8 includes the subject matter of any of Examples 1-7, and further provides that the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the signal's uplink to supply the power Serves slave device with power without interruption of communication on the upstream connection of the bus.

Example 9 includes the subject matter of any of Examples 1-8, and further provides that the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the signal's uplink to supply the power Slave device with power without triggering a line fault is used.

Example 10 includes the subject matter of any of Examples 1-9, and further provides that the upstream connection of the bus is a two-wire connection.

Example 11 includes the subject matter of any of Examples 1-10 and further includes: a downstream transceiver for coupling to a downstream link of the communication system's bus; the circuitry further being for providing power to the downstream link.

Example 12 includes the subject matter of Example 11 and further provides that the circuitry for providing power to the downlink connection from the local power supply serves when the local power supply powers the slave device.

Example 13 includes the subject matter of Example 12, and further provides that the circuitry for providing power to the downstream link is from the bus power when the bus power powers the slave device.

Example 14 includes the subject matter of any of Examples 1-13 and further contemplates that the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the signal's uplink to power the slave Serves slave device with power without triggering a rediscovery of the slave device in the communication system.

Example 15 includes the subject matter of any of Examples 1-14 and further provides that the upstream signal transceiver for periodically receiving a synchronization control frame from the upstream signal connection of the bus.

Example 16 includes the subject matter of any of Examples 1-15 and further includes processing circuitry for generating a clock signal based on a signal received by the upstream signal transceiver via the upstream link from an upstream device, wherein a Timing of receiving and providing signals over the bus by the slave device based on the clock signal.

Example 17 includes the subject matter of Example 16, and further provides that generating the clock signal based on the signal generating the clock signal based on a preamble of a synchronization control frame in the signal.

Example 18 is a communication system that can adaptively use multiple power supplies to power a communication device comprising: a master device; a slave device; and a communication connection between the master device and the slave device, wherein the master device is for providing a bias voltage on the communication link, and the slave device is for switching circuitry to be powered by a local power supply to be supplied by the bias on the communication link.

Example 19 includes the subject matter of Example 18 and further provides that the slave device is a first slave device, the communication link is a first communication link, and the communication system further comprises: a second slave device; and a second communication connection between the first slave device and the second slave device.

Example 20 includes the subject matter of Example 19, and further provides that the circuitry further serves to provide a bias on the second communication link.

Example 21 includes the subject matter of any of Examples 18-20 and further includes: a speaker or microphone coupled to the slave device.

Example 22 is a method of providing a slave device in a communication system with power without interruption of communication in the communication system, comprising: using a local power supply to power the slave device; and using a bias voltage from an upstream communication link to power the slave device upon detection of an interruption or inadequacy of the local power supply.

Example 23 includes the subject matter of Example 22 and further includes using the local power supply to power the slave device upon detection of resumption or inadequacy of the local power supply after use of the bias voltage from the upstream communication link to power the slave device. Device with power.

Example 24 includes the subject matter of any of Examples 22-23 and further includes: transmitting or receiving data on the upstream communication link during detection of the interruption or deficiency of the first power supply, wherein the sending or receiving is not interrupted.

Example 25 includes the subject matter of any of Examples 22-24 and further includes using the bias voltage from the upstream communication link to provide a bias voltage for a downstream communication link upon detection of the interruption or inadequacy of the local power supply.

Example 26 is a method of providing power to a slave device in a communication system without interrupting communication in the communication system, comprising: using a first power supply to power the slave device; and using a second power supply to power the slave device with power upon interruption or deficiency of the first power supply, wherein the first power supply is different from the second power supply, the first power supply is one of a local power supply and a bias of an upstream communications link, and the second power supply is another of the local power supply and the bias voltage from the upstream communication link.

Example 27 includes the subject matter of Example 26 and further includes: using the first power supply to power the slave device with power upon resumption or inadequacy of the first power supply after using the second power supply to power the slave device.

Example 28 includes the subject matter of any of Examples 26-27, and further includes: transmitting or receiving data on the upstream communication link during the interruption or inadequacy of the first power supply, wherein the sending or receiving is not interrupted.

Example 29 includes the subject matter of any of Examples 26-28 and further includes using the second power supply to generate a bias voltage for a downstream communication link upon interruption or inadequacy of the first power supply.

Example 30 is a communication system with adaptive power supply functionality according to any of the embodiments disclosed herein.

Example 31 is a method of providing adaptive power to a slave device in accordance with any of the embodiments disclosed herein.

Example 32 is support circuitry coupled to a slave device to make the slave device adaptive Provide power supply functionality according to any of the embodiments disclosed herein.

Example 33 is a method of operating a slave device in a communication system, comprising: engaging in communication in the communication system during reception of power from a local power supply and continuing to participate in communication without interruption or rediscovery in the communication system while the communication system is in progress Reception of power from the local power supply stopped and power received from a bus bias.

Example 34 may be subject-matter of Example 33, and may further specify that stopping the receipt of power from the local power supply and receiving power from a bus bias voltage when a voltage received from the local power supply is below a voltage received from the bus bias voltage falls.

Example 35 may include the subject matter of any of Examples 33-34, and may continue after continuing to participate in communication without interruption or rediscovery in the communication system while stopping receipt of power from the local power supply and receiving power from a bus bias Participate in communication without interruption or rediscovery in the communication system during the stop of receiving power from the bus bias and receiving power from the local power supply.

Example 36 is a slave device having means for performing any of the adaptive power delivery methods disclosed herein.

In one aspect, disclosed herein are systems and techniques for adaptively using multiple power supplies in a communication system. For example, in some embodiments, a slave device may include: an upstream transceiver for coupling to an upstream link of a bus of a communications system; and circuitry for coupling to the bus's upstream link and to a local power supply, the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the bus's upstream link to the supply the slave device is used with power.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 62532658 [0001]
• US 16020812 [0001]

Claims (25)

A slave device that can adaptively use multiple power supplies, comprising: an upstream transceiver for coupling to an upstream link of a bus of a communications system; and A circuit technique for coupling to the bus's upstream link and to a local power supply, the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the bus's upstream link to supply the bus Slave device with power is used. Slave device after Claim 1 wherein the circuitry for switching from providing the local power supply to powering the slave device with power to provide bus power provided by the upstream bus connection provides power to the slave device when a voltage provided by the local power supply falls under a bias of the signal's uplink on the bus. A slave device according to any one of the preceding claims, wherein the circuitry comprises a unipolar device for coupling between the upstream signal of the bus and a reference ground. Slave device after Claim 3 wherein the unipolar device limits power flow from the signal's uplink to the reference ground. A slave device as claimed in any one of the preceding claims, wherein the circuitry comprises a filter for controlling a turn-on time when the switching circuitry switches to providing bus power provided by the signal's uplink to power the slave device. A slave device as claimed in any one of the preceding claims, wherein the circuitry further is for switching from providing bus power provided by the upstream connection of the bus to powering the slave device with power to provide the local power supply to power the slave device , Slave device after Claim 6 wherein the circuitry for switching supply of power supplied by the upstream connection of the bus to power the slave device provides power to provide the local power supply to power the slave device when a bias is applied to the upstream connection of the bus falls below a voltage provided by the local power supply. A slave device according to any one of the preceding claims, wherein the circuitry for switching from providing the local power supply to power the slave device to provide bus power provided by the signal's uplink to power the slave device without interrupting communications on the upstream Connection of the bus is used. A slave device according to any one of the preceding claims, wherein the circuitry for switching from providing the local power supply to power the slave device provides power to provide bus power provided by the signal's uplink to power the slave device without triggering a power supply Line fault serves. A slave device according to any one of the preceding claims, wherein the upstream signal of the bus is a two-wire connection. A slave device according to any one of the preceding claims, further comprising: a downstream transceiver for coupling to a downstream link of the bus of the communication system; the circuitry further being for providing power to the downstream link. Slave device after Claim 11 wherein the circuitry is for providing power to the downlink connection from the local power supply when the local power supply powers the slave device. Slave device after Claim 12 wherein the circuitry is for providing power to the downstream link from the bus power when the bus power powers the slave device. A slave device as claimed in any one of the preceding claims, wherein the circuitry for switching provision of the local power supply to power the slave device provides power to provide bus power provided by the upstream connection of the bus to power the slave device with power without triggering a rediscovery of the slave device in the communication system. A slave device as claimed in any one of the preceding claims, wherein the upstream signal transceiver is for periodically receiving a synchronization control frame from the upstream signal link of the bus. A slave device according to any one of the preceding claims, further comprising: A processing circuit technique for generating a clock signal based on a signal received by the upstream signal transceiver over the upstream link from an upstream device, wherein timing of receipt and provision of signals over the bus by the slave device on the upstream link Clock signal based. Slave device after Claim 16 wherein generating the clock signal based on the signal generating the clock signal based on a preamble of a synchronization control frame in the signal. A communication system that can adaptively use multiple power supplies to power a communications device having power, comprising: a master device; a slave device; and a communication connection between the master device and the slave device, wherein the master device is for providing a bias voltage on the communication link, and the slave device circuitry for switching from being powered by a local power supply to by the bias on the Communications to be powered. Communication system after Claim 18 wherein the slave device is a first slave device, the communication link is a first communication link, and the communication system further comprises: a second slave device; and a second communication connection between the first slave device and the second slave device. Communication system after Claim 19 The circuit technique further provides for providing a bias on the second communication link. Communication system according to one of Claims 18 to 20 further comprising: a speaker or a microphone coupled to the slave device. A method of powering a slave device in a communication system with power without interruption of communication in the communication system, comprising: Using a first power supply to power the slave device; and Using a second power supply to supply the slave device with power at a break or inadequacy of the first power supply, wherein the first power supply is different from the second power supply, the first power supply is either a local power supply or a bias signal from an upstream communication link and the second power supply is the other of local power supply and the bias voltage from the upstream communication link. Method according to Claim 22 further comprising: using the first power supply to power the slave device with power upon resumption or inadequacy of the first power supply after using the second power supply to power the slave device. Method according to Claim 22 or 23 further comprising: transmitting or receiving data on the upstream communication link during the interruption or inadequacy of the first power supply, wherein the sending or receiving is not interrupted. Method according to one of Claims 22 to 24 further comprising: using the second power supply to generate a bias for a downstream communication link upon the interruption or inadequacy of the first power supply.

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