DE102018114437A1 - High-voltage DC power supply circuit - Google Patents

Abstract

A circuit is disclosed for a high voltage DC power supply having a plurality of series connected high voltage isolated DC-DC converter blocks. Each block includes a primary unit comprising: an inverter receiving input from a DC link and converting the input to high frequency voltage; a high frequency transformer receiving high frequency voltage from the high voltage DC isolation inverter and transmitting the high frequency voltage to a secondary unit; and the secondary unit for converting the high-frequency voltage into a DC voltage. Each block is configured to generate a fixed DC voltage and is sized to provide current equal to the nominal output DC current. One or more of the blocks are enabled or disabled by turning on or off high speed series solid state switches to produce the desired DC output voltage.

Description

TECHNICAL AREA

The present disclosure relates to the field of high voltage direct current (DC) power supply. In particular, the present disclosure provides a high voltage, high power power supply circuit.

BACKGROUND

The background description contains information that may be useful in understanding the present invention. It is not an admission that any information herein is prior art or relevant to the presently claimed invention or that a specifically or implicitly referenced publication is prior art.

High-voltage DC power supplies (HVPSs) based on tetrode-supported vacuum tubes have been used as a type of regulatory configuration in neutral beam (NB) systems for extracting and accelerating ion beams. While such vacuum tube based supplies are rugged with highly stable output, they have some disadvantages such as bulkiness, the need for multiple auxiliary systems for proper operation, and low operating efficiency. Also, electrical failure causes wear of cathodes and electrodes therein when the energy drained exceeds the recommended limits. So critical subsystems are needed to protect the vacuum tube itself. In addition, the vacuum tubes also exploit due to yarn breakage. Therefore, vacuum tubes in such systems result in significant maintenance expenditures and must be replaced after a certain number of operating hours.

Also, high voltage DC power supplies based on semiconductor switches have been used in various types of regulatory configurations in NB systems. For example, that Indian Patent No. 206556 and US Pat. US9041288B2 disclose pulse step modulation (PSM) based on high voltage power supplies. The U.S. Patent No. 5,638,263A discloses a DC power supply for low and medium DC loads with high current flow to the DC load with multisecondary transformer, chopper and current controller. The U.S. Patent No. 2016/0073298 A1 discloses various power conversion techniques for low voltage applications. In addition, the paper entitled '130 kV 130 A high voltage switching mode power supply for neutral beam plasma heating: design issues' (Fusion Engineering and Design 66 / 68 (2003) 615/620 to M / s Jema, hereinafter referred to as the Jema disclosure) provides a multi-module high power, high voltage power supply having an inverter, transformer, rectifier configuration with inverter side regulation using feedback voltage, but feedforward control.

While the above-mentioned semiconductor-based systems / devices offer several advantages over vacuum tube (typically tetrode) high voltage power supplies, even semiconductor-based HVACs have technical challenges and limitations.

In case of failure (BD) or arcing in the load, the output stage shuts down in these HVPSs (and also in most other known HVPS systems). Returning the output to required levels requires time. Repeated failures are not possible except in the Jema disclosure, but even there the frequency of repeated BD achieved is low.

Topologies of prior art techniques mostly use feedforward, with the regulation of the total output voltage of the power supply depending on the assumption that the output voltage of each module remains constant over the entire dynamic current output range. However, this is not the case in the practical implementation where the output voltage of each module, which in turn is unregulated, varies with the load current. US Pat. US9041288B2 Addresses this limitation by implementing boost converters in each module, thereby keeping the output voltage of each module regulated. However, this topology requires the use of an extra large capacitor value at the output of each module, which increases the energy drained in the event of failure or arcing as described above. The Jema disclosure implements a feedback loop for regulating the output voltage. The regulation takes place in the inverter part, which modulates at 2.778 kHz. Therefore, the minimum output voltage regulation time is about 360μs, which is a very long time period.

In addition, existing HVPSs employ sophisticated control logic and associated control hardware and generally use multi-secondary transformers of complicated and critical design and manufacture (including criticality of inter-winding capacity).

Further, most known techniques required the use of high filter capacity, while the Jema disclosure implements a system without a filter capacitor. In the Jema disclosure, the ripple reduction is not Delay-free and requires about 3 ms to calm down. In addition, since the system utilizes modulation in the primary module at a fixed frequency of 2.778 kHz for lower output voltages, where the duty cycle decreases significantly (and thereby the output voltage becomes pulsating), low ripple can not be achieved without the use of an additional filter capacitor at the output ,

Since presently known techniques have no capability for high frequency output voltage modulation, there is a need in the art for a high voltage DC power supply circuit with a simple, flexible and adaptive topology and control circuit. There is a need in the art for a device based on such a circuit that can provide a much shorter minimum output voltage regulation time and recover quickly after single / multiple outages. Further, there is a need in the art for the device that can also provide a hot standby mode while limiting the energy drained into the load at each failure, and having the output voltage modulation capacitance (an important requirement for NB sources). , There is also a need for the device to be much smaller than existing devices for the same output ratings, to use easily and quickly manufactured components, and to be easily scalable and any type of load, continuous, step or arbitrary profile, over a wide current demand range to be able to handle zero load.

TASKS OF THIS DISCLOSURE

Some of the objects of the present disclosure that satisfy at least one embodiment herein are set forth hereinbelow.

It is an object of the present disclosure to provide a circuit for a high voltage DC power supply for generating high voltage, high voltage, continuous mode DC power.

It is another object of the present disclosure to provide a circuit for a high voltage DC power supply which can float at high potential (100kV DC).

It is still another object of the present disclosure to provide a circuit for a high voltage DC power supply having the ability to provide output voltage with a short rise time (<1ms).

It is an object of the present disclosure to provide a circuit for a high voltage DC power supply that can detect and endure repeated failures / short circuits (typically 200 ns) at its output terminals.

It is a further object of the present disclosure to provide a high voltage DC power supply circuit that interrupts high speed (<5 μs) DC output voltage in the event of dropouts / short circuits at its output terminals.

It is still another object of the present disclosure to provide a circuit for a high voltage DC power supply that can keep output DC voltage blocked for a fixed period of time (adjustable from 100 μs to 100 s of ms or beyond) and bring the DC output voltage back to its last setpoint ,

It is an object of the present disclosure to provide a high voltage DC power supply circuit that sets the number of allowable failures / short circuits at its output terminals that can actually count out-of-output failures and break the DC output voltage if the number of actual failures equals the setpoint the permissible failures.

It is another object of the present disclosure to provide a circuit for a high-voltage DC power supply of optimized design to limit the energy discharged in the event of failure / short circuit to <10J.

It is still another object of the present disclosure to provide a high voltage DC power supply circuit circuit with low voltage ripple and good output voltage regulation.

It is an object of the present disclosure to provide a high voltage DC power supply circuit with a simpler HV disconnect mechanism.

It is another object of the present disclosure to provide a high voltage DC power supply circuit having a simpler feedback control system for controlling the output HVDC.

It is still another object of the present disclosure to provide a circuit for a high voltage DC power supply Provide function to provide protection against output overvoltage and overcurrent.

It is an object of the present disclosure to provide a high voltage DC power supply circuit having a DC output voltage modulation function (typically 5 Hz to 0.5 kHz).

It is another object of the present disclosure to provide a circuit for a high voltage (> 85%) high voltage DC power supply.

It is still another object of the present disclosure to provide a circuit for a high voltage DC power supply that uses a simple, flexible and adaptable control circuit with very short response time for output voltage regulation.

It is an object of the present disclosure to provide a high voltage DC power supply circuit having a hot standby mode.

It is another object of the present disclosure to provide a circuit for a high voltage DC power supply that is much smaller than existing devices for the same output ratings.

It is another object of the present disclosure to provide a high voltage DC power supply circuit that uses fast and easy to manufacture components.

It is an object of the present disclosure to provide a circuit for a high voltage DC power supply that is easily scalable and that can handle any type of load, continuously, incrementally or with any profile, over a wide range of current requirements up to no-load.

SUMMARY

The present disclosure relates to a high voltage DC power supply that uses a new circuit topology to achieve performances that are far better than existing ones.

In one aspect, the present disclosure illustrates a high voltage DC power supply circuit comprising a plurality of series-connected high-voltage isolated DC-DC converter blocks, each block including: a primary unit having an inverter receiving an input from a DC link; Input to high frequency voltage converts; a high frequency transformer that receives the high frequency voltage from the high voltage DC isolation inverter and transmits the high frequency voltage to a secondary unit; and the secondary unit for converting the high frequency voltage into a DC voltage, the secondary unit comprising a high frequency full bridge rectifier, a low capacity filter, a high speed series solid state switch, and a solid state parallel switch, each block sized to supply a current equal to the nominal DC output current, and wherein the output of one or more of the blocks is enabled or disabled by turning on or off the high speed series solid state switches of respective blocks to achieve a desired DC output voltage (Fig. V _out ) to create.

In another aspect, the plurality of blocks may include vernier blocks and solid blocks, where each of the vernier blocks may be configured to give a DC output voltage that is a fraction of or less than that of any of the solid blocks, and in FIG Combination with one or more full blocks can be used to set the desired DC output voltage ( V _out ) with minimal voltage resolution V _min to obtain.

wobei V_i die Ausgangsspannung des i-ten Vernier-Blocks ist.In yet another aspect, the circuit may provide the desired DC output voltage by turning on 'n' full blocks according to the DC output voltage of each full block ( V _full ) and turn on 'm' vernier blocks based on the required DC residual voltage, such that: $$\left(V_{Out}\right)=n*V_{full}+{\displaystyle {\Sigma }_{i=1}^m{V}_i}$$

where V _{i is} the output voltage of the ith vernier block.

In one aspect, the minimum _voltage given by one of the vernier blocks may be defined as V _vernier-1 = V _min / K at full load, where K is a decay ratio of the high frequency transformer of the vernier block, where the drop ratio is V_ _(no-load / ₎ V_ _(full-load) is, where
V_ _{(no-load) is} the secondary voltage of the high frequency transformer of the Vernier block at _{no load} , and
V_ _{(full-load) is} the secondary voltage of the high frequency transformer of the Vernier block at full load.

In another aspect, the vernier blocks may be configured such that the sum of Output voltages of each vernier block in the output voltage of a solid block, indicated by: $${\text{V}}_{\text{full}}={\text{V}}_{\text{vernier-1}}+{\text{V}}_{\text{vernier-2}}+{\text{V}}_{\text{vernier-3}}+...+{\text{V}}_{\text{vernier-n}}$$

In yet another aspect, the number of required blocks may be given by the following relation: $$\frac{V_{Out}}{V_{full}}-1$$

In one aspect, the high speed series solid state switch of each block may be turned on or off by a control circuit comprising a programmable master digital controller.

In another aspect, the control circuit may use a voltage feedback system that compares a signal received from a floating voltage sensor with a required DC output voltage signal to derive a correction signal on the basis of which the main programmable digital controller may decide which DC-DC signals to use. Transformer blocks must be turned on or off to produce the desired DC output voltage.

In yet another aspect, in the event of a failure at output terminals or when the output current exceeds a predetermined threshold, the secondary units of respective blocks that are turned on at that time may be turned off at high speed within a break time period and remain off for a lock time the main programmable digital controller can turn on the high-speed series solid state switches of the secondary units and simultaneously turn off the solid state parallel switches of the secondary units to achieve the last set point of the DC output voltage within a short period of time.

In one aspect, the primary unit of each block may include a full-bridge inverter operating with a ZVS (zero voltage switching) phase-shifted technique.

Various objects, features, aspects and advantages of the present disclosure will become apparent from the following detailed description of preferred embodiments, taken in conjunction with the accompanying drawings, in which like reference numerals represent like features.

list of figures

• 1 einen Stromkreis für eine typische RF-angesteuerte Negativionenquelle für eine NB-(Neutralstrahl)-Anwendung;
• 2A das Gesamtlayout eines vorgeschlagenen Hochspannungs-Gleichstromversorgungskreises gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 2B einen eingehenden Leistungsschalter und eine Gleichrichtungseinheit für den vorgeschlagenen Hochspannungs-Gleichstromversorgungskreis gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 3A ein Modul des vorgeschlagenen Hochspannungs-Gleichstromversorgungskreises gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 3B Schalter-Gate-Pulse eines Wechselrichters des vorgeschlagenen Hochspannungs-Gleichstromversorgungskreises gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 4 ein Steuerschema für den vorgeschlagenen Hochspannungs-Gleichstromversorgungskreis gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 5A bis 5D über grafische Darstellungen die Funktionsweise des Hochgeschwindigkeits-Gleichstromversorgungskreises unter verschiedenen Situationen, gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 6A bis 6C Konstruktionsdetails des in dem vorgeschlagenen Hochspannungs-Gleichstromversorgungskreis benutzten Hochfrequenztransformators gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 7 eine Kühlanordnung für einen Transformator, der in dem vorgeschlagenen Hochspannungs-Gleichstromversorgungskreis benutzt wird, gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 8 typische Verbindungen von Primär- und Sekundäreinheiten mit dem Transformator für den vorgeschlagenen Hochspannungs-Gleichstromversorgungskreis gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung;
• 9A und 9B eine Gestellanordnung für den vorgeschlagenen Hochspannungs-Gleichstromversorgungskreis gemäß einer beispielhaften Ausgestaltung der vorliegenden Offenbarung.

The accompanying drawings are included to provide a more thorough understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The diagrams are for illustration only and thus not intended to limit the present disclosure. Showing:

• 1 a circuit for a typical RF driven negative ion source for NB (neutral beam) application;
• 2A the overall layout of a proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure;
• 2 B an incoming power switch and a rectification unit for the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure;
• 3A a module of the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure;
• 3B Switch gate pulses of an inverter of the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure;
• 4 a control scheme for the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure;
• 5A to 5D graphs illustrating the operation of the high-speed DC power supply circuit under various situations, according to an exemplary embodiment of the present disclosure;
• 6A to 6C Construction details of the high-frequency transformer used in the proposed high-voltage DC power supply circuit according to an exemplary embodiment of the present disclosure;
• 7 a cooling arrangement for a transformer used in the proposed high voltage DC power supply circuit, according to an exemplary embodiment of the present disclosure;
• 8th typical connections of primary and secondary units to the transformer for the proposed high voltage DC supply circuit according to an exemplary embodiment of the present disclosure;
• 9A and 9B a rack assembly for the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION

The following is a detailed description of embodiments of the disclosure illustrated in the accompanying drawings. The embodiments are so detailed that they clearly convey the disclosure. However, the amount of detail provided is not intended to limit the anticipated variations of embodiments, but on the contrary, to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

In some embodiments, numbers that express quantities or dimensions of parts and so forth used to describe and claim certain embodiments of the invention shall, in some cases, be understood as modified by the term "about." Accordingly, in some embodiments, the numerical parameters set forth in the written description and the appended claims are approximations that may vary depending on the desired characteristics to be achieved by a particular embodiment. In some embodiments, the numerical parameters are to be understood in terms of the number of reported significant digits and using ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters that set forth the broad scope of some embodiments of the invention are approximate, the numerical values are given as precisely as practically possible according to the specific examples. The numerical values given in some embodiments of the invention may include certain errors that necessarily result from the standard deviation found in their respective test measurements.

The indication of ranges of values herein is to be considered as a quick method that relates individually to each separate value falling within the range. Unless otherwise stated herein, each individual value in the specification is incorporated as if individually indicated therein. All methods described herein may be performed in any suitable order, unless otherwise stated herein or clearly stated otherwise by the context. The use of any and all examples or exemplary language (e.g., "such") as referred to with respect to particular embodiments herein is intended merely to better illuminate the invention and not to limit the scope of the invention claimed otherwise. No language in the specification is to be construed as indicating an unclaimed element essential to the practice of the invention.

Groupings of alternative elements or embodiments of the invention disclosed herein are not to be considered as limitations. Each group element may refer to other elements of the group or other elements found herein and be claimed individually or in any combination. One or more elements of a group may be included in or removed from a group for practical reasons and / or for patentability reasons. In the event of such inclusion or removal, the specification herein is considered to contain the Group modified to conform to the written description of all groups used in the appended claims.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that embodiments of the present invention may be practiced without some of these specific details.

Embodiments of the present invention include various steps that are described below. The steps may be performed by hardware components or embodied in machine-executable instructions that may be used to cause a general purpose or special purpose processor to be programmed with the instructions to perform the steps. Alternatively, steps may be performed by a combination of hardware, software, and firmware and / or by human operators.

If the specification pretends to contain a component or function, or has a "may," "could," or "possibly could" characteristic, then it is not required that this particular component or function be included or have the characteristic ,

The meaning of "a" as used in the description herein and in the following claims also includes the plural when the Context not clearly dictates something else. Likewise, the meaning of "in" as used in the description includes "in" and "on" if the context does not clearly dictate otherwise.

Exemplary embodiments will now be described in more detail with reference to the accompanying drawings in which exemplary embodiments are shown. These exemplary embodiments are given for illustrative purposes only, and thus the present disclosure is thorough and complete, and fully conveys the scope of the invention to one of ordinary skill in the art. However, the disclosed invention may be embodied in many different forms and is not to be considered as limited to the embodiments set forth herein. Various modifications will be quite obvious to the skilled person. The general principles defined herein may also be applied to other embodiments and applications without departing from the spirit and scope of the invention. In addition, all statements herein, indicating the embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future (i.e., elements that perform the same function independent of structure). Likewise, the terminology and language used are intended to describe exemplary embodiments only and are not to be considered as limiting. Thus, it is to be accorded the widest scope to the present invention which encompasses numerous alternatives, modifications, and equivalents consistent with the principles and features disclosed. For the sake of clarity, details relating to technical material known in the technical fields with respect to the invention have not been presented in detail so as not to unnecessarily obscure the present invention.

For example, one of ordinary skill in the art will understand that diagrams, schematics, illustrations, and the like represent conceptual views or processes that illustrate systems and methods embodying the present invention. The functions of the various elements shown in the figures can be provided by using dedicated hardware and hardware that can execute associated software. Likewise, switches shown in the figures are merely conceptual. Their function may be performed by the operation of program logic, by dedicated logic, by the interaction of program control and dedicated logic, or even manually, with the particular technique being selectable by the entity implementing the present invention. One of ordinary skill in the art will further appreciate that the exemplary hardware, software, processes, methods and / or operating systems described herein are for illustrative purposes only and are not to be construed as limited to any particular named element.

Each of the appended claims defines a separate invention which, for injury purposes, is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, in some cases, subsequently, all references to the "invention" may refer only to certain specific embodiments. In other cases, it will be appreciated that references to the "invention" refer to an item as recited in one or more, but not necessarily all, of the claims.

All methods described herein may be performed in any suitable order unless otherwise indicated or unless the context clearly dictates otherwise. The use of any and all examples or exemplary language (e.g., "such") as given with respect to particular embodiments herein is intended merely to better illuminate the invention and is not intended to limit the scope of the invention otherwise claimed. No language in the specification is to be construed as indicating any unclaimed element essential to the practice of the invention.

Various terms as used herein are shown below. To the extent that a term used in a claim is not defined below, it must be given the broadest definition that persons in relative technology have associated with that term as reflected in printed publications and issued patents at the time of filing.

The present disclosure relates to a high voltage DC power supply that uses a new circuit topology to achieve outputs that are significantly better than existing ones.

In one aspect, the present disclosure discusses a high voltage DC power supply circuit comprising a plurality of series-connected high voltage isolated DC-DC converter blocks, each block including: a primary unit having an inverter receiving an input from a DC link and having the input in High frequency voltage converts; a high frequency transformer, which the Receiving high frequency voltage from the inverter for high voltage DC isolation and transmitting the high frequency voltage to a secondary unit; and the secondary unit for converting the high frequency voltage to a DC voltage, the secondary unit comprising a high frequency full bridge rectifier, a low capacity filter, a high speed series solid state switch, and a solid state parallel switch, each block sized to supply current equal to the nominal DC output current, and wherein the output of one or more of the blocks is enabled or disabled by turning on or off the high speed series solid state switches of respective blocks to obtain a desired DC output voltage (Fig. V _out ) to create.

In another aspect, the plurality of blocks may include vernier blocks and solid blocks, wherein each of the vernier blocks may be configured to give a DC output voltage that is a fraction of and less than any of the solid blocks, and in combination with one or more full blocks can be used to obtain the desired DC output voltage ( V _out ) with minimal voltage resolution V _min to obtain.

wobei V_i Ausgangsspannung des i-ten Vernier-Blocks ist.In yet another aspect, the circuit may provide the desired DC output voltage by turning on 'n' full blocks according to the DC output voltage provided by each full block ( V _full ) and switching on, m 'vernier blocks on the basis of the required residual DC voltage, so that: $$\left(V_{Out}\right)=n*V_{full}+{\displaystyle {\Sigma }_{i=1}^m{V}_i}$$

where V _{i is the} output voltage of the ith vernier block.

In one aspect, the minimum _voltage indicated by one of the vernier blocks may be defined as V _vernier-1 = V _min / K) at full load, where K is the drop ratio of the high frequency transformer of the vernier block, where the drop ratio is V_ _(no-load / ₎ V_ ( _full-load) is, where
V_ _{(no-load) is} the secondary voltage of the high frequency transformer of the Vernier block at _{no load} , and
V_ _{(full-load) is} the secondary voltage of the high frequency transformer of the Vernier block at full load.

In another aspect, the vernier blocks are configured such that the sum of output voltages of each vernier block results in the output voltage of a solid block, indicated by: $${\text{V}}_{\text{full}}={\text{V}}_{\text{vernier-1}}+{\text{V}}_{\text{vernier-2}}+{\text{V}}_{\text{vernier-3}}+...+{\text{V}}_{\text{vernier-n}}$$

In yet another aspect, the required number of full blocks may be given by the following relationship: $$\frac{V_{Out}}{V_{full}}-1$$

In one aspect, the high speed series solid state switch of each block may be turned on or off by a control circuit comprising a programmable master digital controller.

In another aspect, the control circuit may use a voltage feedback system that compares a signal received from a floating voltage sensor with a required DC output voltage signal to derive a correction signal on the basis of which the main programmable digital controller may decide which DC-DC signals to use. Transformer blocks must be turned on or off to achieve the desired DC output voltage.

In yet another aspect, in the event of a failure at output terminals or when output current exceeds a predetermined threshold, the secondary units of respective blocks that are turned on at that moment may be turned off at high speed within a break time period and remain off for a lock time after the main programmable digital controller can turn on the secondary unit's high speed series solid state switches and simultaneously turn off the solid state parallel switches of the secondary units to reach the last set point of the DC output voltage within a short period of time.

In one aspect, the primary unit of each block may include a full-bridge inverter operating with a ZVS (zero voltage switching) phase-shifted technique.

The present disclosure discusses a high voltage, high performance, floating DC regulated power supply circuit (hereinafter referred to as interchangeably proposed circuit) for a power supply / device. The proposed circuit uses a new topology consisting of multiple numbers of series-connected DC-DC converter blocks (hereafter referred to as DCCONs), each block consisting of: a primary unit comprising an inverter receiving input from a DC link and him in converts a high frequency voltage; a high-frequency transformer (hereinafter also referred to as high-frequency isolation transformer or transformer) receiving the high-frequency voltage from the inverter for high-voltage direct current isolation, which enables floating of the power supply to high potentials (typically 100 KV DC); and a secondary unit comprising a high frequency full bridge rectifier and a high speed solid state switch. The required DC input to the primary units is fed by an input rectifier equipped with a pre-charge circuit that receives mains power from a circuit breaker. An LR snubber is connected to the output of the proposed circuit to limit the rate of increase of the output leakage current. The circuit is also equipped with a programmable digital controller that controls and monitors the power supplied by the circuit.

In one aspect, the DC output of the disclosed circuit may be regulated or varied in series by switching the output of each DC-DC converter, wherein the amount of DC-DC converters may be decided based on the required DC output voltage. Each DC-DC converter can generate a fixed DC voltage and can be sized to provide current equal to the nominal output DC current. The required output voltage can be achieved by enabling or disabling the required modules (each module being a DC-DC converter) by turning the high-speed semiconductor switch of each module on or off by a control circuit. In order to achieve the minimum resolution, some DC-DC converters can produce a fixed voltage, but with a value equal to or less than the required minimum voltage resolution. The voltage feedback system operates on the basis of the signal received from a floating voltage sensor, the signal can be compared with the required output voltage signal in the control circuit and thereby generate a correction signal. The control algorithm may determine, on the basis of the correction signal, the number of DC-DC converters that must be turned on or off to obtain the required voltage, thereby simplifying the control. Voltage rise, voltage variation, voltage modulation and voltage regulation can be achieved dynamically on a very fast time scale using signal communication on a fiber optic basis. Further, the control circuit may monitor and protect the device based on the proposed circuit versus output overvoltage and overcurrent.

A phase-shifted full-bridge topology based on zero voltage switching (ZVS) can be used in the inverters to reduce switching losses. The inductance needed for the ZVS can be practically provided by the high frequency transformer. The circuit implements a simpler feedback mechanism for regulating output voltage. The DC output voltage is regulated or varied by enabling or disabling the high speed solid state switch in the secondary units with the main controller in the feedback loop. Since rectification occurs in each secondary unit at a very high frequency (typically 25 kHz or above), the capacitance required for filtering is extremely low, so that the energy dumped into the load in the event of light bottoming or failure (BD) is reduced. The disclosed circuit relates to a truly stabilized, modular and scalable closed-loop HVPS that can handle any type of load, continuously, incrementally or with any profile, over a wide range of current requirements up to no-load. Further, in the case of BD or arcing in the load, the output stage of a device based on the proposed circuit goes into a hot standby mode, so again it stays on for less than 100 μs to 100 ms or more, which is user input can be adjusted, including the BD, which takes place at a floating high voltage potential. The proposed circuit thus supports the feature of allowing and sustaining multiple BDs while limiting the energy drained into the load at each BD (typically <10J).

The disclosed circuit may refer to a truly floating system where one end can be grounded or both ends can float to potential (typically 100 kV or above). In one implementation, the user interface control logic and power control logic for the disclosed circuit may be extremely simple, flexible, and adaptive. The power control logic can be made simple by requiring that the required set of modules be turned on or off according to the desired output voltage / voltage. Increasing the rated voltage or even decreasing can be done simply by adding or removing the required number of modules. Similarly, the disclosed invention can do without multi-secondary transformers and all their associated problems.

It will be appreciated that the proposed circuit will find particular utility in neutral beam (NB) sources for heating tokamak plasmas and also for plasma diagnostics The devices for generating feedback-controlled regulated and variable high-voltage DC current with short rise time (<1 ms) and high efficiency (> 85%) with a stored total energy of <10J, fast output voltage interruption (< 5 μs) in the event of a fault, capacity to withstand repeated failures (typically 200 ns) with automatic high speed (<5 μs) interruption after each failure event for typically 15 ms and automatic release of the output voltage back to the last nominal level with short Rise time (<1 ms), capacity to withstand continuous full power rated operation for typically 3600 s and ability to float (or lift) to high potential (voltage) of 100 kVDC or more. The control circuit of the proposed circuit may have the ability to have a number of allowable failures / short circuits at the output terminals and also to count the failures actually occurring at the output and to interrupt the DC output voltage if the actual number of failures exceeds the fixed number of failures permissible failures.

The proposed circuit may allow a device that can deliver high efficiency rated power while floating at high potential with easier HV disconnect mechanism, short rise time, low ripple, and good control with a simpler feedback control mechanism to control the output; the enabled device can withstand and allow repeated outages at the output limiting the energy lost during the fault within 10J; it can break the output voltage at high speed and block it for a fixed period of time before bringing the output voltage back to its last set point on each failure / short circuit; it can modulate the output voltage and can provide protection against output overvoltage and overcurrent.

In one aspect, the proposed circuit may use a simplified isolation scheme that may be integral to the DCCON. The high-frequency transformer used in the DCCON can have a very compact size, a simpler structure, simpler cooling requirements and the ability to withstand high-voltage direct current isolation between the primary side and the secondary side and secondary side and core.

In another aspect, the secondary side of the high frequency transformer (isolation transformer) may feed the secondary unit (AC-DC converter) of the proposed circuit, which includes a high frequency rectification unit. Since the rectification unit operates at high frequency, the value of the output filter capacitor is drastically reduced and thus can be completely avoided, thereby reducing the size and the stored energy. The rectification unit can also use a controllable high speed semiconductor switch at the output, which can interrupt the output voltage (in the case of errors) at very high speed (on the order of a few microseconds).

In another aspect, the proposed circuit implements a feedback-controlled power supply with short rise time, good and dynamic voltage regulation, and a simpler feedback control mechanism for regulating the output voltage for variation and modulation. The proposed circuit may also implement elements for output overvoltage and overcurrent protection.

In one embodiment, due to high frequency rectification, the ripple value obtained at the output of each DCCON converter can be drastically reduced. The maximum ripple achieved on the device based on the proposed circuit may be a summation of the ripple contribution of each DC-DC converter (which includes a module) in the on state. In this way, the proposed circuit can achieve a low voltage ripple at the output.

1 illustrates a circuit for a typical RF driven negative ion source for neutral beam (NB) application.

A circuit for a typical RF driven negative ion source for neutral beam (NB) application is in FIG 1 shown. The ion source comprises several isolated lattice systems, namely plasma lattice (PG) 102 , Extraction grid (EG) 104 and ground grid (GG) 106 , The source is powered by a high power RF generator (RFG) 108 driven to generate plasma in the driver region 110 Also used with a low voltage plasma grid bias power supply (PGPS) 112 is biased. Typically two high voltage regulated DC power supplies (HVPS), namely extraction power supply (EPS) 114 and accelerator power supply (APS) 116 , switched via the grid system as shown in the figure. APS, which is related to the ground potential, is used to accelerate the ion beam, while EPS, which hovers above the APS potential, is used to extract the electrons. During operation of the circuit, both power supplies are synchronized so that they operate simultaneously.

The skilled person will recognize that the proposed circuit relates to power supplies with application and usage similar to EPS and / or APS. However, the disclosed circuit is not limited to use only in HVBs of NB systems, but may be implemented in any load requiring high voltage regulated DC, for example klystron, gyrotron, etc.

2A illustrates the overall layout of a proposed high voltage DC power supply circuit in accordance with an exemplary embodiment of the present disclosure.

In one aspect, the proposed circuit may be an input component U1 include a circuit breaker and a rectification unit with soft start function. The component U1 may convert an incoming three-phase voltage into unregulated DC voltage, illustrated as V-DL, for further use as set forth below.

In another aspect, the unregulated DC power supply V-DL may be applied to a modular DC-DC converter assembly (also called DCCON) through a DC link bus, hereafter referred to as DL. Each module of the DCCON can have a primary unit (as P1 . P2 , ... PN shown), which in turn with a high-frequency DC (HFDC) transformer (as T1 . T2 ... TN shown), which in turn feeds a secondary unit (as shown in FIG S1 . S2 ... SN shown). The secondary unit can generate a DC voltage. With a series switch (in 3A when SW5 shown) contained in each module of the DCCON, several modules of the DCCON can be interconnected to provide the required output.

In one aspect, each primary unit (PI, for example) may convert the unregulated DC power supply V-DL into a high frequency (typically 50 kHz) AC square wave with a H-bridge inverter based on a semiconductor switch (typically IGBT) as in FIG 3A with 308 indicated transform. Such a current can be the HFDC-insulated transformer T1 be fed to the corresponding secondary unit S1 can transfer.

A control scheme, as set out below, may turn on or off different modules of the DCCON as needed to determine the final output voltage that is in 2A as Vout is shown to vary. Optical fibers and corresponding controls, switches, etc. as described herein may be used for such switching.

2 B illustrates an input power switch and a rectification unit for the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure.

In one aspect, the component U1 an input power switch CB and a rectification unit SC, which is a three-phase full-bridge rectifier. The component U1 may also include controls and switches, etc. associated with the power switch CB and the rectifier SC as described herein.

In one aspect, the power switch CB may receive three-phase mains power. The CB can in turn supply power to the three-phase full-bridge rectifier SC. The rectifier SC can be configured as a half-converter, with thyristors TH1 . TH2 and TH3 upper legs form and the diodes D11 . D12 and D13 forming lower legs. Gate pulses of the thyristors may be connected to a precharge control circuit U10 being controlled. A second output can be derived from the output of the CB by the contactor CON, the switching of the CON can be controlled by its coil K, the coil K also by the Vorladesteuerung U10 can be controlled.

In another aspect, the output from the contactor CON may be applied to a precharge rectifier shown as PR, which is charged by the charging resistor R2 can be connected to a DC link bus. The DC link bus can provide the unregulated DC voltage illustrated as V-DL.

When the CB is first turned on, precharge control may be activated U10 Pulse of the thyristors TH1 . TH2 and TH3 lock for a predefined time (which _{may be} referred to as T _precharge ) so as to block the output of the SC. Since the SC is blocked, the precharge control can U10 close the contactor CON for the same time as T _precharge , with the result that the capacitor C6 (in 3A shown) of the primary unit P1 (as well as all currently connected / operating primary units of DCCON) through the precharge rectifier PR and the resistor R2 is loaded.

In yet another aspect, if the pre-defined time T _{precharge has} expired (ie if all the capacitors C6 loaded), the precharge control U10 Open the power contactor CON and gate pulses of the thyristors TH1 . TH2 and TH3 enable so that the rectifier SC closes, which can then feed the DC link bus with unregulated DC power V-DL. In this way, a soft start can be achieved through the implementation of the precharge circuit.

wobei N die Gesamtzahl der Kondensatoren C6 ist. The predefined time T _precharge is calculated by the following relation: $${\text{T}}_{\text{precharge}}\ge \text{R2}\times \text{N}\times \text{C6}$$

where N is the total number of capacitors C6 is.

In the case of overcurrent, as explained below, the power switch CB may be equipped with a main controller U2 (in 2A shown) by a fiber optic connection FOU1 (in 2A shown) with a control scheme according to 4 to be triggered.

3A FIG. 12 shows a module of the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure. FIG.

As discussed above, the proposed circuit includes modules of the DC-DC converter assembly referred to as DCCON. A DCCON is in 3A shown and can be a primary unit P1 for converting the unregulated DC power supply V-DL into a high frequency (typically 50 kHz) AC square wave with a H-bridge inverter (shown as 302) based on the semiconductor switch (typically IGBT) and an HFDC isolated transformer T1 include, the output of P1 into a corresponding secondary unit S1 can transfer.

In one aspect, the inverter 302 with ZVS (Zero Voltage Switching) topology using the leak inductance L of the transformer T1 and the capacity of capacitors C1 to C4 via semiconductor switch SW1 to SW4 (of the inverter 302 ) to achieve quasi-resonance.

In the manner mentioned primary units P1 ... PN the power supply / device based on the proposed circuit includes the full bridge inverter using ZVS (Zero Voltage Switching) technology. Phase-shifted high-frequency PWM pulses can be used as gate signals for the switches in the inverter 302 to be used. Furthermore, the primary units P1 ... PN with fans mounted in the corresponding primary units 304 Forced air cooled. As stated, input current to the inverter 302 V-DL, provided by the DC link bus of rectifier voltage SC (as in 3A illustrated).

In one aspect, the control power supply U9 single-phase mains current, shown as AC _supply , obtained from the AC mains supply available at the input of the input circuit-breaker and the rectifier unit provided by the component U1 is represented (in 2A illustrated).

In another aspect, the capacitors C1 . C2 . C3 . C4 and the diodes D7 . D8 . D9 . D10 each via the switch SW1 . SW2 . SW3 . SW4 be switched. The switches can be controlled by the local control of the U3 illustrated primary unit, which is interchangeably referred to as ZVS (Zero Voltage Switching) control. The ZVS control U3 in turn, from the main controller of the power supply U2 (in 2A shown).

In yet another aspect, the signal that drives the inverter 302 a primary unit P1 activates and turns on, from the ZVS control U3 through the as SP1A illustrated fiber optic cable from the main controller U2 (in 2A shown) while the status or error signal of the primary unit P1 by U3 to U2 through the fiber optic cable SP1B (in 2A shown) can be sent. The inductor L which is on the primary side of the high-frequency transformer T1 shown switched, can from the leakage inductance of the transformer T1 be derived.

In one aspect, the output of the transformer T1 the secondary unit S1 Food. The secondary unit S1 can be a high-frequency bridge rectifier 308 consisting of diodes D1 to D4 include, as shown above the filter capacitor C5 is switched. The filtered voltage output of the high frequency rectifier 308 can with the semiconductor serial switch SW5 be connected. Another semiconductor switch SW6 can be connected across the output terminals of the bridge rectifier as shown. The desk SW6 can be configured to be ON (closed) when SW5 OFF (open) or vice versa.

This way you can SW6 keep the output voltage to zero if SW5 is off, but due to the coupling capacity, some voltage continues to couple to the output. In addition, can SW6 the stored energy in the secondary unit S1 bypassing the output in case of external errors.

In another aspect, both switches SW5 and SW6 through the secondary unit control U4 which in turn are controlled by the programmable digital master controller U2 (in 2A shown) of the power supply can be controlled. The secondary unit control U4 can also power the secondary unit S1 through the current sensor CT1 to capture.

In yet another aspect, the signal may be to turn on SW5 the secondary unit S1 from the controller U4 through the fiber optic cable SS1A from U2 receive and the status or error signal of the secondary unit S1 from U4 to U2 through the fiber optic cable SS1b to be sent, as in 2A shown.

In one aspect, via the last voltage output terminals V-MOD of the secondary unit S1 a freewheeling diode D6 connected to provide a closing path for the last output voltage Vout of the proposed circuit (in 2A shown) regardless of the state of SW5 or SW6 can serve.

In another aspect, all secondary units such as S1 with the fan 306 forced air cooled in the secondary unit S1 can be mounted. The to drive from U4 required control voltage can through the secondary side of the transformer T1 be generated, thereby avoiding the need for a separate transformer.

In one aspect, ZVS (Zero Voltage Switching) control U3 required phase-shifted gate pulses for the switches SW1 . SW2 . SW3 and SW4 as in 3B produce shown.

In another aspect, the housing may be the primary unit P1 and the secondary unit S1 Made of aluminum material with curved edges to avoid sharp corners to minimize corona effect.

In another aspect, the high frequency transformer T1 to: (1) couple the primary side voltage to the secondary at high frequency, typically 50kHz, with the need to step up and down, (2) provide the required leakage inductance to achieve ZVS (zero voltage switching) in the inverter 302 , and (3) provide the required high voltage DC isolation (typically 100 kV) between the secondary side and the primary side and between the secondary side and the core of the transformer, while providing the nominal power (typically 20 kVA).

3B illustrates switch gate pulses of an inverter of the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure.

In one aspect, ZVS (Zero Voltage Switching) control U3 the required phase-shifted gate pulses for the switches SW1 . SW2 . SW3 and SW4 as shown.

4 illustrates a control scheme for the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure.

As described, the primary unit includes P1 the proposed circuit an inverter 302 by a ZVS controller U3 which controls the required phase-shifted gate pulses for the switches SW1 . SW2 . SW3 and SW4 can generate.

In one aspect, an in 2A PD shown high voltage potential divider can be connected to output terminals of the device based on the proposed circuit. The potential divider PD can detect the output voltage Vout at any time and display a (shown as Vfb ( 4 ) proportionally lower value back to the controller U2 through the analog fiber optic link FOPD ( 2A) through the analog transmitter-receiver link (ATx - ARx, shown as 402). PD hovers at high potential (≥Vout).

In another aspect may be at the controller U2 Vfb are compared with a reference voltage Vset proportional to the potential divider ratio and scaled from 0 to Vout. Depending on the difference between Vset and Vfb, the controller may U2 the total number of secondary units including vernier units (such units will be explained in more detail) therein by giving appropriate commands through digital fiber optic (FO) links DTx DRx dedicated for different U4s (eg DTx DRx, as 408) For U4 the secondary unit S1 shown), decide. This feedback controlled loop can thus correct the output voltage Vout on a time scale that is much shorter than the minimum time needed to achieve the correction and thereby Vout (as in FIG 1A shown) dynamically regulated. The value of Vfb can also be used to generate the output voltage monitor signal shown as Vmon.

In yet another aspect, Vfb can also use a high-speed comparator circuit U7 be compared with the threshold overvoltage trip value of the voltage Vov. The instantaneous output voltage exceeds Vov due to overvoltage, the output of U7 can change his condition. This digital signal can then be used for control U2 be transferred and recognized as an interrupt in it. The control U2 can thus immediately all secondary units simultaneously by turning off switch SW5 and switching on switch SW6 ( 3A) by giving appropriate commands through digital fiber optic (FO) links DTx-DRx, for different U4S (eg DTx-DRx 408) dedicated, and concurrent generation disable a signal shown as OV trip, which can be sent to U10 to trigger the input power switch CB (in 2 B shown).

In one aspect, the output current Iout of the proposed circuit may be as Ifb based on the current transformer CT for controlling U2 (in 2A shown). As in 2A shown, the current transformer CT at least three sets of fiber optic links FOCT with the main controller U2 monitor, current monitoring and overcurrent trip signals as output and overcurrent trip command signal as input. The output of CT can with the threshold overcurrent trip value of the current Ioc with a high speed comparator circuit U8 ( 4 ) installed near the output terminals of the proposed circuit.

In another aspect, the controller U2 receive the Ioc value in the form of Ioc-set as input. Ioc-set can be used to control U8 via an analog transmitter-receiver link ATx-ARx (shown as 402). The instantaneous output current exceeds Ioc-set due to overcurrent or failure (BD), the output of U8 can change his condition. This digital signal, shown as BD_Pulse, can then be controlled by the digital fiber optic (FO) Link DTx DRx U2 be transmitted and recognized as a priority interrupt therein. The control U2 Immediately can shut off all secondary units simultaneously by turning off the switch SW5 and turning on the switch SW6 through the digital fiber optic (FO) Link DTx DRx, dedicated for U4 , for a predefined time interval T-inhibit (as in 502 shown, see 5A) (typically about 15 ms duration). Thus, the output voltage at high speed in duration T-cutoff (typically within 5 μs) (as in 504 shown, 5A) interrupt and thereby the increase of the fault current can be limited. After expiration of the period T-inhibit, the controller U2 release the required secondary units to the last setpoint Vout with a short rise time of duration T-rise (as in 506 shown, 5A) [typically ≤ 1 ms].

In yet another aspect, the controller may U2 if the duration of BD_Pulse exceeds a predefined time in microseconds (typically 10 μs), consider BD_Pulse and, accordingly, Ifb as an event that arises due to overcurrent (or persistent failure), and can immediately SW1 . SW2 . SW3 . SW4 through the fiber optic (FO) Link DTx DRx, for U3 dedicated (for example DTx-DRx 406 For U3 ), turn off each primary unit to thereby block the primary inverters, and at the same time can also generate a signal shown as OC-trip. OC-trip can too U1 from U2 over the fiber optic link FOU1 are sent to trigger the input power switch CB (see 4 . 2A and 2 B) , The value of Ifb may also be used to generate the output current monitor signal Imon (see 4 ) to be used.

5A to 5D illustrate, via graphs, the operation of the proposed high voltage DC supply circuit under various situations, according to an exemplary embodiment of the present disclosure.

5A illustrates a failure event of a device based on the proposed circuit in accordance with an exemplary embodiment of the present disclosure.

As in 5A As illustrated, when the output current of the device exceeds a setpoint due to overcurrent or failure, control of the proposed circuit may immediately disable all secondary units simultaneously for a predefined time interval shown as T-inhibit 502. T-inhibit 502 may typically have a duration of about 15 ms.

Thus, the high voltage output voltage may be in duration T cutoff (typically within 5 μs) (as shown at 504, 5A) be interrupted, so that the increase of the fault current can be limited. After the expiration of the period T-inhibit 502, the controller releases the required secondary units to achieve the last setpoint Vout with a short rise time of duration T-rise 506 (typically ≤ 1 ms).

5B illustrates a typical sequence of repeat failure events for a BD set of FIG. 4 in accordance with an exemplary embodiment of the present disclosure.

As in 5B As illustrated, the control of the proposed BDactual circuit may count each time the BD pulse signal is received to determine the number of failures that have actually occurred at the circuit / device output.

The BDactual number can be compared with the desired allowable number of failures or the BDset failure limit. The cycle of power interruption, blocking and re-creating as in 5B can be repeated until BDactual≤BDset, after which the cycle can be terminated and a latched failure limit error signal BD_limit can be generated that does not allow generation of Vout before manual RESET (in 4 as indicated 404) is released. The reset can clear the BD_limit signal and reset the BDactual number to zero.

5C illustrates how a device based on the proposed circuit can provide an output needed in accordance with an exemplary embodiment of the present disclosure.

As described, the proposed circuit may successively turn on a required number of secondary units with a time delay indicated as Tdelay (in milliseconds). Based on the difference between Vset and Vfb, the controller can U2 decide the number of additional units to be turned on or off to reach a value close to the desired output voltage Vout as explained above.

In one embodiment, since the number of secondary units to be turned on to reach a value close to the desired output voltage Vout may be determined by the main controller U2 of the proposed circuit is decided in advance (and therefore known), the amount of voltage overrun and settling time is drastically reduced and a short rise time is achieved. The rise time of the output voltage can be varied by changing the value of Tdelay.

5D illustrates how output voltage of a device based on the proposed circuit may be modulated at low to high frequencies, according to an exemplary embodiment of the present disclosure.

wobei Trise die Anstiegszeit der Ausgangsspannung und T_fall die Abfallzeit der Ausgangsspannung ist.In one aspect, the device's DC output voltage may be at low to high frequencies (typically between 5 Hz and 0.5 kHz) by modulating the HVon and HVoff signals (see 4 and 5D ) of the main controller U2 be modulated on the desired frequency. The maximum frequency (f _mod-max ) at which the modulation can be achieved can always be achieved on the following relationship (taking into account Tfall «Trise and ignoring Tfall): $$f_{mOd-max}<\frac{1}{2x{T}_{rise}}$$

where Trise is the rise time of the output voltage and T _case the fall time of the output voltage is.

wobei f_mod ≤ f_mod-max For a desired modulation frequency fmod, the duration of the release of the HVon (THVon) and HVoff (THVoff) signals can be expressed by the following relation: $$TH{V}_{On}=TH{V}_{Off}=\frac{1}{2x{f}_{mOd}}$$

where f _mod ≤ f _mod-max

6A to 6C illustrate structural details of a high frequency transformer used in the proposed high voltage DC supply circuit according to an exemplary embodiment of the present disclosure.

6A shows a front cross-sectional view, 6B shows a side cross-sectional view and 6C shows a cross-sectional plan view of the transformer.

In one aspect, the transformer T may consist of two U-sections 602 of magnetic material such as amorphous or ferrite material, between two isolated C-channel sections 604 clamped together, which may be made of insulating material such as fiberglass epoxy, held together with two threaded bolts 610 made of the same material, and carried over a base with L-sections 612 from the same material.

In another aspect, both the primary 614 as well as the secondary 616 Winding of any or combination of high voltage (HV) corona resistant wire and HV tape 618 be made. The high-voltage resistance rating of the insulation between the primary 614 and the secondary 616 Winding should be greater than the required minimum HVDC isolation (which may be twice the required isolation level). The windings can be made from core with insulating (fiberglass-epoxy) blocks 620 be separated, which also form the main carrier for the winding and provide the necessary space for the dissipated during operation heat. The final deadlines of the primary windings 614 (With 622 indicated) and the secondary windings 616 (With 624 indicated) can be led out from the diagonally opposite ends to maximize the creepage distance.

7 shows a cooling arrangement for a transformer used in the proposed high voltage DC power supply circuit, according to an exemplary embodiment of the present disclosure.

In one aspect, heat dissipated in the transformer may be through a guided air channel assembly comprised of insulating (typically polycarbonate) material 702 be eliminated. The channel 702 can with two fans 704 be equipped to suck the heat from the channel, and can be designed so that it absorbs the heat of two Transformers simultaneously receives and dissipates. The transformer as well as the air duct can be attached to the base plate 706 be assembled consisting of insulating material such as fiberglass epoxy material. The base plate 706 can with round cutouts 708 Be provided by the primary 710 and secondary 712 Winding connections can happen, as in 3A shown connected to primary and secondary units. The air duct assembly may be configured in such a manner that a fan mounting assembly passes through the primary units and not through the secondary units operating at high voltage.

8th shows typical connections of primary and secondary units to the transformer for the proposed high voltage DC supply circuit according to an exemplary embodiment of the present disclosure.

In one aspect, as shown, input windings of the transformer 804 with the output of the primary unit 802 be connected during output windings of the transformer 804 with inputs of the secondary unit 806 can be connected. The output of the secondary units may be connected to a common bus (not shown).

In another aspect, modules of such an arrangement may be kept in a row as shown, and each row may be connected / disconnected to / from a power supply, depending on the required end output, as already stated.

9A and B illustrate a rack assembly for the proposed high voltage DC power supply circuit according to an exemplary embodiment of the present disclosure.

9A illustrates a top view of the frame assembly and 9B illustrates a front view of the rack assembly.

In one aspect, all primary and secondary units of a device may be based on the proposed circuit on the HV rack 900 be mounted as shown, with the HV frame 900 can be separated for a potential greater than the maximum voltage potential to which the secondary units are referred with respect to ground (Visolation). The frame 900 can also be made of electrical insulating material with sufficient mechanical strength (such as fiberglass epoxy or FR4 material) and can be vertical insulated columns 902 with square cross-section through which the insulated tubes 904 can be connected (routed) with a circular cross-section.

In another aspect, the primary moieties 906 and the secondary units 908 on a flat sheet metal section 910 be mounted from insulating material, in turn, on pipes 904 mounted and secured together with insulated bolts of the same material. Likewise, the transformers 936 on a flat sheet metal section 912 be mounted from the insulating material, in turn, on pipes 904 mounted and secured together with insulated bolts of the same material.

In yet another aspect, the potential divider PD (see also 2A) , the current transformer CT ( 2A) and other auxiliary circuits as in 916 shown on an isolated platform 918 be mounted. The power to these elements can be through one on the same platform 918 mounted isolation transformer 920 be derived. The isolation transformer 960 can be measured for a potential that is equal to Visolation. Additional auxiliary circuits 930 can be on a similar isolated platform 932 be mounted. The positive and negative outputs of the disclosed high voltage DC power supply can be applied to the insulator post 934 be terminated. The height of the lowest layer where the primary and secondary units are mounted may be selected to provide electrical separation from at least visolation of mass.

As can be seen, all secondary units can be electrically isolated from primary units by appropriate transformers (for voltage visibility). In addition, all secondary units may be electrically isolated from ground by the HV frame for a minimum tension of visolation. All sensing devices and auxiliary devices such as PD, CT, etc. can also be electrically powered by the isolation transformer 920 be isolated to the potential Visolation. The proposed circuit may therefore supply the output voltage in the floating mode with the positive or negative terminal grounded or raised to a potential of Visolation.

In one example, the design of various components used in the proposed circuit may be explained below.

INVERTER

• 1. Auf der Basis der Verfügbarkeit des Halbleiterschalters die Eingangsspezifikationen des Wechselrichters abgeschlossen werden, d.h.:

  V_-DL =

  Eingangsgleichspannung

  V_-MOD =

  Ausgangsspannung

  I_out =

  Laststrom

  f =

  Schaltfrequenz

  ∅ =

  Phasenverschiebungswinkel von Gate-Puls zwischen SW3 & SW2 oder SW1 & SW4

  t_d =

  Totzeit des Schalters

  I_ocr =

  maximaler kritischer Laststrom und

  I_ppk =

  primärer Spitzenstrom

• 2. Der Maximaler Arbeitszyklus des Schalters kann berechnet werden durch: $$d_{max}=1-2x{t}_{d}xf$$
  
• 3. Der effektive Arbeitszyklus des Schalters kann berechnet werden durch: $$d_{eff}=1-\frac{\varnothing }{180°}-2\times t_d\times f$$
  
• 4. Das maximale Umdrehungsverhältnis kann abgeleitet werden von: $$n_{max}=d_{eff}\times \frac{V_{-DL}}{V_{-MOD}}$$
  
• 5. Der maximale „L“-Wert kann abgeleitet werden von: $$L_{max}=\frac{V_{-\mathrm{<figure-callout\; id="2"\; label="D\; L"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0057.png"\; state="\{\{state\}\}">D</figure-callout>}L}}{2\times \left(\frac{l_{out}}{n_{max}}\right)}\times \left(\frac{3}{8\times f}-t_d\right)$$
  
• 6. Durch Benutzen von L_max kann der minimale Kondensatorwert zum Schalten über den Schalter wie folgt berechnet werden: $$C_{min}=\frac{1}{L_{max}}\times {\left(\frac{2\times t_d}{\Pi }\right)}^2$$
  
• 7. Der maximale Kondensatorwert zum Schalten über den Schalter kann anhand der minimal möglichen Leckinduktanz (L_min ) des Transformators berechnet werden, der wie folgt erzielt werden kann: $$C_{max}=\frac{1}{L_{min}}\times {\left(\frac{2\times t_d}{\Pi }\right)}^2$$
  
• 8. Unter Berücksichtigung des Wertes von Kondensator C_t, geschaltet über den Schalter zwischen C_min und C_max , berechnet in Sr. 5 und Sr. 6, kann der Wert der im Transformator benötigten Leckinduktanz Lt berechnet werden durch: $$L_t=\frac{1}{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0055.png"\; state="\{\{state\}\}">C</figure-callout>}}_1}\times {\left(\frac{2\times t_d}{\Pi }\right)}^2$$
  
• 9. Der kritische Strom, der den ZVS-(Zero Voltage Switching)-Betrieb erfüllt, kann dann berechnet werden durch: $$I_{cr}=\sqrt{\frac{C_t}{L_t}\times V_{-DL}}$$
  
• 10. Auch der maximale effektive Arbeitszyklus des Schalter kann berechnet werden durch: $$d_{eff}=\frac{d_{max}}{1+\frac{1\times L_t\times I_{out}\times f}{n^2\times V_{-MOD}}}$$
  
• 11. Dann können die Werte von I_cr, I_ppk und d_eff unter den Bedingungen unten geprüft werden, die den ZVS-Betrieb erfüllen: $$\begin{array}{c}{d}_{eff}\ge \frac{n\times V_{-MOD}}{V_{-DL}}\\ I_{cr}\le \frac{I_{ocr}}{n}\\ \frac{I_{out}}{n}\le I_{ppk}\end{array}$$
  

In one aspect, inverter parameters may be decided in consideration of a zero voltage switching phase-shifted full-bridge DC / DC converter. In an exemplary embodiment, the inverter parameters may be determined based on equations known in the art, for example as set forth in the following literature: M. Uslu, "Analysis, Design and Implementation of a 5kW Zero Voltage Switching Phase-shifted Full-Bridge DC / DC Converter Based Power Supply for Arc Welding Machines, "Master's thesis, Middle East Technical University, November 2006.

• 1. On the basis of the availability of the semiconductor switch, the input specifications of the inverter are completed, ie:

  V _-DL =

  DC input voltage

  V _-MOD =

  output voltage

  I _out =

  load current

  f =

  switching frequency

  ∅ =

  Phase shift angle of gate pulse between SW3 & SW2 or SW1 & SW4

  t _d =

  Dead time of the switch

  I _ocr =

  maximum critical load current and

  I _ppk =

  primary peak current

• 2. The maximum duty cycle of the switch can be calculated by: $$d_{max}=1-2x{t}_{d}xf$$
  
• 3. The effective duty cycle of the switch can be calculated by: $$d_{eff}=1-\frac{\varnothing }{180°}-2\times t_d\times f$$
  
• 4. The maximum rotation ratio can be derived from: $$n_{max}=d_{eff}\times \frac{V_{-DL}}{V_{-MOD}}$$
  
• 5. The maximum "L" value can be derived from: $$L_{max}=\frac{V_{-\mathrm{<figure-callout\; id="2"\; label="D\; L"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0057.png"\; state="\{\{state\}\}">D\; </figure-callout>}L}}{2\times \left(\frac{l_{Out}}{n_{max}}\right)}\times \left(\frac{3}{\mathrm{8th}\times f}-t_d\right)$$
  
• 6. By using L _max the minimum capacitor value for switching via the switch can be calculated as follows: $$C_{min}=\frac{1}{L_{max}}\times {\left(\frac{2\times t_d}{\Pi }\right)}^2$$
  
• 7. The maximum capacitor value for switching via the switch can be determined on the basis of the minimum possible leakage inductance ( L _min ) of the transformer, which can be achieved as follows: $$C_{max}=\frac{1}{L_{min}}\times {\left(\frac{2\times t_d}{\Pi }\right)}^2$$
  
• 8. Taking into account the value of capacitor C _t , switched via the switch between C _min and C _max , calculated in Sr. 5 and Sr. 6, the value of the leakage inductance Lt required in the transformer can be calculated by: $$L_t=\frac{1}{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0055.png"\; state="\{\{state\}\}">C</figure-callout>}}_1}\times {\left(\frac{2\times t_d}{\Pi }\right)}^2$$
  
• 9. The critical current that satisfies ZVS (Zero Voltage Switching) operation can then be calculated by: $$I_{cr}=\sqrt{\frac{C_t}{L_t}\times V_{-DL}}$$
  
• 10. The maximum effective duty cycle of the switch can also be calculated by: $$d_{eff}=\frac{d_{max}}{1+\frac{1\times L_t\times I_{Out}\times f}{n^2\times V_{-MOD}}}$$
  
• 11. Then the values of I _cr , I _ppk and d _eff tested under the conditions below that fulfill the ZVS operation: $$\begin{array}{c}{d}_{eff}\ge \frac{n\times V_{-MOD}}{V_{-DL}}\\ I_{cr}\le \frac{I_{Ocr}}{n}\\ \frac{I_{Out}}{n}\le I_{ppk}\end{array}$$
  

The values C _t and L _t can be terminated if the values of I _cr , I _ppk and d _eff conditions mentioned in Sr. 11 conditions, otherwise Sr. 7 can be repeated until Sr. 10 assuming a different value of C _t, until the conditions in Sr. 11 are fulfilled.

TRANSFORMER

In one aspect, the following process of designing the transformer T may be followed:

1. The parameters: primary voltage = Vpri, primary current = ipri, secondary voltage = Vsec, secondary current = isec, operating frequency = f EMF per revolution = et and, needed separation = Visolation.

• Hautdicke des Leiters bei f $$sd=\sqrt{\frac{\rho }{\Pi \times f\times \mu }}$$
  
• Querschnittsfläche für runden Leiter $$Ac=\frac{\mathrm{<figure-callout\; id="2"\; label="\Pi \; D"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0057.png"\; state="\{\{state\}\}">\Pi </figure-callout>}{D}^{}{}^2}{4}-\frac{\Pi \left({\mathrm{<figure-callout\; id="2"\; label="D"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0057.png"\; state="\{\{state\}\}">D</figure-callout>}}^2-s{d}^2\right)}{4}$$
  
• Das Verhältnis zwischen Primärstrom und Querschnittsfläche des Leiters kann angegeben werden durch $$Ac=\frac{Ipri}{J}$$
  
• Parallele Läufe in der Primär- und Sekundärwicklung können benutzt werden, falls der Leiter mit erforderlichem Querschnitt nicht verfügbar ist. Dabei ist:
  • J die Stromdichte des Leiters
  • ρ der spezifische Widerstand des Leiters
  • µ die magnetische Permeabilität des Leiters
  • D der Durchmesser des Leiters.

2. The cross-section or diameter of the conductor needed for the winding can be completed. The cross section of the winding can be derived from the following equations:

• Skin thickness of the conductor at f $$sd=\sqrt{\frac{\rho }{\Pi \times f\times \mu }}$$
  
• Cross-sectional area for round ladder $$Ac=\frac{\mathrm{<figure-callout\; id="2"\; label="\Pi \; D"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0057.png"\; state="\{\{state\}\}">\Pi \; </figure-callout>}{D}^{}{}^2}{4}-\frac{\Pi \left(D^2-s{d}^2\right)}{4}$$
  
• The relationship between primary current and cross-sectional area of the conductor can be indicated by $$Ac=\frac{Ipri}{J}$$
  
• Parallel runs in the primary and secondary windings can be used if the conductor with required cross-section is not available. Where:
  • J is the current density of the conductor
  • ρ the resistivity of the conductor
  • μ the magnetic permeability of the conductor
  • D is the diameter of the conductor.

3. Depending on the availability of core material, cross-sectional area = Ai, window area = Aw, the core can be completed to achieve the required parameter.

4. The flux density B can then be calculated with the following relation: $$B=\frac{et}{\mathrm{4:44}\times f\times Ai}$$

5. If the value of B is far below the saturation flux density of the core, the value of Et can be completed, otherwise the value of B can be calculated by reducing the value of Et and using the equation mentioned in Sr.

6. The number of primary revolutions of the transformer can be expressed by: $$Npri=\frac{Vpri}{et}$$

7. The number of secondary revolutions of the transformer can be expressed by: $$Nsec=\frac{Vsec}{et}$$

8. Depending on the value of Visolation, the insulating material and the thickness of the conductor can be completed.

wobei

• ∑X_perp-lf die Summe von Abmessungen aller Subwicklungen ist, die lotrecht zum Leckfluss orientiert sind;
• X_par-lf die Abmessung der Subwicklungen ist, die parallel zum Leckfluss orientiert sind;
• ∑δ die Summe der Dicken aller Isolierzwischenräume zwischen den Subwicklungen ist,
• n_lf die Anzahl von Isolierzwischenräumen zwischen den Subwicklungen ist;
• N die Anzahl von Umdrehungen der Wicklung ist, auf die sich das Leck bezieht;
• l_m die mittlere Länge pro Umdrehung für die gesamte Anordnung der Wicklungen ist.

In an exemplary embodiment, the leakage inductance of the transformer may be determined based on equations known in the art, for example as cited in the literature: R. Doebbelin and A. Lindemann, "Leakage Inductance Determination for Transformers with Interleaving of Windings", Progress In Electromagnetics Research (PIERS), Vol. 6, No. 6, 2010. The leakage inductance of the transformer can be expressed by the following relation: $$L_t=L=\frac{\mu \mathrm{o}\times {\text{N}}^2\times l_m}{n^2{}_{lf}\times X_{par-lf}\times {\displaystyle \Sigma \delta +\frac{{\displaystyle \Sigma X_{perp-\mathrm{<figure-callout\; id="3"\; label="l\; f"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0057.png"\; state="\{\{state\}\}">l\; </figure-callout>}f}}}{3}}}$$

in which

• ΣX _{perp-lf is} the sum of dimensions of all sub-windings oriented perpendicular to the leak flow;
• X _{par-lf is} the dimension of the sub-windings oriented parallel to the leakage flow;
• Σδ is the sum of the thicknesses of all insulation gaps between the sub-windings,
• n _{lf is} the number of insulating gaps between the sub-windings;
• N is the number of turns of the winding to which the leak relates;
• l _{m is} the mean length per revolution for the entire arrangement of the windings.

wobei

• V_no-load die Sekundärspannung des Transformators bei Nulllast ist
• V_full-load die Sekundärspannung des Transformators bei Volllast ist
• alle Transformatoren T1 bis TN für gleiche Leckinduktanz L ausgelegt sind.

The drop ratio of the transformer T can be expressed by the following relation: $$\text{drop ratio}=K=\frac{V_{nO-lOad}}{V_{full-lOad}}$$

in which

• V _{no-load is} the secondary voltage of the transformer at zero _load
• V _{full-load is} the secondary voltage of the transformer at full load
• all transformers T1 to TN are designed for the same leakage inductance L.

SECONDARY UNIT

In the proposed power supply, those secondary units / modules that generate, fix, and adjust the highest amplitude voltage (Vfull) with respect to the remaining modules may be referred to as "full" units. The remaining units that produce tension less than the full units may be referred to as "vernier" units.

For a desired output voltage Vout with required minimum voltage resolution Vmin, the first vernier module, ie vernier 1 , be designed to deliver the minimum output voltage at full load, expressed by: $$V_{vernier-1}=\frac{V_{min}}{K}$$

The next vernier unit, Vernier 2 , can be designed to deliver the next higher voltage level expressed by: $$V_{vernier-2}=2^{\left(2-1\right)}X{V}_{vernier-1}$$

The next vernier unit, Vernier 3 , can be designed to deliver the next higher voltage level expressed by: $$V_{vernier-3}=2^{\left(3-1\right)}X{V}_{vernier-1}$$

Similarly, the last, ie the n-th Vernier unit, Vernier-n, may be designed to provide the voltage level expressed by: $$V_{vernier-n}=2^{\left(n-1\right)}X{V}_{vernier-1}$$

The full units may be designed to provide the output voltage at full load, expressed by: $$V_{full}=V_{vernier-1}+V_{vernier-2}=V_{vernier-3}+\cdots +V_{vernier-n}$$

The output voltage of the full unit (V_ _full) can be calculated as above are completed on the basis of the highest voltage (thereby also the number of vernier units decides), which can be practically implemented, depending on the availability of technology and simplicity of its implementation.

The required number of full units is expressed by the relation: $$\frac{V_{Out}}{V_{full}}-1$$

The highest rating of each secondary unit is equal to the maximum DC current Iout required at the output of the power supply.

As an example of a typical implementation of a 30 kVDC power supply, the minimum resolution of 200 V requires, taking into account a waste ratio K = 2:

The output voltage of the first vernier module, ie Vernier-1, can be given by: $$V_{vernier-1}=\frac{V_{min}}{K}=\frac{200}{2}=100V$$

The output voltage of the next Vernier unit, Vernier-2, can be given by: $$V_{vernier-2}=2^{\left(2-1\right)}X{V}_{vernier-1}=2X100=200V$$

The output voltage of the next Vernier unit, Vernier-3, can be given by: $$V_{vernier-3}=2^{\left(3-1\right)}X{V}_{vernier-1}=4X100=400V$$

The output voltage of the next Vernier unit, Vernier-3, can be expressed by: $$V_{vernier-4}=2^{\left(4-1\right)}X{V}_{vernier-1}=\mathrm{8th}X100=800V$$

The full units are designed to deliver the output voltage at full load, indicated by: $$\begin{array}{l}{V}_{full}=V_{vernier-1}+V_{vernier-2}+V_{vernier-3}+\cdots +V_{vernier-n}\\ V_{full}=100+200+400+800=1500V\end{array}$$

This may be a useful voltage level from the standpoint of practical implementation or feasibility.

The required number of full units can be specified by: $$\frac{V_{Out}}{V_{full}}-1=\frac{30000}{1500}-1=19einHeiten$$

It will be understood that the disclosed power supply circuit also includes redundancy with respect to the number of primary and secondary units in such a way that when the chain of primary / secondary units becomes faulty, the controller U2 locks this chain (or multiple chains) and automatically releases the chain of redundant units to continue the supply of rated current at the rated voltage. However, if the redundancy chain is fully utilized and there is an additional error in the primary / secondary units, or if the redundancy is insufficient to supply the required output voltage, then the controller, then the controller U2 . SW1 . SW2 . SW3 . SW4 immediately through the digital fiber optic (FO) Link DTx DRx, dedicated for U3 from each primary unit, turn off to thereby block the primary inverters while also generating a signal OC trip, which is then transmitted through the fiber optic link FOU1 to U1 can be sent to trigger the input power switch CB (see 4 . 2A and 2 B) ,

There Vfb . Ifb . U8 and associated circuits hover at high potential, the control supply U6 to be generated by the HV DC isolation transformer Tiso rated for a separation (≥Vout), as in 4 is shown.

The control U2 can also count the number as BDactual each time the BD_Pulse signal is received. This gives the number of failures that actually occurred at the output. The BDactual number is compared with the desired allowable number of failures or the BDset failure limit. The cycle of power off, stall and reinstall as in 5 can be repeated until BDactual≤BDset, after which the cycle can be terminated and a stalled failure limit error signal BD_limit can be generated which will not allow generation of Vout until manual RESET is enabled (see 4 , when 404 shown). The reset clears the BD_limit signal and resets the BDactual number to zero. A typical sequence of failure events is in 5B for a BDset of 4 shown.

In one example, the controller receives U2 the Bdset signal and receives BDactual in the form of a voltage signal with a detection window or band. For a control signal of Vcontrol = 10V the exact voltage for the detection of BDset as 1 or the generation of BDactual as 1 is as follows: $${\mathrm{<figure-callout\; id="1"\; label="V\; B\; D"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0055.png"\; state="\{\{state\}\}">V\; </figure-callout>}}_{BD}=\frac{VcOntrOl}{B{D}_{set-max}OderB{D}_{actual-max}}$$

• Spannung zur Erkennung von BDset oder Erzeugung von BDactual als 1 ist V_BD1 ± (50 % von V_BD1)
• Spannung zur Erkennung von BDset oder Erzeugung von BDactual als 2 ist 2 X V_BD1± (50 % von V_BD1)
• Spannung zur Erkennung von BDset oder Erzeugung von BDactual als 3 ist 3 X V_BD1± (50 % von V_BD1)
• Spannung zur Erkennung von BDset oder Erzeugung von BDactual als 3 ist 3 X V_BD1± (50 % von V_BD1)
• Spannung zur Erkennung von BDset oder Erzeugung von BDactual als „n-1“ ist (n - 1) X V_BD1 ± (50 % von V_BD1)
• Spannung zur Erkennung von BDset oder Erzeugung von BDactual als „n“ ist (n) X V_BD1 bis[(n) X V_BD1] - (50 % von V_BD1)

In a practical implementation of the logic:

• Voltage for detection of BDset or generation of BDactual as 1 is V _BD1 ± (50% of V _BD1 )
• Voltage for detection of BDset or generation of BDactual as 2 is 2 XV _BD1 ± (50% of V _BD1 )
• Voltage for detection of BDset or generation of BDactual as 3 is 3 XV _BD1 ± (50% of V _BD1 )
• Voltage for detection of BDset or generation of BDactual as 3 is 3 XV _BD1 ± (50% of V _BD1 )
• Voltage for detection of BDset or generation of BDactual as "n-1" is (n-1) XV _BD1 ± (50% of V _BD1 )
• Voltage for detecting BDset or generating BDactual as "n" is XV _BD1 to [(n) XV _BD1 ] - (50% of V _BD1 )

In one example, the value of capacitor C5 (please refer 3A) ie, the filter capacitor connected to the output of the high frequency bridge rectifier is drastically reduced due to a high frequency AC square wave input. Further, as the demand of output voltage Vout increases, more and more capacitors can be used C5 each secondary unit in series through the switch SW5 to reduce the effective capacity at the output. For a power supply with a total of N of modules, the effective capacity at the output can be expressed as follows: $$C_{Out}\frac{C5}{N}$$

Thus, the effective energy stored in the power supply can be drastically reduced. Because of this, and also because the system operates with closed-loop feedback control, the need for a bleeder resistor at the output can be completely eliminated. This also eliminates the Ableitwiderstandsverluste. The implementation of a zero voltage circuit (ZVS) square wave inverter in each primary unit dramatically reduces overall circuit losses compared to a similar fixed-device power supply, and thus effectively improves the efficiency of the power supply.

The total energy released into the load at the time of the failure can be expressed by the following relation: $$e{\_}_{dumped}=i^{2}XrXt$$

Where i is the current at failure, r is the resistance of the arc, and t is the time duration for which the leakage current flows.

was Folgendes ergibt: Ibd = 1,414 kAIn one example, assuming a worst case scenario of a constant leakage current Ibd flowing through an arc of 1 ohms for a duration of 5 μs, using the equation above, for an E _-dumped of 10J, the following applies: $$10=I_{bd}^{2}X1X5X{10}^{-6}$$

which gives: Ibd = 1.414 kA

The peak value of the total output current at downtime is determined by using the LR snubber SN-1 (see 2A) reduced, which is connected to the output of the power supply.

dabei ist L1 die Induktanz des Snubbers, R1 ist der Widerstand des Snubbers und C ist die Gesamtstreukapazität des Systems. Der Wert von R1 wird anhand der folgenden Relation berechnet: $$R1=\frac{BemesseneDC-Ausgangsspannung}{zulässigerSpitzenwertvonFehlerstrom}=\frac{V_{out}}{I_{bd}}$$

The value of L and R can be derived from the following relation for a critically damped parallel resonant circuit as follows: $$\mathrm{<figure-callout\; id="1"\; label="L"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0055.png"\; state="\{\{state\}\}">L</figure-callout>}1=4\mathrm{<figure-callout\; id="1"\; label="X\; R"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0055.png"\; state="\{\{state\}\}">X\; </figure-callout>}R{1}^{2}XC$$

is there L1 the inductance of the snubber, R1 is the resistance of the snubber and C is the total stray capacity of the system. The value of R1 is calculated using the following relation: $$\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="DE102018114437A1\_0053.png,DE102018114437A1\_0055.png"\; state="\{\{state\}\}">R</figure-callout>}1=\frac{BemesseneDC-AusGanGsspannunG}{zulässiGerSpitzenwertvOnFeHlerstrOm}=\frac{V_{Out}}{I_{bd}}$$

Thus, by limiting the current slew rate to within 1.414kA with SN-1, E-dumped can be maintained within 10J. Conveniently, the current on failure can gradually increase from zero and the arc resistance is substantially less than 1 ohm (typically 20mΩ), so E-dumped is much smaller than 10J.

Since all components of the power supply / device can be designed for continuous operation based on the proposed circuit, the device can continuously provide the rated output Vout at rated current (i.e., rated power).

Since the rectification occurs at high frequency (typically 50 kHz) in the secondary unit, the capacitor must C5 only filter out this high frequency noise and therefore the value of the output capacitor C5 drastically reduced. The proposed circuit can therefore have the voltage Vout with the rated current Iout with a low ripple value and with a small value of the capacitance C5 deliver at the exit.

Because the capacitor C5 ( 3A) pre-charged, the rise time simply depends on the switching speed of the controlled series switch SW5 which releases or blocks the voltage (V-MOD), and therefore, the circuit can supply the output voltage with short rise time. In addition, the disclosed circuit may be provided with a function to vary the output voltage rise time as required. This can be the main controller U2 decide the number of secondary units to be activated on the basis of the value of Vset ( 4 ). In addition, the controller U2 and make a decision on the time delay between turning on each secondary unit based on the request for the rise time. For a N secondary power supply and a Trise rise time request (in ms), the delay with respect to turning on each secondary unit is given by the following relation: $$T_{delay}=\frac{T_{rise}}{N}$$

The required secondary units are then released upon release of the Hvon signal (see 4 ) by U2 successively with a time delay of Tdelay ms through the digital fiber optic (FO) link DTx DRx dedicated for U4 each secondary unit (see 5C ) switched on. On the basis of the difference between Vset and Vfb decides U2 then further on the number of additional units to be turned on or on the switching off of existing on-units until the desired value of Vout is achieved. Since the required number of secondary units to be turned on to reach a value close to the desired output voltage Vout, in advance from the main controller U2 is decided (and therefore known), the amount of voltage overrun and settling time can be drastically reduced and a fast rise time can be achieved. The rise time of the output voltage can be varied by changing the value of Tdelay.

In one example, the DC output voltage at low to high frequencies (typically between 5 Hz and 0.5 kHz) may be modulated by modulating the HVon and HVoff signals (see 4 and 5D ) of the main controller U2 be modulated at the desired frequency. The maximum frequency at which the modulation can be achieved always follows the following relation (considering Tfall «Trise and ignoring Tfall): $$f_{mOd-max}<\frac{1}{2X{T}_{rise}}$$

dabei ist f_mod ≤ f_mod-max For a desired modulation frequency fmod, the duration of the release of HVon and HVoff signals is given by the following relation: $$TH{V}_{On}=TH{V}_{Off}=\frac{1}{2X{f}_{mOd}}$$

is there f _mod ≤ f _mod-max

As stated, in the event of a failure at the output terminals, the current in the proposed circuit can be detected by a fast-response CT, which floats at high potential. The instantaneous output current exceeds the threshold overcurrent trip value, a signal referred to as a breakdown-down pulse is transmitted to the programmable digital master controller, which then immediately signals to turn off all secondary units (in a period of time called the break time) simultaneously at high speed for a certain duration (called stall time ), due to which the rate of increase of the output current during the failure is limited. After the blocking time, the main programmable digital controller turns on the controlled series switches and simultaneously turns off the controlled parallel switches of said secondary units to achieve (or re-apply) the last setpoint of the output voltage within a short duration called a rise time. In the case of all subsequent failures (i.e., repeated failures), the above interrupt, stall, and rise cycle may be repeated. Since the repetitive failures with the series switches at the output of the power supply, the energy lost at failures is lower, as scattering energies of transformer, rectifier and all the series switches upstream accessories are completely eliminated, reducing the peak current is reduced by the series switch at each Failure flows, and thereby a high failure repetition frequency is achieved.

Further, a primary unit of the described proposed circuit consists of a full-bridge inverter operating with phase-shifted ZVS (Zero Voltage Switching) technique. By applying ZVS in each inverter, high frequency switching is achieved with drastic reduction of switching losses.

In another aspect, the disclosed circuit utilizes multiple high frequency compact transformers in the DC-DC converters (rather than a conventional multi-secondary transformer). The design of these transformers is simple; They are easy to manufacture and require significantly less manufacturing time, so drastically reducing the overall manufacturing time of the described power supply. Likewise, the proposed circuit will dispense with all the associated drawbacks of a multi-secondary transformer based power supply because the circuit is modular and easily scalable. Due to high frequency rectification and the elimination of the multi-secondary transformer, the size of a power supply / device based on the proposed circuit is extremely low for a given output voltage and current.

Also, the proposed circuit provides instant low output ripple across the dynamic range of voltage and current due to high frequency rectification using minimal filter capacitance, if any. Further, due to the elimination or reduction of the output filter capacitance, the stored power of the power supply is also drastically reduced, which reduces the energy lost in failure in the load while the output breaker opening operation (i.e., the shutdown process) continues.

The feedback-controlled regulation of a power supply based on the proposed circuit can be achieved by the output series switches, and therefore the minimum time for output voltage regulation can be very low, since it is ideally limited by the switching time of these series switches.

The secondary units are always charged at their rated voltage to the output series switch, and therefore, a short voltage rise time can be achieved when the power is turned on. Also, when the power is turned off, all the high speed serial switches are turned off by the programmable digital master controller, followed by turning on all the parallel switches (with a dead time of a few microseconds) at high speed to achieve a short voltage drop time. For this reason, output voltage modulation at high frequency can be achieved in a power supply / device based on the proposed circuit.

While the proposed circuit has been discussed above as including all major modules / components, it is quite possible that actual implementations may include only a portion of the proposed modules / components or a combination thereof or a subset thereof to submodules in various combinations across multiple devices operatively coupled with each other. Therefore, all possible modifications, implementations and refinements of where and how the proposed circuit is configured fall within the scope of the present invention.

As used herein, the term "coupled with" is intended to include, unless the context dictates otherwise, both direct coupling (in which two elements are coupled or in contact with each other) and indirect coupling (which involves at least one additional element between the two elements located). Therefore, the terms "coupled to" and "coupled to" are used interchangeably. In the context of the present document, terms "coupled to" and "coupled with" are euphemistically used to mean "communicatively coupled to" over a network, where two or more devices may be able to communicate with each other over the network via one or more intermediate devices ,

Further, in interpreting the specification and the claims, all terms are to be interpreted in the broadest possible manner consistent with the context. In particular, the terms "comprises" and "comprising" with respect to elements, components or steps are to be interpreted in a non-exclusive manner indicating that the referenced elements, components or steps are present, or used or combined with other elements, components or Be steps that are not explicitly referenced. Where the specification claims refer to at least one member of the group consisting of A, B, C .... and N, the text should be interpreted to be only one member of the group, not A plus N or B plus N, etc. needed.

While some embodiments of the present disclosure have been illustrated and described, these are exemplary only. The disclosure is not limited to the embodiments as discussed herein and it will be apparent to one of ordinary skill in the art that many modifications are possible besides those already described without departing from the inventive concepts herein. All such modifications, changes, variations, substitutions, and equivalents fall entirely within the scope of the present disclosure. The inventive subject matter is therefore limited only by the nature of the appended claims.

BENEFITS OF THE PRESENT DISCLOSURE

Some of the objects of the present disclosure that satisfy at least one embodiment herein are listed below.

The present disclosure provides a circuit for a high voltage DC power supply for generating high voltage, high voltage, continuous mode DC power.

The present disclosure provides a circuit for a high voltage DC power supply that can float at high potential (100 kVDC).

The present disclosure provides a circuit for a high voltage DC power supply capable of providing output voltage with a short rise time (<1 ms).

The present disclosure provides a circuit for a high voltage DC power supply that can detect and endure repeated failures / short circuits (typically 200 ns) at its output terminals.

The present disclosure provides a high voltage DC power supply that interrupts DC output voltage at high speed (<5 μs) in the event of dropouts / short circuits at its output terminals.

The present disclosure provides a high voltage DC power supply that can keep output DC voltage blocked for a fixed period of time (from 100 μs to 100 seconds of ms or beyond) and bring the DC output voltage back to its last setpoint.

The present disclosure provides a circuit for a high voltage DC power supply, which can set the number of allowable failures / short circuits at its output terminals, which can count failures that actually occur at the output and can interrupt the DC output voltage if the number of actual failures is equal to the set value of allowable failures.

The present disclosure provides a high-voltage DC power supply with optimized design for limiting the energy dumped in a failure / short circuit fault to <10J.

The present disclosure provides a high voltage DC power supply with low voltage ripple and good output voltage regulation.

The present disclosure provides a high voltage DC power supply with a simpler HV disconnect mechanism.

The present disclosure provides a circuit for a high voltage DC power supply with a simpler feedback control system for controlling the output HVDC.

The present disclosure provides a circuit for a high voltage DC power supply having a function of providing protection from output overvoltage and overcurrent.

The present disclosure provides a circuit for a high voltage DC power supply with a DC output voltage modulation function (typically 5 Hz to 0.5 kHz).

The present disclosure provides a circuit for a high voltage (> 85%) high-voltage DC power supply.

The present disclosure provides a circuit for a high voltage DC power supply that uses a simple, flexible and adaptable control circuit with very short output voltage regulation response time.

The present disclosure provides a circuit for a high voltage DC power supply that has a hot standby mode.

The present disclosure provides a circuit for a high voltage DC power supply that is much smaller than existing devices for the same rated outputs.

The present disclosure provides a circuit for a high voltage DC power supply that uses components that are easy and fast to manufacture.

The present disclosure provides a circuit for a high voltage DC power supply that is easily scalable and can handle any type of load, continuously, incrementally, or with any profile, over a wide range of current requirements up to no-load.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• IN 206556 [0004]
• US 9041288 B2 [0004, 0007]
• US 5638263 A [0004]
• US 2016/0073298 A1 [0004]

Claims (10)

A high voltage DC power supply circuit comprising a plurality of series-connected high voltage isolated DC-DC converter blocks, each block comprising: a primary unit having an inverter receiving an input from a DC link and converting the input to high frequency voltage; a high frequency transformer receiving said high frequency voltage from the high voltage DC isolation inverter and transmitting the high frequency voltage to a secondary unit; and the secondary unit for converting the high frequency voltage into a DC voltage, the secondary unit comprising a high frequency full bridge rectifier, a low capacity filter, a high speed series solid state switch and a solid state parallel switch, each said block being sized to provide current equal to the nominal output DC current and output of one or more of said blocks is enabled or disabled by turning on or off the high speed series solid state switches of respective blocks to produce a desired DC output voltage (V _out ). Circuit after Claim 1 wherein said plurality of blocks comprise vernier blocks and solid blocks, each of said vernier blocks being configured to give a DC output voltage which is a fraction and less than that of any of the solid blocks, and in combination with one or more full blocks is used to obtain the desired DC output voltage (Vout) with minimum voltage resolution V _min . Circuit after Claim 2 wherein said circuit obtains the desired DC output voltage by turning on 'n' full blocks according to the DC output voltage given by each full block (V _full ), and turning on 'm' vernier blocks based on a required residual DC voltage such that: $$\left(V_{Out}\right)=n\mathrm{*}{V}_{full}+{\displaystyle \underset{i=1}{\overset{m}{\Sigma }}{V}_i}$$

where Vi is the output voltage of the ith vernier block. Circuit after Claim 3 , wherein the minimum _voltage indicated by one of the vernier blocks is defined as V _vernier-1 = V _min / K at full load, where K is the _{drop ratio of} the high frequency transformer of the vernier block, said _{drop ratio} V _no-load / V _{full- load} , where V _{no-load is} the secondary voltage of the high frequency transformer of the vernier block at _{no load} , and V _{full-load is} the secondary voltage of the high frequency transformer of the vernier block at full load. Circuit after Claim 3 wherein the vernier blocks are configured such that the sum of output voltages of each vernier block results in an output voltage of a full block, indicated by: $$V_{full}=V_{vernier-1}+V_{vernier-2}+V_{vernier-3}+\cdots +V_{vernier-n}$$

Circuit after Claim 3 , where the number of required full blocks is given by the following relation: $$\frac{V_{Out}}{V_{full}}-1$$

Circuit after Claim 1 wherein the high speed series solid state switch of each block is turned on or off by a control circuit comprising a programmable master digital controller. Circuit after Claim 7 wherein the control circuit employs a voltage feedback system that compares signals received from a floating voltage sensor with a required DC output voltage signal to derive a correction signal on the basis of which the main programmable digital controller decides which DC-DC converter blocks to turn on or off must be turned off to obtain the desired DC output voltage. Circuit after Claim 7 wherein, in the event of a failure at output terminals or when the output current exceeds a predetermined threshold, the secondary units of respective blocks that are turned on at that moment are turned off at high speed within a break time period and remain off for a lock time, after which the main programmable digital controller the high speed series solid state switch of said secondary units turns on and at the same time turns off the solid state parallel switches of said secondary units to achieve the last set value of the DC output voltage within a short duration. Circuit after Claim 1 , wherein the primary unit of each block one Full bridge inverter operating with a ZVS (Zero Voltage Switching) phase shift technique.

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