DE102018110325B3 - Method for counter-controlled signal shaping of the transmission signal of a serial interface to an output signal - Google Patents

Abstract

The invention relates to a method for signal shaping of the transmission signal of a serial interface to an output signal. The method comprises a step of counting at a first pitch in synchronism with a clock to an inverse count to form a count when an edge occurs on the transmit signal and when an edge has occurred on the transmit signal. Furthermore, it has a step of counting after reaching the reverse count with a second step in synchronism with the clock to form a count when an edge has occurred on the transmission signal and half of a predetermined time has elapsed. Likewise, it has a step of inhibiting the counting while maintaining the count when the count corresponds to the output count or crosses the output count during counting and when no edge occurs on the transmit signal, wherein in case of crossing the time history of the count with the output count the counter reading is set to the output counter reading. Finally, it includes a step of integrating the count and generating an output signal.

Description

preamble

The invention is directed to a method and an apparatus for signal shaping of the transmission signal of a serial interface to an output signal.

General introduction

In serial data buses, the reduction of electromagnetic radiation is an important task. Pulse shaping in such communications signals from serial data buses is typically accomplished using analog circuit components or look-up tables in the digital domain. Analog circuits are unfavorable in integration into microelectronic circuits. They often cause increased test times and are usually less robust against manufacturing variations. Solutions based on look-up tables are usually very chip-intensive and therefore not cost-effective.

Object of the invention

The radiation characteristics of such a data bus should be improved by rounding off the edges of the current-modulated signal. In this case, however, the most cost-effective solution with only a small chip area required for integration into microelectronic circuits should be found.

The invention is therefore based on the object to provide a solution which does not have the above disadvantages of the prior art and has further advantages.

This object is achieved by a method according to claim 1.

State of the art

From US 2002/0 074 957 A1 It is known that a repetitive nonlinear waveform is first generated in a waveform generator by varying the number fed into the pulse reduction circuit during the repetition period. Thus, the pulse reduction circuit provides a number of desired output pulses, the number of which varies with time, depending on the input initially. For example, if a low number is fed to the pulse reduction circuit, this will produce a small number of output pulses. Thus, the summation or integration occurs over smaller increments of values in that subperiod, and the change in waveform is less steep.

In the WO 2004/040 758 A1, a transmitter with a controlled signal shape for signal switching is described in a communication line. This consists of a signal generator with a capacitor which generates the switching signal. The capacitor is charged by a charging current. The feedback loop responsible for the charging current generates a first and a second feedback voltage, one function of the feedback voltage of the capacitor rising and the other falling. The feedback current is then generated as a function of the two feedback voltages, with the change in the feedback current increasing over time as it is retained as a function of one of the two feedback voltages while the unselected feedback voltage decreases over time. Ideally, the feedback current is a function of the feedback voltage of the capacitor, thus resembling an e-function for a small period of time and a linear function for the remainder of the period.

The DE 101 63 461 A1 relates to a circuit arrangement for providing an output signal with adjustable edge steepness, in which a plurality of parallel-connected inverter output stages are connected in parallel on the load side. The output stages are generated with a common trapezoidal signal and driven by a ramp signal generator. The output transistors are switched on and off sequentially. As a result, a precisely adjustable, reduced edge steepness of an output signal with a desired driver strength can be achieved with a small area requirement. This in turn allows for an adjustable reduction of the high frequency noise emissions of integrated circuits.

Solution of the task

The task is solved by means of a controlled counter, which can count both upwards and downwards, and an integrator connected behind it. The length of the edge can be easily parameterized with the aid of a clock divider and the increment of the counter. The output can then be converted back into an analog signal using a DAC and then transmitted via the bus.

The proposed device consists of two blocks, a controlled counter and a simple integrator, which can be easily realized in the digital domain.

The input signal (input) corresponds to the communication signal to be transmitted. In this case, it has two different states ('0' and '1').

With a rising edge at the input, the controlled counter starts to count up. The step size of the counter is preferably dependent on the height of the edge. Particularly preferably, the step size is proportional to the flank height. The proportionality factor is preferably adjustable or programmable. After half of a set edge time, the direction is reversed and the counter starts counting down with the same increment. If the counter reaches its initial value, preferably zero, the counter stops again. For the inverse, a comparator compares the counter reading with a set register value representing the value for half of the set edge time.

A falling edge at the input causes the controlled counter to count down from its initial state. The step size of the counter is again preferably dependent on the height of the edge. Particularly preferably, the step size is proportional to the flank height. The proportionality factor is preferably adjustable or programmable. After half of the set edge time, the direction is reversed again and the counter counts up again with the same increment.

The output of this counter is integrated by the integrator and the rounded edges on the output signal (output) result as in 2 shown.

Instead of the integrator other, essentially integrating filters can be used. It is important that the signal change of the output of such a filter in finite time goes to zero, when the output of the counter is in the initial state. In this respect, integrator here can be understood as another integrating filter.

The output of the integrator or integrating filter can then be converted to analog voltage or current using a digital-to-analog converter.

With the aid of the step size of the counter and the time extension of the edge time, the speed of the edge can be adapted very easily.

The application in a serial interface with three logic levels is a potential, exemplary application. In the return channel of such an exemplary serial interface, there are not only two states in the input signal, but three (', +1', '0' and '-1'). The controlled counter then responds not only to a rising or falling edge at the input, but also to the height of the edge. If the change from '+1' to '-1' or from '-1' to '1', the increment of the counter is doubled.

First variant of the proposal

A first embodiment of the proposal relates to a device for signal shaping of the transmission signal of a serial interface to an output signal. It includes an up / down counter, a comparator and an integrator. The apparatus is operated in this embodiment with a clock which typically serves as the time base for the up / down counter and the integrator. The up / down counter may have an output state with an output counter value. The word "may" is to be understood in this context that the up / down counter can also have other counts and thus other states. In this respect, the output state is one of many possible states and the output counter value is one of many possible counter readings. Thus, the word "may" does not constitute an optional claim in the claims. The up / down counter does not count when it is in its initial state and no edge occurs on the transmit signal. The counting process is driven by the clock. Accordingly, the up / down counter counts with a first increment in synchronism with the clock when an edge occurs on the transmission signal, and with a first step in synchronism with the clock when an edge on the transmission signal has already occurred but not yet half a predetermined time has elapsed. This last condition, which has not yet passed half of a given time, is slightly modified in the following second variant of the proposal. The up / down counter counts with a second step in synchronism with the clock when an edge has occurred on the transmission signal and now, however, said half of the predetermined time has elapsed. The up / down counter stops counting when its count becomes equal to or crosses the output counter value during the count, thus assuming the initial state. In this case, "crossing" means that, for example, before a counting step of the counting process, the counter reading is smaller than the output counter value and, after the counting step, is greater than the output counter value. Of course, it is also a "cross", for example, if before a counting step of the counting process, the count is greater than the output counter value and after the counting step is less than the output counter value. The integrator continues to process the count of the up / down counter and generates the output signal. Since the edges of the triangular signal generated by the up / down counter are substantially linear, the counts of an integrator are substantially square, resulting in parabolic waveforms and the disappearance of odd transients in the spectrum. This leads to a substantial reduction of the radiated interference signals.

In a first modification of the first variant of the device, the value of the second step size corresponds to the value of the first step width multiplied by -1.

In a second modification of the first variant of the device, the first and / or second step size is dependent on the height of the edge on the transmission signal.

Preferably, the first step size is equal in magnitude to the second step size.

Preferably, however, the second step size is sign-less than the second step width.

In a fifth modification of the first variant, the magnitude of the step size is proportional to the magnitude of the height of the edge on the transmission signal.

In a sixth modification of the first variant, the sign of the first step size depends on whether the edge on the transmission signal is a rising edge or a falling edge. Of course, then the sign of the second step, which is opposite to the first step, is also dependent on whether the edge on the transmission signal is a rising edge or a falling edge.

Second variant of the proposal

The second variant of the proposal differs from the first variant in that the reversal point of the counting operation of the up / down counter is not timed, but depends on the count of the up / down counter itself. Otherwise, the structuring is similar. In this respect, the following description is a repetition of the foregoing with the said difference.

A second embodiment of the proposal thus relates to a device for signal shaping of the transmission signal of a serial interface to an output signal. It includes an up / down counter, a comparator and an integrator. The apparatus is operated in this embodiment with a clock which typically serves as the time base for the up / down counter and the integrator. The up / down counter may have an output state with an output counter value. The word "may" is to be understood in this context that the up / down counter can also have other counts and thus other states. In this respect, the output state is one of many possible states and the output counter value is one of many possible counter readings. Thus, the word "may" does not constitute an optional claim in the claims. The up / down counter does not count when it is in its initial state and no edge occurs on the transmit signal. The counting process is driven by the clock. Accordingly, the up / down counter counts at a first pitch in synchronization with the clock when an edge occurs on the transmission signal and at a first pitch in synchronism with the clock when an edge on the transmission signal has already occurred and the count of the up / down counter does not exceed a predetermined one Inverse count corresponds to. The last condition is different from the one in the previous section. The advantage is that no additional timer is needed and the up / down counter itself with the help of a simple logic can be used for its own control. The up / down counter counts in a second increment in synchronism with the clock when an edge has occurred on the transmission signal and the count of the up / down counter corresponds to a predetermined inverse count or at a previous time that was after the start of counting, this predetermined counter counter Has. Thus, the up / down counter starts to count from an initial count until its count equals this count of counter and then counts back in the reverse direction until it returns to its output count, resulting in a triangular shape of the time history of its count. In this disclosure, "reaching the reverse count" is understood to mean that the amount of the count of the up / down counter is equal to the amount of the difference between the counter count and the initial count. Typically, the initial count is the value 0 selected. The up / down counter stops counting when its count becomes equal to or crosses the output counter value during the count, thus assuming the initial state. In this case, "crossing" means that, for example, before a counting step of the counting process, the counter reading is smaller than the output counter value and, after the counting step, is greater than the output counter value. Of course, it is also a "cross", for example, if before a counting step of the counting process, the count is greater than the output counter value and after the counting step is less than the output counter value. The integrator continues to process the count of the up / down counter and generates the output signal. Since the edges of the triangular signal generated by the up / down counter are substantially linear, the counts of an integrator are substantially square, resulting in parabolic waveforms and the disappearance of odd transients in the spectrum. This leads to a substantial reduction of the radiated interference signals.

In a first modification of the second variant of the apparatus, the value of the second increment corresponds to the value of the first increment multiplied by -1.

In a second modification of the second variant of the device, the first and / or second step size and the reverse counter reading are dependent on the height of the edge on the transmit signal.

Preferably, the first step size is equal in magnitude to the second step size.

Preferably, however, the second step size is sign-less than the second step width.

In a fifth modification of the second variant, the magnitude of the step size and the inverse count are proportional to the magnitude of the height of the edge on the transmission signal.

In a sixth modification of the second variant, the signs of the first step size and the inverse counter state depend on whether the edge on the transmission signal is a rising edge or a falling edge. Of course, then the sign of the second step, which is opposite to the first step, is also dependent on whether the edge on the transmission signal is a rising edge or a falling edge.

Third variant of the proposal

• • Zählen mit einer ersten Schrittweite synchron zu einem Takt unter Bildung eines Zählerstandes, wenn eine Flanke auf dem Sendesignal auftritt und wenn eine Flanke auf dem Sendesignal aufgetreten ist und noch nicht die Hälfte einer vorgegebenen Zeit verstrichen ist und
• • Zählen mit einer zweiten Schrittweite synchron zum Takt unter Bildung eines Zählerstandes, wenn eine Flanke auf dem Sendesignal aufgetreten ist und die Hälfte einer vorgegebenen Zeit verstrichen ist
• • Unterbinden des Zählens unter Beibehaltung des Zählerstandes, wenn der Zählerstand dem Ausgangszählerstand entspricht oder während des Zählens den Ausgangszählerstand kreuzt und wenn keine Flanke auf dem Sendesignal auftritt, wobei im Falle des Kreuzens des zeitlichen Verlauf des Zählerstands mit dem Ausgangszählerstand ein Setzen des Zählerstands auf den Ausgangszählerstand erfolgt;
• • Integrieren des Zählerstandes und Erzeugen eines Ausgangssignals.

The third variant of the proposal relates to a method for signal shaping of the transmission signal of a serial interface to an output signal. The variant represents the method corresponding to the first variant. The method comprises the steps:

• Counting at a first step in synchronism with a clock to form a count when an edge occurs on the transmission signal and when an edge has occurred on the transmission signal and not yet half a predetermined time has elapsed and
• • Counting at a second increment in synchronism with the clock, generating a count when an edge has occurred on the transmit signal and half a predetermined time has elapsed
• • Suppression of counting while maintaining the count when the count corresponds to the output counter reading or crosses the output counter reading during counting and when no edge occurs on the transmit signal, wherein in case of crossing the time history of the counter reading with the output count setting the counter reading to the Output count is done;
• • Integrating the counter reading and generating an output signal.

According to the first variant, in this third variant, the second increment is preferably the negative increment of the first increment.

According to the first variant, in this third variant, the step size preferably depends on the height of the edge on the transmission signal.

According to the first variant, in this third variant, the magnitude of the step size is preferably proportional to the magnitude of the height of the edge on the transmission signal.

According to the first variant, in this third variant, the sign of the first step size preferably depends on whether the edge on the transmission signal is a rising edge or a falling edge.

Fourth variant of the proposal

• • Zählen mit einer ersten Schrittweite synchron zu einem Takt bis zu einem Umkehrzählerstand unter Bildung eines Zählerstandes, wenn eine Flanke auf dem Sendesignal auftritt und wenn eine Flanke auf dem Sendesignal aufgetreten ist und
• • Zählen nach dem Erreichen des Umkehrzählerstandes mit einer zweiten Schrittweite synchron zum Takt unter Bildung eines Zählerstandes, wenn eine Flanke auf dem Sendesignal aufgetreten ist und die Hälfte einer vorgegebenen Zeit verstrichen ist
• • Unterbinden des Zählens unter Beibehaltung des Zählerstandes, wenn der Zählerstand dem Ausgangszählerstand entspricht oder während des Zählens den Ausgangszählerstand kreuzt und wenn keine Flanke auf dem Sendesignal auftritt, wobei im Falle des Kreuzens des Ausgangszählerstandes auf den der Zählerstand auf den Ausgangszählerstand gesetzt wird;
• • Integrieren des Zählerstandes und Erzeugen eines Ausgangssignals.

The fourth variant of the proposal relates to a method for signal shaping of the transmission signal of a serial interface to an output signal. The variant represents the method corresponding to the second variant. The method comprises the steps:

• Counting at a first increment in synchronism with a clock up to an inverse count to form a count when an edge occurs on the transmit signal and when an edge has occurred on the transmit signal and
• • Counting after reaching the reverse count with a second step in synchronism with the clock to generate a count when an edge has occurred on the transmit signal and half of a predetermined time has elapsed
• • stopping the counting while maintaining the count if the count corresponds to the output count or crosses the output count during counting and if no edge occurs on the transmit signal, wherein in case of crossing the output count to which the count is set to the output count;
• • Integrating the counter reading and generating an output signal.

According to the second variant, in this fourth variant, the second increment is preferably the negative increment of the first increment.

According to the second variant, in this fourth variant, preferably the step size and the inverse counter reading depend on the height of the edge on the transmission signal.

According to the second variant, in this fourth variant, preferably the magnitude of the step size and the inverse counter reading are proportional to the magnitude of the height of the edge on the transmission signal.

According to the second variant, in this fourth variant, the sign of the first step size and the sign of the inverse counter value are preferably dependent on whether the edge on the transmission signal is a rising edge or a falling edge.

list of figures

• 1 shows in the form of a simple schematic block diagram the structure of the signal path.

The transmission signal ( SIG ) is placed in the up / down counter ( UDC ) guided. This counts starting with a first edge of the transmission signal with a first increment starting with an initial count. The up / down counter ( UDC ) a meter reading ( CNT ). After a predetermined time or upon reaching a preset counter reading, the reverse counter reading, the up / down counter ( UDC ) his step size in a second step. Typically, the count direction is then reversed because of another sign of the second step size compared to the first step size. Counted the up / down counter ( UDC ) at the beginning upwards, it now preferably counts downwards. Counted the up / down counter ( UDC ) down to the beginning, it now preferably counts upwards.

Preferably, the amount of the first step size and the second step size is the same and only the sign is different. Preferably, the sign of the first step size and thus also of the second step size depends on the direction of the edge on the transmission signal ( SIG ).

An exemplary integrator ( INT ) integrates the counter reading ( CNT ) of the up / down counter ( UDC ) to the output signal ( OUT ). Up / down counter ( UDC ) and integrator ( INT ) are used with a preferably same clock ( CLK ), which allows counting.

Exemplary Verilog code

For simplified rework the corresponding Verilog code is given:

advantage

Such a device for signal shaping enables, at least in some implementations, a reduction of the harmonics. The advantages are not limited to this.

The solution is cost-effective and robust against external interference, because it can be implemented in the digital domain without analogue parts.

LIST OF REFERENCE NUMBERS

CLK

clock;

CNT

Meter reading;

INT

integrator;

OUT

Output signal;

SIG

Transmission signal;

UDC

Up / down counter;

Claims (5)

Method for signal shaping of the transmission signal (SIG) of a serial interface to an output signal (OUT) with the steps Counting at a first increment in synchronism with a clock (CLK) to an inverse counter reading to form a count (CNT) when an edge occurs on the transmit signal (SIG) and when an edge has occurred on the transmit signal (SIG) and - Counting after reaching the Umkehrzählerstandes with a second step in synchronism with the clock (CLK) to form a count (CNT), when an edge on the transmission signal (SIG) has occurred and half of a predetermined time has elapsed; - Suppression of counting while maintaining the count (CNT) when the count (CNT) corresponds to the output count or crosses the output counter during counting and when no edge on the transmission signal (SIG) occurs, wherein in case of crossing the time history of the count (CNT) with the output counter reading a setting of the counter reading (CNT) takes place on the output counter reading; - Integrating the counter reading (CNT) and generating an output signal (OUT). Method according to Claim 1 - wherein the second step size is the negative step size of the first step size. Method according to Claim 1 and / or 2 - wherein the step size and the inverse count depend on the height of the edge on the transmission signal (SIG). Method according to Claim 3 - wherein the amount of the step size and the Umkehrzählerstand are proportional to the amount of the height of the edge on the transmission signal (SIG). Method according to one or more of the preceding claims - Wherein the sign of the first step size and the Umkehrzählerstand depend on whether it is the edge on the transmission signal (SIG) is a rising edge or a falling edge.

Images