DE102018108894A1 - High-k Metal Gate (HKMG) method for forming a memory cell with a large operating window - Google Patents

Abstract

Various embodiments of the present application relate to an integrated circuit (IC) comprising a memory cell having a large operating window and a high erasing speed. In some embodiments, the IC includes a semiconductor substrate and a memory cell. The memory cell includes a control gate electrode, a select gate electrode, a charge trap layer, and a common source / drain region. The common source / drain is defined by the semiconductor substrate and is one of the n-type. The control gate and select gate electrode overlay the semiconductor substrate and are respectively located on opposite sides of the common source / drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal having a p-type work function. In some embodiments, the select gate electrode comprises a metal having a n-type work function.

Description

REFERENCE TO RELATED APPLICATION

The present application claims the priority of the provisional U.S. Application No. 62 / 552,149 , filed on August 30, 2017, the contents of which are incorporated herein by reference in their entirety.

BACKGROUND

The integrated circuits (ICs) manufacturing industry has experienced exponential growth in recent decades. In the development of the ICs, the functional density (i.e., the number of connected devices per die area) has generally increased while the geometry size (i.e., the smallest component that can be fabricated) has decreased. Some advances in the development of ICs include embedded memory technology and high-k metal gate (HKMG) technology. Embedded memory technology is the integration of memory devices with logic devices on the same semiconductor chip. HKMG technology is the fabrication of semiconductor devices using metal gate electrodes and high-k gate dielectric layers.

list of figures

• 1 veranschaulicht eine Querschnittsansicht einiger Ausführungsformen einer integrierten Schaltung (IC), welche eine Speicherzelle mit einem großen Betriebsfenster und einer hohen Löschgeschwindigkeit umfasst.
• 2A und 2B veranschaulichen Querschnittsansichten verschiedener Ausführungsformen einer IC, welche die Elemente der 1 und einige andere Elemente umfasst.
• 3A und 3B veranschaulichen Querschnittsansichten verschiedener Ausführungsformen einer IC, welche die Speicherzelle der 2A und 2B umfasst und ferner eine zusätzliche Halbleitervorrichtung (z.B. eine Hochspannungsvorrichtung oder eine Logikvorrichtung) umfasst.
• 4 bis 7, 8A, 8B, 9 bis 12, 13A bis 13S und 14A bis 14I veranschaulichen eine Serie von Querschnittsansichten einiger Ausführungsformen eines Verfahrens zum Bilden einer Speicherzelle mit einem großen Betriebsfenster und einer hohen Löschgeschwindigkeit.
• 15 veranschaulicht einen Ablaufplan einiger Ausführungsformen des Verfahrens der 4 bis 7, 8A, 8B, 9 bis 12, 13A bis 13S und 14A bis 14I.

Aspects of the present disclosure are best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that in accordance with common practice in the art, various elements are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased to clarify the description.

• 1 FIG. 12 illustrates a cross-sectional view of some embodiments of an integrated circuit (IC) that includes a memory cell having a large operating window and a high erase speed.
• 2A and 2 B 12 illustrate cross-sectional views of various embodiments of an IC incorporating the elements of FIGS 1 and some other elements.
• 3A and 3B 13 illustrate cross-sectional views of various embodiments of an IC incorporating the memory cell of FIG 2A and 2 B and further comprising an additional semiconductor device (eg, a high voltage device or a logic device).
• 4 to 7 . 8A . 8B . 9 to 12 . 13A to 13S and 14A to 14I illustrate a series of cross-sectional views of some embodiments of a method of forming a memory cell having a large operating window and a high erasing speed.
• 15 FIG. 12 illustrates a flowchart of some embodiments of the method of FIG 4 to 7 . 8A . 8B . 9 to 12 . 13A to 13S and 14A to 14I ,

DETAILED DESCRIPTION

In the following disclosure, many different embodiments or examples for realizing various features of the invention are presented. Hereinafter, specific examples of components and arrangements will be described to simplify the present disclosure. Of course these are just examples and should not be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features exist between the first and second features are formed so that the first and second feature are not in direct contact. In addition, reference numerals and / or letters may be repeated in the various examples in the present disclosure. This repetition is for the purpose of simplicity and clarity and as such does not determine any relationship between the various embodiments and / or configurations described.

Further, to simplify the description, terms of spatial relationship such as "below,""below,""lower,""above,""upper," and the like may be used herein to refer to the relationship of one element or feature to another element (s). or feature (s) as illustrated in the figures. The terms of spatial relationship, in addition to the orientation depicted in the figures, are intended to encompass other orientations of the device or device in use or in service. The device or device may be otherwise oriented (rotated 90 degrees or having other orientations) and the spatial relationship descriptors used herein may equally be interpreted accordingly. Moreover, the terms "first,""second,""third,""fourth," and the like are merely general terms and therefore may be interchanged in various embodiments. For example, an element (eg an opening), although it is in In some embodiments, referred to as a "first" element, in other embodiments may be referred to as a "second" element.

In some cases, an integrated circuit (IC) includes a semiconductor substrate and a memory cell. The memory cell is located on the semiconductor substrate and may be, for example, a two-transistor (2T) silicon-oxide-nitride-oxide-silicon (SONOS) memory cell. In the semiconductor substrate, a p-type control gate well and a p-type select gate well adjoin one another. An n-type common source / drain is located between the p-type control and select gate wells in the semiconductor substrate. A polysilicon select gate electrode overlies the p-type select gate well and is located on a first side of the n-type common source / drain. A charge trapping layer and an n-type polysilicon control gate are stacked on the control gate well and located on a second side of the n-type common source / drain facing the first side. Further, the n-type charge trapping layer and polysilicon control gate electrode overlie a selectively conductive channel in the semiconductor substrate. The selectively conductive channel extends from the common source / drain to an individual source / drain on a common source / drain opposite side of the n-type polysilicon control gate.

During use of the memory cell, the various conductive components (e.g., the n-type polysilicon control gate and common source / drain) of the memory cell are selectively biased to vary the amount of charge stored in the charge trapping layer. In an erased state, a low amount of charge is stored in the charge trapping layer. In a programmed state, a high amount of charge is stored in the charge trapping layer. The low charge amount represents a first data value and the high charge amount represents a second data value, so that the charge trap layer stores one data bit. In addition, during use of the memory cell, the selectively conducting channel selectively conducts depending on whether the n-type polysilicon control gate electrode is biased at a voltage exceeding a threshold voltage. The charge in the charge trapping layer forms an electric field generated by the n-type polysilicon control gate electrode so that the threshold voltage changes depending on the amount of charge stored by the charge trapping layer. Therefore, the data state of the charge trapping layer can be read out by biasing the n-type polysilicon control gate electrode with a voltage between the threshold voltage in the programmed state and the threshold voltage in the erased state.

The voltage range from the threshold voltage in the programmed state to the threshold voltage in the erased state is known as the operating window. The larger the operating window, the more flexible the memory cell is for process variations and noise in reading the data state of the memory cell. For example, when the operating window is small, noise may be of sufficient amplitude to increase or decrease the voltage at which the n-type polysilicon control gate is biased during a read operation to outside the operating window the reading operation can give a wrong result. As another example, in mass production of the memory cell, a process variation for each instance of the memory cell may cause the operating window to vary. If the operating window is small, the likelihood that memory cell instances have operating windows that do not overlap the specification limits increases. This in turn can lead to low yields in mass production and high production costs.

A first problem with the IC is that the n-type polysilicon control gate has a low work function. The low work function may result in the memory cell having a small operating window, a light gate back electron injection, a slow erase rate, a high erase saturation, or any combination of the foregoing. Namely, to achieve a high erasing speed, a high erasing voltage is typically used. However, the low work function results in electron-gate back injection when the high erase voltage is used. Due to the electron-gate back injection, electrons tunnel from the n-type polysilicon control gate to the charge trapping layer while simultaneously removing the electrons from the charge trapping layer. Finally, the electrons entering the charge trapping layer and the electrons leaving the charge trapping layer reach an equilibrium state called the erase saturation level. However, the erase saturation level is high, whereby the memory cell can not be completely erased. Since the memory cell is not completely erased, the shift of the threshold voltage from the programmed state to the erased state is small, resulting in a small operation window. Further, as electrons tunnel from the n-type polysilicon control gate to the charge trapping layer, while removing electrons from the charge trapping layer at the same time, the electron gate re-injection at a low erase rate, even if a high erase voltage is used. A second problem with the IC is that miniaturization of polysilicon gate electrode based semiconductor devices reaches its limits.

One possible solution to the first problem is to use a p-type polysilicon control gate instead of the n-type polysilicon control gate since the polysilicon gate of the p-type control gate has a p-type polysilicon gate. Type has a high work function. However, this solution does not solve the second problem. Further, a p-type polysilicon control gate is not easily integrated into methods of forming the IC. For example, a method of forming the IC may include forming the p-type polysilicon control gate and then forming n-type source / drains in the p-type control gate well. Forming the n-type source / drains may result in opposing doping of the p-type polysilicon control gate, such that the p-type polysilicon control gate may have an average work function. As another example, p-type dopants generated during the formation of the p-type polysilicon control gate, to the p-type control gate well, and a doping profile of the control gate well of the p-type, thereby changing performance parameters of the memory cell. Another possible solution to the first problem is to use the p-type polysilicon control gate instead of the n-type polysilicon control gate and also an n-type control gate well instead of using the p-type control gate well. However, p-channel memory cells are not widely used, whereby p-channel memory cells are not easy to integrate into existing ICs.

One possible solution to the second problem is to utilize the high-k metal gate (HKMG) technology with a metal control gate electrode having an n-type work function. However, like the n-type polysilicon control gate electrode, the metal control gate electrode has a low work function. As noted above, the low work function may result in the memory cell having a small operating window, a light gate back electron injection, a slow erase rate, a high erase saturation, or any combination of the foregoing.

Various embodiments of the present application relate to a memory cell having a large operating window and a high erasing speed, and a method of forming the memory cell using the HKMG technology. In some embodiments, a memory cell is located on a semiconductor substrate and includes a control gate electrode, a select gate electrode, a charge trapping layer, and a common source / drain. The common source / drain is located in the semiconductor substrate and has an n-type doping profile. The charge trap layer and the control gate electrode are stacked over the semiconductor substrate and are located on a first side of the common source / drain. Further, the control gate electrode overlies the charge trapping layer and is or comprises a first metal having a p-type work function. The select gate electrode is over the semiconductor substrate and on a second side of the common source / drain opposite the first side. Further, in some embodiments, the select gate electrode is or includes a second metal having a n-type work function.

By using metal with a p-type work function for the control gate electrode, the control gate electrode has a high work function. The high work function results in a difficult electron gate re-injection, resulting in a high quench rate and a low quench saturation level. In addition, the low erase saturation level results in a large operating window. The operating window is the voltage range from the control gate threshold voltage in a programmed state to the control gate threshold voltage in an erased state, and a large operating window makes the memory cell more flexible for process variations and noise during read operations. The memory cell may also be integrated into methods of forming the IC with minimal cost (e.g., without additional reticles and / or photomasks). Furthermore, metal of the control and select gate together with high-k gate dielectric layers may allow the memory cell to be used for sophisticated process nodes, e.g. 28nm (nm), 20nm and smaller process nodes are downsized.

Referring to 1 , becomes a cross-sectional view 100 of some embodiments of an IC, which is a memory cell 102 with a large operating window and a high erasing speed. The memory cell 102 For example, it may be a 2T metal-oxide-nitride-oxide-silicon (MONOS) memory cell or any other suitable memory cell. As illustrated, includes a semiconductor substrate 104 a control gate pan 106 , a pick-gate pan 108 , a common source / drain 110c , a pair of individual storage source / drains 110i and a pair of selectively conductive memory channels 112 , The semiconductor substrate 104 For example, a solid monocrystalline silicon substrate, a silicon on insulator (SOI) substrate, any other suitable semiconductor substrate (s), or any combination of the foregoing may be or include. As used herein, a term (eg, substrate) appended with "(e)" may be, for example, singular or plural.

The control gate pan 106 and the selection gate pan 108 have a first doping type and boundaries in the semiconductor substrate 104 to each other. In some embodiments, the control and select gate wells 106 . 108 different doping profiles (eg a different doping concentration) on. The shared memory source / drain 110c is above the control and select gate wells 106 . 108 , laterally between the control and select gate wells 106 . 108 , Furthermore, the common source / drain 110c a second doping type opposite to the first doping type. The individual storage source / drains 110i are correspondingly above the control and select gate wells 106 . 108 and are respectively on opposite sides of the common source / drain 110c , Further, the individual memory source / drains 110i the second doping type. The first and second doping types may be, for example, p-type and n-type, respectively, or vice versa. The selectively conductive memory channels 112 are located respectively in the control and select gate wells 106 . 108 and each extend from the common source / drain 110c to a corresponding one of the individual storage source / drains 110i , When operating the IC, the selectively conductive memory channels change 112 reversible between low resistance states and high resistance states.

A control gate electrode 114 , a charge trapping layer 116 and a control gate dielectric layer 118 are on the control gate pan 106 stacked, laterally between the common source / drain 110c and a corresponding one of the individual memory source / drains 110i , The charge trapping layer 116 and the control gate dielectric layer 118 lie under the control gate electrode 114 and isolate the control gate electrode 114 electrically from the control gate pan 106 , Further, the control gate dielectric layer is located 118 over the charge trapping layer 116 , The charge trapping layer 116 For example, it may be an oxide-nitride-oxide (ONO) film or any other suitable charge trapping layer. In some embodiments, the charge trapping layer comprises 116 a lower oxide layer 116l , a middle nitride layer 116m which over the lower oxide layer 116l lies, and an upper oxide layer 116u which over the middle nitride layer 116m lies. The control gate dielectric layer 118 For example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics), silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. For example, as used herein, a high-k dielectric may be or include a dielectric having a dielectric constant κ of greater than 3, 9, 5, 10, 15, or 20.

In some embodiments, in which the common and individual source / drains 110c . 110i those of the p-type are (eg the memory cell 102 a p-channel memory cell) is or includes the control gate electrode 114 a metal with an n-type work function. For example, as used herein, an n-type work function may be: 1) a work function within about 0.1 electron volts (eV), about 0.2 eV, or about 0.4 eV of a polycrystalline silicon work function n-type; 2) a work function of less than about 4.0 eV, about 4.2 eV, or about 4.4 eV; a work function of about 3.5 eV to 4.4 eV, about 4.0 eV to 4.4 eV, or about 3.8 eV to 4.5 eV; 4) any other suitable n-type work function; or 5) any combination of the foregoing. For example, the n-type polycrystalline silicon may have a doping concentration of about 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²⁰ cm ^-3 , about 5 × 10 ¹⁹ cm ^-3 to 8 × 10 ¹⁹ cm ^-3 or about 8 × 10 ¹⁹ cm ^-3 to 8 × 10 ²⁰ cm ^-3 . However, other doping concentrations are also applicable. As used herein, an n-type work function metal may be or include, for example, hafnium, zirconium, titanium, tantalum, aluminum, any other suitable n-type work function metal (s), or any combination of the foregoing.

In some embodiments, where the common and individual source / drains 110c . 110i those of the n-type are (eg the memory cell 102 is an n-channel memory cell), is or includes the control gate electrode 114 a metal with a p-type work function. For example, as used herein, a p-type work function may be: 1) a work function within about 0.1 eV, 0.2 eV, or 0.4 eV of a p-type polycrystalline silicon work function; 2) a work function greater than about 4.8 eV, about 5.0 eV, or about 5.2 eV; a work function of about 4.8 eV to 5.2 eV, about 5.0 eV to 5.4 eV, or about 4.6 eV to 5.6 eV; 4) any other suitable p-type work function, or 5) any combination of the foregoing. For example, the p-type polycrystalline silicon may have a doping concentration of about 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²⁰ cm ^-3 , about 5 × 10 ¹⁹ cm ^-3 to 8 × 10 ¹⁹ cm ^-3, or about 8 × 10 ¹⁹ cm ^-3 to 8 × 10 ²⁰ cm ^-3 . However, other doping concentrations are also applicable. As used herein, a p-type work function metal may include, for example, ruthenium, palladium, platinum, cobalt, nickel, titanium aluminum nitride, tungsten carbonitride, any other suitable metal (other suitable metals) having p-type work function, or any combination of the foregoing be or include.

While using the memory cell 102 become the different conductive components (eg the control gate electrode 114 ) of the memory cell 102 selectively biased to those in the charge trapping layer 116 to vary stored charge amount. In an erased state, the charge trapping layer stores 116 a low amount of charge. In a programmed state, the charge trapping layer stores 116 a high amount of charge. The low charge amount represents a first data value and the high charge amount represents a second data value, such that the charge trapping layer 116 stores a data bit. It also conducts during use of the memory cell 102 one of the selectively conductive memory channels 112 that under the control gate electrode 114 lie selectively depending on whether the control gate electrode 114 is biased with a voltage exceeding a threshold voltage. The charge in the charge trapping layer 116 forms an electric field from the control gate electrode 114 is generated so that the threshold voltage changes depending on the charge amount of the charge trapping layer 116 is stored. Therefore, the data state of the charge trapping layer can be 116 can be read by biasing the control gate electrode 114 with a voltage between the threshold voltage in the programmed state and the threshold voltage in the erased state. As stated above, this voltage range is known as the operating window.

By using a metal with a p-type work function for the control gate electrode 114 has the control gate electrode 114 high work function, resulting in difficult electron gate re-injection during quenching of the charge trapping layer 116 leads. Electron gate back injection is the tunneling of electrons from the control gate electrode 114 to the charge trapping layer 116 , under the influence of a strong electric field (eg from a high erase voltage). Since electron-gate back injection is difficult, the erase saturation level is low. The erase saturation level is the level at which electrons due to electron-gate back injection into the charge trapping layer 116 and electrons which due to erasure enter the charge trapping layer 116 leave, reach a state of equilibrium (ie are balanced). Due to the low erosion saturation level, the charge trapping layer can 116 completely or almost completely erased. Further, the difference between the control gate threshold voltage in the erased state and the control gate threshold voltage in the programmed state is high, whereby the operation window is large. Since the operating window is large, the memory cell 102 For example, be flexible for process variations and noise during read operations. In addition, due to the high work function of the control gate electrode 114 a high erase voltage can be applied without being subjected to a simple electron gate re-injection, a high erase saturation level, and a small operating window. Accordingly, the erasure speed can be high.

A selection gate electrode 120 and a select gate dielectric layer 122 are on the selection gate pan 108 stacked, laterally between the common source / drain 110c and a corresponding one of the individual memory source / drains 110i , The select gate dielectric layer 122 is below the selection gate electrode 120 and isolates the select gate 120 electrically from the selection gate pan 108 , The select gate dielectric layer 122 For example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics), silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The selection gate electrode 120 For example, it may be or include doped polysilicon, a metal, any other suitable conductive material (other suitable conductive materials), or any combination of the foregoing.

In some embodiments, the control gate electrode is or includes 114 a p-type work function metal, the select gate electrode 120 is or includes an n-type work function metal and the common and individual storage source / drains 110c . 110i are those of the n-type. In other embodiments, the control gate electrode is or includes 114 an n-type work function metal, the select gate electrode 120 is or includes a metal having a p-type work function and the common and individual memory source / drains 110c . 110i are those of the p-type. In yet other embodiments, the control gate electrode is or includes 114 a metal having a work function of a first doping type (eg n-type or p-type), the selection gate electrode 120 is or includes one Metal having a work function of the first doping type and the common and individual memory source / drains 110c . 110i are those of a second doping type (eg, p-type or n-type) that is opposite to the first doping type.

By using metal for the control and select gate electrodes 114 . 120 and high-k dielectrics for the control and select gate dielectric layers 118 . 122 (ie by using the HKMG technology), the memory cell 102 for advanced process nodes, such as 28nm, 20nm, and smaller process nodes. Further, by using metal instead of doped polysilicon for the control and select gate electrodes 114 . 120 no doping method for forming the control and selection gate electrodes 114 . 120 , so that the performance parameters of the memory cell 102 be more even in mass production. As noted above, a doping process performed to form polysilicon control and select gate electrodes could alter the doping profile of the control and select gate wells, thereby potentially shifting power parameters of a memory cell. Additionally, by using metal instead of doped polysilicon for the control and select gate electrodes 114 . 120 the work functions of the control and select gate electrodes 114 . 120 be better controlled. As noted above, by a doping process performed to form source / drains, polysilicon control gate electrodes and polysilicon select gate electrodes could be oppositely doped, thereby increasing the work functions of the polysilicon control gate electrodes and polysilicon select gate electrodes are changed.

In some embodiments, the control gate electrode is or includes 114 a p-type work function metal, the select gate electrode 120 is or includes n-type polysilicon and the common and individual memory source / drains 110c . 110i are those of the n-type. In other embodiments, the control gate electrode is or includes 114 an n-type work function metal, the select gate electrode 120 is or includes p-type polysilicon and the common and individual memory source / drains 110c . 110i are those of the p-type. In yet other embodiments, the control gate electrode is or includes 114 a metal having a work function of a first doping type (eg n-type or p-type), the selection gate electrode 120 is or includes polysilicon with the first doping type and the common and individual memory source / drains 110c . 110i are those of a second doping type (eg, p-type or n-type) that is opposite to the first doping type.

In some embodiments, a difference between a work function of the control gate electrode 114 and a work function of the select gate electrode 120 about 0.8 eV to 1.2 eV, 0.9 eV to 1.1 eV, or about 0.5 eV to 1.5 eV. However, other suitable workfunction differences are applicable. In some embodiments (where, for example, the memory cell 102 is an n-channel memory cell) is a work function of the control gate electrode 114 higher than a work function of the select gate electrode 120 , In some embodiments (where, for example, the memory cell 102 a p-channel memory cell) is a work function of the control gate electrode 114 lower than a work function of the selection gate electrode 120 ,

Even though 1 is shown and described as if the control and selection gate wells 106 . 108 it is understood that the control and selection gate wells 106 . 108 may be integrated (ie, one and the same) in other embodiments. Furthermore, the control and selection gate wells can 106 . 108 be omitted in yet other embodiments, so that the selectively conductive memory channels 112 in a main body of the semiconductor substrate 104 are located.

Referring to 2A , there will be a cross-sectional view 200A some embodiments of an IC, in which the IC, the elements of 1 and some additional elements (described hereinafter). Furthermore, the elements of the 1 Subject to modifications (eg, geometry, position, etc. changes) to accommodate the additional elements. For example, the individual memory source / drains 110i a lateral distance from the control and selection gate electrodes 114 . 120 exhibit to source / drain extensions 204 accommodate. The IC of 2A may be formed, for example, according to high-k-first embodiments of the method described below.

As illustrated, the semiconductor substrate comprises 104 Furthermore, a massive semiconductor zone 104b which is under the control gate pan 106 , the selection gate pan 108 , the common source / drain 110c and the individual storage source / drains 110i lies. In other embodiments, the massive semiconductor zone 104b doped. For example, the massive semiconductor zone 104b have a p-type doping profile or an n-type doping profile.

In some embodiments, the semiconductor substrate comprises 104 a deep tub, which under the Control and selection gate tubs 106 . 108 lies. In some embodiments, the deep well 202 a doping type similar to that of the control and selection gate wells 106 . 108 is opposite. For example, the control and selection gate wells 106 . 108 those of the p-type, while the deep tub 202 may be one of the n-type, or vice versa. In some embodiments, the semiconductor substrate comprises 104 Furthermore, several source / drain extensions 204 , To simplify the illustration, only some of the source / drain extensions are 204 marked 204. The source / drain extensions 204 lie above the control and selection gate pans 106 . 108 and each extend laterally from a respective source / drain. For example, the common and individual memory source / drains 110c . 110i through the source / drain extensions 204 be extended. The source / drain extensions 204 each have the same doping type, but a lower doping concentration than the corresponding source / drain.

An isolation structure 206 extends into an upper surface of the semiconductor substrate 104 and extends laterally along boundaries of the control and selection gate wells 106 . 108 so that they have the control and selection gate tubs 106 . 108 encloses. In some embodiments, the isolation structure 206 a flat top layout which is annular or has any other suitable closed-loop shape. The isolation structure 206 For example, it may be or include a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or any other suitable isolation structure.

The control gate electrode 114 lies above the control gate pan 106 and the charge trapping layer 116 and is through one or more control gate dielectric layers of the charge trapping layer 116 electrically isolated. For example, between the control gate electrode 114 and the charge trapping layer 116 a lower control gate dielectric layer 118l , a middle control gate dielectric layer 118m and an upper control gate dielectric layer 118u be stacked. The lower and middle control gate dielectric layers 118l . 118m For example, they may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The upper control gate dielectric layer 118u For example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics) or any combination of the foregoing may be or include.

The selection gate electrode 120 lies above the selection gate pan 108 and is through one or more select gate dielectric layers from the select gate well 108 electrically isolated. For example, between the selection gate electrode 120 and the selection gate pan 108 a bottom select gate dielectric layer 122l and an upper select gate dielectric layer 122U be stacked. The bottom select gate dielectric layer 122l For example, it may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The top select gate dielectric layer 122U For example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics) or any combination of the foregoing may be or include.

Gate spacers 208 clad sidewalls of the control and select gate electrodes 114 . 120 out. In some embodiments, each of the gate spacers 208 a pair of segments, each on opposite sidewalls of a respective gate electrode (eg, the control gate electrode 114 or the selection gate electrode 120 ). The gate spacers 208 For example, silicon nitride, silicon oxide, any other suitable dielectric (other suitable dielectrics) or any combination of the foregoing may be or include.

Additional spacers 210 clad sidewalls of the gate spacers 208 and sidewalls of the charge trapping layer 116 out. In some embodiments, the additional spacers clothe 210 also sidewalls of the bottom select gate dielectric layer 122l Side walls of the lower control gate dielectric layer 118l and sidewalls of the middle control gate dielectric layer 118m out. In some embodiments, each of the additional spacers 210 a pair of segments, respectively on opposite sidewalls of a corresponding one of the gate spacers 208 , The additional spacers 210 For example, silicon oxide, silicon nitride, any other suitable dielectric (other suitable dielectrics) or any combination of the foregoing may be or include.

A back-end-of-line (BEOL) interconnect 212 covers the memory cell 102 and includes an Interlayer Dielectric (ILD) layer 214 and multiple vias 216 , The ILD layer 214 For example, it may be or include silicon oxide, silicon nitride, a low-k dielectric, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. As used herein, a low-k Dielectric, for example, a dielectric having a dielectric constant κ of less than about 3.9, 3, 2 or 1 or include. The vias 216 extend through the ILD layer 214 to the control gate electrode 114 , the selection gate electrode 120 , the individual storage source / drains 110i or any combination of the foregoing. The vias 216 For example, tungsten, copper, aluminum copper, aluminum, any other suitable conductive material (other suitable conductive materials), or any combination of the above may be or include.

In some embodiments, silicide pads are 218 according to the common and individual memory source / drains 110c . 110i arranged. The silicide pads 218 reduce the contact resistance between the common and individual memory source / drains 110c . 110i and corresponding of the vias 216 , The silicide pads 218 For example, nickel silicide, any other suitable silicide (other suitable silicides), or any combination of the foregoing may be or include.

Referring to 2 B , there is a cross-sectional view 200B some alternative embodiments of the IC 2A in which the upper control and select gate dielectric layers 118u . 122U corresponding to a bottom of the control gate electrode 114 and a bottom of the selection gate electrode 120 envelop. The IC of 2 B For example, it may be formed according to high-k-last embodiments of the method described below.

Referring to 3A , there is a cross-sectional view 300A of some embodiments of an IC in which the IC is the memory cell 102 of the 2A and one or more additional semiconductor devices associated with the memory cell 102 are integrated. The one or more semiconductor devices may include, for example, an input / output (I / O) logic device 302 , a high voltage (HV) device 304 and a core logic device 306 , any other suitable semiconductor device (other suitable semiconductor devices) or any combination of the foregoing. The IC of 3A may be formed, for example, according to high-k-first embodiments of the method described below.

The I / O logic device 302 supports I / O operations for the IC. For example, the I / O logic device 302 and other I / O logic devices (not shown) together realize I / O circuits for data input to and / or output from the IC. The HV device 304 is a device that operates at high voltages compared to the I / O logic device 302 and / or the core logic device 306 is working. For example, the high voltages may be about 20 to 50 volts, 10 to 100 volts, 30 to 70 volts, or any other suitable high voltages. In some embodiments, the HV device controls 304 Bit lines and / or word lines in a memory cell array, which the memory cell 102 may include. The core logic device 306 supports core functions for the IC. For example, the core logic device 306 and other core logic devices (not shown) together realize core circuits for the IC. Such core circuits may include, for example, row decoder circuits, column decoder circuits, image signal processing (ISP) circuits, control circuits, any other suitable core circuits, or any combination of the foregoing. The I / O logic device 302 , the HV device 304 and the core logic device 306 For example, metal-oxide-semiconductor (MOS) device (s), MOS field effect transistor (s) (MOSFET (s)), insulated gate field effect transistor (s), (insulated gate FET (s), IGFET (s)), any other suitable semiconductor device (other suitable semiconductor devices), or any combination of the foregoing.

In some embodiments, where the IC is the I / O logic device 302 includes, comprises the semiconductor substrate 104 an I / O tub 308 , a pair of I / O source / drains 310 and a selectively conductive I / O channel 312 , To simplify the illustration, this is just one of the I / O source / drains 310 With 310 characterized. The I / O pan 308 is below the I / O source / drains 310 and has a first doping type. In some embodiments, the I / O tray is located 308 next to the deep tub 202 , In other embodiments, the I / O tray is located 308 over the deep tub 202 , In some embodiments, the isolation structure extends 206 lateral along a boundary of the I / O pan 308 to the I / O pan 308 to enclose (eg completely enclose). The I / O source / drains 310 are located on opposite sides of the I / O tray 308 and have one of the I / O troughs 308 opposite doping on. The selectively conductive I / O channel 312 is located in the I / O tray 308 and extends from one of the I / O source / drains 310 to another of the I / O source / drains 310 ,

An I / O gate electrode 314 and one or more I / O gate dielectric layers are on the selectively conductive I / O channel 312 stacked, lateral between the I / O source / drains 310 , The I / O gate electrode 314 For example, it may be or include doped polysilicon, a metal, any other suitable conductive material (other suitable conductive materials), or any combination of the foregoing. In some embodiments, the I / O source / drains 310 those of the n-type and the I / O gate electrode 314 is or comprises a metal having a n-type work function. In some embodiments, the I / O source / drains 310 those of the p-type and the I / O gate electrode 314 is or comprises a metal having a p-type work function.

The I / O gate dielectric layer (s) is under the I / O gate electrode 314 to the I / O gate electrode 314 electrically from the selectively conductive I / O channel 312 to isolate. For example, a bottom I / O gate dielectric layer 316l and an upper gate I / O dielectric layer 316u between the I / O gate electrode 314 and the selectively conductive I / O channel 312 be stacked. The lower I / O gate dielectric layer 316l For example, it may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The top I / O gate dielectric layer 316u may be or include, for example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics), or any combination of the foregoing. In some embodiments, the I / O gate dielectric layer (s) has an I / O dielectric thickness T _i which is less than a control gate dielectric thickness T _c1 is and / or which is about the same size as a select gate dielectric thickness T _s , The control gate dielectric thickness T _c1 for example, by the charge trapping layer 116 and the control gate dielectric layer (s) may be defined. The selection gate dielectric thickness T _s For example, it may be defined by the select gate dielectric layer (s).

In some embodiments, where the IC is the HV device 304 includes, comprises the semiconductor substrate 104 a HV-tub 318 , a pair of HV source / drains 320 and a selectively conductive HV channel 322 , For ease of illustration, only one of the HV source / drains is 320 With 320 characterized. The HV tub 318 is under the HV Source / Drains 320 and lies above the deep tub 202 , In some embodiments, the isolation structure extends 206 lateral along a boundary of the HV tank 318 to the HV-tub 318 to enclose (eg completely enclose). The HV Source / Drains 320 are located on opposite sides of the HV-tub 318 and have one of the HV tub 318 opposite doping on. The selectively conductive HV channel 322 is located in the HV-tub 318 and extends from one of the HV source / drains 320 to another of the HV source / drains 320 ,

An HV gate electrode 324 and one or more HV gate dielectric layers are on the selectively conducting HV channel 322 stacked, laterally between the HV source / drains 320 , The HV gate electrode 324 For example, it may be or include doped polysilicon, a metal, any other suitable conductive material (other suitable conductive materials), or any combination of the foregoing. In some embodiments, the HV source / drains 320 those of the n-type and the HV gate electrode 324 is or comprises a metal having a n-type work function. In some other embodiments, the HV source / drains 320 those of the p-type and the HV gate electrode 324 is or comprises a metal having a p-type work function.

The HV gate dielectric layer (s) is under the HV gate electrode 324 to the HV gate electrode 324 electrically from the selectively conductive HV channel 322 to isolate. For example, a lower HV gate dielectric layer 326l , a middle HV gate dielectric layer 326m and an upper HV gate dielectric layer 326u between the HV gate electrode 324 and the selectively conductive HV channel 322 be stacked. The lower and middle HV gate dielectric layer 326l . 326m For example, they may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The upper HV gate dielectric layer 326u For example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics), or any combination of the foregoing may be or include. In some embodiments, the HV gate dielectric layer (s) have an HV dielectric thickness T _h which is higher than the control gate dielectric thickness T _c1 and / or the selection gate dielectric thickness T _s is. In some embodiments, the HV dielectric thickness is T _h also higher than the I / O dielectric thickness T _i , It is understood that the HV dielectric thickness T _h higher than the other dielectric thicknesses (eg, the I / O dielectric thickness T _i ) is because the HV device 304 works at higher voltages.

In some embodiments, the IC is the core logic device 306 includes, comprises the semiconductor substrate 104 a core pan 328 , a couple of core source / drains 330 and a selectively conductive core channel 332 , To simplify the illustration, only one of the core source / drains is 330 With 330 characterized. The core sink 328 is below the core source / drains 330 , In some Embodiments is the core pan 328 next to the deep tub 202 , In other embodiments, the core tray is located 328 over the deep tub 202 , In some embodiments, the isolation structure extends 206 lateral along a boundary of the core tub 328 to the core pan 328 to enclose (eg completely enclose). The core source / drains 330 are located respectively on opposite sides of the core pan 328 and have one of the core tub 328 opposite doping on. The selectively conductive core channel 332 is located in the core tub 328 and extends from one of the core source / drains 330 to another of the core source / drains 330 ,

A core-gate electrode 334 and a core-gate dielectric layer are on the selectively conductive core channel 332 stacked, laterally between the core source / drains 330 , The core gate electrode 334 lies above the core-gate dielectric layer 336 and may be or include, for example, doped polysilicon, a metal, any other suitable conductive material (other suitable conductive materials), or any combination of the foregoing. In some embodiments, the core sources are drains 330 those of the n-type and the core-gate electrode 334 is or comprises a metal having a n-type work function. In some other embodiments, the core sources are drains 330 those of the p-type and the core-gate electrode 334 is or comprises a metal having a p-type work function. The core gate electrode 334 For example, hafnium oxide, silicon nitride, alumina, any other suitable high-k dielectric (other suitable high-k dielectrics) or any combination of the foregoing may be or include. In some embodiments, the core-gate dielectric layer 336 a core dielectric thickness T _c2 which is less than the control gate dielectric thickness T _c1 and / or the selection gate dielectric thickness T _s is. In some embodiments, the core dielectric thickness is T _c also lower than the I / O dielectric thickness T _i and / or the HV dielectric thickness T _h ,

In some embodiments, the source / drain extensions expand 204 the I / O source / drains 310 , the HV Source / Drains 320 , the core source / drains 330 or any combination of the foregoing. To simplify the illustration, only some of the source / drain extensions are 204 With 204 characterized. In some embodiments, the gate spacers clothe 208 Side walls of the I / O gate electrode 314 Side walls of the HV gate electrode 324 Side walls of the core gate electrode 334 or any combination of the above. In some embodiments, the additional spacers clothe 210 Side walls of the gate spacers 208 on the I / O tray 308 , the I / O tub 318 , the core-sink 328 or any combination of the above.

The BEOL connection structure 212 covers the memory cell 102 and the additional semiconductor device (s) (eg, the I / O logic device 302 ). The BEOL connection structure 212 includes the ILD layer 214 and the multiple vias 216 , To simplify the illustration, only some of the vias are 216 With 216 characterized. The vias 216 extend through the ILD layer 214 to the selection gate electrode 120 , the control gate electrode 114 , the individual storage source / drains 110i or any combination of the foregoing. In some embodiments, the vias extend 216 also through the ILD layer 214 to the I / O gate electrode 314 , the I / O source / drains 310 , the HV gate electrode 324 , the HV source / drains 320 , the core gate electrode 334 , the core source / drains 330 or any combination of the foregoing.

In some embodiments, the silicide pads are 218 according to the common memory source / drain 110c and the individual storage source / drains 110i , Further, in some embodiments, the silicide pads are located 218 corresponding to the I / O source / drains 310 , the HV source / drains 320 , the core source / drains 330 or any combination of the foregoing. For ease of illustration, only some of the silicide pads are 218 With 218 characterized.

Referring to 3B , there is a cross-sectional view 300B some alternative embodiments of the IC 3A in which the upper control and select gate dielectric layers 118u . 122U corresponding to a bottom of the control gate electrode 114 and a bottom of the selection gate electrode 120 envelop. Further, the upper I / O gate dielectric layer envelops 316U , the upper HV gate dielectric layer 326u and the core-gate dielectric layer 336 corresponding to a bottom of the I / O gate electrode 314 , a bottom of the HV gate electrode 324 and a bottom of the core-gate electrode 334 , The IC of 2A For example, it may be formed according to high-k-last embodiments of the method described below.

In some embodiments, there is a residual dielectric layer 338 under the gate spacers and additional spacers 208 . 210 on the core pan 328 , In some embodiments, the residual dielectric layer comprises 338 a pair of segments corresponding to opposite sidewalls of the core-gate dielectric 336 on. The residual dielectric layer 338 For example, it may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing.

Referring to 4 to 7 . 8A . 8B . 9 to 12 . 13A to 13S and 14A to 14I , there is a series of cross-sectional views 400 to 700 . 800A . 800B . 900 to 1200 . 1300A to 1300S . 1400A to 1400i various embodiments of a method for forming the ICs of 3A and 3B shown. 13A to 13S are alternatives to 14A to 14I so that the procedure from the steps of 12 can go to: 1) the steps of 13A to 13S or 2 ) the steps of 14A to 14I ,

In 13A to 13S gets in before removing the victim gates 13O an upper select gate dielectric layer 122U (see for example 13C) educated. In contrast, in 14A to 14I the top select gate dielectric layer 122U after removing the victim gates in 14E educated. Therefore, in embodiments where the top select gate dielectric layer is equivalent 122U includes a high-k dielectric, 13A to 13S High-k "first" embodiments of the method while 14A to 14I High-k "last" embodiments of the method. In addition, at 13A to 13S a second gate dielectric layer 1202 in 12 from a core semiconductor zone 104c removed before in 13C the victim gates are formed. In contrast, at 14A to 14I the second gate dielectric layer 1202 in 12 partly during the formation of silicide spacers 219 in 14C and partially while removing the victim gates in 14E from the core semiconductor zone 104c away. 13A to 13S for example, can be applied to the structure of 3A to form while 14A to 14I for example, can be applied to the structure of 3B to build.

As through the cross-sectional view 400 of the 4 illustrates, a semiconductor substrate 104 provided. In some embodiments, the semiconductor substrate is or includes 104 a solid monocrystalline silicon substrate, an SOI substrate, any other suitable semiconductor substrate (other suitable semiconductor substrates), or any combination of the foregoing.

As well as the cross-sectional view 400 of the 4 is illustrated in the semiconductor substrate 104 an isolation structure 206 formed around a core semiconductor zone 104c , an HV semiconductor zone 104h , a memory semiconductor zone 104m and an I / O semiconductor zone 104i demarcate and disconnect electrically. The isolation structure 206 For example, it may be or include an STI structure, a DTI structure, any other suitable isolation structure (other suitable isolation structures), or any combination of the foregoing. In some embodiments, a method of forming the isolation structure comprises 206 Patterning of the semiconductor substrate 104 to a ditch with a layout of the isolation structure 206 and then filling the trench with a dielectric material. The patterning can be done, for example, by photolithography, any other suitable patterning method (other suitable patterning methods), or any combination of the foregoing. As used herein, a term (eg, process) appended with "(e)" may be, for example, singular or plural.

As well as the cross-sectional view 400 of the 4 is illustrated on the semiconductor substrate 104 and the isolation structure 206 a sacrificial dielectric layer 402 educated. The sacrificial dielectric layer 402 For example, it may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The sacrificial dielectric layer 402 For example, by thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, any other suitable deposition process (other suitable techniques) Deposition method) or any combination of the above.

As through the cross-sectional view 500 of the 5 is illustrated in the HV and memory semiconductor zones 104h . 104m a deep tub 202 formed over a massive semiconductor zone 104b of the semiconductor substrate 104 lies. In some embodiments, the deep well 202 and the massive semiconductor zone 104b opposite doping types on. In some embodiments, a method of forming the deep well comprises 202 selectively doping the semiconductor substrate 104 , The selective doping may be performed, for example, by ion implantation with an arrayed mask, any other suitable selective doping method (other suitable selective doping methods), or any combination of the foregoing. The mask comes with a layout of the deep tub 202 structured and may, for example, a photoresist mask, any other suitable mask (others suitable masks) or any combination of the above. It should be noted that the ion implantation may be performed, for example, while the sacrificial dielectric layer 402 is selected by selecting an implantation energy high enough to allow ions of ion implantation through the sacrificial dielectric layer 402 reach.

As through the cross-sectional view 600 of the 6 illustrates, multiple wells in the semiconductor substrate 104 educated. The tubs include an I / O tub 308 , an I / O tub 308 , a pick-gate pan 108 and a core sink 328 which are correspondingly in the I / O semiconductor zone 104i , the HV semiconductor zone 104h , the memory semiconductor zone 104m and the core semiconductor zone 104c are formed. The pick gate pan 108 and the HV tub 318 lie over the deep tub 202 , Further, there is the selection gate well 108 on a first side of the memory semiconductor zone 104m and laterally spaced from a second side of the memory semiconductor zone 104m on, which is opposite the first page. In some embodiments, the I / O tray 308 a first doping type while the HV tub 318 , the selection gate pan 108 and the core-sink 328 have a second doping type, which is opposite to the first doping. The first and second doping types may be, for example, the n-type and the p-type, respectively, or vice versa. In some embodiments, the first doping type is the same as that of the deep well 202 ,

In some embodiments, a method of forming the wells includes a series of selective doping methods. For example, by a first selective doping process, one or more n-type wells (eg, the I / O well 308 ) and, by a second selective doping process, one or more p-type wells (eg, the select gate well 108 , the HV tub 318 and the core-sink 328 ) are formed. Any of the selective doping methods may be performed, for example, by ion implantation with an arrayed mask, any other suitable selective doping method (other suitable selective doping methods), or any combination of the foregoing. The mask is patterned with a layout of the well (s) to be formed, and may be, for example, a photoresist mask, any other suitable mask (s), or any combination of the foregoing. It should be noted that the ion implantation may be performed, for example, while the sacrificial dielectric layer 402 is selected by selecting an implantation energy high enough to allow ions of ion implantation through the sacrificial dielectric layer 402 reach.

As through the cross-sectional view 700 of the 7 is illustrated in the memory semiconductor zone 104m next to the selection gate pan 108 a control gate pan 106 educated. Further, the control gate well is located 106 over the deep tub 202 , The control gate pan 106 has the same doping type as the select gate well 108 and, in some embodiments, has a different doping profile than the selection gate well 108 , For example, the selection and control gate pan 108 . 106 both of the p-type and the control gate pan 106 may have a different doping concentration than the selection gate well 108 , The control gate pan 106 For example, it may be performed by ion implantation with an arrayed mask, any other suitable selective doping method (other suitable selective doping methods), or any combination of the foregoing. The mask comes with a layout of the control gate pan 106 and may be, for example, a photoresist mask, any other suitable mask (s), or any combination of the foregoing. It should be noted that the ion implantation may be performed, for example, while the sacrificial dielectric layer 402 is selected by selecting an implantation energy high enough to allow ions of ion implantation through the sacrificial dielectric layer 402 reach.

As also by the cross-sectional view 700 of the 7 illustrates the sacrificial dielectric layer 402 structured so that the sacrificial dielectric layer 402 from the control gate pan 106 is removed while the sacrificial dielectric layer 402 on the selection gate pan 108 , the I / O tub 308 , the HV tub 318 and the core pan 328 is left. The patterning can be done, for example, by photolithography, any other suitable patterning method (other suitable patterning methods), or any combination of the foregoing. In some embodiments, the patterning includes etching into the sacrificial dielectric layer 402 by a mask (eg, a photoresist mask) used in the selective doping process (s) that is performed around the control gate well 106 to build. Further, the patterning may be, for example, before or after forming the control gate well 106 be performed.

As through the cross-sectional view 800A of the 8A illustrates a charge trapping layer 116 formed the structure of the 7 covered. The charge trapping layer 116 can to Example, an ONO film or any other suitable charge trapping layer. In some embodiments, as by the cross-sectional view 800B of the 8B includes the charge trapping layer 116 a lower oxide layer 116l , a middle nitride layer 116m and an upper oxide layer 116u , The lower oxide layer 116l For example, a thickness T _l from about 1 to 3 nanometers, about 1.5 to 2.5 nanometers, or about 1 to 5 nanometers. However, there are other values for the thickness T _l applicable. The middle oxide layer 116m For example, a thickness T _m from about 2 to 14 nanometers, about 6 to 10 nanometers, or about 7.5 to 8.5 nanometers. However, there are other values for the thickness T _m applicable. The upper oxide layer 116u For example, a thickness T _u from about 2 to 8 nanometers, about 3 to 5 nanometers, or about 3.5 to 5.5 nanometers. However, there are other values for the thickness T _u applicable. The cross-sectional view 800B of the 8B For example, see an enlarged view of the charge trapping layer 116 be in an enlarged view of the circle labeled " 8B " in 8A , The charge trapping layer 116 For example, it may be formed by thermal oxidation, CVD, PVD, ALD, sputtering, any other suitable deposition method (other suitable deposition methods), or any combination of the foregoing.

As through the cross-sectional view 900 of the 9 illustrates the sacrificial dielectric layer 402 and the charge trapping layer 116 structured so that the sacrificial dielectric layer 402 and the charge trapping layer 116 from the HV tub 318 be removed. In structuring, the sacrificial dielectric layer becomes 402 and the charge trapping layer 116 on the I / O tray 308 , the selection gate pan 108 and the core pan 328 and, moreover, the charge trapping layer becomes 116 on the control gate pan 106 leave. The patterning can be done, for example, by photolithography, any other suitable patterning method (other suitable patterning methods), or any combination of the foregoing.

As through the cross-sectional view 1000 of the 10 illustrates a first gate dielectric layer 1002 formed the structure of the 9 covered. The first gate dielectric layer 1002 For example, it may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The first gate dielectric layer 1002 For example, it may be formed by thermal oxidation, CVD, PVD, ALD, sputtering, any other suitable deposition method (other suitable deposition methods), or any combination of the foregoing. In some embodiments, the first gate dielectric layer 1002 a first thickness T ₁ on the HV tub 318 and a second thickness T ₂ on the I / O tray 308 , the selection gate pan 108 , the control gate sink 106 and the core pan 328 on, with the second thickness T ₂ less than the first thickness T ₁ , This can happen when the first gate dielectric layer 1002 formed by thermal oxidation and the charge trapping layer 116 An ONO film is because oxide of thermal oxidation on the semiconductor material of the semiconductor substrate 104 forms faster than on oxide of the charge trapping layer 116 ,

As through the cross-sectional view 1100 of the 11 illustrates the first gate dielectric layer 1002 and the charge trapping layer 116 structured so that the first gate dielectric layer 1002 and the charge trapping layer 116 from the I / O tub 308 , the selection gate pan 108 and the core pan 328 be removed. In structuring, the first gate dielectric layer becomes 1002 on the HV tub 318 and the control gate pan 106 leave. The patterning can be done, for example, by photolithography, any other suitable patterning method (other suitable patterning methods), or any combination of the foregoing.

As through the cross-sectional view 1200 of the 12 illustrates a second gate dielectric layer 1202 formed the structure of the 11 covered. The second gate dielectric layer 1202 For example, it may be or include silicon oxide, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. The second gate dielectric layer 1202 For example, it may be formed by thermal oxidation, CVD, PVD, ALD, sputtering, any other suitable deposition method (other suitable deposition methods), or any combination of the foregoing. In some embodiments, the second gate dielectric layer 1202 a first thickness T ₁ on the I / O tray 308 , the selection gate pan 108 and the core pan 328 and a second thickness T ₂ on the HV tub 318 and the control gate pan 106 on, with the second thickness T ₂ less than the first thickness T ₁ , This can be done when the second gate dielectric layer 1202 formed by thermal oxidation and the first gate dielectric layer 1002 is an oxide, since oxide of the thermal oxidation on the semiconductor material of the semiconductor substrate 104 forms faster than on oxide of the first gate dielectric layer 1002 ,

As through the cross-sectional view 1300A of the 13A illustrates, the second gate dielectric 1202 structured such that the second gate dielectric layer 1202 from the core pan 328 Will get removed. Furthermore, in structuring, the second gate dielectric layer becomes 1202 on the HV tub 318 , the control gate sink 106 , the selection gate pan 108 and the I / O pan 308 leave. The patterning can be done, for example, by photolithography, any other suitable patterning method (other suitable patterning methods), or any combination of the foregoing.

As through the cross-sectional view 1300B of the 13B illustrates a third gate dielectric layer 1302 , a sacrificial gate layer 1304 and a gate hard mask layer 1306 formed, stacked on the structure of 13A , The sacrificial gate layer 1304 is above the third gate dielectric layer 1302 and the gate hardmask layer 1306 lies above the sacrificial gate layer 1304 , The third gate dielectric layer 1302 For example, hafnium oxide, silicon nitride, alumina, any other suitable high-k dielectric (other suitable high-k dielectrics) or any combination of the foregoing may be or include. In some embodiments, the third gate dielectric layer 1302 a thickness T of about 1 to 3 nanometers, about 1.5 to 2.5 nanometers, or about 1 to 5 nanometers. However, other values for the thickness T are applicable. The sacrificial gate layer 1304 For example, n-type or p-type doped polysilicon, undoped polysilicon may be or include any other suitable material (other suitable materials) or any combination of the foregoing. The gate hard mask layer 1306 For example, it may be or include silicon nitride, silicon oxide, any other suitable material (other suitable materials), or any combination of the foregoing. In some embodiments, a method of forming the third gate dielectric layer comprises 1302 , the victim gate layer 1304 and the gate hardmask layer 1306 thermal oxidation, CVD, PVD, ALD, sputtering, any other suitable deposition method (other suitable deposition methods) or any combination of the above.

As through the cross-sectional view 1300C of the 13C illustrates the third gate dielectric layer 1302 (please refer 13B) , the sacrificial gate layer 1304 (please refer 13B) and the gate hardmask layer 1306 (please refer 13B) structured. The patterning becomes a core-gate dielectric layer 336 , a core sacrificial gate 1308 and a core-gate hardmask 1310 formed, stacked on the core pan 328 , The patterning becomes an upper HV gate dielectric layer 326u , a HV Victim Gate 1312 and an HV gate hardmask 1314 formed, stacked on the HV sink 318 , The patterning becomes an upper control gate dielectric layer 118u , a tax victim gate 1316 and a control gate hardmask 1318 formed, stacked on the control gate sink 106 , The patterning becomes an upper select gate dielectric layer 122U , a pick-and-shoot-gate 1320 and a sacrificial gate hard mask 1322 formed, stacked on the pick gate pan 108 , The patterning becomes an upper gate I / O dielectric layer 316U , an I / O victim gate 1324 and an I / O gate hardmask 1326 formed, stacked on the I / O pan 308 , The core-gate dielectric layer 336 , the upper HV gate dielectric layer 326u , the upper control gate dielectric layer 118u , the top select gate dielectric layer 122U and the top I / O gate dielectric layer 316U , are made from the third gate dielectric layer 1302 educated. The Core Victim Gate 1308 , the HV Victim Gate 1312 , the tax victim gate 1316 , the Selection Ofer Gate 1320 and the I / O Victim Gate 1324 (collectively, the sacrificial gates) are taken from the sacrificial gate layer 1304 educated. The core-gate hardmask 1310 , the HV gate hard mask 1314 , the control gate hardmask 1318 , the sacrificial gate hard mask 1322 and the I / O Gate Hardmask 1326 (collectively, the gate hard masks) become out of the gate hardmask layer 1306 educated.

In some embodiments, a method of patterning the third gate dielectric layer includes 1302 , the victim gate layer 1304 and the gate hardmask layer 1306 Structuring the gate hardmask layer 1306 for forming the gate hard masks. The patterning can be done, for example, by photolithography, any other suitable patterning method (other suitable patterning methods), or any combination of the foregoing. Subsequently, the method comprises performing an etching process in the sacrificial gate layer 1304 and the third gate dielectric layer 1302 with the gate hard masks arranged to form a structure of the gate hard masks on the sacrificial gate layer 1304 and the third gate dielectric layer 1302 transferred to. In some embodiments, the semiconductor substrate is used 104 and / or the second gate dielectric layer 1202 as an etch stop for the etching process.

As through the cross-sectional view 1300D of the 13D Illustrated are multiple gate spacers 208 on sidewalls of the Core, HV, Control, Selection and I / O Victims Gate 1308 . 1312 . 1316 . 1320 . 1324 educated. The gate spacers 208 For example, silicon nitride, silicon oxynitride, any other suitable material (s), or any combination of the foregoing may be or include. In some embodiments includes a method of forming the gate spacers 208 Depositing a gate spacer layer, which has the structure of 13C and then performing etching back into the gate spacer layer. The etch back removes horizontal segments of the gate spacer layer without removing vertical segments of the gate spacer layer. Upon completion of the etch back, the remaining vertical segments of the gate spacer correspond to the gate spacers 208 ,

As through the cross-sectional view 1300E of the 13E are illustrated in the semiconductor substrate 104 first source / drain extensions 204a educated. For ease of illustration, only a few of the first source / drain extensions 204a With 204a characterized. The first source / drain extensions 204a include a first pair of source / drain extensions over the core well 328 , a second pair of source / drain extensions over the HV well 318 and a third pair of source / drain extensions over the I / O tray 308 , Furthermore, the first source / drain extensions 204a corresponding troughs opposite doping types. For example, the source / drain extensions of the first pair have one of the core wells 328 opposite doping on.

In some embodiments, a method of forming the first source / drain extensions comprises 204a a series of selective doping methods. For example, n-type source / drain extensions can be formed by a first selective doping process, and then p-type source / drain extensions can be formed by a second selective doping process. The source / drain extensions in the core and HV tub 328 . 318 For example, they may be of the n-type, while the source / drain extensions in the I / O well may be, for example, p-type, or vice versa. Any of the selective doping methods may be performed, for example, by ion implantation with an arrayed mask, any other suitable selective doping method (other suitable selective doping methods), or any combination of the foregoing. The mask is patterned with a layout of the source / drain extensions to be formed, and may be, for example, a photoresist mask, any other suitable mask (s), or any combination of the foregoing. It should be noted that the ion implantation may be performed, for example, while the first and second gate dielectric layers 1002 . 1202 by selecting an implantation energy high enough to allow ions of ion implantation through the first and second gate dielectric layers 1002 . 1202 reach.

As through the cross-sectional view 1300F of the 13F illustrates the first gate dielectric layer 1002 , the second gate dielectric layer 1202 and the charge trapping layer 116 structured. In structuring, the charge trapping layer becomes 116 directly under the upper control gate dielectric layer 118u and the gate spacers 208 positioned. The patterning becomes a central control gate dielectric layer 118m and a lower control gate dielectric layer 118l formed stacked between the upper control gate dielectric layer 118l and the charge trapping layer 116 , The patterning becomes a bottom select gate dielectric layer 122l formed below the top select gate dielectric layer 122U lies. The middle control gate dielectric layer 118m and the lower select gate dielectric layer 122l are made of the second gate dielectric layer 1202 formed and the lower control gate dielectric layer 118l becomes from the first gate dielectric layer 1002 educated. The patterning can be done, for example, by photolithography, any other suitable patterning method (other suitable patterning methods), or any combination of the foregoing. For example, a photoresist mask may be formed comprising the core, HV, and I / O wells 328, 318 . 308 covered while the selection and control gate pan 108 . 106 remain uncovered. Then, an etching process may be introduced into the first gate dielectric layer 1002 , the second gate dielectric layer 1202 and the charge trapping layer 116 can be performed while the photoresist mask is disposed, and then the photoresist mask can be removed. During the etching, the photoresist mask serves as a mask together with the control gate hardmask 1318 , the selection gate hardmask 1322 and the gate spacers 208 ,

As through the cross-sectional view 1300G of the 13G are illustrated in the semiconductor substrate 104 second source / drain extensions 204b educated. The second source / drain extensions 204a include a common source / drain extension and a pair of individual source / drain extensions. The common source / drain extension is over both the select gate well 108 as well as above the control gate pan 106 , between the Pick Victims Gate 1320 and the Tax Victim Gate 1316 , The individual source / drain extensions are correspondingly above the select gate well 108 and above the control gate pan 106 so that the control and selection victim gate 1316 . 1320 and the common source / drain extension between the individual source / drain extensions are arranged. The second source / drain extensions 204b have one of the control and select gate wells 106 . 108 opposite doping type on.

In some embodiments, a method of forming the second source / drain extensions 204b a selective doping process. The selective doping process can be performed, for example, by ion implantation with an arrayed mask, any other suitable selective doping method (other suitable selective doping methods), or any combination of the foregoing. The mask comes with a layout of the second source / drain extensions 240b and may be, for example, a photoresist mask, any other suitable mask (s), or any combination of the foregoing. In some embodiments, the structuring of the 13F and the selective doping method of 13G performed with the same arranged photoresist mask.

As through the cross-sectional view 1300H of the 13H illustrates, on sidewalls, the gate spacers 208 several additional spacers 210 educated. The additional spacers 210 For example, silicon nitride, silicon oxynitride, any other suitable dielectric material (other suitable dielectric materials), or any combination of the foregoing may be or include. In some embodiments, a method of forming the additional spacers 210 Depositing a main spacer layer, which has the structure of 13G and then performing etching back into the main spacer layer. The etchback removes horizontal segments of the main spacer layer without removing vertical segments of the main spacer layer. The remaining vertical segments of the main spacer layer correspond to the additional spacers 210 ,

As through the cross-sectional view 1300I of the 13I are illustrated in the semiconductor substrate 104 Source / Drains formed. The source / drains include a pair of core source / drains 330 , a pair of HV source / drains 320 , a pair of I / O source / drains 310 , a shared memory source / drain 110c and a pair of individual storage source / drains 110i , The core source / drains 330 , the HV Source / Drains 320 and the I / O source / drains 310 be appropriately on the core pan 328 , the HV tub 318 and the I / O pan 308 educated. The core source / drains 330 , the HV Source / Drains 320 and the I / O source / drains 310 each adjacent to a corresponding one of the first source / drain extensions 204a and have the same doping type as the corresponding source / drain extension, but a higher doping concentration. The shared memory source / drain 110c is located on the selection and control gate wells 108 . 106 between the selection and the tax victim gate 1316 . 1320 , The individual storage source / drains 110i are located respectively on the selection and control gate wells 108 . 106 so that the selection and the tax victim gate 1316 . 1320 and the shared memory source / drain 110c between the individual storage source / drains 110i are located. The common and the individual storage source / drains 110c . 110i each adjacent to a corresponding one of the second source / drain extensions 204b and have the same doping type as the corresponding source / drain extension, but a higher doping concentration.

In some embodiments, a method of forming the source / drains comprises a series of selective doping methods. For example, n-type source / drains may be formed by a first selective doping process, and then p-type source / drains may be formed by a second selective doping process. The core source / drains 330 , the HV Source / Drains 320 , the common memory source / drain 110c and the individual storage source / drains 110i For example, these may be of the n-type while the I / O source / drains 310 may be those of the p-type. Any of the selective doping methods may be performed, for example, by ion implantation with an arrayed mask, any other suitable selective doping method (other suitable selective doping methods), or any combination of the foregoing. The mask is patterned with a layout of the source / drains to be formed, and may be, for example, a photoresist mask, any other suitable mask (s), or any combination of the foregoing. It should be noted that the ion implantation may be performed, for example, while the first and second gate dielectric layers 1002 . 1202 by selecting an implantation energy high enough to allow ions of ion implantation through the gate dielectric layers 1002 . 1202 reach.

As through the cross-sectional view 1300J of the 13J illustrated on the core source / drains 330 , the HV source / drains 320 , the I / O source / drains 310 , the common memory source / drain 110c and the individual storage source / drains 110i (summarizing the source / drains) silicide pads 218 educated. The silicide pads 218 for example Nickel silicide, any other suitable silicide (other suitable silicides), or any combination of the above. In some embodiments, a method of forming the silicide pads comprises 218 : 1) forming a protective dielectric layer, which has the structure of 13I covered and lined; 2) patterning the protective dielectric layer to expose the source / drains; 3) performing a salicide process while the protective dielectric layer is disposed, and 4) removing the protective dielectric layer. In some embodiments, the removal is performed by an etching process or any other suitable removal process (other suitable removal processes). The etching process preferably removes material (eg, oxide) of the protective dielectric layer as compared to other material (eg, nitride or silicide) underlying and / or adjacent to the protective dielectric layer.

As also by the cross-sectional view 1300J of the 13J illustrates the first and second gate dielectric layers 1002 . 1202 (please refer 13I) structured. The patterning results in a lower HV gate dielectric layer 326l and a middle HV gate dielectric layer 326m formed under the upper HV gate dielectric layer 326u are stacked. The patterning further provides a bottom I / O gate dielectric layer 316l formed under the upper I / O gate dielectric layer 316U lies. The lower HV gate dielectric layer 326l becomes from the first gate dielectric layer 1002 formed and the middle HV gate dielectric layer 326m and the bottom I / O gate dielectric layer 316l are made of the second gate dielectric layer 1202 educated. The patterning can be done, for example, by an etching process or any other suitable patterning method (other suitable patterning methods). In some embodiments, the etching process is the same etching process as that with which the protective dielectric layer is removed when forming the silicide pads 218 is used.

As through the cross-sectional view 1300K of the 13K illustrates an etch-back layer 1328 formed the structure of the 13J covered. In some embodiments, the etch back layer is 1328 around a flowable, self-leveling material, so that gravity causes an upper surface of the etchback layer 1328 is leveled. In some embodiments, the etch back layer is 1328 an organic material, an antireflective coating (ARC), any other suitable material (other suitable materials), or any combination of the foregoing.

As through the cross-sectional view 1300L of the L illustrates an etching process is performed to the etch back 1328 and further around the core-gate hardmask 1310 (please refer 13K) , the HV gate hard mask 1314 (please refer 13K) , the control gate hardmask 1318 (please refer 13K) , the sacrificial gate hard mask 1322 (please refer 13K) and the I / O Gate Hardmask 1326 (please refer 13K) to remove. To abbreviate, the core-gate hardmask 1310 , the HV gate hard mask 1314 , the control gate hardmask 1318 , the sacrificial gate hard mask 1322 and the I / O Gate Hardmask 1326 collectively referred to as "the hard masks". The etching process is carried out with an etchant which is used for the etch-back layer 1328 the same or substantially the same etching rate as for the hard masks. Thereby, an upper surface of the back etching layer becomes 1328 and top surfaces of the hard masks are etched back together once the etch back layer 1328 is sufficiently etched to expose the hard masks. Further, the etchant has a low etch rate for the sacrificial core gate 1308 , the HV Victim Gate 1312 , the tax victim gate 1316 , the Pick Victims Gate 1320 and the I / O Victim Gate 1324 as compared to the etch-back layer 1328 and the hard masks.

As through the cross-sectional view 1300M of the 13M illustrates the etchback layer 1328 (please refer 13L) removed and instead of the etch back 1328 becomes a lower ILD layer 214l educated. The lower ILD layer 214l For example, it may be or include oxide, a low-k dielectric, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. In some embodiments, a method of removing the etch back layer 1328 an etching process or any other suitable removal method (other suitable removal methods). In some embodiments, a method comprises forming the bottom ILD layer 214l Depositing the lower ILD layer 214l by CVD, PVD, ALD, sputtering, any other suitable deposition method (other suitable deposition methods) or a combination of the above.

As through the cross-sectional view 1300N of the 13N illustrates planarization into the lower ILD layer 214l performed to a top surface of the lower ILD layer 214l together with upper surfaces of the core sacrificial gate 1308 , HV Victims Gate 1312 , the Tax Victim Gate 1316 , Pick Victims Gate 1320 or the I / O Victim Gate 1324 to planarize. The planarization can be done, for example, by a CMP or any other suitable planarization process (other suitable planarization process).

As through the cross-sectional view 1300O of the 13O illustrates, first victim gates are removed. The first sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 p-channel memory device, the control victim gate 1316 but not the pick-and-shoot gate 1320 (please refer 13N) , The first sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 an n-channel memory device, the selection victim gate 1320 but not the tax victim gate 1316 , Further, the first sacrificial gates include sacrificial gates which correspond to n-channel semiconductor devices and which correspond to the control and selection sacrificial gates 1316 . 1320 are adjacent. In some embodiments, the first sacrificial gates include the core sacrificial gate 1308 (please refer 13N) , the HV Victim Gate 1312 (please refer 13N) and the Pick Victims Gate 1320 , The removal leads to first gate openings 1330 instead of the sacrificial gate electrodes removed. The removal may be accomplished by, for example, a selective etching process, any other suitable removal process (other suitable removal processes), or any combination of the foregoing. In some embodiments, the selective etching comprises: 1) forming a mask on the structure of 13N ; 2 ) Performing an etching process in the sacrificial gates which are not covered by the mask; and 3) subsequently removing the mask. The mask has a layout of sacrificial gates to be removed, and may be or include, for example, a photoresist mask, any other suitable mask (s), or any combination of the foregoing.

As through the cross-sectional view 1300P of the 13P illustrated in the first gate openings 1330 (please refer 13O) Metal gate electrodes having n-type work functions (hereinafter referred to as n-type metal gate electrodes) are formed. For example, the n-type work function may be: 1) a work function within about 0.1 eV, 0.2 eV, or 0.4 eV of a work function for n-type polycrystalline silicon; 2) a work function of less than about 4.0 eV, 4.2 eV or 4.4 eV; 3) a work function of about 3.5 eV to 4.4 eV, 4.0 eV to 4.4 eV or 3.8 eV to 4.5 eV; 4) any other suitable n-type work function; or 5) any combination of the foregoing. Further, the n-type metal gate electrodes may be or include, for example, hafnium, zirconium, titanium, tantalum, aluminum, any other suitable n-type work function metal (s), or any combination of the foregoing. In some embodiments, the n-type metal gate electrodes include a core-gate electrode 334 , an HV gate electrode 324 and a selection gate electrode 120 , The core gate electrode 334 , the HV gate electrode 324 and the selection gate electrode 120 fill the first gate openings 1330 appropriately on the core pan 328 , the HV tub 318 and the selection gate pan 108 ,

In some embodiments, a method of forming the n-type metal gate electrodes comprises forming a conductive layer having the structure of 13O covered and also the first gate openings 1330 crowded. The conductive layer is or comprises n-type work function metal and may be formed, for example, by CVD, PVD, electroless plating, electroplating, any other suitable growth or deposition method (other suitable growth or deposition methods), or any combination of the foregoing , Subsequently, a planarization is performed in the conductive layer until the lower ILD layer 214l is reached. The planarization can be performed, for example, by a CMP or any other suitable planarization process (other suitable planarization techniques).

As through the cross-sectional view 1300Q of the 13Q illustrates, second victim gates are removed. The second sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 an n-channel memory device, the control victim gate 1316 (please refer 13N) but not the pick-and-shoot gate 1320 (please refer 13N) , The second sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 a p-channel memory device, the selection victim gate 1320 but not the tax victim gate 1316 , Further, the second sacrificial gates include sacrificial gates which correspond to p-channel semiconductor devices and which correspond to the control and selection sacrificial gates 1316 . 1320 are adjacent. In some embodiments, the second sacrificial gates include the sacrificial I / O gate 1324 (please refer 13N) and the tax victim gate 1316 , The removal leads to second gate openings 1332 instead of the sacrificial gate electrodes removed, and may be performed, for example, as related to 13O described.

As through the cross-sectional view 1300R of the 13R illustrated in the second gate openings 1332 (please refer 13Q) Metal-gate electrodes with p-type work functions (hereinafter referred to as p-type metal gate electrodes) are formed. The work function of the p-type may be, for example: 1) a work function within about 0.1 eV, 0.2 eV or 0.4 eV of a p-type polycrystalline work function; 2) a work function greater than about 4.8 eV, 5.0 eV or 5.2 eV; 3) a work function of about 4.8 eV to 5.2 eV, 5.0 eV to 5.4 eV or 4.6 eV to 5.6 eV; 4) any other suitable p-type work function, or 5) any combination of the foregoing. The p-type metal gate electrodes may be, for example, ruthenium, palladium, platinum, cobalt, nickel, titanium aluminum nitride, tungsten carbonitride, any other suitable metal (other suitable metals) having p-type work function, or any combination of the foregoing , In some embodiments, the p-type metal gate electrodes include a control gate electrode 114 and an I / O gate electrode 314 , The control gate electrode 114 and the I / O gate electrode 314 fill the second gate openings 1332 corresponding to the control gate pan 106 and the I / O pan 308 ,

In some embodiments, a method of forming the p-type metal gate electrodes comprises forming a conductive layer having the structure of 13Q covered and also the second gate openings 1332 crowded. The conductive layer is or comprises p-type work function metal and may be formed, for example, by CVD, PVD, electroless plating, electroplating, any other suitable growth or deposition method (other suitable growth or deposition methods), or any combination of the foregoing , Subsequently, a planarization is performed in the conductive layer until the lower ILD layer 214l is reached. The planarization can be performed, for example, by a CMP or any other suitable planarization process (other suitable planarization techniques).

As through the cross-sectional view 1300S of the 13S illustrates an upper ILD layer 214u formed the structure of the 13R covered, and with an upper surface that is planar or largely planar. The top ILD layer 214u For example, it may be or include oxide, a low-k dielectric, any other suitable dielectric (other suitable dielectrics), or any combination of the foregoing. Furthermore, the upper ILD layer 214u for example, by depositing the upper ILD layer 214u and then performing planarization in the top surface of the top layer 214u be formed. The deposition can be carried out, for example, by CVD, PVD, sputtering, any other suitable deposition method (other suitable deposition methods), or a combination of the above. The planarization can be performed, for example, by a CMP or any other suitable planarization process (other suitable planarization techniques).

As also by the cross-sectional view 1300S of the 13S illustrated, vias become 216 formed through the upper ILD layer 214u and the lower ILD layer 214l to the silicide pads 218 , the control gate electrode 114 , the selection gate electrode 120 , the core gate electrode 334 , the HV gate electrode 324 , the I / O gate electrode 314 or any combination of the foregoing. The vias 216 For example, they can be formed by patterning the top ILD layer 214u and the lower ILD layer 214l with a layout of the vias 216 to define a plurality of vias, and then filling the vias with metal, any other suitable conductive material (other suitable conductive materials), or any combination of the foregoing.

As indicated above 13A to 13S Alternatives to 14A to 14I so that the procedure from the steps of 12 can go to: 1) the steps of 13A to 13S or 2 ) the steps of 14A to 14I , 13A to 13S describe first embodiments of the method, which can be applied, for example, to the structure of 3A to build. 14A to 14I describe second embodiments of the method, which can be applied, for example, to the structure of 3B to build. The second embodiments are variants of the first embodiments in which the structuring in 13A and the third gate dielectric layer 1302 in 13B be omitted. In addition, the core dielectric layer become 336 and upper HV, control, select, and I / O gate dielectric layers 326u, 118u, 122u, 316U be after the removal of the victim gates in 13O and 13Q educated.

As through the cross-sectional view 1400A of the 14A illustrates the sacrificial gate layer 1304 and the gate hardmask layer 1306 formed, stacked on the structure of 12 , The sacrificial gate layer 1304 and the gate hardmask layer 1306 can be formed, for example, as with respect to 13B described.

As through the cross-sectional view 1400B of the 14B illustrates become the first and second gate dielectric layers 1002 . 1202 , the charge trapping layer 116 , the sacrificial gate layer 1304 (please refer 14A) and the gate hardmask layer 1306 (please refer 14A) structured. Further, the first and second source / drain extensions become 204a . 204b , the core, HV and I / O source / drains 330, 230, 310 and the common and individual storage source / drains 110c . 110i educated. In addition, the gate spacers 208 and the additional spacers 210 educated. The patterning and the forming can be done, for example, by the steps described in relation to FIG 13C to 13I illustrated and described.

As through the cross-sectional view 1400C of the 14C illustrates the silicide pads 218 on the core, HV and I / O source / drains 330, 230, 310 and the common and individual storage source / drains 110c . 110i (summarized on the source / drains). The silicide pads 218 can be formed, for example, as with respect to 13J described. In some embodiments, a method of forming the silicide pads comprises 218 : 1) forming a protective dielectric layer, which has the structure of 14B covered and lined; 2) patterning the protective dielectric layer to expose the source / drains; 3) performing a salicide process while the protective dielectric layer is disposed, and 4) removing the protective dielectric layer. In some embodiments, the removal is performed by an etching process or any other suitable removal method (other suitable removal methods).

As also by the cross-sectional view 1400C of the 14C illustrates the first and second dielectric layers 1002 . 1202 (please refer 14B) structured. The patterning results in the lower HV gate dielectric layer 3261 and the middle HV gate dielectric layer 326m formed, stacked under the HV Victim Gate 1312 , The patterning further results in the bottom I / O gate dielectric layer 316l which is under the I / O victim gate 1324 and a dummy gate dielectric layer 1402 formed under the core sacrificial gate 1308 lies. The patterning may be performed, for example, by an etching process or any other suitable patterning process (other suitable patterning methods). In some embodiments, the etching process is the same etching process as that with which the protective dielectric layer is removed when forming the silicide pads 218 is used.

As through the cross-sectional view 1400D of the 14D illustrate the core, HV, control, select, and I / O gate hardmask 1310, 1314, 1318, 1322, 1326 (please refer 14C) Further, upper surfaces of the core, HV, control, select, and I / O victim gates are removed 1308 . 1312 . 1316 . 1320 . 1324 planarized together. The removal and joint planarization may be performed, for example, by the steps relating to 13K to 13N illustrated and described.

As through the cross-sectional view 1400E of the 14E illustrates, first victim gates are removed. The first sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 p-channel memory device, the control victim gate 1316 but not the pick-and-shoot gate 1320 (please refer 14D) , The first sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 an n-channel memory device, the selection victim gate 1320 but not the tax victim gate 1316 , Further, the first sacrificial gates include sacrificial gates which correspond to n-channel semiconductor devices and which correspond to the control and selection sacrificial gates 1316 . 1320 are adjacent. For example, the first sacrificial gates may further include the core and HV sacrificial gates 1308 . 1312 (please refer 14D) include. In embodiments where the core sacrificial gate 1308 is removed, also becomes a part of the dummy gate dielectric layer 1402 (please refer 14D) removed, under the core sacrificial gate 1308 which results in a residual dielectric layer 338 leads. The removal leads to the first gate openings 1330 instead of the remote victim gates and can be performed, for example, as to 13O described.

As through the cross-sectional view 1400F of the 14F illustrated in the first gate openings 1330 (please refer 14D) Formed n-type metal gate electrodes and gate dielectric layers. The gate dielectric layers wrap around undersurfaces of the n-type metal gate electrodes and may be, for example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics), or any combination of the foregoing or include. For example, the n-type metal gate electrodes may be those as described with respect to FIG 13P described. In some embodiments, the n-type metal gate electrodes include the core, HV, and select gate electrodes 334 . 324 . 120 while the gate dielectric layers are the core-gate dielectric layer 336 , the upper HV gate dielectric layer 326u and the top select gate dielectric layer 122U include.

In some embodiments, a method of forming the n-type metal gate electrodes and the gate dielectric layers comprises forming a third gate dielectric layer having the structure of 14E covered and lined, and then forming a conductive layer over the third gate dielectric layer. The conductive layer may be formed, for example, by CVD, PVD, electroless plating, electroplating, any other suitable growth or deposition method (other suitable growth or deposition methods), or any combination of the foregoing. The third gate dielectric layer may be formed, for example, by CVD, PVD, sputtering, any other suitable deposition method (other suitable deposition methods), or any combination of the foregoing. Subsequently, a planarization is performed in the conductive layer and the third gate dielectric layer until the lower ILD layer 214l is reached. The planarization can be performed, for example, by a CMP or any other suitable planarization process (other suitable planarization techniques).

As through the cross-sectional view 1400G of the 14G illustrates, second victim gates are removed. The second sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 an n-channel memory device, the control victim gate 1316 (please refer 14D) but not the pick-and-shoot gate 1320 (please refer 14D) , The second sacrificial gates, in some embodiments, include the control and selection sacrificial gates 1316 . 1320 a p-channel memory device, the selection victim gate 1320 but not the tax victim gate 1316 , Further, the first sacrificial gates include sacrificial gates which correspond to p-channel semiconductor devices and which correspond to the control and selection sacrificial gates 1316 . 1320 are adjacent. For example, the first victim gates may also have the I / O victim gate 1324 (please refer 14D) include. In embodiments where the core sacrificial gate 1308 is removed, also becomes a part of the dummy gate dielectric layer 1402 (please refer 14D) removed, under the core sacrificial gate 1308 which results in a residual dielectric layer 338 leads. The removal leads to second gate openings 1332 instead of the sacrificial gate electrodes removed, and may be performed, for example, as related to 13Q described.

As through the cross-sectional view 1400H of the 14H illustrated in the second gate openings 1332 (please refer 14G) Formed p-type metal gate electrodes and gate dielectric layers. The gate dielectric layers wrap around sub-sides of the p-type metal gate electrodes and may be, for example, hafnium oxide, alumina, silicon nitride, any other suitable high-k dielectric (other suitable high-k dielectrics), or any combination of the foregoing or include. For example, the p-type metal gate electrodes may be those as described with respect to FIG 13R described. In some embodiments, the p-type metal gate electrodes include the I / O and control gate electrodes 314 . 114 while the gate dielectric layers are the top I / O gate dielectric layer 316U and the upper control gate dielectric layer 118u include.

In some embodiments, a method of forming the p-type metal gate electrodes and the additional gate dielectric layers comprises forming a fourth gate dielectric layer that has the structure of the 14G and then forming a conductive layer over the fourth gate dielectric layer. The conductive layer may be formed, for example, by CVD, PVD, electroless plating, electroplating, any other suitable growth or deposition method (other suitable growth or deposition methods), or any combination of the foregoing. The fourth gate dielectric layer may be formed, for example, by CVD, PVD, sputtering, any other suitable deposition method (other suitable deposition methods), or any combination of the foregoing. Subsequently, a planarization is performed in the conductive layer and the fourth gate dielectric layer until the lower ILD layer 214l is reached. The planarization can be performed, for example, by a CMP or any other suitable planarization process (other suitable planarization techniques).

As through the cross-sectional view 1400i of the 14I illustrates an upper ILD layer 214u formed the structure of the 14H covered, and with an upper surface that is planar or largely planar. In addition, vias become 216 formed through the upper ILD layer 214u and the lower ILD layer 214l to the silicide pads 218 , the control gate electrode 114 , the selection gate electrode 120 , the core gate electrode 334 , the HV gate electrode 324 , the I / O gate electrode 314 or any combination of the foregoing. The top ILD layer 214u and the vias 216 can be formed, for example, as with respect to 13S described.

As stated above, the victim gates (eg the tax victim gate 1316 in 13C and 14B) after forming the source / drains (eg the common memory source / drains 110c) through gate electrodes (eg the control gate electrode 114 ) replaced. Therefore, the doping process used to form the source / drains does not affect the Work functions of the gate electrodes. In addition, since the sacrificial gates are replaced by the gate electrodes, the sacrificial gates may be undoped polysilicon or any other suitable material that does not depend on a doping process. Therefore, the doping profiles are subject to the semiconductor substrate 104 (eg, doping profiles of the control and select gate wells 106 . 108 ) no damage from a doping process in forming the sacrificial gates. Further, because the gate electrodes are metal, the doping profiles are in the semiconductor substrate 104 no damage from a doping process in forming the gate electrodes. Further, since the gate electrodes are metal and they may be on high-k dielectrics (eg, the upper control gate dielectric layer 118 ), the gate electrodes are scaled down for advanced process nodes, eg for 28mm, 20nm and smaller process nodes.

Even though 4 to 7 . 8A . 8B . 9 to 12 . 13A to 13S and 14A to 14I the replacement of Pick Victims Gate 1320 (see eg 13N) by metal, it should be noted that the selection victim gate 1320 in other embodiments does not need to be replaced. In some such other embodiments, the selection victim gate becomes 1320 Made of a conductive material and remains in a finished integrated circuit. The conductive material may include, for example, n-type or p-type polysilicon, or any other suitable conductive material. In some embodiments, where the control gate electrode 120 (see eg 13R) a metal having a work function of a first doping type (eg, n-type or p-type) is or will become the selection sacrificial gate 1320 formed from doped polysilicon with the first doping type or any other suitable material having a work function of the first doping type. In other embodiments, where the control gate electrode 120 (see eg 13R) a metal having a work function of a first doping type (eg, n-type or p-type) is or will become the selection sacrificial gate 1320 formed from doped polysilicon with a second doping type or any other suitable material having a work function of the second doping type, wherein the second doping type is opposite to the first doping type.

Even though 4 to 7 . 8A . 8B . 9 to 12 . 13A to 13S and 14A to 14I the replacement of Pick Victims Gate 1320 (see eg 13N) and the Tax Victim Gate 1316 (see eg 13N) Through various metals, the Pick Victims Gate 1320 and the tax victim gate 1316 be replaced by the same metal in other embodiments. For example, if the tax victim gate 1316 is replaced by metal with an n-type work function, the selection sacrificial gate 1320 also be replaced by the metal with a work function of the n-type. If, as another example, the tax victim gate 1316 is replaced by metal with a p-type work function, the selection sacrificial gate 1320 also be replaced by the metal with a work function of the p-type.

Referring to 15 , there is a flow chart of some embodiments of the method of 4 to 7 . 8A . 8B . 9 to 12 . 13A to 13S and 14A to 14I provided. For example, the method may be used to form a memory cell having a large operating window and a high erasing speed.

at 1502 an insulating structure is formed, which extends into a semiconductor substrate. The isolation structure separates and separates a storage zone, an I / O zone, a core zone, and an HV zone. See for example 4 ,

at 1504 A deep well is formed in the storage zone and the HV zone. See for example 5 ,

at 1506 For example, a core well, an HV well, a select gate well, and an I / O well are formed, respectively, in the core zone, the HV zone, the storage zone, and the I / O zone. See for example 6 ,

at 1508 For example, a control gate well is formed in the memory zone adjacent to the select gate well. See for example 7 ,

at 1510 Gate piles are formed, corresponding to the core pan, the HV pan, the control gate pan, the selection gate pan, and the I / O pan. Each of the gate stacks includes a gate hardmask, a sacrificial gate, and a gate dielectric layer. A control gate stack of the gate stacks also includes a charge trapping layer. See for example 8th to 12 and 13A to 13C or 8th to 12 . 14A and 14B ,

at 1512 Gate spacers are formed on sidewalls of the gate stack. See for example 13D or 14B ,

at 1514 are formed in the semiconductor substrate source / drain extensions, respectively over the core well, the HV well, the control gate well, the selection gate well and the I / O tray. See for example 13E to 13G or 14B ,

at 1516 additional spacers are formed on side walls of the gate spacers. See for example 13H or 14B ,

at 1518 In the semiconductor substrate, source / drains are formed, which adjoin the source / drain extensions accordingly. See for example 13I or 14B ,

at 1520 silicide pads are formed on the source / drains. See for example 13J or 14C ,

at 1522 the gate hard masks of the gate stacks are removed. See for example 13K and 13L or 14D ,

at 1524 The sacrificial gate electrodes are replaced by metal gate electrodes. A sacrificial gate electrode on the control gate well is replaced by a metal control gate electrode having a work function of a first doping type, wherein the first doping type is a second doping type of source / drain on the control gate. Tub is opposite. See for example 13M to 13R or 14E to 14H ,

In embodiments in which the memory cell is an n-channel memory cell, the source / drains on the control gate well are those of the n-type and the metal control gate electrode has a p-type work function. By using metal with a p-type work function for the metal control gate electrode, the metal control gate electrode has a high work function. The high work function results in a difficult electron gate re-injection. The difficult electron gate back injection allows the application of a high erase voltage to achieve a high erase rate. Further, the difficult electron gate back injection results in a low erase saturation level and a large operating window. The operating window is the voltage range from the control gate threshold voltage in a programmed state to the control gate threshold voltage in an erased state, and a large operating window makes the memory cell more flexible for process variations and noise in read operations. Additionally, the metal of the control and select gate electrodes, along with control and select high-k gate dielectrics, allows the memory cell to be scaled down for advanced process nodes, for example, 28nm, 20nm - and smaller process nodes.

at 1526 a connection structure is formed on the metal gate electrodes. See for example 13S or 14I ,

Although the schedule 1500 of the 15 is illustrated and described herein as a series of acts or events, it is to be understood that the illustrated order of such acts or events is not to be construed as limiting. For example, some steps may be in other orders and / or concurrent with steps or events other than those illustrated and / or described herein. Further, not all illustrated steps may be required to implement one or more aspects or embodiments of the description herein, and one or more of the steps depicted herein may be performed in one or more separate steps and / or phases.

In some embodiments, the present application provides an IC comprising: a semiconductor substrate and a memory cell on the semiconductor substrate, wherein the memory cell comprises a control gate electrode, a select gate electrode, a charge trap layer, and a common source / drain, wherein the common source / drain is in the semiconductor substrate and has a first doping type, wherein the control gate electrode and the selection gate electrode are over the semiconductor substrate and are respectively on opposite sides of the common source / drain, the control Gate electrode overlying the charge trapping layer and comprising a metal having a work function of a second doping type and wherein the second doping type is opposite to the first doping type. In some embodiments, the first doping type is the n-type and the second doping type is the p-type. In some embodiments, the first doping type is the p-type and the second doping type is the n-type. In some embodiments, the work function of the metal exceeds about 5.0 electron volts. In some embodiments, the metal comprises ruthenium, palladium, platinum, cobalt, nickel, titanium aluminum nitride, tungsten carbonitride or any combination of the foregoing. In some embodiments, the select gate electrode comprises a second metal having a work function of the first doping type. In some embodiments, the second metal comprises hafnium, zirconium, titanium, tantalum, aluminum, or any combination of the foregoing. In some embodiments, the memory cell further includes a control gate dielectric layer overlying a bottom surface of a control gate electrode, the control gate dielectric layer overlying the charge trapping layer, and wherein the control gate dielectric layer Side walls of the control gate electrode and a lower surface of the control gate electrode lines. In some embodiments, the select gate electrode comprises polysilicon. In some embodiments, the memory cell further includes a high-k control gate dielectric layer and a high-k select gate dielectric layer, the first doping type being n-type, the second doping type being p-type, wherein the high-k control gate dielectric layer is under the control gate electrode, between the charge trapping layer and the control gate electrode, with the high-k select gate dielectric layer under the select gate electrode and wherein the selection gate electrode comprises a metal having a work function of the first doping type.

In some embodiments, the present application provides a method of making an IC, the method comprising: forming a charge trapping layer on a semiconductor substrate; Forming a sacrificial gate layer covering the charge trapping layer; Patterning the sacrificial gate layer to form a control sacrificial gate overlying the charge trapping layer and also to form a select victim gate that is adjacent to the charge trapping layer and the sacrificial control gate ; Forming a common source / drain in the semiconductor substrate, between the control and select victim gates, the common source / drain having a first doping type; and replacing the control sacrificial gate by a control gate electrode, wherein the control gate electrode comprises a metal having a work function of a second doping type and wherein the second doping type is opposite to the first doping type. In some embodiments, the first doping type is n-type, with the second doping type being p-type. In some embodiments, the method further comprises: depositing a high-k dielectric layer covering the charge-trapping layer, wherein the sacrificial gate layer is formed over the high-k dielectric layer; and patterning the high-k dielectric layer to form a high-k control gate dielectric layer underlying the sacrificial control gate and further to form a high-k select gate dielectric layer lies under the Pick Victims Gate. In some embodiments, when replaced, the control sacrificial gate is replaced by the control gate electrode and a high-k control gate dielectric layer, where the high-k control gate dielectric layer is a bottom surface of the control gate. Electrode wrapped. In some embodiments, the method further comprises replacing the select victim gate with a select gate electrode, wherein the select gate electrode comprises a metal having a work function of the first doping type, wherein the work function of the first doping type is about 3.5 to 4.4 electron volts and wherein the work function of the second doping type is about 4.8 to 5.2 electron volts. In some embodiments, the semiconductor substrate includes a memory semiconductor zone and a peripheral semiconductor zone, wherein the control and select victim gates are formed on the memory semiconductor zone, and wherein the method further comprises: forming a gate dielectric layer that supports the memory Semiconductor zone and the peripheral semiconductor zone covered; Removing the gate dielectric layer from the peripheral semiconductor zone but not from the memory semiconductor zone, wherein the sacrificial gate layer is formed after removal and is formed to cover the peripheral and memory semiconductor regions over the gate dielectric layer and wherein structuring further forms a sacrificial gate on the peripheral semiconductor region; and replacing the sacrificial gate with a gate electrode, wherein the gate electrode comprises a metal having a work function of the first or second doping type. In some embodiments, the semiconductor substrate includes a memory semiconductor zone and a peripheral semiconductor zone, wherein the control and select victim gates are formed on the memory semiconductor zone, and wherein the method further comprises: forming a gate dielectric layer that supports the memory Covering the semiconductor zone and the peripheral semiconductor zone, wherein the sacrificial gate layer is formed so that it covers the peripheral and the memory semiconductor region over the gate dielectric layer, and wherein in structuring further a sacrificial gate on the peripheral semiconductor zone is formed ; and replacing the sacrificial gate with a gate electrode, wherein the gate electrode comprises a metal having a work function of the first or second doping type, and wherein when replaced, the gate dielectric layer is removed from the peripheral semiconductor zone.

In some embodiments, the present application provides another integrated circuit including: a semiconductor substrate and a memory cell including a pair of source / drain regions in the semiconductor substrate, and further comprising a control gate electrode, a data storage layer, and a control circuit. A gate dielectric layer stacked over the semiconductor substrate and between the source / drain regions, the source / drain regions having a first doping type, the control gate dielectric layer being between the data storage layer and the control gate electrode the control gate electrode having opposite sidewalls lined by the control gate dielectric layer, the control gate electrode comprising a metal having a work function of a second doping type and wherein the second doping type is opposite to the first doping type. In some embodiments, the first one is The n-type doping type wherein the work function of the metal exceeds about 5.0 electron volts. In some embodiments, the semiconductor substrate comprises a peripheral semiconductor zone and a memory semiconductor zone, wherein the memory cell is located on the memory semiconductor zone, and wherein the IC further comprises a semiconductor device on the peripheral semiconductor zone, wherein the semiconductor device comprises a metal gate electrode and a Gate dielectric layer and wherein the metal gate electrode overlying the gate dielectric layer.

In the foregoing, features of various embodiments are outlined so that those skilled in the art can better understand the aspects of the present disclosure. One skilled in the art will recognize that he may readily use the present disclosure as a basis for designing or modifying other methods and structures to accomplish the same purposes and / or obtain the same advantages as the embodiments presented herein. Those skilled in the art also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that it can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 62552149 [0001]

Claims (20)

Integrated circuit (IC), comprising: a semiconductor substrate; and a memory cell on the semiconductor substrate; wherein the memory cell comprises a control gate electrode, a selection gate electrode, a charge trapping layer and a common source / drain, wherein the common source / drain is located in the semiconductor substrate and has a first doping type, the control gate electrode and the select gate electrode overlying the semiconductor substrate and being respectively on opposite sides of the common source / drain, wherein the control gate electrode overlies the charge trapping layer and comprises a metal having a work function of a second doping type, and wherein the second doping type is opposite to the first doping type. IC after Claim 1 wherein the first doping type is n-type and the second doping type is p-type. IC after Claim 1 wherein the first doping type is the p-type and the second doping type is the n-type. The IC of any one of the preceding claims, wherein the work function of the metal exceeds about 5.0 electron volts. An IC according to any one of the preceding claims wherein the metal comprises ruthenium, palladium, platinum, cobalt, nickel, titanium aluminum nitride, tungsten carbonitride or any combination of the foregoing. An IC according to any one of the preceding claims, wherein the selection gate electrode comprises a second metal having a work function of the first doping type. IC after Claim 6 wherein the second metal comprises hafnium, zirconium, titanium, tantalum, aluminum or any combination of the foregoing. The IC of any one of the preceding claims, wherein the memory cell further comprises: a control gate dielectric layer overlying a bottom surface of a control gate electrode, the control gate dielectric layer overlying the charge trapping layer, and wherein the control gate dielectric layer includes sidewalls of the control gate electrode and a bottom surface of the control gate -Gate electrode lines. An IC according to any one of the preceding claims, wherein the selection gate electrode comprises polysilicon. The integrated circuit of claim 1, wherein the memory cell further comprises a high-k control gate dielectric layer and a high-k select gate dielectric layer, wherein the first doping type is n-type, wherein the second doping type is p-type Type, with the high-k control gate dielectric layer under the control gate electrode, between the charge-trapping layer and the control gate electrode, the high-k select gate dielectric layer being under the selection gate. Gate electrode and wherein the selection gate electrode comprises a metal having a work function of the first doping type. A method of manufacturing an integrated circuit (IC), the method comprising: Forming a charge trapping layer on a semiconductor substrate; Forming a sacrificial gate layer covering the charge trapping layer; Patterning the sacrificial gate layer to form a control sacrificial gate overlying the charge trapping layer and also to form a select victim gate that is adjacent to the charge trapping layer and the sacrificial control gate ; Forming a common source / drain in the semiconductor substrate, between the control and select victim gates, the common source / drain having a first doping type; and Replacing the control sacrificial gate by a control gate electrode, wherein the control gate electrode comprises a metal having a work function of a second doping type and wherein the second doping type is opposite to the first doping type. Method according to Claim 11 wherein the first doping type is the n-type and wherein the second doping type is the p-type. Method according to Claim 11 or 12 further comprising: depositing a high-k dielectric layer covering the charge-trapping layer, wherein the sacrificial gate layer is formed over the high-k dielectric layer; and patterning the high-k dielectric layer to form a high-k control gate dielectric layer underlying the sacrificial control gate and further to form a high-k select gate dielectric layer lies under the Pick Victims Gate. Method according to one of the preceding Claims 11 to 13 wherein, at replacement, the control sacrificial gate passes through the control gate and a high-k control gate dielectric layer is replaced, wherein the high-k control gate dielectric layer envelops a bottom surface of the control gate electrode. Method according to one of the preceding Claims 11 to 14 , further comprising: replacing the select victim gate by a select gate electrode, wherein the select gate electrode comprises a metal having a work function of the first doping type, wherein the work function of the first doping type is about 3.5 to 4.4 Electron volts and wherein the work function of the second doping type is about 4.8 to 5.2 electron volts. Method according to one of the preceding Claims 11 to 15 wherein the semiconductor substrate comprises a memory semiconductor zone and a peripheral semiconductor zone, wherein the control and selection sacrificial gates are formed on the memory semiconductor zone, the method further comprising: forming a gate dielectric layer comprising the memory semiconductor zone and covering the peripheral semiconductor zone; Removing the gate dielectric layer from the peripheral semiconductor zone but not from the memory semiconductor zone, wherein the sacrificial gate layer is formed after removal and is formed to cover the peripheral and memory semiconductor regions over the gate dielectric layer and wherein structuring further forms a sacrificial gate on the peripheral semiconductor region; and replacing the sacrificial gate with a gate electrode, wherein the gate electrode comprises a metal having a work function of the first or second doping type. Method according to one of the preceding Claims 11 to 16 wherein the semiconductor substrate comprises a memory semiconductor zone and a peripheral semiconductor zone, wherein the control and selection sacrificial gates are formed on the memory semiconductor zone, the method further comprising: forming a gate dielectric layer comprising the memory semiconductor zone and covering the peripheral semiconductor region, wherein the sacrificial gate layer is formed to cover the peripheral and memory semiconductor regions over the gate dielectric layer, and wherein structuring further forms a sacrificial gate on the peripheral semiconductor region; and replacing the sacrificial gate with a gate electrode, wherein the gate electrode comprises a metal having a work function of the first or second doping type, and wherein when replaced, the gate dielectric layer is removed from the peripheral semiconductor zone. Integrated circuit (IC), comprising: a semiconductor substrate; and a memory cell including a pair of source / drain regions in the semiconductor substrate, and further comprising a control gate electrode, a data storage layer, and a control gate dielectric layer stacked over the semiconductor substrate and between the source / drain regions; wherein the source / drain zones have a first doping type, wherein the control gate dielectric layer is between the data storage layer and the control gate electrode, wherein the control gate electrode has opposite sidewalls lined by the control gate dielectric layer, wherein the control gate electrode comprises a metal having a work function of a second doping type, and wherein the second doping type is opposite to the first doping type. IC after Claim 18 wherein the first doping type is n-type, wherein the work function of the metal exceeds about 5.0 electron volts. IC after Claim 18 or 19 wherein the semiconductor substrate comprises a peripheral semiconductor zone and a memory semiconductor zone, wherein the memory cell is located on the memory semiconductor zone, and wherein the IC further comprises: a semiconductor device on the peripheral semiconductor zone, wherein the semiconductor device comprises a metal gate electrode and a semiconductor device Gate dielectric layer, wherein the metal gate electrode overlying the gate dielectric layer.

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