DE102018108431A1 - MIXING ACCURACY COMPROMISE METHOD CIRCUIT ARRANGEMENT IN SPECIALIZED PROCESSING BLOCKS - Google Patents

Abstract

The present embodiments relate to integrated circuits having a circuit that efficiently executes composite precision floating point arithmetic operations. Such circuitry may be implemented in specialized processing blocks. The specialized processing blocks may include configurable interconnect circuitry to support a variety of different usage modes. For example, the specialized processing blocks may optionally include fixed point addition, floating point addition, fixed point multiplication, floating point multiplication, the sum of two multiplications in a first floating point precision, with or without conversion to a second floating point precision, and the latter followed by a subsequent addition in the second floating point inaccuracy, to implement just to name a few. In some embodiments, two or more specialized processing blocks may be arranged in a cascade chain and together perform more complex operations, such as a recursive dot product of two floating-point vectors with a first floating-point precision and the output of the dot product in a second floating point precision.

Description

Field of engineering

The present embodiments relate to integrated circuits, and more particularly to mixed precision floating point arithmetic circuitry in specialized processing blocks in an integrated circuit.

background

As applications become more complex, specialized processing blocks are increasingly being incorporated into integrated circuits. Such specialized processing blocks may be partially or fully hardwired to perform one or more specific tasks, such as a logical or mathematical operation. A specialized processing block may also include one or more specialized structures, such as an array of configurable storage elements.

Examples of structures that are often implemented in such specialized processing blocks include: multipliers, adders, accumulators, arithmetic logic units (ALUs), barrel shifters, various memory elements or memory circuits, such as first-in-first Out (FIFO) circuits, Last In First Out (LIFO) circuits, Serial In Parallel Out (SIPO) shift register circuits, Parallel In Serial Out (PISO) shift register circuits, Random access memory (RAM) circuits, read only memory (ROM) circuits, content addressable memory (CAM) circuits and register files, logical AND, logical NAND, logical OR, logical NOR arrays etc. or combinations thereof.

One particularly useful type of specialized processing block, sometimes referred to as a Digital Signal Processing Block (DSP Block), can be used to process digital signals such as video signals, audio signals, and so forth. Such blocks are often referred to as multiply-accumulate (MAC) blocks because they include structures for performing multiplication operations and sums and / or accumulations of multiplication operations.

Integrated circuits, such as programmable integrated circuits, often include specialized processing blocks. Each of these specialized processing blocks includes multipliers, adders, and registers, as well as programmable connectors (eg, multiplexers) that enable the different configuration of the various components of the block.

Traditionally, the arithmetic operators (adders and multipliers) in such specialized processing blocks have heretofore been fixed-point operators. If floating-point operators were needed, they would be created outside of the specialized processing block by means of programmable general purpose logic of the device or by a combination of the fixed-point operators within the specialized processing block with additional logic in the multipurpose programmable logic.

list of figures

• 1 ein Diagramm einer exemplarischen integrierten Schaltung, wie beispielsweise einer programmierbaren integrierten Schaltung, nach einigen Ausführungsformen;
• 2 ein Diagramm eines exemplarischen spezialisierten Verarbeitungsblocks zum Ausführen von Mischgenauigkeitsgleitkommaoperationen nach einigen Ausführungsformen;
• 3 ein Diagramm zweier exemplarischer spezialisierter Verarbeitungsblöcke, die in einer Kaskadenkette angeordnet sind und zusammen eine erste Stufe einer rekursiven Skalarproduktoperation ausführen, nach einigen Ausführungsformen;
• 4 ein Diagramm zweier exemplarischer spezialisierter Verarbeitungsblöcke, die in einer Kaskadenkette angeordnet sind und zusammen eine erste Stufe einer rekursiven Skalarproduktoperation und einer Akkumulationsoperation ausführen, nach einigen Ausführungsformen;
• 5 ein Diagramm von sechs exemplarischen spezialisierten Verarbeitungsblöcken, die in einer Kaskadenkette angeordnet sind und ein Skalarprodukt zweier Vektoren von Gleitkommazahlen erzeugen, nach einigen Ausführungsformen;
• 6 ein Diagramm von vier exemplarischen spezialisierten Verarbeitungsblöcken, die in einer Kaskadenkette angeordnet sind und ein rekursives Skalarprodukt zweier Vektoren von Gleitkommazahlen und eine Akkumulation des Ergebnisses ausführen, nach einigen Ausführungsformen;
• 7 ein Ablaufdiagramm exemplarischer Operationen zum Betreiben einer integrierten Schaltung, die ein Skalarprodukt eines ersten und eines zweiten Vektors erzeugt, nach einigen Ausführungsformen;
• 8 eine Querschnittsansicht eines magnetischen Datenspeichermediums, das mit einem Satz maschinenausführbarer Anweisungen zum Konfigurieren einer integrierten Schaltung zum Erzeugen eines Skalarprodukts eines ersten und eines zweiten Vektors codiert ist, nach einigen Ausführungsformen;
• 9 eine Querschnittsansicht eines optisch lesbaren Datenspeichermediums, das mit einem Satz maschinenausführbarer Anweisungen zum Konfigurieren einer integrierten Schaltung zum Erzeugen eines Skalarprodukts eines ersten und eines zweiten Vektors codiert ist, nach einigen Ausführungsformen.

Show it:

• 1 a diagram of an exemplary integrated circuit, such as a programmable integrated circuit, according to some embodiments;
• 2 5 is a diagram of an exemplary specialized processing block for performing compound precision floating point operations, in accordance with some embodiments;
• 3 Figure 4 is a diagram of two exemplary specialized processing blocks arranged in a cascade chain and together performing a first stage of recursive dot product operation, according to some embodiments;
• 4 3 is a diagram of two exemplary specialized processing blocks arranged in a cascade chain and together performing a first stage of a recursive dot product operation and an accumulation operation, according to some embodiments;
• 5 5 is a diagram of six exemplary specialized processing blocks arranged in a cascade chain that produce a scalar product of two floating point vector vectors, according to some embodiments;
• 6 4 is a diagram of four exemplary specialized processing blocks arranged in a cascade chain that execute a recursive dot product of two floating-point vector vectors and an accumulation of the result, according to some embodiments;
• 7 5 is a flowchart of exemplary operations for operating an integrated circuit that generates a scalar product of a first and a second vector, according to some embodiments;
• 8th a cross-sectional view of a magnetic data storage medium encoded with a set of machine-executable instructions for configuring an integrated circuit to produce a scalar product of a first and a second vector, according to some embodiments;
• 9 12 is a cross-sectional view of an optically readable data storage medium encoded with a set of machine-executable instructions for configuring an integrated circuit to produce a scalar product of a first and a second vector, according to some embodiments.

Detailed description

The present embodiments set forth herein relate to integrated circuits, and more particularly to mixed precision floating point arithmetic circuitry in specialized processing blocks in an integrated circuit.

Floating-point numbers are commonplace in representing real numbers in scientific notation in computing systems and are designed to cover a large numerical bandwidth and various accuracy requirements. The on 29th of August 2008 published standard IEEE 754 or standard ANSI / IEEE 754 - 2008 is commonly used for floating-point numbers. A floating-point number includes three distinct parts: a sign, a mantissa, sometimes referred to as a signifier, and an exponent. Each of these parts can be represented by a binary number and in the format of the IEEE standard 754 have different bit sizes depending on the accuracy. For example, a single-precision floating-point number may require 32 bits, which are distributed as follows: a sign bit (bits 31 ), eight exponent bits (bits [30:23]) and 23 mantissa bits (bits [22: 0]). A double-precision floating-point number may require 64 bits and a sign bit (bits 63 ), 11 exponent bits (bits [62:52]) and 52 mantissa bits (bits [51: 0]). A half-precision floating-point number may require 16 bits and a sign bit (bits 15 ), 5 exponent bits (bits [14:10]) and 10 mantissa bits (bits [9: 0]).

According to the IEEE standard 754 For example, a mantissa may also have additional bits. A mantissa with extra bits is sometimes referred to as an extended mantissa. For example, an extended single-precision mantissa may have five extra bits (ie, a single-precision extended mantissa may consist of 28 bits instead of 23 bits). The last three bits added to the right of the Least Significant Bit (LSB) represent a round, a guard, and a sticky bit.

Round and guard bits can provide additional accuracy in performing arithmetic operations. For example, dividing a mantissa by a "1" in the least significant bit position by two may result in the round bit becoming "1". An additional division by two can cause the guard bit to become "1". In this way, the Round and Guard bits allow for the representation of numbers that are smaller than a mantissa without these extra bits would be able to accurately represent. The sticky bit can record any bits of significance "1" which are shifted by performing a logical OR operation with the round and guard bits beyond the precision of the mantissa.

If desired, two bits may be added beyond the Most Significant Bit (MSB) position and absorb any overflow generated by a floating point arithmetic operation.

The sign of a floating-point number according to the IEEE standard 754 is represented by a single bit, where a zero denotes a positive number and a one denotes a negative number.

The exponent of a floating-point number is preferably an unsigned binary number ranging from 0 to 255 in the single precision format. To represent a very small number, negative exponents must be used. Thus, the exponent preferably has a negative bias. For single-precision floating-point numbers, the bias is preferably -127. For example, a value of 140 for the exponent actually ( 140 - 127 ) = 13, and a value of 100 represents ( 100 - 127 ) = -27. For double and half precision floating-point numbers, the exponent bias is preferably -1023 and -15, respectively.

As discussed above, according to the IEEE standard 754 the mantissa is a normalized number (ie it does not have leading zeros and represents the precision component of a floating-point number). Since the mantissa is stored in binary format, the leading bit may be either a 0 or a 1, and for a normalized number, it will always be a 1. Thus, in a system in which numbers are always normalized, the leading bit need not be stored and can be implied, effectively conferring an additional precision bit to the mantissa.

Specialized processing blocks that perform arithmetic operations often involve a plurality of multipliers, adders, registers, and programmable connectors (eg, multiplexers) that enable the various components of the specialized processing block to be designed in different ways. Traditionally, the arithmetic operators in such specialized processing blocks have heretofore been fixed-point operators.

If floating-point operators were needed, they would be created outside of the specialized processing block (eg, by additional logic in the integrated circuit or by a combination of the fixed-point operators within the specialized processing block with additional logic in the integrated circuit).

However, as applications become more complex, floating-point operators are increasingly used. In addition, different applications may have different accuracy requirements. For example, some applications may require the use of double precision floating point arithmetic operators, while for other applications the use of half precision floating point arithmetic operators is sufficient. Consequently, it is desirable to provide a specialized processing block that is adaptable to floating point operations with different accuracies (eg, according to the IEEE standard 754 To efficiently implement half-precision and / or single-precision floating-point operations and / or double-precision floating-point operations and / or quad-precision floating-point operations and / or eight-precision floating-point operations).

Those skilled in the art will recognize that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, a detailed description of known operations has been omitted so as not to unnecessarily obscure the present embodiments.

1 shows a diagram of an exemplary integrated circuit, such as a programmable integrated circuit 100 , according to some embodiments.

The programmable integrated circuit 100 may be an input / output circuitry 102 for driving signals from the programmable integrated circuit 100 out and receive signals from other devices. The input / output circuitry 102 may include conventional input / output circuitry, serial data transceiver circuitry, differential receiver / transmitter circuitry, or other circuitry used to connect one integrated circuit to another integrated circuit.

As shown, the input / output circuitry 102 may be around the periphery of the programmable integrated circuit 100 be arranged around. On request, the programmable integrated circuit 100 have an otherwise arranged input / output circuitry 102. For example, the input / output circuitry 102 form one or more input / output circuit arrays that may be located anywhere on the programmable integrated circuit (eg, evenly distributed across the width of the programmable integrated circuit). If desired, the input / output circuitry 102 may form one or more rows of input / output elements (eg, distributed over the height of the programmable integrated circuit). Alternatively, the input / output circuitry 102 Form islands of input / output elements that may be distributed over the area of the programmable integrated circuit or bundled in selected areas.

Vertical connection resources 140 and horizontal connection resources 150 , such as global and local vertical and horizontal conductive lines and buses, can be used to send signals to the programmable integrated circuit 100 forward. The vertical and horizontal connection resources 140 and 150 include conductive lines and programmable connections between respective conductive lines and are therefore sometimes referred to as programmable interconnects, configurable connections or configurable interconnect circuitry.

Programmable logic areas may include programmable components, such as digital signal processing circuitry 120 and a memory circuitry 130 , which may both be organized in specialized blocks, or other combinatorial and sequential logic circuitry used in logic array blocks 110 is organized. The programmable logic areas may be configured to perform a custom logic function. If desired, the digital signal processing circuitry 120 and the memory circuitry 130 have limited configurability. In some embodiments, the programmable logic area may include additional specialized blocks, such as a programmable logic array Phase locked loop circuitry, programmable delay locked loop circuitry, or other specialized blocks with limited configurability.

In some embodiments, the digital signal processing circuitry 120 be adaptable to efficiently implement floating point operations with different accuracies. For example, the digital signal processing circuitry 120 Implement half-precision floating-point operations and / or single-precision floating-point operations and / or double-precision floating-point operations and / or quad-precision floating-point operations.

In some embodiments, multiple blocks of the digital signal processing circuitry 120 in a cascade chain, and two or more blocks in the cascade chain of the digital signal processing circuitry 120 Together they can implement a scalar product of two vectors.

For example, each block of the digital signal processing circuitry 120 implementing one or more multiplication operations each producing a respective product by multiplying a tuple of one of the two vectors by a tuple of the other of the two vectors. If desired, a first block of the digital signal processing circuitry 120 provide a sum of the respective products generated by the first block and provide the sum at a cascade output, which is sometimes referred to as a chain OUT, cascade output port, chain output port or cascade chain output.

A second block of digital signal processing circuitry 120 For example, the sum of the first block may be received via a cascade or chain connection at a cascade input, sometimes referred to as a cascade IN, cascade input port, chain input port, or cascade input.

The second block may generate a sum of the respective products generated by the second block and the sum received at the cascade input and the generated sum at a cascade output for further processing in an additional block of the digital signal processing circuitry 120 provide, if desired.

The programmable integrated circuit 100 may include programmable memory elements. These memory elements may be loaded with configuration data (sometimes also referred to as programming data) from the input / output circuitry 102. After loading, the memory elements each provide a corresponding static control signal that controls the operation of an associated logic component in a programmable logic area. In a typical scenario, the outputs of the charged memory elements are applied to the gates of transistors in the programmable logic area to turn certain transistors on or off, thereby configuring the logic and routing paths in the programmable logic area. The programmable logic circuit elements controllable in this manner include portions of multiplexers (eg, multiplexers used to form routing paths in programmable interconnects), lookup tables, logic arrays, XOR, AND, OR, NAND, and NOR logic gate, pass gate, inverter etc.

Memory elements may be any suitable volatile and / or non-volatile memory structures, such as random access memory (RAM) cells, fuses, anti-fuses, programmable read only memory cells, mask programmed and laser programmed structures, combinations of these structures, etc. , use. Since the memory elements are loaded with configuration data during programming, the memory elements are sometimes referred to as configuration memory, configuration RAM or programmable memory elements.

The circuit arrangement of the programmable integrated circuit 100 can be organized by any suitable architecture. As an example, the logic of the programmable integrated circuit 100 be organized in a series of rows and columns of larger programmable logic areas, each containing several smaller logic areas.

The smaller areas may be, for example, logic areas, sometimes referred to as logic elements (LEs), each containing a lookup table, one or more registers, and programmable multiplexer circuitry. For example, the smaller areas may also be logic areas, sometimes referred to as adaptive logic modules (ALMs) or slices. Each logical region may include a pair of adders, a pair of associated registers, shift registers, and one or more look-up tables or another block of shared combinatorial logic (ie, resources of a pair LEs, sometimes referred to herein as adaptive logic elements (ALEs)); include. The larger areas can be, for example, logic array blocks (LABs) or configurable logic blocks (CLBs) containing multiple logic elements or multiple ALMs or multiple slices.

While programming the device into the programmable integrated circuit 100 Loading configuration data that configures the programmable logic areas so that their logic resources perform desired logic functions.

An exemplary embodiment of a specialized processing block 200 , which is adaptable to efficiently implement mixed-precision floating-point arithmetic operations, is disclosed in U.S.P. 2 shown. To simplify the discussion, this logical presentation will refer to implementation details, such as registers, and some programmable routing functions, such as multiplexers and routes, that may allow the output of a particular structure to or around different components specialized processing block is passed out, omitted. In addition, some of the elements shown may be implemented more than once in an actual embodiment. For example, the multiplier 202 actually represent two or more multipliers.

As shown, the specialized processing block 200 the input terminals 271 . 273 . 275 . 277 and 279 , the output terminal 280 , the chain IN connector 262 sometimes referred to as a cascade IN or cascade input, the chain OUT connector 263 sometimes also referred to as cascade OUT or cascade output, the multiplexers 230 . 231 . 232 and 235 , the multiplier stage 205 , the adder circuits 203 and 204 , the registers 213 . 214 . 215 . 216 . 217 . 218 . 219 . 220 . 221 . 222 and 223 and the conversion function circuit 250 include. The multiplier stage 205 can the multiplier circuits 201 and 202 include.

The specialized processing block 200 can output signals at the output terminal 280 generate and input signals to the input terminals 271 . 273 . 275 . 277 and 279 receive. On request, the specialized processing block 200 in a cascade chain with other specialized processing blocks (e.g., in a row or column) and at the chain IN port 262 receive, via a direct cascade connection, additional input signals from a neighboring specialized processing block and at the chain OUT port 263 provide additional output signals to another adjacent specialized processing block via another direct cascade connection.

In some embodiments, the adder circuit 203 and the multiplier stage 205 with the multiplier circuits 201 and 202 on floating-point numbers of a first floating-point precision (eg according to the standard IEEE 754 half accuracy, single precision, double precision, fourfold accuracy or eightfold accuracy), and the adder circuit 204 may refer to floating-point numbers of a second floating-point precision (eg, according to the IEEE standard 754 half accuracy, single precision, double precision, fourfold accuracy or eightfold accuracy). If desired, the second floating point precision may differ from the first floating point precision.

For example, the second floating point precision may be more accurate than the first floating point precision. For example, according to the IEEE standard 754 the second floating-point precision of single precision, double precision, quadruple accuracy or eightfold accuracy, if the first floating-point precision is half accuracy; may be the second floating point precision of double precision, fourfold accuracy or eightfold accuracy if the first floating point precision is single precision; For example, the second floating point precision may be quadruple precision or eightfold accuracy if the first floating point precision is double precision; or the second floating point precision may be eightfold accuracy if the first floating point precision is quadruple accuracy.

As another example, the second floating point precision may be a lower accuracy than the first floating point accuracy. For example, according to the IEEE standard 754 the second floating point precision is half accuracy, single precision, double precision, or quadruple accuracy if the first floating point precision is eightfold accuracy; For example, if the first floating point precision is quadruple precision, the second floating point precision may be half accuracy, single precision, or double precision; the second floating point precision may be half accuracy or single precision if the first floating point precision is double precision; or may be the second floating point precision of half accuracy if the first floating point precision is single precision.

In some embodiments, the conversion function circuit may 250 the output of the adder circuit 203 from the first floating point inaccuracy to the second floating point inaccuracy. For example, the output of the adder circuit 203 be a half-precision floating-point number, and the Conversion function circuitry can convert the product sum into a single precision floating point number. As another example, the output of the adder circuit 203 be a double precision floating point number, and the conversion function circuit 250 can convert the product total to a single-precision floating-point number.

To convert a glide ratio from a first floating-point inaccuracy to a second floating-point inaccuracy that is higher than the first floating-point inaccuracy, which is sometimes referred to as upconversion, the transform function circuit may 250 increase the number of bits of the mantissa and the number of bits of the exponent and adjust the bias of the exponent accordingly. For example, to convert a half-precision floating-point number to a single-precision floating-point number, the conversion function circuit may 250 increase the size of the mantissa from 10 bits to 23 bits (eg by adding 13 zeros to the right of the least significant bit (LSB) position) and increase the exponent size from 5 bits to 8 bits (e.g. B. by adding 3 zeros to the left of the Most Significant Bit (MSB) position). The conversion function circuit 250 can adjust the bias of the exponent by adding 112 to the floating point exponent with half accuracy.

To convert a floating-point number from a first floating-point inaccuracy to a second floating-point inaccuracy that is lower than the first floating-point inaccuracy, which is sometimes referred to as a down-conversion, the conversion function circuit may 250 lower the number of bits of the mantissa (eg by rounding), adjust the exponent's bias accordingly, and decrease the exponent's bit count.

On request, the conversion function circuit 250 include the conversion of special cases (eg, the first floating-point inaccuracy number may be denormalized, zero, infinite or no number (Not a Number or NaN)). As an example, a denormalized first floating-point inaccuracy number may be converted to zero, sometimes referred to as Denormal Are-Zero (DAZ). As another example, in downconversion, zero, a denormal number, or too large an exponent underflow number may be converted to zero, and infinity or exponent overflow may be converted to infinity.

The configurable interconnect circuitry in the specialized processing block 200 can signals between the input terminals 271 . 273 . 275 . 277 and 279 , the output terminal 280 , the chain IN connector 262 , the chain OUT connector 263 , the multiplier circuits 201 and 202 , the adder circuits 203 and 204 , the registers 213 . 214 . 215 . 216 . 217 . 218 . 219 . 220 . 221 . 222 and 223 and the conversion function circuit 250 hand off.

As shown, the configurable interconnect circuitry may be the multiplexers 230 . 231 . 232 and 235 and links, sometimes referred to as routing lanes. The configurable interconnect circuitry may be used to configure some of the components of the specialized processing block 200 to bridge. For example, the multiplexer 231 between the output of the conversion function circuit 250 and the output of the multiplier stage 205 choose the registers 218 and 219 and the adder circuit 203 bridged. Likewise, the multiplexer 235 between the output of the register 223 and the output of the adder circuit 203 while allowing a bypass path containing the conversion function circuit 250 , the multiplexer 231 , the registry 221 , the adder circuit 204 and the register 223 bridged.

If desired, the configurable interconnect circuitry may include additional multiplexers to provide the flexibility of interconnecting the various components of the specialized processing block 200 increase and allow for additional bridging paths. For example, additional multiplexers may be in front of the registers 218 and 219 a bridging path around the multiplier stage 205 allow additional multiplexers behind a register (e.g., registers 218 . 219 . 220 , etc.) can provide a bridging path around the respective register, etc.

Control signals can be through the multiplexers 230 . 231 . 232 and 235 control selected selection. The control signals may be generated by logic circuits which dynamically control the selection of the respective multiplexers and / or stored in memory circuits. The logic circuits and / or memory circuits may be within the specialized processing block 200 are located. If desired, some or all of the logic circuits and / or memory circuits may be external to the specialized processing block 200 and the control signals may be provided to the respective multiplexers through additional input terminals.

The control signals may be stored individually for each multiplexer or in groups for multiple multiplexers. The memory circuits may receive the control signals during the Configuration or reconfiguration of the specialized processing block 200 load. In some embodiments, the memory circuits may include programmable memory elements of an integrated circuit (eg, the programmable integrated circuit 100 out 1 ) be.

The multiplexer 230 may be between the forwarding of outputs of the conversion function circuit 250 and the register 220 and 223 to the cascade exit 263 choose. The multiplexer 231 may be between forwarding outputs of the multiplier stage 205 , the conversion function circuit 250 and the register 220 to the register 221 choose. The multiplexer 232 may be between forwarding the output of the register 220 and a signal from the cascade input 262 to the register 222 choose. The multiplexer 235 may be between forwarding the outputs of the conversion function circuit 250 and the register 223 to the output terminal 280 choose.

In the logical representation 2 can be the specialized processing block 200 a fixed point addition, a floating point addition, a fixed point multiplication, a floating point multiplication, a sum of two multiplications in a first floating point precision, with or without conversion to a second floating point precision, and the latter followed by a subsequent addition in the second floating point precision implement, if desired, etc ,

Now consider the scenario where the specialized processing block 200 the input signals A, B, C, D and E at the input terminals 271 . 273 . 275 . 277 respectively. 279 and the chain IN signal CHAIN_IN at the cascade input 262 receives. Further assume that the input signals A, B, C and D are signals that are floating-point numbers of a first floating-point precision (eg, half accuracy, single precision, double precision, or quadruple accuracy according to the IEEE standard 754 ) and that the input signal E and the string IN signal are CHAIN_IN signals that are floating point numbers of a second floating point precision that is more accurate than the first floating point precision (eg, single precision if the first floating point precision is half accuracy) double precision when the first floating point precision is single precision, quadruple accuracy when the first double precision precision floating point precision, or eightfold accuracy when the first floating point precision is quadruple accuracy according to the IEEE standard 754 ) code.

In this scenario, the multiplier stage 205 the product of A and B (ie A * B) in the multiplier circuit 201 and the product of C and D (ie, C * D) in the multiplier circuit 202 to calculate. The products can be in the registers 218 respectively. 219 saved, if desired. The adder circuit 203 can produce the sum of the products (ie A * B + C * D).

In some embodiments, the conversion function circuit may 250 Convert the product's total from the first floating-point precision to the second floating-point precision. For example, the product sum may be a half-precision floating point number, and the conversion function circuit may convert the product sum to a single precision floating point number. As another example, the product sum may be a double precision floating point number and conversion function circuitry 250 can convert the product total to a single-precision floating-point number.

Configurable interconnect circuitry may control the output of the transform function circuit 250 in the multiplexer 231 and the CHAIN_IN signal at the cascade input 262 in the multiplexer 232 and thus the converted product sum from the output of the conversion function circuit 250 to the adder circuit 204 and the CHAIN_IN signal from the cascade input 262 to the adder circuit 204 conduct.

If desired, the adder circuit 204 add the product sum to the CHAIN_IN signal to generate another sum signal. The multiplexer 235 The configurable interconnect circuitry may be between the sum of products from the adder circuit 203 and the further sum signal from the adder circuit 204 choose. The configurable connection circuitry may be selected by selecting the output of the adder circuit 203 in the multiplexer 235 the product sum to the exit 280 conduct. Alternatively, the configurable connection circuit may be selected by selecting the output of the adder circuit 204 in the multiplexer 235 the further sum to the exit 280 conduct.

In some embodiments, the specialized processing block 200 implement additional properties. For example, the specialized processing block 200 a path from the output of the register 223 to an additional input of the multiplexer 231 or to an additional input of the multiplexer 232 and thereby allow the implementation of an accumulation operation, if desired.

Based on the configuration of the configurable interconnect circuitry, the specialized processing block 200 Implement various arithmetic operations, such as has been described above. 3 Figure 12 is a diagram of the two exemplary specialized processing blocks 300A and 300B which are arranged in a cascade chain and together execute a first stage of recursive dot product operation, according to some embodiments.

On request, the specialized processing block 200 out 2 each of the specialized processing blocks 300A and 300B to implement. To simplify the discussion, look at the logical representation 3 on implementation details of the specialized processing blocks 300A and 300B such as registers, and some programmable routing functions, such as multiplexers, omitted.

As shown, the specialized processing blocks 300A and 300B both the entrances 371 . 373 . 375 and 377 , the exit 380 , the conversion function circuit 350 , the multiplier circuits 301 and 302 and the adder circuits 303 and 304 include. A cascade connection may be a cascade output of the specialized processing block 300B with a cascade input of the specialized processing block 300A couple.

In some embodiments, the multiplier circuits 301 and 302 and the adder circuit 303 operate on floating point numbers of a first floating point inaccuracy, the adder circuit 304 to floating point numbers of a second floating point inaccuracy and can operate the conversion function circuit 350 in a same way as the conversion function circuit 250 out 2 can operate with the output of the adder circuit 303 be coupled to the output of the adder circuit 303 from the first floating point inaccuracy to the second floating point inaccuracy.

Consider the scenario in which the specialized processing blocks 300A and 300B together a scalar product of a first vector Y with the tuples A, C, E and G (ie Y = (A, C, E, G) ^∧ T) and a second vector Z with the tuples B, D, F and H (ie Z = (B, D, F, H) ^∧ T). Assume further that the tuples of the vectors Y and Z have a first floating-point precision (eg according to the IEEE standard 754 half accuracy, single precision, double precision or quadruple accuracy).

In this scenario, the specialized processing block 300A two tuples from both the vector Y and Z (eg, the tuples A and C from the vector Y and the tuples B and D from the vector Z) and the specialized processing block 300B the other two tuples from both the vector Y and Z (eg, the tuples E and G from the vector Y and the tuples F and H from the vector Z) at the inputs 371 . 375 . 373 respectively. 377 receive.

The multiplier circuits 301 and 302 , the adder circuit 303 and the conversion function circuit 350 the specialized processing block 300B may have a first partial result with a second floating-point precision that has a higher accuracy than the first floating-point accuracy (eg according to the IEEE standard 754 single precision, double precision, fourfold accuracy, eightfold accuracy) based on a first quaternary reduction of the inputs 371 . 373 . 375 and 377 receive received tuples of vectors Y and Z. For example, in the specialized processing block 300B the multiplier circuit 301 the product E * F, the multiplier circuit 302 the product G * H and the adder circuit 303 Generate the product sum E * F + G * H. The conversion function circuit 350 in the specialized processing block 300B For example, the product sum E * F + G * H may be converted from the first floating point inaccuracy into the second floating point inaccuracy, as set forth above, thereby producing the first partial result.

Likewise, the multiplier circuits 301 and 302 , the adder circuit 303 and the conversion function circuit 350 the specialized processing block 300A a second partial result with the second floating point precision based on a second quaternary reduction of the inputs 371 . 373 . 375 and 377 receive received tuples of vectors Y and Z. For example, in the specialized processing block 300A the multiplier circuit 301 the product A * B, the multiplier circuit 302 the product C * D and the adder circuit 303 Generate the product sum A * B + C * D. The conversion function circuit 350 in the specialized processing block 300A For example, the product sum A * B + C * D may be converted from the first floating point inaccuracy to the second floating point inaccuracy, as set forth above, thereby producing the second partial result.

The configurable interconnect circuitry in the specialized processing blocks 300A and 300B may be the first partial result of the conversion function circuit 350 in the specialized processing block 300B via the cascade connection to the adder circuit 304 in the second specialized processing block 300A and the second partial result from the conversion function circuit 350 to the adder circuit 304 in the specialized processing block 300A hand off.

The adder circuit 304 the specialized processing block 300A can the scalar product of the vectors Y and Z (ie Y * Z = A * B + C * D + E * F + G * H) by performing a binary reduction (ie, addition) of the first and second part results, and generating the dot product as signal J at the output 380 the specialized processing block 300A provide.

4 FIG. 12 is a diagram of two exemplary specialized processing blocks arranged in a cascade chain and together performing a first stage of a recursive dot product operation and an accumulation operation, according to some embodiments.

On request, the specialized processing block 200 out 2 each of the specialized processing blocks 400A and 400B to implement. To simplify the discussion, look at the logical representation 4 on implementation details of the specialized processing blocks 400A and 400B such as registers, and some programmable routing functions, such as multiplexers, omitted.

As shown, the specialized processing blocks 400A and 400B both the entrances 471 . 473 . 475 and 477 , the exit 480 , the conversion function circuit 450 , the multiplier circuits 401 and 402 and the adder circuits 403 and 404 include. The specialized processing block 400B may also be the entrance 479 and the register 405 between the output of the adder circuit 404 and the exit 480 and an input of the adder circuit 404 is coupled. A cascade connection may be a cascade output of the specialized processing block 400B with a cascade input of the specialized processing block 400A couple.

The specialized processing blocks 400A and 400B Together, they can implement the dot product of vectors Y and Z, as in 3 described. On request, the specialized processing block 400B additionally an accumulation operation of the input 479 implement received signal I. For example, signal I may encode a floating point number of floating point inaccuracy other than A, B, C, D, E, F, G, or H signals. The adder circuit 404 the specialized processing block 400B can that be in the register 405 stored signal (eg zero at reset) to the input 479 add the received signal. The registry 405 may be determined by the adder circuit 404 store generated sum, and the adder circuit 404 can save the stored sum to the one at the entrance 479 add the received signal and thus implement an accumulation operation.

By using the two specialized processing blocks 300A and 300B out 3 As building blocks of neighboring specialized processing blocks, a recursive tree can be constructed for generating a scalar product of two vectors. 5 FIG. 12 is a diagram of six exemplary specialized processing blocks arranged in a cascade chain and generating a scalar product of two floating point vectors, according to some embodiments.

On request, the specialized processing block 200 out 2 each of the specialized processing blocks 500A . 500B . 500C . 500D . 500E and 500F to implement. To simplify the discussion, look at the logical representation 5 on implementation details of the specialized processing blocks 500A . 500B . 500C . 500D . 500E and 500F such as registers, and some programmable routing functions, such as multiplexers, omitted.

As shown, the specialized processing blocks 500A - 500F (ie 500A, 500B, 500C, 500D, 500E and 500F) respectively the inputs 571 . 573 . 575 and 577 , the exit 580 , the conversion function circuit 550 , the multiplier circuits 501 and 502 and the adder circuits 503 and 504 include. The specialized processing blocks 500B . 500C . 500D and 500E can also use the entrance 579 include. A cascade connection may be a cascade output of the specialized processing blocks 500F . 500E . 500D . 500C and 500B with a cascade input of the specialized processing blocks 500E . 500D . 500C . 500B respectively. 500A couple.

Now consider the scenario in which the specialized processing blocks 500A - 500F together the scalar product of the vector Y with the tuples A, C, E, G, I, K, M, O, Q, S, U, W (ie Y = (A, C, E, G, I, K, M , 0, Q, S, U, W) ^ T) and the vector Z with the tuples B, D, F, H, J, L, N, P, R, T, V and X (ie Z = (B , D, F, H, J, L, N, P, R, T, V, X) ^ T). Assume further that the tuples of the vectors Y and Z have a first floating-point precision (eg according to the standard IEEE 754 half accuracy, single precision, double precision or quadruple accuracy).

In this scenario, the specialized processing block 500A two tuples from both the vector Y and Z (eg, the tuples A and C from the vector Y and the tuples B and D from the vector Z) at the inputs 571 . 573 . 575 respectively. 577 receive. Likewise, the specialized processing blocks 500B - 500F every two tuples from both the vector Y and Z at the entrances 571 . 573 . 575 respectively. 577 500B receives the tuples E and G from the vector Y and the tuples F and H from the vector Z, 500C receives I, J, K and L, 500D receives M, N, O, P, 500E receives Q, R, S, T and 500F receives U, V, W and X).

Each pair of specialized processing blocks may implement the first stage of a recursive dot product operation, as in FIG 3 shown by a partial result based on a quaternary reduction of the inputs 571 . 573 . 575 and 577 received tuples of vectors Y and Z based on the multiplier circuits 501 and 502 , the adder circuit 503 and the conversion function circuit 550 followed by a binary reduction of the partial result produced in the current specialized processing block and the partial result generated in a neighboring specialized processing block.

For example, the multiplier circuits 501 and 502 , the adder circuit 503 and the conversion function circuit 550 the specialized processing block 500B which converts the first floating point inaccuracy to a second floating point inaccuracy, which has a higher floating point inaccuracy, as set forth above, converted product sum E * F + G * H and thus produces a partial result. Likewise, the multiplier circuits 501 and 502 , the adder circuit 503 and the conversion function circuit 550 the specialized processing block 500A generate the product sum A * B + C * D converted from the first floating point inaccuracy to the second floating point inaccuracy and thus generate another partial result.

The configurable interconnect circuitry in the specialized processing blocks 500A and 500B can the two partial results to the adder circuit 504 in the specialized processing block 500A hand off.

The adder circuit 504 the specialized processing block 500A the first step result of the scalar product of the vectors Y and Z (ie A * B + C * D + E * F + G * H) can be obtained by performing a binary reduction (ie addition) of the two partial results (ie A * B + C * D and E * F + G * H) and the first step result of the dot product at the output 580 the specialized processing block 500 provide. Likewise, the specialized processing blocks 500C and 500D the first step result I * J + K * L + M * N + O * P and the specialized processing blocks 500E and 500F generate the first step result Q * R + S * T + U * V + W * X.

By utilizing the building blocks of neighboring specialized processing blocks (ie, 500A and 500B, 500C and 500D, and 500E and 500F), a recursive tree can be constructed. For example, the first stage results of the dot product of the vectors Y and Z (ie, the outputs of the specialized processing blocks 500A . 500C and 500E ) have routing resources that are outside the specialized processing blocks 500A - 500F located (for example, using the vertical connection resources 140 and the horizontal connection resources 150 the programmable integrated circuit 100 out 1 ) to the inputs 579 the specialized processing blocks 500B . 500C respectively. 500E to get redirected.

As shown, the configurable interconnect circuitry in the specialized processing blocks 500B and 500C the first step result I * J + K * L + M * N + O * P from the input 579 the specialized processing block 500C via a cascade connection to the adder circuit 504 the specialized processing block 500B and the first step result A * B + C * D + E * F + G * H from the input 579 to the adder circuit 504 the specialized processing block 500B hand off. The specialized processing block 500B can the adder 504 to produce the second step result (ie A * B + C * D + E * F + G * H + I * J + K * L + M * N + O * P) and the second step result at the output 580 provide.

The second stage result may have routing resources that are outside of the specialized processing blocks 500A - 500F located at the entrance 579 the specialized processing block 500D and from there to the adder 504 the specialized processing block 500D to get redirected. The configurable interconnect circuitry in the specialized processing blocks 500D and 500D can the first step result Q * R + S * T + U * V + W * X from the input 579 the specialized processing block 500E via a cascade connection to the adder circuit 504 the specialized processing block 500D hand off. The specialized processing block 500D can the adder 504 use the final scalar product result (ie A * B + C * D + E * F + G * H + I * J + K * L + M * N + O * P + Q * R + S * T + U * V + W * X) in a third stage, and the final scalar product at the output 580 provide.

Upon request, at any stage of the in 5 described recursive tree register pipelining (eg, to simplify routing and / or improve the speed). Since the adders of the stages following the first stage (ie the adders 504 the specialized processing blocks 500B and 500D ) are absolutely independent of the first stage adder (and each other), the adders of subsequent stages in any one of the specialized processing blocks 500B . 500D or 500F in which the adder 504 is unused in the first stage of scalar product computation. This can be done, for example, in later stages where the Lengths from one step to another can be helpful.

On the adder circuit 504 the specialized processing block 500F can be omitted since a scalar product of two vectors with N-tuples in each vector requires N multiplier circuits and (N-1) adder circuits. Alternatively, the Nth adder circuit 504 be used independently for other purposes.

6 is a diagram of four exemplary specialized processing blocks 600A - 600D (ie, 600A, 600B, 600C, and 600D) arranged in a cascade chain and executing a recursive dot product of two floating-point vector vectors and accumulating the result, according to some embodiments.

On request, the specialized processing block 200 out 2 each of the specialized processing blocks 600A - 600D to implement. To simplify the discussion, look at the logical representation 6 on implementation details of the specialized processing blocks 600A - 600D such as registers, and some programmable routing functions, such as multiplexers, omitted.

As shown, the specialized processing blocks 600A - 600D everyone the inputs 671 . 673 . 675 and 677 , the exit 680 , the conversion function circuit 650 , the multiplier circuits 601 and 602 and the adder circuits 603 and 604 include. The specialized processing blocks 600B . 600C and 600D can also use the entrance 679 include, and the specialized processing block 600D can the register 605 including an accumulator having the adder circuit 604 can implement. A cascade connection may be a cascade output of the specialized processing blocks 600D . 600C and 600B with a cascade input of the specialized processing blocks 600C . 600B respectively. 600A couple.

As an example, the specialized processing blocks 600A - 600D the first two stages of in 5 implement recursive dot product generation. In other words, the specialized processing blocks 600A - 600D the dot product Y * Z = A * B + C * D + E * F + G * H + I * J + K * L + M * N + O * P of the vector Y with the tuples A, C, E, G, I, K, M and O (ie Y = (A, C, E, G, I, K, M, O) ^ T) and the vector Z with the tuples B, D, F, H, J, L N and P (ie Z = (B, D, F, H, J, L, N, P) ^ T) and produce the dot product at the output 680 the specialized processing block 600B provide.

Upon request, the dot product may have routing resources that are outside of the specialized processing blocks 600A - 600D located at the entrance 679 the specialized processing blocks 600D and from there to the adder 604 the specialized processing block 600D to get redirected. The adder circuit 604 the specialized processing block 600D can that be in the register 605 stored signal (eg zero at reset) to the input 679 add the received signal. The registry 605 may be determined by the adder circuit 604 store generated sum, and the adder circuit 604 can save the stored sum to the one at the entrance 679 add together received signal and thus implement an accumulation operation of the scalar product.

7 FIG. 10 is a flowchart showing exemplary operations for operating an integrated circuit that generates a scalar product of a first and a second vector, according to some embodiments.

During the operation 710 For example, the integrated circuit may generate a first partial result of a first floating-point precision with a first specialized processing block. As an example, an integrated circuit such as the programmable integrated circuit 100 out 1 , the specialized processing blocks 300A and 300B out 3 include; and the specialized processing block 300B can produce the product sum E * F + G * H as a first partial result with a first floating point precision (eg, a single precision floating point format).

During the operation 720 For example, the integrated circuit may provide the first partial result to a cascade output of the first specialized processing block. For example, the specialized processing block 300B out 3 provide the first partial result (ie the product sum E * F + G * H) at the cascade output.

During the operation 730 The integrated circuit may receive the first partial result via a cascade connection from the cascade output of the first specialized processing block at a cascade input of a second specialized processing block. For example, the specialized processing block 300A out 3 the product sum E * F + G * H via the cascade connection at the cascade input from the specialized processing block 300B receive.

During the operation 740 For example, the integrated circuit may provide a second partial result with the first floating point inaccuracy based on a quaternary reduction of two tuples with one generate second floating point inaccuracy from both the first and second vectors in the second specialized processing block. For example, the specialized processing block 300A out 3 receive the tuples A and C from a vector Y and the tuples B and D from a vector Z. If desired, tuples A, B, C, and D may have a second floating point precision (eg, a half-precision floating point format). The specialized processing block 300A can the multiplier circuits 301 and 302 and the adder circuit 303 with a subsequent conversion to the first floating point inaccuracy in the conversion function circuit 350 to produce the product sum A * B + C * D as a second partial result with the first floating-point precision (for example, a single-precision floating-point number format).

During the operation 750 For example, the integrated circuit may generate the dot product by performing a binary reduction of the first and second part results in the second specialized processing block. For example, the adder circuit 304 in the specialized processing block 300A out 3 generate the scalar product by adding the first partial product (ie, E * F + G * H) to the first partial product (ie, A * B + C * D), thereby generating the dot product of the vector Y with the tuples A, C, E, and G, and Create vector Z with the tuples B, D, F and H.

A machine-readable medium may include instructions for carrying out a method (eg, instructions for configuring an integrated circuit to generate a dot product of a first and a second vector, as determined by the method 7 described) on an integrated circuit according to some embodiments. A suitable computer or similar device may execute these instructions to implement the method in the integrated circuit. For example, a personal computer may be provided with an interface to which the integrated circuit may be connected, and appropriate software tools and / or a user may program the method via the interface into the integrated circuit using the personal computer.

In some embodiments, the instructions for carrying out the method may be generated by other instructions encoded on the same or an additional machine-readable medium. In other words, a first set of instructions (eg, a C-language compiler or an Electronic Design Automation (EDA) tool executing on a computer or similar device may include a second set of Generate instructions (eg, assembler code or a bit string for programming a configurable circuit arrangement), the second set of instructions including the method described on an integrated circuit (eg, on a microprocessor or a programmable integrated circuit device such as a microprocessor) for example, the programmable integrated circuit 100 out 1 ) is performed.

A machine-readable medium may include any type of device or technology that enables storage of instructions, including semiconductor memory that may be volatile (eg, Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM) ), etc.) or non-volatile (e.g., programmable read only memory (PROM), flash memory, etc.), magnetic storage devices, optical storage devices, or a combination thereof.

8th shows a cross section of a magnetic data storage medium 800 , which may be encoded with a machine executable program that may be executed by systems such as the aforementioned personal computer or other computer or similar device. The medium 800 may be a floppy disk or a hard disk or a magnetic tape with a suitable substrate 810 , which may be conventional, and a suitable coating 820 , which may be conventional, on one or both sides containing magnetic areas whose polarity or orientation can be magnetically changed. Except in the case of a magnetic tape, the medium 800 also have an opening for receiving the spindle of a hard disk or other data storage device.

The magnetic areas of the coating 820 of the medium 800 may be poled or oriented to encode, in a manner that may be conventional, a machine executable program executed by a programming system, such as a personal computer or other computer, or a similar system having a slot or peripheral port, into which the integrated circuit to be configured may be inserted for the purpose of configuring appropriate portions of the integrated circuit, including its optional specialized processing blocks, according to some embodiments.

9 shows a cross section of an optically readable data storage medium 900 , which can be coded with an aforementioned machine-executable program, by systems such as the aforementioned Personal computer, or other computer or similar device to be executed. The medium 900 can be a Blu-ray Disc (BD), a conventional Compact Disc Read Only Memory (CD-ROM) or a Digital Versatile Disc (DVD, sometimes referred to as Digital Video Disc) read-only memory or any rewritable medium such as a CD R, CD RW, DVD R, DVD RW, DVD + R, DVD + RW or DVD-RAM or a magneto-optical disc that is optically readable and magneto-optically rewritable. The medium 900 can be a suitable substrate 910 and a suitable coating 920 usually on one or both sides of the substrate 910 is located.

In the case of a CD-based or DVD-based medium, the coating is 920 As is well known, reflective and comes with a plurality of pits 930 stacked on one or more layers embossed to code the machine executable program. The arrangement of pits is made by reflecting laser light on the surface of the coating 920 read. On top of the coating 920 can be a protective coating 940 be provided.

In the case of Magneto-Optical Disc rejects the coating 920 as is well known, no pits 930 but a plurality of magnetic regions whose polarity or orientation can be magnetically changed when heated above a certain temperature, for example by a laser. Alignment of the regions can be achieved by measuring the polarization of the coating 920 be measured reflected laser light. The arrangement of the areas may code the program as described above.

The method and apparatus described herein may be incorporated into any suitable circuitry or circuit systems. For example, the method and apparatus may be integrated into various types of devices, such as microprocessors or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPGAs), electronically programmable logic devices (Electrically Programmable Logic Devices, EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), coarse granular reconfigurable architectures (coarse-grained Reconfigurable Architectures, CGRAs), Digital Signal Processing Circuits (DSP), Application Specific Standard Products (ASSPs), Application Specific Integrated Circuits (ASICs), to name just a few.

The integrated circuit described herein may be part of a data processing system that includes one or more of the following components: a processor; Storage; I / O circuitry and peripherals. The data processing system is useful in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application in which the benefit of using circuitry that efficiently executes composite precision floating point arithmetic operations is desirable.

The integrated circuit may be configured to perform a variety of different logic functions. For example, the integrated circuit may be configured as a processor or controller that cooperates with a system processor. The integrated circuit may also be used as an intermediary to provide access to a shared resource in the data processing system. In yet another example, the integrated circuit may be configured as an interface between a processor and one of the other components in the system. In one embodiment, the integrated circuit may be one of the families of devices owned by the assignee.

Although the method operations have been described in a particular order, it should be understood that other operations may be performed between described operations, described operations may be adapted to occur at slightly different times, or described operations may be distributed in a system which includes the Performing the processing operations in different, associated with the processing intervals allows.

The foregoing is merely exemplary of the principles of the embodiments, and numerous modifications can be made by those skilled in the art without departing from the scope and spirit of the embodiments disclosed herein. The above embodiments may be implemented individually or in any combination.

The following examples relate to further embodiments.

Example 1 is an integrated circuit that generates a scalar product of a first and a second vector and includes: a first specialized processing block that provides a first partial result of a first floating-point inaccuracy, and a second specialized processing block that cascades the first partial result from the first and a first floating point arithmetic operator circuit which generates a second partial result with the first floating point precision based on a quaternary reduction of two tuples with a second floating point precision from both the first and second vectors, and a second floating point arithmetic operator circuit which generates the scalar product by generating a binary reduction of the first and second part results.

Example 2 includes the subject matter of the example 1 wherein the first floating point arithmetic operator circuitry further generates a first multiplier circuit that generates a first product based on a first tuple of the two tuples from the first vector and a first tuple of the two tuples from the second vector, the first product having the second floating point precision, and a second multiplier circuit that generates a second product based on a second tuple of the two tuples from the first vector and a second tuple of the two tuples from the second vector, the second product having the second floating point precision.

Example 3 includes the subject matter of the example 2 wherein the first floating point arithmetic operator circuitry further includes an adder circuit that generates a sum of the first and second products, the sum having the second floating point precision.

Example 4 includes the subject matter of the example 3 wherein the first floating point arithmetic operator circuitry further includes a conversion function circuit that receives the sum from the adder circuit and generates the second partial result by converting the sum of the second floating point inaccuracy into the first floating point inaccuracy.

Example 5 includes the subject of the example 4 wherein the conversion function circuit increases the exponent size of the sum from the second to the first floating point precision.

Example 6 includes the subject matter of any of Examples 4 or 5, wherein the conversion function circuit adjusts the bias of the exponent of the sum of the bias of the second floating-point precision to the bias of the second floating-point accuracy.

Example 7 includes the subject matter of one of Examples 4-6, wherein the second specialized processing block further includes an output port coupled to the second floating point arithmetic operator circuitry and a bypass path between the adder circuit and the output port, the bypass path comprising the conversion function circuit and the second Floating-point arithmetic operator circuitry bypasses.

Example 8 includes the subject matter of any of Examples 1-7, wherein the second floating point arithmetic operator circuitry further includes an adder circuit that generates the scalar product by adding the first and second subtotals.

Example 9 is a method of operating an integrated circuit that generates a scalar product of a first and a second vector and includes: generating a first partial result of a first floating-point inaccuracy with a first specialized processing block, providing the first partial result at a cascade output of the first specialized processing block; Receiving a first partial result via a cascade connection from the cascade output of the first specialized processing block at a cascade input of a second specialized processing block, generating a second partial result with the first floating point precision based on a quaternary reduction of two tuples with a second floating point precision from both the first and second vectors in FIG second specialized processing block and generating the dot product by performing a binary reduction of the first and second partial results s in the second specialized processing block.

Example 10 includes the subject matter of the example 9 wherein generating the second partial result further comprises using a first multiplier circuit to generate a first product based on a first tuple of the two tuples from the first vector and a first tuple of the two tuples from the second vector, the first product having the second floating point precision and using a second multiplier circuit to generate a second product based on a second tuple of the two tuples from the first vector and a second tuple of the two tuples from the second vector, the second product having the second floating point precision.

Example 11 includes the subject of the example 10 and further using an adder circuit to generate a sum of the first and second products, the sum having the second floating point precision.

Example 12 includes the subject of the example 11 and further using a conversion function circuit that receives the sum from the adder circuit and generates the second partial result by converting the sum of the second floating-point inaccuracy to the first floating-point precision.

Example 13 includes the subject matter of the example 12 and further increasing the exponent size of the sum of the second to the first floating point inaccuracy with the conversion function circuit.

Example 14 includes the subject matter of any of Examples 12 or 13, and further adjusting the bias of the exponent of the sum of the second floating-point inaccuracy bias to the bias of the second floating-point inaccuracy with the conversion function circuit.

Example 15 includes the subject matter of any of Examples 12-14 and further comprising bypassing the conversion function circuit on a bypass path that couples the adder circuit to an output terminal of the second specialized processing block.

Example 16 is a non-transitory machine-readable storage medium encoded with instructions for configuring an integrated circuit device to produce a scalar product of a first and a second vector, the integrated circuit device including first and second specialized processing blocks coupled by a cascade connection wherein the first and second specialized processing blocks each include first and second floating point arithmetic operator circuitry and configurable interconnect circuitry, the instructions including instructions for configuring the first floating point arithmetic operator circuitry in the first specialized processing block to provide a first partial result with a first Floating point inaccuracy based on a first quaternary reduction of the first two tuples with a second floating point inaccuracy from both the he to generate the first partial result from the first floating point arithmetic operator circuitry in the first specialized processing block through the cascade circuit to the second arithmetic operator circuitry in the second specialized processing block, Instructions for configuring the first floating point arithmetic operator circuitry in the second specialized processing block to produce a second partial result with the first floating point precision based on a second quaternary reduction of the second two tuples with the second floating point inaccuracy from both the first and second vectors, and instructions for configuring the second floating point arithmetic operator circuitry in the second specialized processing block to obtain the scalar product du To produce a binary reduction of the first and second partial results.

Example 17 includes the subject matter of the example 16 and further instructions for generating the instructions of Example 16.

Example 18 includes the subject matter of any of Examples 16 or 17, wherein the instructions for configuring the first floating-point arithmetic operator circuitry in the first specialized processing block further include instructions for configuring a first multiplier circuit to produce a first product based on a first tuple of the first two tuplets from the first vector and a first tuple of the first two tuples from the second vector, the first product having the second floating point precision, and instructions for configuring a second multiplier circuit to produce a second product based on a second tuple of the first two tuples generate the first vector and a second tuple of the first two tuples from the second vector, the second product having the second floating point precision.

Example 19 includes the subject of the example 18 wherein the instructions for configuring the first floating point arithmetic operator circuitry in the first specialized processing block further include instructions for configuring an adder circuit to produce a sum of the first and second products, the sum having the second floating point precision.

Example 20 includes the subject of the example 19 wherein the instructions for configuring the first floating point arithmetic operator circuitry in the first specialized processing block further include instructions for configuring a conversion function circuit to generate the second partial result by converting the sum of the second floating point precision to the first floating point precision.

Example 21 includes the subject of the example 20 and further instructions for increasing the exponent size of the sum of the second to the first floating point inaccuracy.

Example 22 includes the subject matter of any of Examples 20 or 21, and further instructions for adjusting the bias of the exponent of the sum of the bias of the second floating-point inaccuracy to the bias of the first floating-point inaccuracy.

Example 23 includes the subject matter of the example 19 wherein the instructions for configuring the second floating-point arithmetic operator circuitry in the second specialized processing block to generate the dot product by performing a binary reduction of the first and second part results further include instructions for adding the first and second part results.

Example 24 is an integrated circuit for generating a scalar product of a first and a second vector, including a first specialized processing block for providing a first partial result of a first floating point precision and a second specialized processing block receiving the first partial result from the first specialized processing block via a cascade connection and first Means for generating a second partial result having the first floating point inaccuracy based on a quaternary reduction of two tuples with a second floating point precision from both the first and second vectors and second means for generating the dot product by performing a binary reduction of the first and second partial results.

Example 25 includes the subject of the example 24 and further a memory circuit for storing at least one tuple of the first vector.

Example 26 includes the subject of the example 25 wherein the memory circuit is selected from the group consisting of a first-in first-out circuit, a last-in first-out circuit, a serial-in-parallel-out shift register circuit, a random access memory Circuit, a read-only memory circuit, a content-addressable memory circuit and a register file.

Example 27 includes the subject matter of any of Examples 24 or 25, and further comprising configurable connection circuitry that includes connection resources for forwarding the first and second vectors to the first and second specialized processing blocks.

Example 28 includes the subject matter of the example 27 wherein the connection resources outside the first and second specialized processing blocks further include vertical connection resources and horizontal connection resources.

Example 29 includes the subject matter of the example 28 and further a plurality of conductive lines.

Example 30 includes the subject of the example 29 and a programmable connection between a first conductive line of the plurality of conductive lines and a second conductive line of the plurality of conductive lines.

Example 31 includes the subject matter of any of Examples 28-30, wherein the vertical and horizontal connection resources pass signals on the integrated circuit.

Example 32 includes the subject of the example 27 The configurable interconnect circuitry further includes a plurality of multiplexers.

Example 33 includes the subject of the example 32 and a multiplexer of the plurality of multiplexers that selects between a first output of a conversion function circuit and a second output of a multiplier stage.

Example 34 includes the subject matter of any of Examples 24, 25, or 27 and further includes a programmable logic area.

Example 35 includes the subject of the example 34 wherein the programmable logic area further includes a plurality of logic blocks selected from the group consisting of logic array blocks and configurable logic blocks.

Example 36 includes the subject of the example 35 wherein at least one logic block of the plurality of logic blocks further includes a plurality of logic block components.

Example 37 includes the subject of the example 36 wherein at least one logic block component of the plurality of logic block components is selected from the group consisting of a lookup table circuit, a register, a slice, an additional adder, and a shift register.

The embodiments described above are presented for purposes of illustration and not of limitation, and the present invention is limited only by the following claims.

Claims (21)

Claimed is: An integrated circuit generating a scalar product of a first and a second vector, comprising: a first specialized processing block providing a first partial result of a first floating point inaccuracy; and a second specialized processing block that receives the first partial result via a cascade connection from the first specialized processing block and comprises: a first floating-point arithmetic operator circuit which generates a second partial result with the first floating-point precision based on a quaternary reduction of two tuples with a second floating-point accuracy from each of the first and second vectors, and a second floating point arithmetic operator circuit that generates the dot product by performing a binary reduction of the first and second part results. Integrated circuit after Claim 1 wherein the first floating point arithmetic operator circuitry further comprises: a first multiplier circuit that generates a first product based on a first tuple of the two tuples from the first vector and a first tuple of the two tuples from the second vector, wherein the first product is the second one Has floating point inaccuracy; and a second multiplier circuit that generates a second product based on a second tuple of the two tuples from the first vector and a second tuple of the two tuples from the second vector, the second product having the second floating point precision. Integrated circuit after Claim 2 wherein the first floating point arithmetic operator circuitry further comprises: an adder circuit that generates a sum of the first and second products, the sum having the second floating point precision. Integrated circuit after Claim 3 wherein the first floating point arithmetic operator circuitry further comprises: a conversion function circuit that receives the sum from the adder circuit and generates the second partial result by converting the sum of the second floating point inaccuracy to the first floating point precision. Integrated circuit after Claim 4 wherein the conversion function circuit increases the exponent size of the sum from the second to the first floating point precision. Integrated circuit after Claim 4 wherein the conversion function circuit adjusts the bias of the exponent of the sum of the bias of the second floating-point inaccuracy to the bias of the second floating-point accuracy. Integrated circuit after Claim 4 wherein the second specialized processing block further comprises: an output port coupled to the second floating point arithmetic operator circuitry; and a bypass path between the adder circuit and the output terminal, the bypass path bypassing the conversion function circuit and the second floating point arithmetic operator circuitry. Integrated circuit after Claim 1 wherein the second floating point arithmetic operator circuitry further comprises: an adder circuit that generates the scalar product by adding the first and second subtotals. A method of operating an integrated circuit that generates a scalar product of a first and a second vector, comprising: Generating a first partial result of a first floating point precision with a first specialized processing block; Providing the first partial result to a cascade output of the first specialized processing block; Receiving the first partial result via a cascade connection from the cascade output of the first specialized processing block at a cascade input of a second specialized processing block; Generating a second partial result with the first floating point precision based on a quaternary reduction of two tuples with a second floating point precision from both the first and second vectors in the second specialized processing block; and Generating the dot product by performing a binary reduction of the first and second part results in the second specialized processing block. Method according to Claim 9 wherein generating the second partial result further comprises: using a first multiplier circuit to generate a first product based on a first tuple to generate the two tuples from the first vector and a first tuple of the two tuples from the second vector, the first product having the second floating point inaccuracy; and using a second multiplier circuit to generate a second product based on a second tuple of the two tuples from the first vector and a second tuple of the two tuples from the second vector, the second product having the second floating point precision. Method according to Claim 10 , further comprising: using an adder circuit to generate a sum of the first and second products, the sum having the second floating point precision. Method according to Claim 11 further comprising: using a conversion function circuit which receives the sum from the adder circuit and generates the second partial result by converting the sum of the second floating-point inaccuracy to the first floating-point precision. Method according to Claim 12 , further comprising: increasing the exponent size of the sum from the second to the first floating point inaccuracy with the conversion function circuit. Method according to Claim 12 , further comprising: adjusting the bias of the exponent of the sum of the bias of the second floating-point precision on the bias of the second floating-point precision with the conversion function circuit. Method according to Claim 12 , further comprising: bypassing the conversion function circuit on a bypass path that couples the adder circuit to an output terminal of the second specialized processing block. A non-transitory machine-readable storage medium configured with instructions for configuring an integrated circuit to produce a scalar product of a first and a second vector, the integrated circuit including first and second specialized processing blocks coupled by a cascade connection, the first one and the second specialized processing block comprises respective first and second floating point arithmetic operator circuitry and configurable interconnect circuitry, the instructions comprising: Instructions for configuring the first floating point arithmetic operator circuitry in the first specialized processing block to produce a first partial result having a first floating point precision based on a first quaternary reduction of the first two tuples with a second floating point precision from both the first and second vectors; Instructions for configuring the configurable interconnect circuitry in the first and second specialized processing blocks to pass the first partial result from the first floating point arithmetic operator circuitry in the first specialized processing block through the cascade circuit to the second arithmetic operator circuitry in the second specialized processing block; Instructions for configuring the first floating-point arithmetic operator circuitry in the second specialized processing block to produce a second partial result with the first floating-point precision based on a second quaternary reduction of the second two-tuples with the second floating-point precision from both the first and second vectors; and Instructions for configuring the second floating point arithmetic operator circuitry in the second specialized processing block to generate the dot product by performing a binary reduction of the first and second part results. Non-transitory machine-readable storage medium according to Claim 16 , further comprising: instructions for generating the instructions Claim 16 , Non-transitory machine-readable storage medium according to Claim 16 wherein the instructions for configuring the first floating-point arithmetic operator circuitry in the first specialized processing block further include instructions for configuring a first multiplier circuit to generate a first product based on a first tuple of the first two tuples from the first vector and a first tuple of the first two Generate tuples from the second vector, the first product having the second floating point inaccuracy; and instructions for configuring a second multiplier circuit to generate a second product based on a second tuple of the first two tuples from the first vector and a second tuple of the first two tuples from the second vector, the second product having the second floating point precision. Non-transitory machine-readable storage medium according to Claim 18 , where the Instructions for configuring the first floating point arithmetic operator circuitry in the first specialized processing block further include: instructions for configuring an adder circuit to produce a sum of the first and second products, the sum having the second floating point precision. Non-transitory machine-readable storage medium according to Claim 19 wherein the instructions for configuring the first floating-point arithmetic operator circuitry in the first specialized processing block further include instructions for configuring a conversion function circuit to generate the second partial result by converting the sum of the second floating-point inaccuracy to the first floating-point precision.

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