DE102018107293A1 - PROCESS FOR MACHINING A SEMICONDUCTOR LAYER AND OPTOELECTRONIC SEMICONDUCTOR CHIP - Google Patents

Abstract

In one embodiment, the method for processing a semiconductor layer sequence comprises a step A), in which a semiconductor layer sequence (1) having a first layer (10), a first marker layer (11), a first intermediate layer (12) and an etch stop layer (13), which are stacked in this order is provided. In a step B), a first etching process is used with which the first layer is etched away in a first predetermined region of the semiconductor layer sequence, wherein etching is carried out at least as far as the first marker layer. In a step C), a signal is detected which signals an impact of a first etchant used in the first etching process on the first marker layer. In a step D), a second etching process is used, with which the intermediate layer is etched away in the first predetermined region, etching up to the etching stop layer and wherein the second etching process is set so that the second etching process is completed before the etching stop layer is completely etched through is.

Description

A method for processing a semiconductor layer sequence is specified. In addition, an optoelectronic semiconductor chip is specified.

An object to be solved is to provide a method for processing a semiconductor layer sequence, by means of which structures, such as mesa trenches or blind holes, can be produced with a high depth uniformity. Another object to be solved is to specify an optoelectronic semiconductor chip which can be produced by such a method.

These objects are achieved by the subject-matter of the independent claims. Advantageous embodiments and further developments are the subject of the dependent claims.

In accordance with at least one embodiment, the method for processing a semiconductor layer sequence comprises a step A), in which a semiconductor layer sequence having a first layer, a first marker layer, a first intermediate layer and an etching stop layer is provided. The said layers are stacked in this order. In particular, these layers all epitaxially grown.

The layers mentioned are all semiconductor layers of the semiconductor layer sequence. Preferably, the said layers have grown directly above one another in this order, without further layers being arranged between them. In particular, the first layer and / or the first intermediate layer may itself consist of several individual layers of different composition.

The semiconductor layer sequence preferably also comprises an active layer for generating electromagnetic radiation. The semiconductor layer sequence is based, for example, on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material such as Al _n In _{1 nm} Ga _m N, or a phosphide compound semiconductor material such as Al _n In _{1 nm} Ga _m P, or an arsenide compound semiconductor material. As Al _n In _1-nm Ga _m As or Al _n In _1-nm Ga _m AsP, wherein each 0 ≦ n ≦ 1, 0 ≦ m ≦ 1 and m + n ≦ 1. In this case, the semiconductor layer sequence may have dopants and additional constituents. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, that is to say Al, As, Ga, In, N or P, are indicated, even if these may be partially replaced and / or supplemented by small amounts of further substances. The semiconductor layer sequence is preferably based on AlInGaN.

The active layer of the semiconductor layer sequence contains in particular at least one pn junction and / or at least one quantum well structure and can, for example, generate electromagnetic radiation in the blue or green or red spectral range or in the UV range during normal operation. The first layer or the first intermediate layer may comprise the active layer.

In accordance with at least one embodiment, the method comprises a step B), in which a first etching process is used with which the first layer is etched away in a first predetermined region of the semiconductor layer sequence, wherein at least until the first marker layer is etched. In particular, it is etched from an upper side of the semiconductor layer sequence in the direction of an underside of the semiconductor layer sequence. In this etching direction, the first layer is arranged in front of the first marker layer.

The first predetermined range can be predetermined, for example, by the use of a mask which is arranged, for example, on the upper side. By way of example, the first predetermined area is an area in which one or more isolation trenches or one or more blind holes are to be created.

In the first etching process, a first etchant is used. During the etching through of the first layer and until reaching the marker layer, the first etchant is preferably not changed. The first etching process is, for example, a dry chemical etching process.

In accordance with at least one embodiment, the method comprises a step C), in which a signal is detected which signals an impact of a first etchant used in the first etching process on the first marker layer. For example, the first marker layer has a specific chemical composition that differs from the chemical composition of at least the first layer. If the first etchant strikes the first marker layer, characteristic particles or molecules or atoms are liberated for the first marker layer which can be measured. Measuring an increase in the concentration of these particles or molecules or atoms then signals the achievement of the first marker layer.

For example, the first layer and the first marker layer are based on AlInGaN, with the first marker layer having a higher proportion of Al having. In the first etching process, the content of released Al and Ga can be measured. As the ratio between Al and Ga increases, this indicates that the first marker layer has been reached.

After detecting the signal that signals the impact of the first etchant used in the first etching process on the first marker layer, the first etching process is terminated, for example.

In accordance with at least one embodiment, the method comprises a step D), in which a second etching process is used with which the intermediate layer is etched away in the first predetermined region, etching to the etch stop layer, and wherein the second etching process is set such that the second etching process is completed before the Ätzstoppschicht is completely etched through.

In the second etching process, a second etchant is used. The second etchant may be different from the first etchant. The second etching process is preferably performed from the same direction as the first etching process. That is, it is in turn etched from the top of the semiconductor layer sequence. For example, the same mask as in the first etching process is used for this purpose. Separation trenches or blind holes created in the first etching process are preferably recessed by the second etching process.

The second etching process is set so that the second etching process is completed before the etching stop layer is completely etched through. That is, the second etching process is not terminated manually, but ends automatically after a predetermined period of time and before the etch stop layer is completely etched through. For example, the etch stop layer for the second etchant has a low etch rate, so that the complete etching through of the etch stop layer takes a longer time. The time period of the second etching process can be predetermined before the second etching process such that the duration of the second etching process is not sufficient to completely etch through the etching stop layer. In particular, layers on a side of the etch stop layer facing away from the upper side are thus not attacked or etched with the second etching process.

In accordance with at least one embodiment, steps A) to D) are carried out in the stated order and / or in succession.

In at least one embodiment, the method for processing a semiconductor layer sequence comprises a step A), in which a semiconductor layer sequence having a first layer, a first marker layer, a first intermediate layer and an etch stop layer, which are stacked in this order, is provided. In a step B), a first etching process is used with which the first layer is etched away in a first predetermined region of the semiconductor layer sequence, wherein etching is carried out at least as far as the first marker layer. In a step C), a signal is detected which signals an impact of a first etchant used in the first etching process on the first marker layer. In a step D), a second etching process is used, with which the intermediate layer is etched away in the first predetermined region, etching up to the etching stop layer and wherein the second etching process is set so that the second etching process is completed before the etching stop layer is completely etched through is.

The present invention is based inter alia on the task of introducing structurings having a high depth uniformity into a semiconductor layer sequence. In the present case, this is achieved, in particular, by the use of an etching stop layer, in which the second etching process ends automatically. Since the etch stop layer has grown epitaxially, its position and homogeneity within the semiconductor layer sequence can be set very precisely. The homogeneity of the etched structure is correspondingly high. So that the second etching process really automatically ends in the etch stop layer, usually the second etchant is selected accordingly. However, the selected second etchant may have disadvantages such as a low etch rate for the layers before the etch stop layer or a small slope of the edges in the resulting structures or the like.

The invention therefore additionally makes use of a first marker layer. As a result, firstly a first etching process can be carried out with a first etching agent, wherein the first etching agent advantageously does not have the abovementioned disadvantages. With this first etchant, it is not necessary to pay attention to a high depth uniformity or to a low etching rate for the etching stop layer, because before the first etchant reaches the etch stop layer, the reaching of the first marker layer is detected by means of a characteristic signal. Then the first etching process is terminated and switched to the second etching process, which ensures the high depth uniformity.

Overall, therefore, a high depth homogeneity with other requirements for the etched structures can be realized by the method used.

In accordance with at least one embodiment, in the second etching process, the etching rate for the first intermediate layer is at least 20 times greater, or at least 40 times greater, or at least 60 times greater than for the etching stop layer. This is especially true also for all single layers of the first intermediate layer. The etchant used in the second etching process is not changed, for example, during the etching through of the first intermediate layer and until the etching stop layer has been reached.

In accordance with at least one embodiment, the first etchant used in the first etching process has a different composition than a second etchant used in the second etching process.

In accordance with at least one embodiment, the etching rate when etching through the first intermediate layer in the second etching process is lower than the etching rate when etching through the first layer in the first etching process. This applies in particular to all individual layers of the first intermediate layer and the first layer. For example, the etching rate for the first layer in the first etching process is at least twice as large, or at least five times as large, or at least ten times greater than the etching rate for the first intermediate layer in the second etching process.

According to at least one embodiment, the etch stop layer is exposed after the second etching process in the entire first predetermined range. Preferably, the exposed etch stop layer extends over the entire first predetermined range. The section of the exposed etch stop layer is preferably continuous, in particular simply coherent. That is, the etch stop layer is completely etched through in the first predetermined area at any point.

For example, the average roughness of the exposed etch stop layer is at most 5 nm or at most 2 nm or at most 1 nm. Preferably, the exposed etch stop layer is flat over the entire first predetermined range.

In accordance with at least one embodiment, at least 2 μm or at least 3 μm or at least 4 μm is etched through the semiconductor layer sequence with steps B) and D) before the etching stop layer is reached. In particular, a distance between the etch stop layer and the upper side of the semiconductor layer sequence is therefore one of the abovementioned values.

In accordance with at least one embodiment, the semiconductor layer sequence is based on a III-nitride semiconductor material. Preferably, all previously mentioned layers of the semiconductor layer sequence are based on such a III-nitride semiconductor material. Most preferably, the III-nitride semiconductor material is AlInGaN.

In accordance with at least one embodiment, the first marker layer and the etch stop layer are based on Al _n Ga _m In _1-mn N, where n ≥ 0.05. The Al content of n ≥ 0.05 is preferably everywhere in the first marker layer and the etch stop layer.

In accordance with at least one embodiment, a dry-chemical etching method is used in each case for the first etching process and the second etching process.

In accordance with at least one embodiment, in addition to the first etching process, fluorine and / or oxygen is additionally added to the etchant for the second etching process. The fluorine and / or oxygen content of the second etchant is therefore greater than that of the first etchant. By way of example, the first etchant of the first etching process is chlorine. The second etchant of the second etching process is, for example, chlorine mixed with fluorine and / or oxygen.

For example, if the etch stop layer comprises Al, then the oxygen of the second etchant may react with the aluminum of the etch stop layer to form alumina, which forms a protective layer against the second etchant within the etch stop layer and thus results in the slow etch rate in the etch stop layer.

In accordance with at least one embodiment, the etch stop layer has a thickness of at least 10 nm or at least 30 nm or at least 50 nm. Alternatively or additionally, the thickness of the etching stop layer may be at most 200 nm or at most 100 nm or at most 80 nm.

In accordance with at least one embodiment, the first marker layer has a thickness of at least 10 nm or at least 30 nm or at least 50 nm. Alternatively or additionally, the thickness of the first marker layer may be at most 200 nm or at most 100 nm or at most 80 nm.

In accordance with at least one embodiment, the first intermediate layer has a thickness of at least 20 nm or at least 100 nm or at least 200 nm. Alternatively or additionally, the thickness of the first intermediate layer may be at most 1000 nm or at most 800 nm or at most 500 nm. The first intermediate layer is preferably in direct contact both with the first marker layer and with the etching stop layer. The distance between the etch stop layer and the first marker layer then corresponds to the thickness of the first intermediate layer.

The thickness of a layer is understood as meaning, for example, the average thickness or the maximum thickness measured along the entire lateral extent of this layer in the semiconductor layer sequence. The lateral extent is the Expansion along a main extension plane of the semiconductor layer sequence.

In accordance with at least one embodiment, the semiconductor layer sequence comprises a second layer on a side of the first etching stop layer which is remote from the first layer. The second layer is likewise a semiconductor layer of the semiconductor layer sequence and can be based on one of the abovementioned materials. The second layer has preferably also grown epitaxially. Furthermore, the second layer may consist of a plurality of individual layers.

In accordance with at least one embodiment, the method comprises a further step E), in which a third etching process is carried out with which the second layer is etched away in a second predetermined region. In the third etching process is preferably etched from the bottom in the direction of the top. That is, in the third etching process, the etching direction is opposite to the etching direction in the first and second etching processes.

The second predetermined range may be different from the first predetermined range. When looking along a growth direction of the semiconductor layer sequence, the first predetermined area and the second predetermined area may overlap each other or be offset from each other. For example, the second predetermined range is greater than the first predetermined range. The second predetermined region may extend over the entire lateral extent of the semiconductor layer sequence, for example.

In the third etching process, a third etchant is used. The third etchant may be the same etchant as the first or second etchant or different from the first and second etchants. For example, during the entire third etching process, the third etchant is not changed.

The step E) is preferably carried out after the step D).

In accordance with at least one embodiment, the third etching process etches to the first etching stop layer. For example, in this case, the third etchant is selected as the second etchant. Furthermore, in this case, the second layer may be in direct contact with the etch stop layer. Within the etch stop layer, the third etching process preferably comes to a standstill, for example by specifying a time period for the third etching process, as described above in connection with the second etching process. In the third etching process, therefore, the etching stop layer is then exposed in the second predetermined region.

In accordance with at least one embodiment, the semiconductor layer sequence comprises a second marker layer between the second layer and the etch stop layer and a second intermediate layer between the etch stop layer and the second marker layer. The second marker layer and the second intermediate layer are also semiconductor layers of the semiconductor layer sequence, for example based on one of the abovementioned materials. The second intermediate layer and the second marker layer have also grown epitaxially. The second intermediate layer can consist of several individual layers of different composition.

The second interlayer may be in direct contact with the second marker layer and the etch stop layer. The second marker layer, in turn, may be in direct contact with the second layer. The thicknesses of the second marker layer and the second intermediate layer may be selected as described in connection with the first marker layer and the first intermediate layer. The second marker layer may be constructed as described in connection with the first marker layer.

In accordance with at least one embodiment, etching is carried out at least until the second marker layer in step E).

In accordance with at least one embodiment, the method comprises a step F), in which a signal is detected that signals an impact of a third etchant used in the third etching process on the second marker layer. The statements made in connection with step C) or the first etching process may apply correspondingly to step F) or the third etching process. Preferably, step F) is carried out after step E).

In accordance with at least one embodiment, the method comprises a step G), in which a fourth etching process is used with which the second intermediate layer is etched away in the second predetermined region, etching up to the etching stop layer and the fourth etching process being set such that the fourth etching process is completed before the etch stop layer is completely etched through. The statements made in connection with step D) or the second etching process can then apply correspondingly to step G) or the fourth etching process. The step G) is carried out in particular after the step F). After the step G), the etching stop layer is preferably exposed in the entire second predetermined range.

In accordance with at least one embodiment, the method further comprises a step H), in which a fifth etching process is carried out with which the etch stop layer is etched away in the second predetermined region, in particular is completely etched away. Step H) is preferably carried out after step E) or after steps F) and G). For example, a different etchant is used for this than in the fourth etching process.

In accordance with at least one embodiment, the method produces a plurality of semiconductor chips, in particular optoelectronic semiconductor chips.

In accordance with at least one embodiment, the semiconductor layer sequence provided in step A) is grown on a growth substrate and still comprises the growth substrate. The growth substrate is, for example, sapphire. The first layer of the semiconductor layer sequence faces away from the growth substrate, and the second layer of the semiconductor layer sequence faces the growth substrate. The second layer is, for example, grown directly on the growth substrate.

In accordance with at least one embodiment, separating trenches between neighboring semiconductor chips to be formed are etched by the first and second etching processes. That is, the first predetermined range corresponds to the position and lateral extent of the separation trenches to be etched. By the separation trenches so the lateral dimensions of the resulting semiconductor chips are given.

According to at least one embodiment, after step D) and before step E), the semiconductor layer sequence is applied to a subcarrier so that the growth substrate faces away from the subcarrier, with the growth substrate subsequently being removed. The growth substrate can be separated for example by means of laser lift-off.

According to at least one embodiment, after step E), for example after step G) or after step H), the semiconductor layer sequence is singulated into a plurality of semiconductor chips. The separation lines then run in particular through the separation trenches.

According to at least one embodiment, blind holes are introduced into the semiconductor layer sequence when steps A) to D) are carried out. After the steps A) to D), the blind holes are laterally, ie parallel to a main extension plane of the semiconductor layer sequence, completely surrounded by the first layer, the first marker layer and the first intermediate layer. The blind holes are filled in the later process, for example, with a metal or other electrically conductive material and then form through holes through the semiconductor layer sequence. The blind holes preferably also penetrate an active layer of the semiconductor layer sequence and after completion are completely laterally surrounded by the active layer.

In addition, an optoelectronic semiconductor chip is specified. The optoelectronic semiconductor chip can be produced, for example, by the method just described. That is, all features disclosed in connection with the method are also disclosed for the optoelectronic semiconductor chip and vice versa.

In accordance with at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor layer sequence with a first layer, a first marker layer, a first intermediate layer and an etch stop layer, which are stacked in this order.

In accordance with at least one embodiment, the semiconductor chip comprises an active layer in which electromagnetic radiation is generated during normal operation of the semiconductor chip. The active layer is part of the semiconductor layer sequence.

According to at least one embodiment, based the first marker layer and the etch stop layer in each case on Al _n Ga _m In ₁ - _mn N, n being ≥ 0.05.

In accordance with at least one embodiment, the first intermediate _layer is based on Al _x Ga _y In _{1- y x} N, wherein the Al content is smaller than in the first marker layer and the etching stop layer. This preferably also applies to all individual layers of the first intermediate layer.

According to at least one embodiment, a distance between the first marker layer and the etch stop layer is between 20 nm and 1000 nm inclusive.

According to at least one embodiment, a blind hole is introduced into the semiconductor layer sequence, which extends through the first marker layer and opens into the etching stop layer. Laterally, the blind hole is preferably completely surrounded by the marker layer, the first intermediate layer and the active layer.

Hereinafter, a method described here for processing a semiconductor layer sequence as well as an optoelectronic semiconductor chip described herein with reference to drawings using exemplary embodiments will be explained in more detail. The same reference numerals indicate the same elements in the individual figures. However, no scale relationships are shown here, Rather, individual elements may be exaggerated in size for better understanding.

• 1A bis 1C verschiedene Positionen in einem ersten Ausführungsbeispiel des Verfahrens,
• 2A bis 2G verschiedene Positionen in einem zweiten Ausführungsbeispiel des Verfahrens,
• 3 ein Ausführungsbeispiel eines optoelektronischen Halbleiterchips in Querschnittsansicht.

Show it:

• 1A to 1C different positions in a first embodiment of the method,
• 2A to 2G different positions in a second embodiment of the method,
• 3 an embodiment of an optoelectronic semiconductor chip in cross-sectional view.

In the 1A is shown a first position in a first embodiment of the method for processing a semiconductor layer sequence. A semiconductor layer sequence 1 with a top 20 and an underside opposite the top 21 is provided. The semiconductor layer sequence 1 includes starting from the bottom 21 a second layer 16 , an etch stop layer 13 , a first intermediate layer 12 , a first marker layer 11 and a first layer 10 , All of these layers are based on a semiconductor material, in this case for example AlInGaN. The layers mentioned are arranged one above the other in the stated order and grown epitaxially. The bottom 21 the semiconductor layer sequence 1 is for example grown on a growth substrate, in particular sapphire (not shown).

In the 1B a second position of the method is shown. On the top 20 the semiconductor layer sequence 1 is a mask 3 , For example, a photomask applied. The mask 3 includes a hole defining a first region in which the semiconductor layer sequence 1 should be etched. The predetermined first area defines, for example, a region in which a separation trench is created by the etching process 23 or a blind hole 22 should arise.

Furthermore, in the 1B shown a first etching process (indicated by the arrow), starting from the top 20 is carried out. The first etching process becomes the first layer 10 etched through in the first predetermined region and at least until the first marker layer 11 etched. The first etching process is, for example, a dry chemical etching process using as a first etchant, for example, chlorine.

Once the first etchant of the first etching process, the first marker layer 11 is reached, a signal is detected, which signals that the first etchant, the first marker layer 11 has reached. In the present case, the Al content is in the first marker layer 11 for example, greater than the Al content in the first layer 10 , For example, during the first etching process, the ratio of Al atoms released by the first etching process to Ga atoms is measured. An increase in this ratio signals the impact of the first etchant on the first marker layer 11 , Subsequently, the first etching process is terminated.

The first etching process may, for example, be chosen to be the first intermediate layer 10 etched particularly quickly or a particularly high slope on the flanks of the separation trench 23 or the blind hole 22 is reached.

In the right picture of the 1B is shown in the left image by a dashed box framed section enlarged. It can be seen that a low depth uniformity is achieved with the first etching process.

In the 1C a third position of the method is shown, in which a second etching process is performed, which follows the first etching process. The second etching process may again be a dry chemical etching process. Compared with the first chlorine etchant, the second etchant can be a mixture of chlorine and oxygen / fluorine.

With the second etching process, the second intermediate layer becomes 12 up to the etching stop layer 13 etched. The second etching process is set so that the second etching process is completed before the etching stop layer 13 completely etched through. For example, the etch stop layer 13 an at least 20 times lower etch rate for the second etchant than the first interlayer 12 such that in a predetermined period of time for the second etching process, the etch stop layer 13 can not be etched through by the second etchant. This includes the etch stop layer 13 For example, an Al content of more than 5% and a thickness of at least 10 nm.

In the right picture of the 1C the section in the left picture with the dashed box is enlarged. It can be seen that with the second etching process, the etch stop layer 13 is exposed in the first predetermined area. The second etching process is performed by the etch stop layer 13 stopped and the etch stop layer 13 is hardly etched through. Because the etch stop layer 13 has grown epitaxially, their uniformity and position within the semiconductor layer sequence is set very precisely. The depth uniformity of the structure produced by the etching processes in the semiconductor layer sequence is correspondingly high 1 ,

In the 2A a first position is shown in a second embodiment of the method. Again, first is a semiconductor layer sequence 1 provided. In addition to those related to the 1A said layers comprises this semiconductor layer sequence 1 on one of the top 20 opposite side of the etch stop layer 13 still a second intermediate layer 14 and a second marker layer 15 , The semiconductor layer sequence 1 is on a growth substrate 18 , for example sapphire, grew up.

In the 2 B and 2C Positions are shown in which the first etching process and the second etching process are performed. In the present case, with the first etching process and the second etching process in the first predetermined area separation trenches 23 formed between emerging semiconductor chips.

In the position of 2D is the semiconductor layer sequence 1 with the formed separating trenches 23 to a subcarrier 2 applied, such that the second layer 16 the subcarrier 2 turned away. The growth substrate 18 is replaced, for example by means of a laser lift-off process.

In the position of 2E a third etching process is applied, in which in a second predetermined range starting from the bottom 21 the semiconductor layer sequence 1 through the second layer 16 towards the top 20 at least until the second marker layer 15 is etched. In the present case, the second predetermined range is the entire lateral extent of the semiconductor layer sequence 1 educated. That is, the first layer 16 becomes everywhere on the semiconductor layer sequence 1 etched through or etched away.

In the third etching process, a signal is again detected, which is the impact of the third etchant used in the third etching process on the second marker layer 15 signaled. These can be the second marker layer 15 and the third etchant, as in the context of the first marker layer 11 and the first etchant described. During or after reaching the second marker layer 15 the third etching process is ended.

In the position of 2F is converted to a fourth etching process, with the second intermediate layer in the second predetermined area 14 is etched through or etched away and until the etch stop layer 13 is etched. The fourth etching process is performed, for example, analogously to the second etching process. That is, the fourth etching process is again selected so that the fourth etching process comes to a halt in the etching stop layer. For example, in the fourth etching process, the same etchant as in the second etching process is used.

After the fourth etching process, the etch stop layer is exposed in the entire second predetermined range.

In the 2G a position is shown in which by means of a fifth etching process, the etch stop layer 13 is etched away. This is the originally contiguous semiconductor layer sequence 1 into a plurality of individual semiconductor chips 100 divided by each other through the etched separation trenches 23 are spaced. Due to the method used, all semiconductor chips 100 almost identical thicknesses.

In the 3 is an embodiment of an optoelectronic semiconductor chip 200 shown. The optoelectronic semiconductor chip 200 includes one related to the 2A specified semiconductor layer sequence 1 , The first shift 10 the semiconductor layer sequence 1 further comprises an active layer 17 , in the normal operation of the optoelectronic semiconductor chip 200 electromagnetic radiation, for example in the blue spectral range or in the UV range, is generated.

The semiconductor layer sequence 1 has a blind hole 22 on, starting from the top 20 the semiconductor layer sequence 1 through the first layer 10 including the active layer 17 , through the first marker layer 11 and the first intermediate layer 12 extends and into the etch stop layer 13 empties. A bottom surface of the blind hole 22 is through the etch stop layer 13 educated. The blind hole 22 For example, with the related to the 1A to 1C explained method in the semiconductor layer sequence 1 be introduced. The blind hole 22 may be further filled with electrically conductive material to realize an electrical via.

The invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if these features or this combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

1

Semiconductor layer sequence

2

subcarrier

3

mask

10

first shift

11

first marker layer

12

first intermediate layer

13

etch stop layer

14

second intermediate layer

15

second marker layer

16

second layer

17

active layer

18

growth substrate

20

top

21

bottom

22

blind

23

separating trench

100

Semiconductor chip

200

optoelectronic semiconductor chip

Claims (17)

Method for processing a semiconductor layer sequence (1), comprising the steps: A) providing a semiconductor layer sequence (1) having a first layer (10), a first marker layer (11), a first intermediate layer (12) and an etch stop layer (13) stacked in this order; B) applying a first etching process, with which the first layer (10) is etched away in a first predetermined region of the semiconductor layer sequence (1), wherein at least until the first marker layer (11) is etched; C) detecting a signal indicative of an impact of a first etchant used in the first etching process on the first marker layer (11); D) applying a second etching process by etching away the intermediate layer (12) in the first predetermined region, etching to the etch stop layer (13), and setting the second etching process such that the second etching process is completed before the etch stop layer (13) is completely etched through. Method according to Claim 1 In the second etching process, the etching rate for the first intermediate layer (12) is at least 20 times greater than for the etching stop layer (13). Method according to Claim 1 or 2 wherein the first etchant used in the first etching process has a different composition than a second etchant used in the second etching process. Method according to one of the preceding claims, wherein the etching rate when etching through the first intermediate layer (12) in the second etching process is lower than the etching rate when etching through the first layer (10) in the first etching process. Method according to one of the preceding claims, wherein the etching stop layer (13) after the second etching process in the entire first predetermined range is exposed. Method according to one of the preceding claims, wherein with the steps B) and D) at least 2 microns is etched through the semiconductor layer sequence (1) before the Ätzstoppschicht (13) is reached. Method according to one of the preceding claims, wherein - the semiconductor layer sequence (1) is based on a III-nitride semiconductor material, - the first marker layer (11) and the etch stop layer (13) are based on Al _n Ga _m In _1-mn N, where n ≥ 0.05. Method according to one of the preceding claims, wherein a dry-chemical etching process is used in each case for the first etching process and the second etching process, - For the second etching process compared to the first etching process additionally fluorine and / or oxygen is added to the etchant. Method according to one of the preceding claims, wherein the etching stop layer (13) has a thickness of at least 10 nm, the first marker layer (11) has a thickness of at least 10 nm, - The first intermediate layer (12) has a thickness between 20 nm and 1000 nm inclusive. Method according to one of the preceding claims, wherein - the semiconductor layer sequence (1) comprises a second layer (16) on a side of the first etching stop layer (12) facing away from the first layer (10), the method further comprises the step of: E) applying a third etching process, with which the second layer (16) is etched away in a second predetermined region. Method according to Claim 10 wherein in the third etching process is etched to the first Ätzstoppschicht (13). Method according to Claim 10 in which - the semiconductor layer sequence (1) comprises a second marker layer (15) between the second layer (16) and the etch stop layer (13) and a second intermediate layer (14) between the etch stop layer (13) and the second marker layer (15), in step E) is etched at least as far as the second marker layer (15), the method further comprises the steps: F) detecting a signal indicative of an impact of a third etchant used in the third etching process on the second marker layer (15); G) applying a fourth etching process, with which the second intermediate layer (14) is etched away in the second predetermined region, etching up to the etch stop layer (13), and wherein the fourth etching process is set so that the fourth etching process is completed before the etch stop layer (13) is fully etched through. Method according to one of Claims 11 or 12 further comprising a step H), in which a fifth etching process is performed, with which the etching stop layer (13) is etched away in the second predetermined region. Method according to one of Claims 10 to 13 , with which a plurality of semiconductor chips (100) is produced, wherein - the semiconductor layer sequence (1) provided in step A) is grown on a growth substrate (18), the first layer (10) facing away from the growth substrate (18) and the second Layer (16) facing the growth substrate (18), - are etched by the first and second etching process separation trenches (23) between neighboring semiconductor chips (100) to be etched, - after step D) and before step E) the semiconductor layer sequence ( 1) is applied to a subcarrier (2) so that the growth substrate (18) faces away from the subcarrier (2), the growth substrate (18) being subsequently removed, after the step E) the semiconductor layer sequence (1) into a plurality of Semiconductor chips (100) is isolated. Method according to one of the preceding claims, wherein with the implementation of steps A) to D) blind holes (22) are introduced into the semiconductor layer sequence (1). An optoelectronic semiconductor chip (200) comprising: - a semiconductor layer sequence (1) having a first layer (10), a first marker layer (11), a first intermediate layer (12) and an etch stop layer (13) stacked in this order; - An active layer (17) in which electromagnetic radiation is generated during normal operation of the semiconductor chip (200); wherein - the first marker layer (11) and the etch stop layer (13) are each based on Al _n Ga _m In _1-mn N, where n ≥ 0.05, - the first intermediate _layer is based on Al _x Ga _y In _{1- y x} N. wherein the Al content is none other than in the first marker layer (11) and the etch stop layer (13), a distance between the first marker layer (11) and the etch stop layer (13) is between 20 nm and 1000 nm inclusive. Optoelectronic semiconductor chip (200) according to Claim 16 , wherein in the semiconductor layer sequence (1) a blind hole (22) is introduced, which extends through the first marker layer (11) and opens into the Ätztoppschicht (13).

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