DE102018106680A1 - Optoelectronic semiconductor chip and method for producing an optoelectronic semiconductor chip - Google Patents

Abstract

The invention relates to an optoelectronic semiconductor chip (1) comprising a semiconductor body comprising a first semiconductor region (5) and a second semiconductor region (4), a plurality of first recesses (12) extending through the first semiconductor region (5) and each having a bottom surface on which the second semiconductor region (4) is exposed, and- a first electrically insulating separation layer (15) and a second electrically insulating separation layer (16), wherein the first recesses (12) are laterally spaced from each other, - first recesses (12) each having at least a first side surface (12a) and at least a second side surface (12b), - the first side surface (12a) is covered by the first separation layer (15) and is in direct contact therewith and the second side surface (12b) is partially covered by and in direct contact with the second separating layer (16), and the first and second separating layers (16) 15, 16) have different material compositions.

Description

An optoelectronic semiconductor chip is specified. Furthermore, a method for producing an optoelectronic semiconductor chip is specified.

An object to be solved is to provide an optoelectronic semiconductor chip having an improved efficiency. Another object to be solved is to specify a method with which such an optoelectronic semiconductor chip can be produced.

An optoelectronic semiconductor chip is specified. The optoelectronic semiconductor chip emits electromagnetic radiation, in particular visible light, during operation, for example. The optoelectronic semiconductor chip is, for example, a light-emitting diode chip, in short an LED chip or a laser diode chip.

In accordance with at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor body, comprising a first semiconductor region and a second semiconductor region. The semiconductor body is, for example, an epitaxially grown semiconductor body. The semiconductor body may be based on a III-V compound material. The semiconductor body may, for example, comprise an active region which is designed to generate the electromagnetic radiation.

The semiconductor body comprises, for example, the first semiconductor region of a first conductivity type and the second semiconductor region of a second, different conductivity type. For example, the first semiconductor region is n-doped and thus n-type and the second semiconductor region is p-doped and thus p-type.

Between the first semiconductor region and the second semiconductor region, the active region is arranged. For example, the active region directly adjoins the two semiconductor regions. The semiconductor body, in particular the two semiconductor regions and the intermediate active region, has a main extension plane. The semiconductor body has a growth direction transverse or perpendicular to the main plane of extension.

In accordance with at least one embodiment, the optoelectronic semiconductor chip comprises a multiplicity of first recesses which extend through the first semiconductor region and each have a bottom surface on which the second semiconductor region is exposed. That is, the first recesses completely penetrate the first semiconductor region. The first semiconductor region is in the region of the recess, so completely removed and is broken through the first recesses. Further, the first recesses completely break through the active area. The bottom surfaces are formed by a part of the second semiconductor region. The first recesses may, for example, have a rectangular, round or oval-shaped cross-sectional area that runs parallel to the main extension direction of the semiconductor body.

The first recesses only partially penetrate the second semiconductor region. That is, in the region of the first recesses, the second semiconductor region is only removed to a certain depth. For example, it is possible for the first recesses to not completely penetrate the second semiconductor region at any point. The second semiconductor region is then only partially removed and not broken through by the first recesses.

In accordance with at least one embodiment, the optoelectronic semiconductor chip comprises a first electrically insulating separating layer and a second electrically insulating separating layer. That is, the first separation layer and the second separation layer are formed to block a current flow. The first separating layer and the second separating layer may, for example, be in direct and direct contact with the bottom surface and thus with the second semiconductor region. The separating layers are each formed with an electrically insulating, for example dielectric, material.

In accordance with at least one embodiment, the first recesses are laterally spaced from each other. That is, the first recesses are spaced apart parallel to the main plane of extension. The first recesses may, for example, be arranged along lines or in a matrix, that is to say arranged along rows and columns. The first recesses may be arranged, for example, at grid points of a regular grid. Alternatively, it is possible that the first recesses are arranged along curved curves.

In accordance with at least one embodiment, the first recesses each have at least one first side surface and at least one second side surface. The at least one first side surface and the at least one second side surface are formed, for example, by the first semiconductor region and the second semiconductor region.

For example, if the first recesses have a rectangular cross-sectional area that is parallel to the main extension direction of the semiconductor body, the first recesses each have four side surfaces. In this case are two opposing side surfaces formed by the first side surface and the second side surface, respectively.

Alternatively, it is possible that the first recesses have a round cross-sectional area that runs parallel to the main extension direction of the semiconductor body. The first recesses then each have only one side surface, for example. In this case, a circumference of the first recesses is divided, for example, into four equal areas. The opposing regions are then formed, for example, by the first side surface or the second side surface.

Furthermore, it is possible that the first recesses have, for example, an oval cross-sectional area which runs parallel to the main extension direction of the semiconductor body. The first recesses then each have only one side surface. The opposite side surfaces of a major axis then correspond, for example, the first side surface and the opposite side surfaces of a minor axis correspond, for example, the second side surface.

In accordance with at least one embodiment, the first side surface is covered by the first separation layer and is in direct contact therewith. In addition, the second side surface of the second separation layer is partially covered and is in direct contact with this. For example, the first separation layer has a main surface completely covering the first side surface. In addition, the at least one side surface of the first separating layer, which is transverse to the main surface, at least partially cover the second side surface and are in direct contact therewith. The second side surface, which is not covered by the first separation layer, may for example be completely covered by the second separation layer.

The first separating layer advantageously protects the first and regionally the second side surface against chemical and mechanical damage and forms an electrical insulation of the side surfaces. The second separating layer advantageously protects the second side area from chemical and mechanical damage in some areas and partially forms an electrical insulation of the second side area.

In accordance with at least one embodiment, the first and second separating layers have different material compositions. The first and second separating layers have, for example, at least one electrically insulating material or consist thereof. The electrically insulating material and / or the material composition of the electrically insulating material are different for the first and second separating layers.

In at least one embodiment, the optoelectronic semiconductor chip comprises a semiconductor body comprising a first semiconductor region and a second semiconductor region, a plurality of first recesses extending through the first semiconductor region and each having a bottom surface on which the second semiconductor region is exposed, and a first electrically insulating separating layer and a second electrically insulating separating layer, wherein the first recesses are laterally spaced apart, the first recesses each having at least a first side surface and a second side surface, the first side surface is covered by the first separation layer and in direct contact with the second side surface is covered by and in direct contact with the second separation layer, and the first and second separation layers have different material compositions.

In order to energize the second semiconductor region, the first and partly the second semiconductor region may be removed over a continuous region. In this remote area, the active area is completely removed and is no longer available for light generation.

The optoelectronic semiconductor chip described here now makes use, inter alia, of the idea that the first and in some cases the second semiconductor region are only partially removed. That is, the removed areas are discontinuous and only separate recesses break through the active area.

This will remove less area of the active area. Advantageously, the area of the active area for a semiconductor chip with an area of 1.2 mm ² increases by 1.8% and for a semiconductor chip with an area of 0.5 mm ² by 2.1%. In addition, the side surfaces of the recesses are electrically insulated by two different separating layers.

In accordance with at least one embodiment, the first separation layer is a mirror layer. In particular, the mirror layer is a dielectric mirror or preferably a Bragg mirror. The Bragg mirror comprises, for example, alternately arranged layers of a high-refractive and a low-refractive material. The Bragg mirror is then formed, for example, electrically insulating.

The Bragg mirror preferably has a reflectivity of at least 90% for the electromagnetic radiation generated in the active region.

In accordance with at least one embodiment, the second separating layer is a light-permeable passivation layer. The passivation layer is transparent, for example, for the electromagnetic radiation generated during operation of the optoelectronic semiconductor chip. The passivation layer comprises, for example, a transparent, electrically insulating material or consists thereof. The transparent, electrically insulating material may comprise, for example, silicon nitride, silicon dioxide, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and / or niobium oxide or consist of one of the materials mentioned.

In accordance with at least one embodiment, the first and the second separating layer are in direct contact with one another. A major surface of the first separation layer which is not in contact with the first sidewall may be in direct and direct contact with the second separation layer in regions. The side surfaces are thereby advantageously completely electrically isolated.

In accordance with at least one embodiment, a Bragg mirror layer is arranged in places on the first semiconductor region. The Bragg mirror layer comprises, for example, alternately arranged layers of a high-refractive and a low-refractive material. The Bragg mirror layer is then formed, for example, electrically insulating.

The Bragg reflector layer preferably has a reflectivity of at least 90% for the electromagnetic radiation generated in the active region.

Furthermore, the Bragg mirror layer is in direct and direct contact with the first semiconductor region and covers it in regions. By way of example, the Bragg mirror layer is formed integrally and extends, for example, along a path or along a multiplicity of paths parallel to the main extension plane of the holder body. For example, the web or webs have a substantially constant width. Substantially constant means that the width may vary due to manufacturing tolerances.

In accordance with at least one embodiment, a current spreading layer completely covers the first semiconductor region and the Bragg mirror layer. The current spreading layer is transparent, for example, for the electromagnetic radiation generated during operation of the optoelectronic semiconductor chip. In addition, the current spreading layer is formed of a transparent, electrically conductive material. The current spreading layer has, for example, transparent conductive metals or transparent conductive oxides ("TCO" for short). TCOs are transparent, conductive materials and include, for example, zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide or indium tin oxide (ITO). In addition to binary metal oxygen compounds, such as ZnO, SnO2 or In2O3, ternary metal oxygen compounds such as Zn2SnO4, CdSnO3, ZnSnO3, MgIn204, GaInO3, Zn2In2O5 or In4Sn3O12 or mixtures of different transparent conductive oxides also belong to the group of TCOs.

For example, the current spreading layer is in direct and direct contact with the first semiconductor region and the Bragg mirror layer. The current spreading layer terminates in lateral directions, for example, flush with the first semiconductor region. In addition, the current spreading layer covers an outer surface of the Bragg mirror layer that is not covered by the first semiconductor region.

In accordance with at least one embodiment, the first separation layer is arranged in regions on the current spreading layer. The current spreading layer is also broken by the plurality of first recesses, for example. That is, the at least one first side surface and the at least one second side surface are formed by the first semiconductor region, the second semiconductor region, and the current spreading layer. For example, a plurality of regions of the current spreading layer lying between adjacent first recesses is covered with the first separation layer, for example. In addition, the at least one first side surface of the recesses of the current spreading layer is covered by the first separating layer. The first separating layer stands, for example, in direct and direct contact with the current spreading layer.

In accordance with at least one embodiment, the current spreading layer is covered in regions by the second separating layer. For example, the second separation layer covers the areas of the current spreading layer that are not covered by the first separation layer. The second separating layer terminates in lateral directions, for example, flush with the current spreading layer and thus completely covers a top surface of the current spreading layer. In addition, the at least one second side surface of the recesses of the current spreading layer is covered by the first separation layer. The second separating layer is in, for example direct and immediate contact with the current spreading layer.

In accordance with at least one embodiment, a cover surface of the first separating layer is covered in regions by the second separating layer. For example, the second release layer does not completely cover the top surface of the first release layer. The second separating layer is on the top surface of the first separating layer, for example in direct and direct contact with the first separating layer.

In accordance with at least one embodiment, the second separating layer is interrupted by at least two second recesses. The second recesses are each formed contiguous. For example, the at least two second recesses comprise a second recess and a further second recess. It is possible that the second recess completely breaks through the second separating layer over the first separating layer, which is arranged between adjacent first recesses. A width of the second recess is less than a width of the first separating layer.

The width corresponds in each case to a smallest extent of a cross-sectional area of the second recess or the first separation layer in a direction parallel to the main extension plane at the level of the active area. That is, the width is in each case the distance between, for example, two opposite inner sides of the second recess or the first separation layer, parallel to the main extension plane of the semiconductor body.

In addition, the second recess breaks through the second separating layer between adjacent first separating layers and thus exposes the second semiconductor body in regions. The region where the second semiconductor body is exposed forms a plurality of third recesses. In particular, the plurality of third recesses is a part of the second recesses.

Furthermore, it is possible that the further second recess completely breaks through the second separating layer over the Bragg mirror layer. A bottom of the further second recess is then formed by the current spreading layer. A width of the further second recess is less than a width of the Bragg mirror layer. In addition, a length of the further second recess may be smaller than a length of the Bragg mirror layer.

In accordance with at least one embodiment, a cross-sectional area of the plurality of third recesses exposing the second semiconductor body is smaller than a cross-sectional area of the plurality of first recesses. For example, the third recesses each have at least a third side surface formed by the first separation layer and a fourth side surface formed by the second separation layer.

The cross-sectional area of the third recesses is formed by an average width and an average length of the third recesses parallel to the main extension plane at the level of the active area. The cross-sectional area of the first recesses is formed by an average width and an average length of the first recesses parallel to the main extension plane at the level of the active area. Preferably, the average width and the average length of the third recesses are formed smaller than the average width and the average length of the first recesses.

The plurality of third recesses is arranged, for example, respectively in the center of the plurality of first recesses. That is, the cross-sectional area of the third recesses is arranged in plan view in each case completely over the cross-sectional area of the recesses.

In accordance with at least one embodiment, an electrically conductive connection layer is arranged in the at least two second recesses. The connection layer is arranged, for example, in the second recesses, which expose the mirror layer and the second semiconductor body in regions and has the third recesses. The connection layer is in these areas, for example, in direct and direct contact with the mirror layer of the second semiconductor body. Advantageously, the second semiconductor body can be supplied with current through the electrically conductive connection layer. By the first and second separation layer, the connection layer is electrically insulated from the side surfaces and short circuits are prevented.

Furthermore, it is possible that the connection layer of the further second recess is in direct and direct contact with the current spreading layer. Advantageously, an energization of the first semiconductor region via the connection layer and the current spreading layer is possible.

In addition, a method for producing an optoelectronic semiconductor chip is specified. This method is suitable for producing an optoelectronic semiconductor chip described here. That is, an optoelectronic semiconductor chip described here can be produced by the method described or is produced by the described method. All in Therefore, features disclosed in connection with the optoelectronic semiconductor chip are also disclosed in connection with the method and vice versa.

According to at least one embodiment, the method comprises the step of providing a semiconductor wafer comprising a first semiconductor region and a second semiconductor region. The semiconductor wafer is, for example, an epitaxially grown semiconductor wafer. That is, the first semiconductor region and the second semiconductor region may be epitaxially deposited, for example. In addition, the semiconductor wafer may comprise a carrier. The carrier represents, for example, the mechanically supporting component of the semiconductor wafer.

In accordance with at least one embodiment, the method comprises the step of applying a first structured sacrificial layer to the semiconductor wafer by means of a first mask. The sacrificial layer is produced, for example, by sputtering or vapor deposition on an upper side of the semiconductor wafer.

In accordance with at least one embodiment, the first mask has a plurality of non-contiguous first apertures. For example, the first diaphragms prevent the first sacrificial layer from being applied to the semiconductor wafer. That is, the semiconductor wafer is not covered with the first patterned sacrificial layer below the first aperture and thus forms a first plurality of first recesses in the sacrificial layer. The first recesses then have, for example, the shape of the first panels. In particular, due to the manufacturing process, a cross-sectional area parallel to the main extension plane of the first recesses is greater than a cross-sectional area parallel to the main extension plane of the first apertures.

The diaphragms may, for example, have a rectangular, round or oval-shaped cross-sectional area which runs parallel to the main extension direction of the semiconductor body.

In accordance with at least one embodiment, the method comprises the step of generating a multiplicity of first recesses in the semiconductor wafer below the first diaphragms. The material removal of the first recesses can be produced, for example, by etching. The semiconductor wafer covered, for example, by the first patterned sacrificial layer is not removed by the etching.

According to at least one embodiment, the first recesses extend through the first semiconductor region and each have a bottom surface on which the second semiconductor region is exposed.

In accordance with at least one embodiment, the method comprises the step of applying a second patterned sacrificial layer to the semiconductor wafer by means of a second mask. The second sacrificial layer is produced, for example, by sputtering or vapor deposition on an upper side of the semiconductor wafer.

In accordance with at least one embodiment, the second mask has a plurality of non-contiguous second diaphragms. The second diaphragms, for example, prevent the second sacrificial layer from being applied to the semiconductor wafer. That is, the semiconductor wafer is not covered below the second aperture with the second patterned sacrificial layer and thus forms a first plurality of second recesses in the sacrificial layer. The second recesses then have, for example, the shape of the second diaphragm. In particular, due to the production, a cross-sectional area parallel to the main extension plane of the second recesses is larger than a cross-sectional area parallel to the main extension plane of the second apertures.

By way of example, the second diaphragms can have a rectangular, round or oval-shaped cross-sectional area which runs parallel to the main extension direction of the semiconductor body.

In particular, the second diaphragms are displaced relative to the first diaphragms such that the second recesses are arranged between adjacent first recesses. In this case, the second recesses overlap in plan view in each case with a first side surface of the first recesses. That is, each second recess includes two first side surfaces each of two adjacent first recesses and an area interposed therebetween. This area may include, for example, a current spreading layer.

In accordance with at least one embodiment, the method comprises the step of applying a first separation layer under the second diaphragms. The first separation layer is applied, for example, by sputtering, vapor deposition, chemical vapor deposition (CVD) or a sol-gel process.

In accordance with at least one embodiment, the method comprises the step of applying a second separation layer to the semiconductor wafer. This step is preferably carried out after the application of the first separating layer and after removal of the second sacrificial layer. The second separation layer is for example by means of a applied chemical vapor deposition process.

In accordance with at least one embodiment, the method comprises the step of singulating to a plurality of the optoelectronic semiconductor chips. The semiconductor wafer is separated, for example, by cuts parallel to the growth direction through the semiconductor wafer to optoelectronic semiconductor chips.

In accordance with at least one embodiment, the method comprises the step, after the application of the second separating layer, of applying a third structured sacrificial layer to the second separating layer by means of a third mask. The third sacrificial layer is produced, for example, by sputtering or vapor deposition on an upper side of the semiconductor wafer.

In accordance with at least one embodiment, the third mask has a multiplicity of contiguous third diaphragms. For example, the third diaphragms prevent the third sacrificial layer from being applied to the second separating layer. That is, the second separation layer is not covered with the third structured sacrificial layer below the second diaphragms and thus forms a first plurality of third recesses in the third sacrificial layer. The third recesses then have, for example, the shape of the third diaphragm. In particular, due to the manufacturing process, a cross-sectional area parallel to the main extension plane of the third recesses is larger than a cross-sectional area parallel to the main extension plane of the third apertures.

In accordance with at least one embodiment, the method comprises the step of generating a plurality of second recesses in the second separation layer below the third diaphragms. The material removal of the second recesses can be produced, for example, by etching. The second separation layer, which is covered, for example, by the third patterned sacrificial layer, is not removed by the etching.

In accordance with at least one embodiment, the second recesses extend through the second separating layer. The second separating layer is completely removed, for example, in the region of the second recesses.

In the following, the optoelectronic semiconductor chip and the method for producing an optoelectronic semiconductor chip will be explained in more detail on the basis of exemplary embodiments and the associated figures.

1A . 1B . 2A . 2 B . 3A . 3B . 4A . 4B . 5A . 5B . 6A . 6B . 7A . 7B . 7C . 8A . 8B . 9A . 9B . 9C . 10A . 10B . 11A . 11B . 12A . 12B . 13A . 13B . 13C . 14A . 14B . 15A . 15B . 16A . 16B . 16C . 17A . 17B . 18A . 18B and 18C show schematic sectional views of method steps of an embodiment of a method for producing an optoelectronic semiconductor chip.

In particular, in conjunction with the 18A . 18B and 18C an embodiment of an optoelectronic semiconductor chip described here.

The same, similar or equivalent elements are provided in the figures with the same reference numerals. The figures and the proportions of the elements shown in the figures with each other are not to be considered to scale. Rather, individual elements may be exaggerated in size for better representability and / or better intelligibility.

In conjunction with the 1A to 18C , is an exemplary embodiment of a manufacturing method for optoelectronic semiconductor chips described here 1 shown in a schematic sectional view. In conjunction with the 2A to 17A in each case a plan view of the respective method step is shown and with the 2 B to 13B and 13C and FIGS. 15B to 18B and 18C are a sectional view, respectively. In conjunction with the 7C . 9C and 16C in each case an enlargement of the respective plan views is shown.

According to the 1A and 1B becomes a semiconductor wafer in a first process step 2 provided a first semiconductor region 5 and a second semiconductor region 4 includes. Here, the first semiconductor region 5 for example, p-doped and the second semiconductor region 4 n-doped. The first semiconductor area 5 is here on the second semiconductor area 4 arranged. In addition, the two semiconductor regions 4 and 5 for example, on a carrier 3 be arranged.

As in the 2A and 2 B is shown, in a next process step, a fourth sacrificial layer 6 applied to the semiconductor wafer by means of a fourth mask. The fourth sacrificial layer 6 here has four recesses 7 on. The fourth sacrificial layer 6 is generated for example by sputtering or vapor deposition.

According to the 3A and 3B In a next process step, a Bragg mirror layer is formed 8th on the fourth sacrificial layer 6 and on the exposed first semiconductor region 5 applied.

According to the 4A and 4B becomes the fourth sacrificial layer in a next process step 6 removed by, for example, chemical etching. The Bragg mirror layer 8th on the fourth sacrificial layer 6 is also removed by the etching. The Bragg mirror layer 8th is then in places on the first semiconductor region 5 is arranged.

As in the 5A and 5B is shown, in a next process step, a current spreading layer 9 over the semiconductor wafer 2 applied. The current spreading layer 9 covers the first semiconductor region 5 and the Bragg mirror layer 8th completely.

In a next process step is in connection with the 6A and 6B a first structured sacrificial layer 10 shown above the semiconductor wafer 2 is applied by means of a first mask. The first sacrificial layer 10 has first recesses 11 which are not contiguous and laterally spaced from each other.

According to the 7A and 7B In a next method step, a plurality of the first recesses 12 in the semiconductor wafer 2 generated. The areas under the first sacrificial layer 10 are arranged are not removed here. The material removal is produced for example by chemical etching. The first recesses 12 thereby extend through the first semiconductor region 5 and each have a bottom surface on which the second semiconductor region 4 exposed. In addition, the first recesses are laterally spaced from each other. Furthermore, the first recesses 12 each a first side surface 12a and a second side surface 12b on.

According to the 7C can the first recesses 12 For example, have a rectangular, round or oval-shaped cross-sectional area, which are parallel to the main extension direction of the semiconductor wafer 2 runs.

As in the 8A and 8B is shown, in a next process step, the first sacrificial layer 10 removed by, for example, chemical etching.

The 9A and 9B show a next process step, in which a second structured sacrificial layer 13 by means of a second mask over the semiconductor wafer 2 is applied. The second sacrificial layer 13 has second recesses 14 which have a rectangular cross-sectional area parallel to the main extension direction of the semiconductor wafer 2 runs.

According to the 9C is a second recess 14 shown enlarged. The second recess 14 is in each case between adjacent first recesses 12 arranged and covers in plan view a first side surface 12a the first recesses 12 , partially a second side surface 12b the first recesses 12 , as well as partially the current spreading layer 9 that between the first recesses 12 is arranged.

According to the 10A and 10B 11A and 11B are other sectional views through the optoelectronic semiconductor chip, respectively 1 shown by the dashed line in the plan views according to 10B and 11B are marked. The semiconductor chips are analogous to the 9A and 9B educated.

According to the 12A and 12B In a next method step, a first electrically insulating separating layer is produced 15 over the semiconductor wafer 2 applied. The first separation layer 15 is, for example, a mirror layer in the form of a Bragg mirror.

As in the 13A . 13B and 13C is shown, in a next process step, the second sacrificial layer 13 and the first separation layer 15 that on the second sacrificial layer 13 is arranged away. The 13B shows a sectional view along the section line A , shown in 13A , The 13C shows a sectional view along the section line B, also shown in FIG 13A , The first separation layer 15 is partially on the current spreading layer 9 arranged. In particular, the first separation layer 15 between adjacent first recesses 12 on the current spreading layer 9 arranged. In addition, the first side surfaces 12a from the first release layer 15 covered and are in direct contact with this.

According to the 14A and 14B In a next process step, a second separation layer is formed 16 over the semiconductor wafer 2 applied. The second separation layer 16 is applied over the entire surface.

According to the 15A and 15B In a next method step, a third structured sacrificial layer is formed 17 by means of a third mask over the semiconductor wafer 2 applied, the third recesses 18 having. The third sacrificial layer 6 is generated for example by sputtering or vapor deposition.

As in the 16A and 16B are shown in a next step in the third recesses 18 , second recesses 19 in the second separation layer 16 generated. The material removal of the second separation layer 16 is generated for example by chemical etching. The second recesses 19 penetrate the second separation layer 16 Completely. Furthermore, the second side surface 12b partially from the second separating layer 16 covered and in direct contact with this. In addition, a top surface of the first release layer 15 partially from the second separating layer 16 partially covered. In addition, there are the first and the second separation layer 15 . 16 in direct contact.

An enlargement of the top view of the 16A is in the 16C shown. For clarity, the third sacrificial layer 17 Not shown. The second recesses 19 include a plurality of third recesses 20 , where the second half-staff area 4 is exposed. The third recesses 20 are each through the first and second separation layer 15 and 16 limited.

According to the 17A and 17B becomes in a next process step is an electrically conductive connection layer 21 over the semiconductor wafer 2 applied.

In a next method step, according to the 18A . 18B and 18C , the third sacrificial layer 17 and the metallic terminal layer 21 that's about the third sacrificial layer 17 is arranged away. The 18B shows a sectional view along the section line A , shown in 18A , The 18C shows a sectional view along the section line B, also shown in FIG 18A ,

The second semiconductor area 4 is about the first recesses 12 , or via the third recesses 20 by means of the connection layer 21 supplied with current. The first and second side surfaces 12a . 12b the first recesses are through the first separation layer 15 and the second separation layer 16 electrically isolated. That is, the first semiconductor region 5 and the current spreading layer 9 are through the first and second separation layer 15 . 16 against the connection contact 21 , which supplies current to the second semiconductor region 4 serves, are isolated. Furthermore, the first semiconductor region 5 by means of the connection layer 21 over the current spreading layer 9 supplied with current.

The invention is not limited by the description based on the embodiments of these. Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

1

optoelectronic semiconductor chip

2

Semiconductor wafer

3

carrier

4

second semiconductor region

5

first semiconductor area

6

fourth sacrificial layer

7

fourth recesses

8th

Bragg mirror layer

9

Current spreading layer

10

first sacrificial layer

11

first recesses

12

first recesses

12a

first side surface of the first recesses

12b

second side surface of the first recesses

13

second sacrificial layer

14

second recesses

15

first separation layer

16

second separating layer

17

third sacrificial layer

18

third recesses

19

second recesses

20

third recesses

21

connection layer

Claims (15)

An optoelectronic semiconductor chip (1) comprising - a semiconductor body comprising a first semiconductor region (5) and a second semiconductor region (4), - a plurality of first recesses (12) extending through the first semiconductor region (5) and each having a bottom surface in which the second semiconductor region (4) is exposed, and - a first electrically insulating separating layer (15) and a second electrically insulating separating layer (16), wherein - the first recesses (12) are laterally spaced from each other, - the first recesses (12 ) each have at least one first side surface (12a) and at least one second side surface (12b), - the first side surface (12a) is covered by the first separation layer (15) and is in direct contact therewith and the second side surface (12b) partially covered by and in direct contact with the second separation layer (16), and - the first and second separation layers (15, 16) have different material compositions. An optoelectronic semiconductor chip (1) according to the preceding claim, wherein the first separation layer (15) is a mirror layer. Optoelectronic semiconductor chip (1) according to one of the preceding claims, in which the second separating layer (16) is a light-transmitting passivation layer. Optoelectronic semiconductor chip (1) according to one of the preceding claims, in which the first and the second separating layer (15, 16) are in direct contact. Optoelectronic semiconductor chip (1) according to one of the preceding claims, in which a Bragg mirror layer (8) is arranged in places on the first semiconductor region (5). An optoelectronic semiconductor chip (1) according to the preceding claim, wherein a current spreading layer (9) completely covers the first semiconductor region (5) and the Bragg mirror layer (8). Optoelectronic semiconductor chip (1) according to the preceding claim, in which the first separation layer (15) is arranged in regions on the current spreading layer (9). Optoelectronic semiconductor chip according to one of the two preceding claims, in which the current spreading layer (9) is covered in regions by the second separating layer (16). Optoelectronic semiconductor chip (1) according to one of the preceding claims, in which a cover surface of the first separation layer (15) is partially covered by the second separation layer (16). Optoelectronic semiconductor chip (1) according to one of the preceding claims, in which the second separating layer (16) is interrupted by at least two second recesses (19). An optoelectronic semiconductor chip (1) according to the preceding claim, wherein a cross-sectional area of a plurality of third recesses (20) exposing the second semiconductor body (4) is smaller than a cross-sectional area of the plurality of first recesses (12). Optoelectronic semiconductor chip (1) according to the two preceding claims, wherein an electrically conductive connection layer (21) in the at least two second recesses (19) is arranged. Method for producing a plurality of optoelectronic semiconductor chips (1) with the following steps: Providing a semiconductor wafer (2) comprising a first semiconductor region (5) and a second semiconductor region (4), - applying a first patterned sacrificial layer (10) to the semiconductor wafer (2) by means of a first mask, the first mask having a plurality of non-contiguous first apertures, Producing a multiplicity of first recesses (12) in the semiconductor wafer (2) under the first diaphragms, the first recesses (12) extending through the first semiconductor region (5) and each having a bottom surface on which the second semiconductor region (4) exposed Depositing a second patterned sacrificial layer (13) on the semiconductor wafer (2) by means of a second mask, the second mask having a plurality of discontinuous second apertures, - Applying a first separating layer (15) under the second diaphragm, and - Applying a second separation layer (16) on the semiconductor wafer (2), and - Separating to a plurality of optoelectronic semiconductor chips (1). Method according to the preceding claim, wherein after the application of the second separating layer (16), a third structured sacrificial layer (17) is applied to the second separating layer (16) by means of a third mask, the third mask having a multiplicity of contiguous third stops. Method according to the preceding claim, wherein a plurality of second recesses (19) in the second separating layer (16) is produced under the third diaphragm, wherein the second recesses (19) extend through the second separating layer (16).

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