DE102018106268A1 - GATE SPACER HOLDER STRUCTURES FOR SEMICONDUCTOR COMPONENTS AND METHOD THEREFOR - Google Patents

Abstract

A semiconductor device comprises: a substrate having a channel region; a gate stack over the channel area; a seal spacer covering a sidewall of the gate stack, the seal spacer comprising silicon nitride; a gate spacer covering a side wall of the seal spacer, the gate spacer comprising silicon oxide and having a first vertical part and a first horizontal part; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer comprising silicon nitride.

Description

priority claim

This application claims priority to US provisional patent application Ser. No. 62 / 590,003, filed Nov. 22, 2017, entitled "Semiconductor Device Gate Spacer Structures and Methods Thereof." The invention relates to "Gate Spacer Structures for Semiconductor Devices and Methods Therefor", which is incorporated by reference.

background

The IC (integrated circuit semiconductor integrated circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have spawned generations of ICs, with each generation having smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per die area) has generally increased while the feature size (i.e., the smallest component or line that can be produced with a fabrication process) has decreased. This process of downsizing generally provides benefits by increasing production output and reducing the associated costs. However, this downsizing has also increased the complexity of processing and manufacturing ICs, and in order for these advances to be realized, similar developments in IC processing and fabrication are required.

For example, it is generally desirable to reduce stray capacitance among the features of field effect transistors, such as the capacitance between a gate structure and source / drain contacts, to increase switching speed, reduce switching power consumption, and / or coupling noise to reduce the transistors. Certain low-k materials have been proposed as insulating materials that encapsulate gate structures to provide a lower dielectric constant (or relative permittivity) and to reduce stray capacitance. However, as semiconductor technology evolves into smaller geometries, the distances between the gate structure and the source / drain contacts are further reduced, resulting in stray capacitance still being high. While existing approaches to transistor fabrication have been broadly appropriate for their intended purpose, they are not entirely satisfactory in every respect.

list of figures

• Die 1A, 1B und 1C zeigen Ablaufdiagramme eines Verfahrens zur Herstellung eines Halbleiter-Bauelements gemäß verschiedenen Aspekten der vorliegenden Erfindung.
• Die 2 bis 17 sind Schnittansichten eines Teils eines Halbleiter-Bauelements während eines Herstellungsprozesses gemäß dem Verfahren der 1A bis 1C, gemäß einigen Ausführungsformen.

Aspects of the present invention will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to common practice in the industry, various elements are not drawn to scale. Rather, for the sake of clarity of the discussion, the dimensions of the various elements can be arbitrarily increased or reduced.

• The 1A . 1B and 1C 12 show flowcharts of a method for manufacturing a semiconductor device according to various aspects of the present invention.
• The 2 to 17 are sectional views of a portion of a semiconductor device during a fabrication process according to the method of FIG 1A to 1C according to some embodiments.

Detailed description

The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Hereinafter, specific examples of components and arrangements will be described in order to simplify the present invention. Of course these are just examples and should not be limiting. For example, the manufacture of a first element over or on a second element in the description below may include embodiments in which the first and second elements are made in direct contact, and may also include embodiments in which additional elements are interposed between the first and second elements the second element can be made so that the first and the second element are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for simplicity and clarity and as such does not dictate any relationship between the various embodiments and / or configurations discussed.

• Figuren dargestellt sind. Die räumlich relativen Begriffe sollen zusätzlich zu der in den
• Figuren dargestellten Orientierung andere Orientierungen des in Gebrauch oder in Betrieb befindlichen Bauelements umfassen. Das Bauelement kann anders ausgerichtet werden (um 90 Grad gedreht oder in einer anderen Orientierung), und die räumlich relativen Deskriptoren, die hier verwendet werden, können ebenso entsprechend interpretiert werden.

Moreover, spatially relative terms such as "underlying", "below", "lower" / "lower", "above", "upper", "upper", and the like, may be simply used Description of the relationship of an element or structure to one or more other elements or structures used in the

• Figures are shown. The spatially relative terms are in addition to those in the
• Figures illustrated orientation other orientations of the in use or operating component include. The device may be reoriented (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may also be interpreted accordingly.

The present invention relates generally to semiconductor devices and methods of making the same. More particularly, the present invention relates to the provision of low-k gate spacer structures and methods of making same in order to reduce stray capacitance between a gate structure and source / drain contacts of field effect transistors (FETs) in semiconductor fabrication. In the manufacture of FETs, the goal is to increase the switching speed, lower the switching power consumption and reduce the coupling noise. The stray capacitance, in particular the stray capacitance between a gate structure and source / drain contacts, generally has a negative influence on these parameters. As semiconductor technology evolves toward smaller geometries, the gaps between the gate and the source / drain contacts become smaller, resulting in greater stray capacitance. As a result, stray capacitance has become more problematic in FETs. The present invention provides solutions in the fabrication of low-k gate spacer structures that enclose gate stacks, such as polysilicon gates or metal gates. The low-k gate spacer structures reduce the dielectric constant (or relative permittivity) between the gate stack and the source / drain contacts as compared to conventional silicon nitride (eg, Si ₃ N ₄ ) gate spacers. exist, reducing their stray capacitance. In addition, the low-k gate spacer structures help to reduce the interfacial voltage between gate stacks and source / drain regions, thus improving the carrier mobility of the channel.

The 1A . 1B and 1C show flowcharts of a method 100 for producing semiconductor devices according to the present invention. The procedure 100 is an example, and it is not intended to limit the present invention beyond what is explicitly set forth in the claims. Further steps may be taken before, during and after the procedure 100 can be provided, and some of the steps described can be replaced, omitted or moved in further embodiments of the method. The procedure 100 is described below with reference to the 2 to 16 described the sectional views of a semiconductor device 200 at various stages of manufacture according to some embodiments of the method 100 demonstrate.

The component 200 may be an intermediate device fabricated during processing of an integrated circuit (IC), or part thereof, and may include: SRAM and / or logic circuits (SRAM: static random access memory); passive components, such as resistors, capacitors and inductors; and active components such as p-FETs (PFETs), n-FETs (NFETs), FinFETs, metal oxide semiconductor field effect transistors (MOSFETs), CMOS transistors (CMOS: complementary metal oxide semiconductor), bipolar transistors, high voltage transistors , High frequency transistors, other memory cells and combinations thereof. Moreover, the various structural elements that comprise transistors, gate stacks, active areas, isolation structures, and other structural elements in various embodiments of the present invention are provided for simplicity and clarity, and do not necessarily limit the embodiments to one type of device. a number of devices, a number of regions, or a configuration of structures or regions.

In step 102 will in the process 100 ( 1A) a component structure 200 ( 2 ) provided. For ease of explanation, the component structure will become 200 also as a component 200 designated. The component 200 can be a substrate 202 and have various structural elements fabricated therein and thereon. The substrate 202 In the illustrated embodiment, it is a silicon substrate. Alternatively, the substrate 202 Comprising: another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. In another alternative, the substrate is 202 a semiconductor on insulator (SOI). In some embodiments, the substrate 202 fin-like regions ("fins") for making FinFETs. The fins can be structured using a suitable method. For example, the fins may be patterned with one or more photolithographic processes, such as double patterning or multiple patterning processes. In general, double structuring or multiple structuring processes combine photolithographic and self-aligned processes to create structures having, for example, pitches that are smaller than those of which can otherwise be achieved with a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is over the substrate 202 which is then patterned using a photolithographic process. Spacers are made along the patterned sacrificial layer using a self-aligned process. Then the sacrificial layer is removed and the remaining spacers, or mandrels, can then be used to pattern the substrate 202 used to make the fins. In some embodiments, the fins may include one or more layers of epitaxially grown semiconductor materials.

In some embodiments, the substrate 202 an insulator (or separation structure) which may be silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass (FSG), a low-k dielectric material, and / or other suitable insulating material. The insulator may comprise STI structural elements (STI: shallow trench isolation). In one embodiment, the insulator is fabricated as follows: etching trenches in the substrate 202 (for example, as part of the fin fabrication process discussed above); Filling the trenches with an insulating material; and performing chemical mechanical planarization (CMP) on the substrate 202 that has the insulating material. The substrate may also have other separation structures, such as Local Oxidation of Silicon (LOCOS). The substrate 202 may have a multi-layered release structure.

In step 104 will in the process 100 ( 1A) a gate stack 208 above the substrate 202 manufactured ( 2 ). In various embodiments, the gate stack is 208 a multi-layered structure. In some embodiments, the gate stack is 208 a polysilicon gate structure, which is an intermediate layer 210 with silicon oxide or silicon nitride and an electrode layer 212 comprising polysilicon. Thus, in some embodiments, the fabrication of the gate stack includes 208 the following steps: depositing the interlayer 210 above the substrate 202 by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD) or other suitable methods; Depositing the electrode layer 212 above the interlayer 210 by low pressure chemical vapor deposition (LPCVD) or by other suitable methods; and then structuring the intermediate layer 210 and the electrode layer 212 in a lithographic process to the gate stack 208 manufacture. The gate stack 208 defines a channel area 215 under him in the substrate 202 or in a fin of the substrate 202 , In the illustrated embodiment, the channel area 215 a channel length D ranging from about 5 nm to about 180 nm.

In a specific embodiment, the method comprises 100 a gate replacement process which will be described later. The intermediate layer 210 may be a temporary intermediate layer of silicon oxide or silicon nitride, and the electrode layer 212 may be a temporary electrode layer with polysilicon.

The step 104 may further include forming a seal spacer layer 214 that the building element 200 covered, cover. In the illustrated embodiment, the seal spacer layer becomes 214 as a protective layer over a top and sidewalls of the gate stack 208 and over an upper surface of the substrate 202 deposited. In addition, in the illustrated embodiment, the seal spacer layer 214 Silicon nitride (eg, Si ₃ N ₄ ), and may be deposited by plasma enhanced chemical vapor deposition (PECVD), LPCVD, ALD, or other suitable methods. The seal spacer layer 214 may be from about 0.5 nm to about 10 nm thick, e.g. B. about 3 nm, are deposited.

In step 106 will in the process 100 ( 1A) an anisotropic etching process on the seal spacer layer 214 carried out ( 3 ). The anisotropic etch process is designed to selectively seal the spacer layer 214 etched, but not the substrate 202 etched. In the step 106 become parts of the seal spacer layer 214 from the top of the substrate 202 removed, leaving the top of the substrate 202 is exposed. The part of the seal spacer layer 214 on the side walls of the gate stack 208 remains substantially unetched due to the highly directional etch. In addition, the top of the gate stack 208 be exposed or not with this anisotropic etch process. In an embodiment wherein the seal spacer layer 214 Silicon nitride may, for the step 106 an O ₂ / N ₂ furnace discharge with a fluorine-containing gas, such as CF ₄ , NF ₃ or SF ₆ , and additionally hydrogen (H ₂ ) or CH ₄ may be used. Various other methods of selectively etching the seal spacer layer 214 are also possible. For simplicity, the structured seal spacer layer 214 as a seal spacer 214 be designated. In a particular embodiment, the seal spacer is 214 with the sidewall of the gate stack 208 compliant, and has a conical profile close to the bottom of the gate stack 208 , The seal spacer 214 can be considered as a gasket spacer, which is a horizontal part 214a standing on the conical profile based, and a vertical part 214b having. The horizontal part 214a joins the bottom of the vertical part 214b and extends laterally in one direction from the gate stack 208 path. The horizontal part 122a For example, a width (along the x-direction) of about 0.5 nm to about 5 nm, e.g. B. about 3 nm, have.

In step 108 be in the process 100 ( 1A) lightly doped source / drain regions (LDD regions) 216 in the substrate 202 by performing an ion implantation process 218 manufactured ( 4 ). For the ion implantation process 218 For example, n-dopants such as phosphorus (P) or arsenic (As) may be used for NFETs or p-dopants such as boron (B) or indium (In) for PFETs. The LDD areas 216 are with the gate stack 208 and the seal spacer 214 self-aligned. It may be a masking layer (not shown) for covering other areas of the substrate 202 used when the LDD areas 216 the ion implantation process 218 be subjected. In some embodiments, the mask layer is a patterned photoresist. In some embodiments, the mask layer is a patterned hard mask of a material such as silicon oxide, silicon nitride or silicon oxynitride, or a combination thereof. The mask layer becomes in the LDD areas after completion of LDD implantation 216 away. At the in 4 illustrated embodiment, the step 108 after the step 106 executed. In an alternative embodiment, the step 108 before the step 106 executed.

In step 110 will in the process 100 ( 1A) a gate spacer layer 220 Made to be the component 200 covered ( 5 ). In the illustrated embodiment, the gate spacer layer becomes 220 as a protective layer over sidewalls of the gasket spacer 214 , above a top of the gate stack 208 and over the top of the substrate 202 deposited. In some devices, silicon nitride has heretofore been used as a material for gate spacers in semiconductor manufacturing. However, silicon nitride has a relatively high dielectric constant, usually 6.8 to 8.3, e.g. About 7.5, which in some cases results in high stray capacitance between a gate stack and source / drain contacts and / or other FET devices. To reduce stray capacitance, materials other than silicon nitride, which have relatively low dielectric constants, must be used for gate spacers. In one embodiment, the gate spacer layer 220 Silicon oxide (eg SiO ₂ ) on. Silicon oxide has a lower dielectric constant than silicon nitride, and is usually 3.4 to 4.2, e.g. B. about 3.9. In some embodiments, the deposition of the gate spacer layer comprises 220 introducing a silicon-containing compound and an oxygen-containing compound that react to form a dielectric material. The gate spacer layer 220 may include undoped silicate glass (USG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). In another embodiment, the gate spacer layer 220 Germanium oxide (eg GeO ₂ ). The gate spacer layer 220 can be prepared by a suitable method such as PECVD, LPCVD and ALD. In the illustrated embodiment, the gate spacer layer 220 Silica on, and it is deposited by a conformal deposition method, such as ALD. The gate spacer layer 220 can with a thickness T ₁ about 10% to about 70% of the length D of the channel region 215 is. In some embodiments, the thickness is T ₁ about 3 nm to about 20 nm, e.g. B. about 5 nm.

In step 112 will in the process 100 ( 1A) a hardmask layer 224 made to be the gate spacer layer 220 covered ( 6 ). The hard mask layer 224 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or silicon carboxide nitride, or other dielectric materials or combinations thereof. The composition of the hard mask layer 224 is chosen so that the hard mask layer 224 a certain etch selectivity with respect to the gate spacer layer 220 Has. In some embodiments, the hardmask layer 224 Silicon nitride (eg, Si ₃ N ₄ ). The hard mask layer 224 can be prepared by a suitable method such as PECVD, LPCVD and ALD. In the illustrated embodiment, the hard mask layer becomes 224 deposited by LPCVD. The hard mask layer 224 comes with a thickness T2 deposited, which is about 10% to about 70% of the length D of the channel region 215 is. In some embodiments, the thickness is T ₂ about 3 nm to about 20 nm, e.g. About 4 nm. In some embodiments, the hardmask layer is 224 thinner than the gate spacer layer 220 ( T ₂ < T ₁ ), for example up to 1 nm thinner.

In step 114 be in the process 100 ( 1A) the hardmask layer 224 and the gate spacer layer 220 subjected to an etching process ( 7 ). The etching process in one embodiment includes an anisotropic etch. Part of the hard mask layer 224 on the sidewalls of the gate spacer layer 220 remains substantially unetched due to the highly directional etch, as in 7 is shown. In an embodiment wherein the hardmask layer 224 Silicon nitride may, for the step 114 an O ₂ / N ₂ - Remote discharge with a fluorine-containing gas, such as CF ₄ , NF ₃ or SF ₆ , and additionally hydrogen ( H ₂ ) or CH ₄ can be used. In the anisotropic etching, moreover, the gate spacer layer 220 etched after removal of parts of the hardmask layer 224 exposed. Alternatively, the etching process may include multiple etching steps with different etching chemicals, such as an anisotropic etch, which is a particular hard mask layer material 224 and subsequently wet etching or dry etching the gate spacer layer 220 targeted, using the non-etched hardmask layer 224 as an etching mask. The top of the gate stack 208 can be exposed or not with this etching process.

We stay with you 7 , The structured gate spacer layer 220 can be used as a gate spacer for simplicity 220 while the patterned hardmask layer 224 as a hard mask 224 can be designated. The gate spacer 220 includes a horizontal part 220a that is directly under the hard mask 224 located, and a vertical part 220b , the side walls of the seal spacer 214 covered. The vertical part 220b has a side wall 225 on. The side wall 225 is from the hard mask 224 covered. In some embodiments, the sidewall is 225 substantially perpendicular (ie, along the z-axis) to the top of the substrate 202 , The horizontal part 220a includes a top 226 and a side wall 228 , The side wall 228 may be substantially perpendicular (ie, along the z-axis) to the top of the substrate 202 his. The side wall 225 , the top 226 and the side wall 228 form a step profile. The hard mask 224 is right above the top 226 arranged. In one embodiment, the hardmask covers 224 completely the top 226 , In another embodiment, the hardmask is due to a higher sidewall etch loss 224 during the step 114 the hard mask 224 thinner than the width W ₁ of the horizontal part 220a ( T ₂ < W ₁ ). Therefore, part of the top 226 that's to the sidewall 228 is adjacent, and may have a width along the x-axis of about 0.5 nm to about 2 nm. The top 226 cuts the sidewall 225 so an angle Θ between the top 226 and the side wall 225 arises. In some embodiments, the angle is Θ about 85 ° to about 95 °, and the top 226 can be considered substantially perpendicular to the sidewall 225 be considered. In various embodiments, a height is H ₁ of the horizontal part 220a about 10% to about 70% of the length D of the channel area 215 , In a particular embodiment, the height is H ₁ equal to the thickness T ₁ of the vertical part 220b ( H ₁ = T ₁ ). In one embodiment, the height is H ₁ of the thickness T ₁ of the vertical part 220b different ( H ₁ ≠ T ₁ ), and H ₁ is for example 1 nm smaller or larger than the thickness T ₁ , A top point of the horizontal part 220a can be higher than a top point of the horizontal part 214a of the seal spacer 214 his.

In step 118 be in the process 100 ( 1B) heavily doped source / drain regions (HDD regions) 230 in the substrate 202 manufactured ( 8th ). The HDD areas 230 may be n-doped regions and / or p-doped regions for producing active devices. The HDD areas 230 and the LDD areas 216 are collectively considered source / drain regions (S / D regions). The HDD areas 230 are more heavily doped than the LDD regions 216 , The HDD areas 230 can by performing an ion implantation process 232 getting produced. For the ion implantation process 232 For example, n-dopants such as phosphorus (P) or arsenic (As) may be used for NFETs or p-dopants such as boron (B) or indium (In) for PFETs. The HDD areas 230 are with the gate stack 208 and the gate spacer 220 self-aligned. It may be a masking layer (not shown) for covering other areas of the substrate 202 used when the HDD areas 230 the ion implantation process 232 be subjected. In some embodiments, the mask layer is a patterned photoresist. In some embodiments, the mask layer is a patterned hard mask of a material such as silicon oxide, silicon nitride or silicon oxynitride, or a combination thereof. The mask layer becomes in the HDD areas after completion of HDD implantation 230 away.

The production of HDD areas 230 In addition, etching of S / D recesses in the substrate may be first 202 and subsequent epitaxial growth of HDD regions 230 in the respective recesses. In some embodiments, where the gate stack 208 and the gate spacer layer 220 Thicker than desired, the HDD areas can 230 be made to have a substantially diamond-shaped profile, such as the HDD areas 230 in 9 , In 9 run some sidewalls of the HDD areas 230 to the gate stack 208 under the gate spacer 220 , such as under the vertical part 220b , In one example, the HDD areas are running 230 continue under the horizontal part 214a of the seal spacer 214 but not under its vertical part 214b , In another example, the HDD areas run 230 still under the gate stack 208 , In one example, the S / D cavities are formed with an etch process that includes dry etching and wet etching, with their etch parameters (such as etchants used, etch temperature, etch solution concentration, etch pressure, Power Source Voltage, Radio Frequency (RF) Bias Voltage, RF Bias Power, Etch Throughput, and Other Suitable Parameters) can be adjusted to achieve the desired cutoff profile. The HDD areas 230 can a salicylic part 231 on the top. Parts of the salicide part 231 can from the horizontal part 220a and / or the vertical part 220b of the gate spacer 220 be covered. Due to the greater amount of salicylic acid 231 can be a bottom of the horizontal part 220a higher than a bottom of the vertical part 220b his. For ease of discussion, the device becomes 200 with the HDD areas in the in 8th shown as an example of subsequent steps used. One of ordinary skill in the art would recognize that the device 200 with the HDD areas in the in 9 shown form can also be used for the subsequent steps.

We come to 8th back. In one embodiment, the HDD areas include 230 further silicidation or germanosilicidation regions (not shown). The silicidation may be achieved, for example, by a process comprising the steps of: depositing a metal layer; Annealing the metal layer so that the metal layer can react with silicon to silicide; and then removing the unreacted metal layer. The step 118 may further comprise one or more annealing processes for activating the S / D regions. After activation, the LDD areas 216 to the gate stack 208 under the seal spacer 214 run, and the HDD areas 230 can partially under the horizontal part 220a of the gate spacer 220 run. In other words, the seal spacer 214 and the vertical part 214b of the gate spacer 220 can be in physical contact with the LDD areas 216 be, and the horizontal part 220a of the gate spacer 220 can be in physical contact with the LDD areas 216 and the HDD areas 230 his. The low dielectric constant of the material composition of the gate spacer 220 also contributes to reducing the interfacial tension between the gate stack and the source / drain regions and thus improves the carrier mobility of the channel. In one embodiment, the device 200 fin-like active regions for fabricating multi-gate FETs, such as FinFETs. Furthermore, in this embodiment, the S / D regions and the channel region 215 be made in or on the Finns. The channel area 215 is under the gate stack 208 and is between a pair of LDD areas 216 layered. The channel area 215 conducts currents between the respective S / D regions when the semiconductor device 200 is turned on, such as by biasing the gate electrode layer 212 ,

In step 120 will in the process 100 ( 1B) a contact etch stop layer (CES layer) 246 Made to be the component 200 covered ( 10 ). In the illustrated embodiment, the CES layer becomes 246 as a protective layer over the sidewalls and the top of the gate spacer 220 , the hard mask 224 , the seal spacer 214 , the gate stack 208 and over the top of the HDD areas 230 deposited. The CES layer 246 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, or silicon carboxide nitride, or other dielectric materials or combinations thereof. The CES layer 246 can be prepared by plasma enhanced chemical vapor deposition (PECVD) and / or other suitable deposition or oxidation processes. In the illustrated embodiment, the hard mask 224 and the CES layer 246 both silicon nitride (eg, Si ₃ N ₄ ) on, with the hard mask 224 produced by LPCVD and the CES layer 246 produced by PECVD, so that the silicon nitride material in the hard mask 224 another crystal structure (eg, a different lattice constant) than in the CES layer 246 Has. In a specific embodiment, the CES layer has 246 a step profile 248 along its vertical side wall due to the sidewall profile of the horizontal part 220a and the hard mask 224 under the CES layer 246 ,

In step 122 will in the process 100 ( 1B) an interlayer dielectric (ILD) layer 252 over the CES layer 246 manufactured ( 11 ). The ILD layer 252 For example, materials such as silica, doped silica, such as borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, fused silica (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), a low-k dielectric material, and / or have other suitable dielectric materials. The ILD layer 252 can be deposited by PECVD, flowable CVD (FCVD) or other suitable deposition method. The compositions of the CES layer 246 and the ILD layer 252 are chosen to have some etch selectivity with respect to the ILD layer 252 to have.

In step 214 be in the process 100 ( 1B) One or more CMP processes (CMP: chemical mechanical planarization) performed to the ILD layer 252 to polish and the gate stack 208 to expose ( 12 ). In some embodiments, the ILD layer has 252 a higher surface loss during planarization than the gate stack 208 due, for example, to the relatively lower material density and the top of the ILD layer 252 has a concave profile, like the dashed line 253 is shown. A lowermost part of the top of the ILD layer 252 may be about 0.1 nm to about 25 nm lower than the top of the gate stack 208 his.

In step 126 goes the procedure 100 ( 1B) to further processes continue to manufacture the device 200 complete. For example, in the method 100 a metal gate stack can be made in a gate replacement process.

In the gate replacement process, the gate stack is 208 a temporary gate structure. The temporary gate structure can be produced by deposition and etching processes. Subsequently, in the step 126 the temporary gate structure is removed, leaving a gate trench (not shown) between the seal spacers 214 and a high-k metal gate stack 290 is deposited in the gate trench ( 13 ). The high-k metal gate stack 290 may include a high-k dielectric layer 292 and a conductive layer 294 have on it. The high-k metal gate stack 290 may also include an intermediate layer (eg, SiO ₂ ) (not shown) between the high-k dielectric layer 292 and the channel region 215 respectively. The intermediate layer can be made by chemical oxidation, thermal oxidation, ALD, CVD and / or other suitable methods.

The high-k dielectric layer 292 may comprise one or more high-k dielectric materials (or one or more high-k dielectric material layers) such as hafnium silicon oxide (HfSiO), hafnium oxide (HfO ₂ ), alumina (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ) or strontium titanate (SrTiO ₃ ), or a combination thereof. The high-k dielectric layer 292 may be deposited by CVD, ALD, and / or other suitable methods.

The conductive layer 294 may include one or more metal layers, such as work function metal layers, conductive barrier layers, and metal fill layers. The work-function metal layer may be a p-type or an n-type work-function metal layer, depending on the type of transistor (p- or n-type transistor). The p-type workfunction metal layer comprises a metal of, among others, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), and platinum (Pt), or combinations thereof. The n-type workfunction metal layer comprises a metal of, inter alia, titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbide nitride (TaCN), tantalum silicon nitride (TaSiN), or titanium silicon nitride (TiSiN), or combinations thereof. The metal fill layer may comprise aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials. The conductive layer 294 can be deposited by CVD, PVD, plating and / or other suitable methods.

The step 126 may include other processes to the manufacture of the device 200 finish. For example, in the step 126 S / D contacts (not shown) and a multilayer interconnect structure are fabricated which interconnect the gate stacks and the S / D contacts with other parts of the device 200 connects to a complete IC.

The procedure 100 can have different embodiments. For example, the procedure 100 an optional step 116 ( 1C) between the steps 114 and 118 to remove the hard mask 224 sidewalls of the gate spacer 220 have, as in 14 is shown. In the illustrated embodiment, the hard mask 224 Silicon nitride, which has a higher dielectric constant than the material compositions of the gate spacer 220 Has. By removing the hard mask 224 becomes the total dielectric constant of the insulating material between the gate stack 208 and the S / D contacts (not shown), which results in even lower stray capacitances among the FET features.

Removing the hard mask 224 can be done with a suitable etching method such as wet etching, dry etching, reactive ion etching (RIE), detachment and / or with other etching methods. In some embodiments, the etchant is selected such that the hard mask 224 and the gate spacer 220 have a high Ätzselektivität. The etch selectivities between the hardmask 224 and the gate spacer 220 For example, have a ratio of about 5: 1 or greater, such. B. 5: 1 to 20: 1. In the etching process can also be the profile of the horizontal part 220a of the gate spacer 220 be downsized. In one embodiment, the top is 226 in a proportion of about 3% to about 30% of the length D of the channel area 215 shortened, for example, by about 1 nm to about 8 nm, z. B. 2 nm, and the sidewall 228 becomes conical with an angle β with respect to the sidewall 225 which is less than 45 °, z. B. is about 20 °. The procedure 100 can then follow the steps 118 . 120 . 122 . 124 and 126 move on to other structural elements of the device 200 manufacture. These steps include making the HDD areas 230 using the truncated gate spacer 220 as a mask; the deposition of the CES layer 246 directly over sidewalls of the truncated gate spacer 220 ; and establishing the ILD layer 252 on the device 200 , as in 15 is shown. In another embodiment, at step 116 ( 1C) the top 226 of the horizontal part 220a straightened so the side wall 228 the side wall 225 with an angle β directly cuts, which is smaller than 45 °, z. B. is about 20 °, as in 16 is shown. The procedure 100 can then follow the steps 118 . 120 . 122 . 124 and 126 go on, which are not repeated for the sake of simplicity, in order to produce other structural elements of the device 200 continue as in 17 is shown.

However, one or more embodiments of the present invention, which are not intended to be limiting, provide numerous advantages to a semiconductor device, such as a fin field effect transistor (FinFET), and to the fabrication thereof. For example, the fins may be structured to provide a relatively small spacing between structural elements for which the present invention is well suited. Gate spacers used in making fins of FinFETs can be machined according to the above invention. For example, embodiments of the present invention provide a method of making low-k gate spacers that enclose the gate stack. The dielectric constant of the insulating materials between the gate stack and the S / D contacts is reduced, thereby reducing interference, noise, and parasitic coupling capacitance between interconnects. In addition, the low-k gate spacers help to reduce the interfacial tension between gate stacks and S / D contacts, thereby improving the carrier mobility of the channel. In addition, the described methods can be easily integrated into existing semiconductor manufacturing processes.

In an exemplary aspect, the present invention is directed to a semiconductor device. In an embodiment, the semiconductor device comprises: a substrate having a channel region; a gate stack over the channel area; a seal spacer covering a sidewall of the gate stack, the seal spacer comprising silicon nitride; a gate spacer covering a side wall of the seal spacer, the gate spacer comprising silicon oxide and having a first vertical part and a first horizontal part; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer comprising silicon nitride. In one embodiment, the seal spacer has a second vertical part and a second horizontal part, and the first dielectric layer has a third vertical part and a third horizontal part. In one embodiment, the first, second, and third horizontal portions are each in physical contact with an upper surface of the substrate. In one embodiment, a top point of the second horizontal part is lower than a top point of the first horizontal part. In one embodiment, the substrate has a source / drain (S / D) region, the S / D region having a first doped S / D region adjacent to the channel region and a second doped S / D region. Includes the region adjacent to the first doped S / D region, wherein the second doped S / D region is doped more strongly than the first doped S / D region, the first vertical part opposite to the second doped S / D region. And the first horizontal part is in physical contact with the first doped S / D region and the second doped S / D region. In one embodiment, a height of the first horizontal part is substantially equal to a width of the first vertical part. In one embodiment, the first vertical portion has a first sidewall, the first sidewall being substantially perpendicular to an upper surface of the substrate, and the first horizontal portion having a second sidewall, the second sidewall intersecting the first sidewall at an angle that is smaller than 45 °. In one embodiment, the first vertical part has a first sidewall, wherein the first sidewall is substantially perpendicular to an upper side of the substrate, and the first horizontal part has a second sidewall and a first upper face extending between the first sidewall and the second sidewall is located, wherein the first top is substantially perpendicular to the first side wall. In one embodiment, the semiconductor device further comprises a second dielectric layer layered between the gate spacer and the first dielectric layer, the second dielectric layer being over the first horizontal part, the second dielectric layer and the gate Spacers have different material compositions. In one embodiment, the second dielectric layer partially covers the first top. In one embodiment, the second sidewall is substantially perpendicular to an upper surface of the substrate. In an embodiment, the gate stack comprises a polysilicon gate or a metal gate.

In another exemplary aspect, the present invention is directed to a semiconductor device. In an embodiment, the semiconductor device comprises: a substrate having source / drain (S / D) regions, wherein a channel region is sandwiched between the S / D regions; a gate stack over the channel area; a dielectric layer covering sidewalls of the gate stack, the dielectric layer comprising a nitride; a spacer layer covering sidewalls of the dielectric layer, the spacer layer comprising an oxide, wherein a sidewall of the spacer layer has an upper sidewall, a horizontal surface, and a lower sidewall to provide a step profile; and a contact etch stop layer (CES layer) covering the sidewall of the spacer layer, the CES layer comprising a nitride. In one embodiment, the upper sidewall intersects the horizontal surface so as to define an angle between the upper sidewall and the horizontal surface that is in the range of 85 ° to 95 °. In one embodiment, the semiconductor device further comprises a hardmask layer sandwiched between the spacer layer and the CES layer, wherein a dielectric constant of the hardmask layer is higher than a dielectric constant of the spacer layer. In one embodiment, the S / D regions include a first doped S / D region and a second doped S / D region that is more heavily doped than the first doped S / D region, with the top sidewall directly above the S / D region first doped S / D region and the lower sidewall is directly above the second S / D region. In one embodiment, a thickness of the spacer layer is 10% to 70% of a length of the channel region.

In yet another aspect, the present invention is directed to a method. In an embodiment, the method comprises the steps of: forming a gate structure on a substrate; Forming a gasket spacer so as to cover the gate structure; Atomic Deposition (ALD) forming a gate spacer so as to cover the seal spacer, the gate spacer having a first vertical part and a first horizontal part; Forming a hardmask layer so as to cover the gate spacer, the hardmask layer having a second vertical part and a second horizontal part; Removing the second horizontal portion of the hardmask layer and a portion of the first horizontal portion of the gate spacer located below the second horizontal portion of the hardmask layer; and forming a contact etch stop layer (CES layer) so as to cover the gate spacer. In an embodiment, prior to forming the CES layer, the method further comprises removing the second vertical portion of the hardmask layer. In one embodiment, the gate spacer has the lowest dielectric constant in the group of seal spacers, gate spacers, hard mask layer, and CES layer. In one embodiment, the seal spacer comprises silicon nitride, the gate spacer comprises silicon oxide, and the CES layer comprises silicon nitride. In an embodiment, the method further comprises the steps of: forming a first source / drain region with an ion implantation process after the seal spacer is made and before the gate spacer is fabricated; and fabricating a second source / drain region adjacent to the first source / drain region after removing the second horizontal portion of the hardmask layer and prior to fabricating the CES layer, the second source / drain region. Region is more heavily doped than the first source / drain region. In one embodiment, the gate structure is a polysilicon gate structure or a metal gate structure.

Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objects and / or advantages of the same as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent interpretations do not depart from the spirit and scope of the present invention and that they may make various changes, substitutions and alterations here without departing from the spirit and scope of the present invention.

Claims (20)

Semiconductor device with: a substrate having a channel region; a gate stack over the channel area; a seal spacer covering a sidewall of the gate stack, the seal spacer comprising silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer comprising silicon oxide and having a first vertical part and a first horizontal part; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer comprising silicon nitride. Semiconductor device according to Claim 1 wherein the seal spacer has a second vertical part and a second horizontal part, and the first dielectric layer has a third vertical part and a third horizontal part. Semiconductor device according to Claim 2 , wherein the first, the second and the third horizontal part each in physical contact with an upper surface of the substrate. Semiconductor device according to Claim 2 or 3 wherein a top point of the second horizontal part is lower than a top point of the first horizontal part. A semiconductor device according to any one of the preceding claims, wherein the substrate has a source / drain (S / D) region, wherein the S / D region comprises a first doped S / D region adjacent to the channel region and a second doped S / D region, which is adjacent to the first doped S / D region, the second doped S / D region being doped more strongly than the first doped S / D region, the first vertical part is offset from the second doped S / D region and is in physical contact with the first doped S / D region, and the first horizontal part is in physical contact with the first doped S / D region and the second doped S / D region. A semiconductor device according to any one of the preceding claims, wherein a height of the first horizontal part is substantially equal to a width of the first vertical part. A semiconductor device according to any one of the preceding claims, wherein the first vertical part has a first sidewall, the first sidewall being substantially perpendicular to an upper surface of the substrate, and the first horizontal part has a second sidewall, the second sidewall intersecting the first sidewall at an angle less than 45 °. A semiconductor device according to any one of the preceding claims, wherein the first vertical part has a first sidewall, the first sidewall being substantially perpendicular to an upper surface of the substrate, and the first horizontal part has a second side wall and a first top side located between the first side wall and the second side wall, the first top side being substantially perpendicular to the first side wall. Semiconductor device according to Claim 8 further comprising a second dielectric layer sandwiched between the gate spacer and the first dielectric layer, the second dielectric layer overlying the first horizontal portion, the second dielectric layer and the gate spacer having different material compositions. Semiconductor device according to Claim 9 wherein the second dielectric layer partially covers the first top. Semiconductor device according to Claim 9 or 10 wherein the second sidewall is substantially perpendicular to an upper surface of the substrate. Semiconductor device according to one of the preceding claims, wherein the gate stack comprises a polysilicon gate or a metal gate. Semiconductor device with: a substrate with source / drain (S / D) regions, with a channel region located between the S / D regions; a gate stack over the channel area; a dielectric layer covering sidewalls of the gate stack, the dielectric layer comprising a nitride; a spacer layer covering sidewalls of the dielectric layer, the spacer layer comprising an oxide, wherein a sidewall of the spacer layer has an upper sidewall, a horizontal surface, and a lower sidewall to form a step profile; and a contact etch stop layer (CES layer) covering the sidewall of the spacer layer, the CES layer comprising a nitride. Semiconductor device according to Claim 13 wherein the upper sidewall intersects the horizontal surface so as to define an angle between the upper sidewall and the horizontal surface which is in a range of 85 ° to 95 °. Semiconductor device according to Claim 13 or 14 further comprising a hard mask layer disposed between the spacer layer and the CES layer, wherein a dielectric constant of the hard mask layer is higher than a dielectric constant of the spacer layer. Semiconductor device according to one of Claims 13 to 15 wherein the S / D regions include a first doped S / D region and a second doped S / D region that is doped more heavily than the first doped S / D region, with the upper sidewall directly over the first doped S / D area and the lower sidewall is just above the second S / D area. Semiconductor device according to one of Claims 13 to 16 wherein a thickness of the spacer layer is 10% to 70% of a length of the channel region. Procedure with the following steps: Forming a gate structure on a substrate; Forming a gasket spacer so as to cover the gate structure; Atomic Deposition (ALD) forming a gate spacer so as to cover the seal spacer, the gate spacer having a first vertical part and a first horizontal part; Forming a hardmask layer so as to cover the gate spacer, the hardmask layer having a second vertical part and a second horizontal part; Removing the second horizontal portion of the hardmask layer and a portion of the first horizontal portion of the gate spacer located below the second horizontal portion of the hardmask layer; and forming a contact etch stop layer (CES layer) so as to cover the gate spacer. Method according to Claim 18 which further comprises removing the second vertical portion of the hardmask layer prior to forming the CES layer. Method according to Claim 18 or 19 wherein the gate spacer has the lowest dielectric constant in the group comprising the seal spacer, the gate spacer, the hard mask layer, and the CES layer.

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