DE102018105554A1 - METALIZATION STRUCTURES IN SEMICONDUCTOR PACKAGES AND METHOD FOR THE PROCESSING THEREOF - Google Patents

Abstract

A method of one embodiment includes encapsulating a semiconductor die in an encapsulant, planarizing the encapsulant, and depositing a polymeric material onto the encapsulant. The method further includes planarizing the polymeric material and forming a metallization structure on the polymeric material. The metallization structure electrically connects a die connector of the semiconductor die with a conductive feature disposed outside of the semiconductor die.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the priority of the provisional U.S. Application No. 62 / 586,558 filed on 15 November 2017, which is hereby incorporated by reference.

STATE OF THE ART

The semiconductor industry has experienced rapid growth due to continual improvements in the integration density of various electronic devices (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, the improvement in integration density has resulted from incremental reductions in the minimum feature size, allowing more components to be integrated into a particular area. With the growing need for downsizing of electronic devices, a need has arisen for smaller and more inventive semiconductor packaging dies. An example of such packaging systems is the Package-on-Package (PoP) technology. In a PoP device, an upper semiconductor package is stacked on a lower semiconductor package to provide high integration and component density. The PoP technology generally enables fabrication of semiconductor devices with improved functionality and small footprint on a printed circuit board (PCB).

list of figures

• 1, 2, 3, 4A, 4B, 5, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25A und 25B zeigen Querschnittsansichten von Zwischenschritten während eines Prozesses zum Ausbilden eines Package gemäß einigen Ausführungsformen.
• 26A, 26B und 27 zeigen Querschnittsansichten von Zwischenschritten während eines Prozesses zum Ausbilden eines Package gemäß einigen Ausführungsformen.
• 28A, 28B, 29A, 29B, 30A, 30B, 31A, 31B, 32A, 32B, 32C, 33A, 33B, 33C, 34A und 34B zeigen Querschnittsansichten von Zwischenschritten während eines Prozesses zum Ausbilden eines Package gemäß einigen Ausführungsformen.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to the standard method in the industry, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

• 1 . 2 . 3 . 4A . 4B . 5 . 6A . 6B . 7A . 7B . 8A . 8B . 9A . 9B . 10A . 10B . 11A . 11B . 12 . 13 . 14 . 15 . 16 . 17 . 18 . 19 . 20 . 21 . 22 . 23 . 24 . 25A and 25B 12 show cross-sectional views of intermediate steps during a process of forming a package according to some embodiments.
• 26A . 26B and 27 12 show cross-sectional views of intermediate steps during a process of forming a package according to some embodiments.
• 28A . 28B . 29A . 29B . 30A . 30B . 31A . 31B . 32A . 32B . 32C . 33A . 33B . 33C . 34A and 34B 12 show cross-sectional views of intermediate steps during a process of forming a package according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Concrete examples of components and arrangements are described below to simplify the present disclosure. These are of course only examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are included between the first and second features second feature may be formed so that the first and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the sake of simplicity and clarity and as such does not dictate any relationship between the various embodiments and / or embodiments discussed.

In addition, terms related to spatial relativity, such as those described herein, may be used herein. "Below," "below," "below," "above," "above," and the like, may be used to facilitate the discussion of the relationship of one element or feature to another element or feature (to other elements or features); as shown in the figures to describe. The terms relating to spatial relativity are intended to encompass different orientations of the device used or operated in addition to the orientation shown in the figures. The device may be oriented in a different manner (rotated 90 degrees or otherwise oriented) and the terms used herein relating to spatial relativity may equally be construed accordingly.

Embodiments discussed herein may be discussed in a specific context, namely, a package structure (eg, a package-on-package (PoP) structure) that includes a polymer layer disposed on an encapsulant. The encapsulant is around one or more integrated circuit dies and conductive vias extending through the encapsulant are disposed. Additionally, the encapsulant may be distributed, cured, and then planarized to expose integrated circuit die and via contacts. However, due to fillers disposed within the encapsulant, the planarization process may result in a molding compound having an uneven top surface after planarization. The uneven top surface may also cause manufacturing defects in features formed over the encapsulant. For example, some of the fillers may have hollow cores, and planarizing these fillers may result in pits (eg, resulting from exposure of the cores) to the top surface of the molding compound after planarization. Even without hollow core fillers, a surface texture of the molding compound may be undesirably rough after planarization. As a result of the pits and the rough surface of the molding compound, metallization structures (sometimes referred to as redistribution lines or redistribution layers) formed on the molding compound can cause manufacturing defects, such as broken lines in the metallization structure (eg, leading to open circuits) and / or Lines with bridge formation in the metallization structure (eg lead short circuited circuits) have.

In order to provide an improved surface topography for subsequent formation of metallization structures, in various embodiments, a polymeric material may be distributed over the molding compound. A planarization process can then be applied to the polymeric material. In some embodiments, the polymeric material may be substantially free of fillers, which allows an upper surface of the polymeric material to exhibit improved smoothness after planarization as compared to the molding compound. It has been found that by incorporating this polymer material on the top surface of the molding compound, manufacturing defects in forming metallization structures over the molding compound can be advantageously reduced.

1 to 25 10 illustrate cross-sectional views of intermediate steps during a process of forming a first package component according to some embodiments. 1 shows a carrier substrate 100 and one on the carrier substrate 100 formed release layer 102 , A first package area 600 and a second package area 602 , respectively for forming a first package and a second package, are shown.

The carrier substrate 100 may be a glass substrate, a ceramic substrate or the like. The carrier substrate 100 may be a wafer, allowing multiple packages on the carrier substrate 100 can be trained simultaneously. The release layer 102 may be formed of a polymer-based material that together with the carrier substrate 100 can be removed from the overlying structures formed in subsequent steps. In some embodiments, the release layer is 102 an epoxy-based thermal release material that loses its adhesive property when heated, such as an LTHC release coating (Light to Heat Conversion). In other embodiments, the release layer 102 an ultraviolet (UV) adhesive that loses its adhesive property when exposed to UV light. The release layer 102 can be distributed as a liquid and cured, it may be a laminate film on the carrier substrate 100 is piled up, or it may be the like. The upper surface of the release layer 102 can be leveled and it can have a high degree of coplanarity.

2 to 3 show the formation of an optional backside redistribution structure 110 (please refer 3 ) and optional vias 112 (please refer 3 ). In other embodiments, the backside redistribution structure 110 and the vias 112 be omitted (see, for example, the embodiment of 4B and 25B) , In 2 become a dielectric layer 104 and a metallization structure 106 (sometimes as a redistribution layer 106 or a redistribution line 106 is designated) formed. As in 2 is shown, a dielectric layer 104 on the release layer 102 educated. The bottom surface of the dielectric layer 104 can be in contact with the upper surface of the release layer 102 stand. In some embodiments, the dielectric layer becomes 104 from a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) or the like. In other embodiments, the dielectric layer becomes 104 nitride such as silicon nitride; an oxide such as silica, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG) or the like; or the like is formed. The dielectric layer 104 can be formed by any suitable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof.

The metallization structure 106 is on the dielectric layer 104 educated. To the metallization structure 106 For example, a seed layer (not shown) is formed over the dielectric layer 104 educated. In some In embodiments, the seed layer is a metal layer which may be a single layer or a composite layer comprising a plurality of sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, a PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by means of a spin coating or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 106 , The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by means of plating such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portions of the seed layer on which the conductive material has not been formed are removed. The photoresist may be removed by a suitable ashing or ablation process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, such as by using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization structure 106 ,

In 3 becomes a dielectric layer 108 on the metallization structure 106 and the dielectric layer 104 educated. In some embodiments, the dielectric layer becomes 108 formed of a polymer which may be a photosensitive material such as PBO, polyimide, BCB or the like, which may be patterned using a lithographic mask. In other embodiments, the dielectric layer becomes 108 formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 108 can be formed by means of spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 108 is then patterned to form openings to allow portions of the metallization structure 106 be exposed. The patterning may be done by a suitable process, such as by exposing the dielectric layer 108 with light when the dielectric layer is a photosensitive material, or by etching, for example, using anisotropic etching.

The dielectric layers 104 and 108 and the metallization structures 106 can be considered a back-side redistribution structure 110 be designated. As illustrated, the backside redistribution structure includes 110 the two dielectric layers 104 and 108 and a metallization structure 106 , In other embodiments, the backside redistribution structure 110 comprise any number of dielectric layers, metallization structures, and vias, or the backside redistribution structure 110 can be completely omitted. One or more additional metallization structures and dielectric layers may be in the backside redistribution structure 110 be formed by the processes for forming a metallization structure 106 and a dielectric layer 108 be repeated. Vias may be formed during the formation of a metallization structure by forming the seed layer and the conductive material of the metallization structure in the opening of the underlying dielectric layer. The vias may therefore interconnect and electrically couple the various metallization structures. In some embodiments, the backside redistribution structure may 110 be excluded.

Furthermore, in 3 optional vias 112 educated. As an example, for forming the vias 112 becomes a seed layer over the backside redistribution structure 110 (if present), eg the dielectric layer and the exposed portions of the metallization structure 106 formed as shown. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer that includes multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, a PVD or the like. A photoresist is formed on the seed layer and patterned. The photoresist may be formed by means of a spin coating or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to plated-through holes. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be by means of plating, such as electroplating or electroless plating, or the like be formed. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and the portions of the seed layer on which the conductive material has not been formed are removed. The photoresist may be removed by a suitable ashing or ablation process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, such as by using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the vias 112 , In other embodiments, the vias 112 be omitted (see, eg 4B and 25B) ,

In 4A become integrated circuit dies 114A and 114B using an adhesive 116 at the dielectric layer 108 adhered. As in 4A Shown are two integrated circuit dies 114A / 114B in each of the first package area 600 and the second package area 602 attached, and in other embodiments, more or less integrated circuit dies 114A / 114B be attached in every area. For example, in one embodiment, only one integrated circuit die 114A and or 114B be attached in every area. The integrated circuit dies may include logical dies (eg, central processing unit, microcontroller, etc.), memories thereof (eg, a DRAM die (dynamic random access memory), an SRAM die (static random access memory), an HMC die (hybrid memory cube) WideIO-die (wide input / output), mRAM-die (magnetoresistive random access memory), rRAM-die (resistive random access memory), etc.), power management dies (eg, a PMIC-die (integrated power management circuit), radio frequency dies (HF These), sensor dies, MEMS dies (microelectromechanical system), signal processing dies (eg, DSP die (digital signal processing)), front end dies (eg, AFE dies (analog front end), the like, or a combination thereof For example, the integrated circuit dies 114A / 114B perform the same type of functions or different types of functions. In one embodiment, the integrated circuit die 114A a processor die, while the integrated circuit die 114B a memory-die is. Additionally, in some embodiments, the integrated circuit dies may 114A / 114B different sizes (eg, different heights and / or areas), and in other embodiments, the integrated circuit die 114A / 114B the same size (eg equal heights and / or areas) have.

Before joining the dielectric layer 108 can be adhered to, the integrated circuit dies 114A / 114B Processed according to appropriate manufacturing processes to integrated circuits in the integrated circuit dies 114A / 114B train. For example, the integrated circuit dies include this 114A / 114B each a semiconductor substrate 118 , such as doped or undoped silicon, or an active layer of an SOI substrate (semiconductor on an insulator). The semiconductor substrate may comprise other semiconductor materials such as germanium, a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP. or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, etc. may be in and / or on the semiconductor substrate 118 be formed and can by using connection structures 120 by, for example, metallization structures in one or more dielectric layers on the semiconductor substrate 118 are formed to be interconnected to form an integrated circuit.

The integrated circuit dies 114A / 114B further comprise pads 122 such as aluminum pads on which external connections are made. The pads 122 These are on the integrated circuit die pages, which are the respective active sides of the integrated circuit dies 114A / 114B can be designated. passivation 124 are on the integrated circuit dies 114A / 114B and on sections of the pads 122 , These are openings through the passivation films 124 to the pads 122 available. The connector 126 , such as conductive pillars (including, for example, a metal such as copper) are in the openings through the passivation films 124 present and are mechanically and electrically with the respective pads 122 coupled. The die connectors 126 For example, they may be formed by plating or the like. The die connectors 126 electrically couple the respective integrated circuit die integrated circuits 114A / 114B ,

A dielectric material 128 is located on the active sides of the integrated circuit dies 114A , such as on the passivation films 124 and the die connectors 126 , The dielectric material 128 encapsulates the die connectors on the side 126 and the dielectric material 128 is laterally to the respective integrated circuit dies 114A adjacent. The dielectric material 128 For example, a polymer such as PBO, polyimide, BCB or the like; a nitride such as a silicon nitride or the like; an oxide such as a silica, PSG, BSG, BPSG or the like; the like or a combination thereof, and may be formed by, for example, spin coating, lamination, CVD or the like. Additionally, in some embodiments, the dielectric material becomes 128 in the integrated circuit dies 114B omitted, leaving upper surfaces and sidewalls of the die connector 126 are exposed. In other embodiments (not shown), the dielectric material 128 around the die connectors of the integrated circuit dies 114B be trained around.

An adhesive 116 is located on back sides of the integrated circuit dies 114A / 114B and is liable for the integrated circuit dies 114A / 114B to the backside redistribution structure 110 on, such as the dielectric layer 108 in the presentation. The adhesive 116 may be any suitable adhesive, epoxy, a die attach film (DAF), or the like. The adhesive 116 Can be on a back of the integrated circuit dies 114A / 114B , such as a backside of the corresponding semiconductor wafer, may be applied or may over the surface of the carrier substrate 100 be applied. The integrated circuit dies 114A / 114B For example, they can be singulated by sawing or dicing and attached to the dielectric layer 108 through the adhesive 116 For example, be adhered using a placement tool. In some embodiments (such as by 4A shown) becomes the adhesive 116 at each of the integrated circuit dies 114A / 114B adhered before the integrated circuit dies 114A / 114B on the carrier substrate 100 be attached. In other embodiments (such as by 4B in particular, when the backside RDLs 110 and the vias 112 are omitted, the adhesive 116 area-wide on the carrier substrate 110 be deposited, leaving a continuous adhesive 116 an entirety of the carrier substrate 110 covers. In such embodiments, after the adhesive 116 was deposited, the integrated circuit dies 114A / 114B on the adhesive 116 arranged and to the carrier substrate 100 adhered.

In 5 becomes an encapsulant 130 formed on the various components. The encapsulating material 130 may be a molding compound, an epoxy or the like and may be applied by molding, transfer molding or the like. The encapsulating material 130 may further fillers, such as silica or the like (eg fillers 130A , please refer 6B) include. In some embodiments, some or all of the fillers may be in the encapsulant 130 be hollow. The encapsulating material 130 can be in a liquid form around the vias 112 and the integrated circuit dies 114A / 114B be distributed. In embodiments in which sidewalls of the die connectors 126 the integrated circuit dies 114B In addition, the encapsulant may further surround the die connectors 126 the integrated circuit dies are distributed. For example, the encapsulant 130 the die connectors 126 the integrated circuit dies 114B physically contact. The encapsulant may be distributed such that it has upper surfaces of the vias 112 and the integrated circuit dies 114A / 114B covers. After the encapsulant 130 A hardening process can be performed to remove the encapsulating material 130 to harden.

After curing, the encapsulant can 130 a planarization process (eg, mechanical grinding, chemical mechanical polishing (CMP), or the like) to the vias 112 and the die connectors 126 to expose, as in 6A shown. 6B shows a detailed cross-sectional view of the area 604 in 6A , As a result of the planarization process, an upper surface of the encapsulant may 130 be uneven. The unevenness of the upper surface of the encapsulant 130 may at least partially be a consequence of the filler in the encapsulant 130 his. With reference to 6B For example, the planarization process may be the hollow core 130B the one or more fillers 130A expose, causing pits on the upper surface of the molding 130 leads. Even if the fillers 130A massive cores may also have the planarization of the fillers 130A break and / or the fillers 130A remove, leaving an upper surface of the encapsulant 130 is uneven after planarization.

After planarization becomes a polymer material 131 on the encapsulant 130 trained as through 7A shown. 7B shows a detailed cross-sectional view of the area 604 in 7A , The polymer material 131 may include PBO, polyimide, BCB or the like. In some embodiments, the polymeric material is 131 a photosensitive material. The formation of the polymer material 131 may include a coating process, such as a spin-on process. The polymer material 131 can be piled up to pits and other depressions on the top surface of the encapsulant 130 to fill. The polymer material 131 Further, upper surfaces of the die connectors 126 and the vias 112 cover. With reference to 7A For example, the polymer material 131 any exposed hollow cores 130B (please refer 6B) the fillers 130A to fill. The polymer material 131 can be up to a thickness T1 to provide adequate coverage of the uneven topography of the encapsulant 130 provide. In some Embodiments may be a ratio of the thickness T1 the polymer layer to an average diameter of the fillers 130A to the thickness T1 of the polymer layer is at least about 0.5. In some embodiments, the thickness is T1 the polymer layer at least 10 microns. In some embodiments, the method may be to form the polymeric material 131 along the uneven topography of the encapsulant 130 used coating process cause an upper surface of the polymer material 131 is not plan. For example, portions of the upper surface of the polymeric material 131 directly over exposed hollow cores 130B (please refer 6B) be uneven.

After coating, a curing process (eg, annealing) may be applied to the polymeric material 131 be applied. In embodiments where one or more of the integrated circuit dies 114A / 114B temperature-sensitive (eg, storage dies), the polymer material may be 131 comprise a low temperature polymer which is cured at a relatively low temperature (eg, less than about 300 ° C) such that the integrated circuit die 114A / 114B not be damaged. In other embodiments, the polymeric material 131 be cured at any suitable temperature.

In 8A and 8B becomes a planarization process on the polymer material 131 applied to the die connectors 126 and the vias 112 expose. 8B shows a detailed cross-sectional view of the area 604 in 8A , The planarization process also provides an upper surface with a high degree of flatness for forming additional features (eg, metallization structures) over the encapsulant 130 and the polymer material 131 ready. In some embodiments, the planarization process includes a CMP that uses a chemical suspension that is the polymeric material 131 at a higher rate than the encapsulant 130 selectively removed. For example, the chemical suspension may include silica, alumina, combinations thereof, or the like. The planarization may also be a timed process wherein an endpoint of the planarization process is determined by timing.

After planarization, sections of the polymer material may 131 , the pits and other depressions in the upper surface of the encapsulant 130 fill, remain. In addition, the planarization process may include other portions of the polymeric material 131 Remove so that areas of the encapsulant 130 (eg area 130B in 8B) be exposed. For example, after planarization, top surfaces of the polymeric material may 131 , the encapsulant 130 , the integrated circuit dies 114A / 114B and the vias 112 to be essentially coplanar. In addition, after planarization, a thickness of the polymeric material 131 vary and may range from 0 μm to about 0.1 μm across an upper surface of the encapsulant 130 lie. In addition, the planarization process can lead to a CMP backlog (for example, backlog 133 that also as pollution 133 referred to) on the upper surface of the polymer material 131 and / or the encapsulant 130 remains. The CMP residue (also referred to as a contaminant) is a different material than the polymeric material 131 and the CMP residue may comprise a material of the chemical suspension used during the CMP. For example, if the chemical suspension comprises silica, alumina, combinations thereof, or the like, the CMP residue may equally comprise molecules of silicon, aluminum, oxygen, combinations thereof, or the like.

In 9A to 19 becomes a front-side redistribution structure 160 educated. As in 20 will be illustrated, includes the front-side redistribution structure 160 dielectric layers 132 . 140 . 148 and 156 and metallization structures 138 . 146 and 154 (sometimes as redistribution layers 138 . 146 and 154 or redistribution lines 138 . 146 and 154 be designated).

In 9A and 9B becomes the dielectric layer 132 on the encapsulant 130 , the polymer material 131 , the vias 112 and the die connectors 126 arranged. 9B shows a detailed cross-sectional view of the area 604 in 9A , In some embodiments, the dielectric layer becomes 132 formed of a polymer which may be a photosensitive material such as PBO, polyimide, BCB or the like, which may be patterned using a lithographic mask. In other embodiments, the dielectric layer becomes 132 formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. A material composition of the dielectric layer 132 and the polymer material 131 can be the same or different. The dielectric layer 132 can be formed by means of spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 132 can interfacial with the polymer material 131 and / or the encapsulant 130 form. In addition, in some embodiments, the CMP residue (eg, residue 133 ) at the interface between the dielectric layer 132 and the polymer material 131 and / or at the interface between the dielectric layer 132 and the encapsulant 130 (not explicit shown). By picking up the polymer material 131 for filling recesses in the upper surface of the encapsulant 130 becomes the dielectric material 132 formed on a surface having improved flatness, resulting in an upper surface of the dielectric material 132 leads, which also has a relatively flat topography.

In 10A and 10B then becomes the dielectric layer 132 structured. The patterning forms openings around portions of the vias 112 and the die connectors 126 expose. 10B shows a detailed cross-sectional view of the area 604 in 10A , The patterning may be done by a suitable process, such as by exposing the dielectric layer 132 with light when the dielectric layer 132 is a photosensitive material, or by etching, for example, using an anisotropic etch. When the dielectric layer 132 is a photosensitive material, the dielectric layer 132 developed after exposure (eg cured by means of a cure).

In 11A and 11B becomes a metallization structure 138 with vias on the dielectric layer 132 educated. 11B shows a detailed cross-sectional view of the area 604 in 11A , To the metallization structure 138 For example, a seed layer (not shown) is formed over the dielectric layer 132 and in openings through the dielectric layer 132 educated. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer that includes multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, a PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by means of a spin coating or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 138 , The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by means of plating such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portions of the seed layer on which the conductive material has not been formed are removed. The photoresist may be removed by a suitable ashing or ablation process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, such as by using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization structure 138 and vias. The vias become openings through the dielectric layer 132 eg to the vias 112 and / or the die connectors 126 educated. In some embodiments, the metallization structure is 138 Redistribution lines with a fine pitch, which have a line width of, for example, 5 microns or less. In other embodiments, the metallization structure 138 have other dimensions. By picking up the polymer material 131 for filling recesses in the upper surface of the encapsulant 130 can the metallization structure 138 on the relatively flat upper surface of the dielectric layer 132 be formed. Consequently, manufacturing defects in the metallization structure 138 (eg broken and / or linked conductive lines) are advantageously reduced.

In 12 becomes the dielectric layer 140 on the metallization structure 138 and the dielectric layer 132 deposited. In some embodiments, the dielectric layer becomes 140 formed of a polymer which may be a photosensitive material such as PBO, polyimide, BCB or the like, which may be patterned using a lithographic mask. In other embodiments, the dielectric layer becomes 140 formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 140 can be formed by means of spin coating, lamination, CVD, the like, or a combination thereof.

In 13 then becomes the dielectric layer 140 structured. The patterning forms openings around portions of the metallization structure 138 expose. The patterning may be done by a suitable process, such as by exposing the dielectric layer 140 with light when the dielectric layer is a photosensitive material, or with etching using, for example, anisotropic etching. When the dielectric layer 140 is a photosensitive material, the dielectric layer 140 be developed after exposure.

In 14 becomes a metallization structure 146 with vias on the dielectric layer 140 educated. To the metallization structure 146 For example, a seed layer (not shown) is formed over the dielectric layer 140 and in openings through the dielectric layer 140 educated. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer that includes multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, a PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by means of a spin coating or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 146 , The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by means of plating such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portions of the seed layer on which the conductive material has not been formed are removed. The photoresist may be removed by a suitable ashing or ablation process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, such as by using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization structure 146 and vias. The vias become openings through the dielectric layer 140 , eg to sections of the metallization structure 138 educated.

In 15 becomes the dielectric layer 148 on the metallization structure 146 and the dielectric layer 140 deposited. In some embodiments, the dielectric layer becomes 148 formed of a polymer which may be a photosensitive material such as PBO, polyimide, BCB or the like, which may be patterned using a lithographic mask. In other embodiments, the dielectric layer becomes 148 formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 148 can be formed by means of spin coating, lamination, CVD, the like, or a combination thereof.

In 16 then becomes the dielectric layer 148 structured. The patterning forms openings around portions of the metallization structure 146 expose. The patterning may be done by a suitable process, such as by exposing the dielectric layer 148 with light when the dielectric layer is a photosensitive material, or with etching using, for example, anisotropic etching. When the dielectric layer 148 is a photosensitive material, the dielectric layer 148 be developed after exposure.

In 17 becomes a metallization structure 154 with vias on the dielectric layer 148 educated. To the metallization structure 154 For example, a seed layer (not shown) is formed over the dielectric layer 148 and in openings through the dielectric layer 148 educated. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer that includes multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, a PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by means of a spin coating or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 154 , The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by means of plating such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portions of the seed layer on which the conductive material has not been formed are removed. The photoresist may be removed by a suitable ashing or ablation process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, such as by using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization structure 154 and vias. The vias are through in openings the dielectric layer 148 , eg to sections of the metallization structure 146 educated.

In 18 becomes the dielectric layer 156 on the metallization structure 154 and the dielectric layer 148 deposited. In some embodiments, the dielectric layer becomes 156 formed of a polymer which may be a photosensitive material such as PBO, polyimide, BCB or the like, which may be patterned using a lithographic mask. In other embodiments, the dielectric layer becomes 156 formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. The dielectric layer 156 can be formed by means of spin coating, lamination, CVD, the like, or a combination thereof.

In 19 then becomes the dielectric layer 156 structured. The patterning forms openings around portions of the metallization structure 154 expose. The patterning may be done by a suitable process, such as by exposing the dielectric layer 156 with light when the dielectric layer is a photosensitive material, or with etching using, for example, anisotropic etching. When the dielectric layer 156 is a photosensitive material, the dielectric layer 156 be developed after exposure.

The front-side redistribution structure 160 is shown as an example. More or less dielectric layers and metallization structures may be used in the front-side redistribution structure 160 be formed. When fewer dielectric layers and metallization structures are to be formed, steps and processes discussed above may be omitted. As more dielectric layers and metallization structures are to be formed, steps and processes discussed above may be repeated. One of ordinary skill in the art will readily understand which steps and processes would be omitted or repeated.

In 20 become pads 162 on an outside of the front-side redistribution structure 160 educated. The pads 162 are used to connect with conductive connectors 166 (please refer 21 ) and may be referred to as UBMs (solderable metallizations) 162 or conductive columns 162 (please refer 25B) be designated. In the illustrated embodiment, the pads 162 through openings through the dielectric layer 156 to the metallization structure 154 educated. To the pads 162 For example, a seed layer (not shown) is formed over the dielectric layer 156 educated. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer that includes multiple sublayers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, a PVD or the like. A photoresist is then formed on the seed layer and patterned. The photoresist may be formed by means of a spin coating or the like and may be exposed to light for patterning. The structure of the photoresist corresponds to the pads 162 , The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by means of plating such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and the portions of the seed layer on which the conductive material has not been formed are removed. The photoresist may be removed by a suitable ashing or ablation process, such as using an oxygen plasma or the like. After the photoresist has been removed, exposed portions of the seed layer are removed, such as by using a suitable etching process, such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the pads 162 , In the embodiment in which the pads 162 otherwise, more photoresist and patterning steps can be used.

In 21 become the conductive connectors 166 on the UBMs 162 educated. The conductive connectors 166 For example, BGA connectors, solder balls, solder caps, metal columns, Controlled Collapse Chip Connection (C4) bumps, micro bumps, bumps (bumps) formed by ENEPIG technology (electroless nickel-electroless palladium-immersion gold), or the like. The conductive connectors 166 may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive connectors 166 is formed by initially forming a layer of solder using such commonly used methods as evaporation, electroplating, printing, solder transfer, ball placement, or the like. After a layer of solder has been formed on the structure, a reflow may be performed to form the material into the desired hillock shapes. In a In another embodiment, the conductive connectors 166 Metal columns (such as copper columns) formed by sputtering, printing, electroplating, electroless plating, CVD or the like. The metal columns may be free of solder and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) attaches to the top of metal columns 166 educated. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

In 22 a debonding of a carrier substrate is performed to the carrier substrate 100 from the backside redistribution structure, eg, the dielectric layer 104 to sever (debonden). According to some embodiments, debonding comprises projecting a light, such as a laser light or a UV light, onto the release layer 102 , so that the release layer 102 decomposed under the heat of light and the carrier substrate 100 can be removed. The structure is then turned over and on a tape 190 arranged.

As in further 22 are shown, openings through the dielectric layer 104 formed to portions of the metallization structure 106 expose. The openings may be formed using, for example, laser drilling, etching, or the like.

In 23 is a singulation process by sawing 184 along scoring frame areas, eg between adjacent areas 600 and 602 , carried out. Sawing 184 isolated the first package area 600 from the second package area 602 ,

23 shows a resulting isolated package 200 that of one of the first package area 600 or the second package area 602 can be. The package 200 may also be referred to as an integrated fan-out package (InFO package) 200.

24 shows a package structure 500 that the package 200 (which as a first package 200 can be designated) and an optional second package 300 includes. The second package 300 includes a substrate 302 and one or more stacked dies 308 (308A and 308B) with the substrate 302 are coupled. The substrate 302 can be made of a semiconductor material such as silicon, germanium, diamond or the like. In some embodiments, composites such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these and the like can also be used. In addition, the substrate can 302 an SOI substrate (silicon on an insulator). In general, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on an insulator (SGOI), or combinations thereof. The substrate 302 is based in an alternative embodiment on an insulating core, such as a glass fiber reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or alternatively other printed circuit board (PCB) materials or films. Build-up films, such as an Ajinomoto build-up film (ABF), or other laminates, may be used for the substrate 302 be used.

The substrate 302 may include active and passive devices (not in 21 shown). As one skilled in the art will appreciate, a wide variety of devices, such as transistors, capacitors, resistors, combinations of these, and the like, may be used to meet the structural and functional requirements of the semiconductor package design 300 to create. The devices may be formed using any suitable method.

The substrate 302 may also include metallization layers (not shown) and vias 306 include. The first metallization layers may be formed over the active and passive devices and are configured to connect the various devices to form a functional circuit. The metallization layers may be formed of alternating layers of a dielectric (eg, a low-k dielectric material) and a conductive material (eg, copper), with vias connecting the layers of conductive material, and may be formed by any suitable process (such as Deposition, damascene, dual damascene or the like). In some embodiments, the substrate is 302 essentially free of active and passive devices.

The substrate 302 can bondpads 303 on a first side of the substrate 202 to deal with the stacked dies 308 be coupled, and bond pads 304 on a second side of the substrate 302 wherein the second side is opposite the first side of the substrate 302 lies with the functional connectors 314 to be coupled. In some embodiments, the bond pads become 303 and 304 by forming recesses (not shown) in dielectric layers (not shown) on the first and second sides of the substrate 302 educated. The recesses are formed to allow the bond pads 303 and 304 embedded in the dielectric layers. In other embodiments, the recesses are omitted because the bond pads 303 and 304 can be formed on the dielectric layer. In some embodiments, the bond pads include 303 and 304 a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of bond pads 303 and 304 can be deposited over the thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, a CVD, an ALD, a PVD, the like, or a combination thereof. In one embodiment, the conductive material is the bond pads 303 and 304 Copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In one embodiment, the bond pads are 303 and 304 UCMs comprising three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one skilled in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium-tungsten / copper, or an arrangement of copper / nickel / Gold, responsible for training the UBMs 303 and 304 are suitable. Any suitable materials or layers of material suitable for the UBMs 303 and 304 are intended to be fully encompassed by the scope of the present application. In some embodiments, the vias extend 306 through the substrate 302 and couple at least one bonding pad 303 with at least one bondpad 304 ,

In the illustrated embodiment, the stacked dies 308 with the substrate 302 using wire bonds 310 coupled, although other connections, such as conductive mounds, can be used. In one embodiment, the stacked dies 308 This memory. For example, the stacked memory dies 308 Low Power Double Data Rate (LPDDR) memory modules such as LPDDR1, LPDDR2, LPDDR3, LPDDR4 memory modules or the like.

In some embodiments, the stacked dies 308 and the wire bonds 310 through a molding material 312 be encapsulated. The mold material 312 Can on the stacked dies 308 and the wire bonds are formed using, for example, compression molding. In some embodiments, the molding material is 312 a molding compound, a polymer, an epoxy, silica filler, the like, or a combination thereof. A curing step may be performed to remove the molding material 312 wherein the curing may be a thermal curing, a UV curing, the like, or a combination thereof.

In some embodiments, the stacked dies 308 and the wire bonds 310 in the mold material 312 buried, and after hardening of the mold material 312 For example, a planarization step, such as grinding, is performed to remove excess portions of the mold material 312 to remove and a substantially planar surface for the second packages 300 provide.

After the second packages 300 were trained, the packages are 300 mechanically and electrically to the first packages 200 using the function connector 314 , the Bondpads 304 and the metallization structure 106 bonded. In some embodiments, the stacked memory dies 308 to the integrated circuit dies 114 through the wire bonds 310 , the bond pads 303 and 304 , the vias 306 , the functional connector 314 and the vias 112 be coupled.

The functional connector 314 may be the conductive connectors described above 166 be similar and the description is not repeated here, although the function connector 314 and the conductive connectors 166 are not necessarily the same. The functional connector 314 can be on a relative to the stacked memory dies 308 opposite side of the substrate 302 to be ordered. In some embodiments, a solder resist 318 also on the side of the substrate 302 opposite the stacked dies 308 be formed. The functional connector 314 may be in openings in the solder mask 318 be arranged to work with conductive features (eg the bond pads 304 ) in the substrate 302 to be coupled electrically and mechanically. The solder mask 318 Can be used to protect areas of the substrate 302 to protect against external damage.

In some embodiments, prior to bonding, the functional connector 314 the functional connectors 314 with a flux (not shown), such as a no-clean flux coated. The functional connector 314 may be immersed in the flux or the flux may be on the functional connector 314 be sprayed. In another embodiment, the flux may be applied to the surfaces of the metallization structures 106 be applied.

In some embodiments, the functional connectors 314 have an optional epoxide flux (not shown) formed thereon before being remelted with at least a portion of the epoxide portion of the epoxide flux remaining after the second package 300 on the first package 200 was attached. This remaining epoxide section may act as an underfill to reduce stress and the linkages resulting from reflow of the functional connectors 314 result, protect.

The bonding between the second package 300 and the first package 200 may be a solder joint. In one embodiment, the second package becomes 300 to the first package 200 bonded using a reflow process. During the reflow process are the function connectors 314 with the bondpads 304 and the metallization structures 106 in contact to the second process 300 with the first process 200 to couple physically and electrically. After the bonding process, an intermetallic compound (IMC, not shown) may form at the interface of the metallization structures 106 and the functional connector 314 and also at the interface between the functional connectors 314 and the bondpads 304 (not shown) train. Even though 23 and 24 the second package 300 to represent it to the first package 200 is bonded after the first package 200 has been singulated, in other embodiments, the second package 300 to the first package 200 before separation (eg during the first package 200 is part of a package wafer, see 21 ) are bonded. After the second package 300 to the first package 200 can be the first package 200 then be separated from other packages in the package wafer.

The second package 300 is optional. In other embodiments (eg see 25B) can, especially if the backside RDL 110 and the vias 112 be omitted, the second package 300 also be omitted. In such embodiments, the memory component of the package may be replaced by the integrated circuit die 114B provided in the first package 200 along with the integrated circuit die 114A (eg a processor die). By encapsulating both the memory component and the processor component in a single encapsulated layer, a form factor of the final package (eg, Package 550 from 25B) and manufacturing costs are advantageously reduced.

25A shows the semiconductor package 500 after the packages 200 and 300 on a substrate 400 were fastened. A substrate 400 can be considered a package substrate 400 be designated. The package 200 is attached to the package substrate 400 using the conductive connectors 166 attached.

The package substrate 400 can be made of a semiconductor material such as silicon, germanium, diamond or the like. Alternatively, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these and the like may also be used. In addition, the package substrate 400 be an SOI substrate. In general, an SOI substrate comprises a layer of a semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate 400 is based in an alternative embodiment on an insulating core, such as a glass fiber reinforced resin core. An example of a core material is glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide triazine resin BT resin, or alternatively other circuit board materials or films. Build-up films such as ABF or other laminates may be used for the package substrate 400 be used.

The package substrate 400 may include active and passive devices (not in 29 shown). As one skilled in the art will appreciate, a wide variety of devices, such as transistors, capacitors, resistors, combinations of these, and the like, may be used to meet the structural and functional requirements of the semiconductor package design 500 to create. The devices may be formed using any suitable method.

The package substrate 400 may also include metallization layers and vias (not shown) and bond pads 402 over the metallization layers and the vias. The first metallization layers may be formed over the active and passive devices and are configured to connect the various devices to form a functional circuit. The metallization layers may be formed of alternating layers of a dielectric (eg, a low-k dielectric material) and a conductive material (eg, copper), with vias connecting the layers of conductive material, and may be formed by any suitable process (such as Deposition, damascene, dual damascene or the like). In some embodiments the package substrate 400 essentially free of active and passive devices.

In some embodiments, the conductive connectors 166 be remelted to the package 200 at the bondpads 402 to fix. The conductive connectors 166 electrically and / or physically couple the substrate 400 including the metallization layers in the substrate 400 , with the first package 200 , In some embodiments, passive devices (eg, surface mounted devices (SMDs), not shown) may be mounted on the substrate 400 on the package 200 attached (eg to the bond pads 402 bonded). In such embodiments, the passive devices may be attached to a same surface of the package 200 like the conductive connectors 166 be bonded.

The conductive connectors 166 may have an epoxide flux (not shown) formed thereon before being remelted with at least a portion of the epoxy portion of the epoxide flux remaining after the package 200 on the substrate 400 was attached. This remaining epoxy portion may act as an underfill to reduce stress and the bonds resulting from reflow of the conductive connectors 166 result, protect. In some embodiments, an underfill (not shown) may be between the first package 200 and the substrate 400 and the conductive connectors 166 be formed surrounding. The underfill may be formed by a capillary flow process after the package 200 or it may be formed by a suitable deposition process before the package 200 is attached.

Other features and processes can also be included. For example, test structures may be included to support the verification test of the 3D package or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which enables testing of the 3D package or 3DIC, the use of needles and / or probe cards, and / or. The verification test can be performed on intermediate structures as well as the final structure. In addition, the structures and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of known good dies to increase yield and reduce costs.

25B shows a package 550 according to some embodiments. The package 550 includes a first package 250 that to a package 400 using connectors 154A and 166A is bonded. The connectors 164A and 166A may be BGA balls, C4 hills or the like. In some embodiments, the connectors include 164A and 166A a lot cap 116A standing on a conductive pillar 164A is arranged. The package 550 can the package 500 (please refer 25A) be substantially similar, wherein like reference numerals refer to like elements. However, in package 250 the optional backside RDL 110 and the vias 112 omitted. In addition, there is no memory module (eg similar to the package 300 , as in 25B shown) on a relative to the package 400 opposite side of the first package 250 bonded. In some embodiments, the memory component of the package becomes 550 through an integrated circuit die 114B provided as described above. Although they are referred to as a "die," the integrated circuit dies 114A and or 114B unhoused chips or packaged chips (eg comprising one or more dies and / or redistribution features).

26A to 27 show cross-sectional views of different stages of manufacturing a package 502 (please refer 27 ) according to alternative embodiments. With reference to 26A and 26B is an intermediate process step for forming the package 502 (please refer 27 ). 26B shows a detailed cross-sectional view of the area 604 in from 26A , The package 502 can essentially be the package 500 (please refer 25A) be similar, wherein like reference numerals refer to like elements using the same process steps (eg as described above with reference to 1 to 11B described) are formed. Similar to the embodiments described above, the backside redistribution structure is 110 and / or the vias 112 optional and can be omitted. However, in package 502 the dielectric layer 132 (please refer 11A and 11B) omitted, and the metallization structure 138 is directly on the encapsulant 130 and the polymer material 131 designed to be the die connector 126 Integrated Circuit Die 114A who have Die Connector 126 Integrated Circuit Die 114A and the vias 112 electrically connect with each other. For example, the metallization structure forms 138 Interfaces with the encapsulant 130 and the polymer material 131 , In addition, CMP residue may be due to planarization of the polymer material 131 (shown as a residue 133 ) at the interface between the metallization structure 138 and the polymer material 131 and / or the interface between the metallization structure 138 and the encapsulant 130 to be ordered. As discussed above, the CMP residue (also as an impurity referred to) comprise a material of the chemical suspension, during the CMP of the polymer material 131 is used. For example, if the chemical suspension comprises silica, alumina, combinations thereof, or the like, the CMP residue may equally comprise molecules of silicon, aluminum, oxygen, combinations thereof, or the like. 27 shows the completed package 502 after further processing, for example, by applying the same process steps as those described above with reference to FIG 12 to 25A were discussed. In other embodiments (eg similar 25B) can, especially if the optional back-side redistribution structure 110 and the vias 112 be omitted, the package 300 be omitted.

28A to 34B show cross-sectional views of different stages of manufacturing a package 504 (please refer 34A) and / or a package 506 (please refer 34B) according to alternative embodiments. With reference to 28A and 28B is an intermediate process step for forming the packages 504 and 506 (please refer 34A and 34B) shown. 28B shows a detailed cross-sectional view of the area 604 from 28A , The features of 28A and 28B may be substantially similar to the features described above with reference to FIG 6A and 6B have been described, wherein like reference numerals indicate like elements that are formed using the same process steps. Similar to the embodiments described above, the backside redistribution structure is 110 and / or the vias 112 optional and can be omitted.

Next will be in 29A and 29B the conductive vias 112 and the die connectors 126 structured. 29B shows a detailed cross-sectional view of the area 604 in from 29A , The structuring of the conductive vias 112 and the die connectors 126 may include an etch-back process, a drilling process, combinations thereof, or the like, around the conductive vias 112 and the die connectors 126 below upper surfaces of the encapsulant 130 and the dielectric material 128 train. In some embodiments, patterning the conductive vias removes 112 and the die connectors 126 a native oxide (eg, copper oxide) attached to the top surfaces of the conductive vias 112 and the die connectors 126 is trained. It has been found that by removing this native oxide conductivity of the conductive vias 112 and the die connectors 126 can be improved. In some embodiments, when structuring the conductive vias 112 and the die connectors 126 respective heights of each of the conductive vias 112 and the die connectors 126 by a thickness T2 (please refer 29B) reduced, which may be in the range of about 0.1 microns to about 20 microns.

Next, the polymer material becomes 131 on the encapsulant 130 trained as through 30A shown. 30B shows a detailed cross-sectional view of the area 604 in 30A , The polymer material 131 may include PBO, polyimide, BCB or the like. In some embodiments, the polymeric material is 131 a photosensitive material. The formation of the polymer material 131 may include a coating process, such as a spin-on process. The polymer material 131 can be piled up to pits and other depressions on the top surface of the encapsulant 130 to fill. The polymer material 131 can also fill openings caused by the structuring of the conductive vias 112 and the die connectors 126 (please refer 29A / 29B) are defined. For example, the polymer material 131 further upper surfaces of the die connectors 126 and the vias 112 cover.

With reference to 30B may be the polymer material 131 any exposed hollow cores 130B (please refer 28B) the fillers 130A to fill. The polymer material 131 can be up to a thickness T1 to provide adequate coverage of the uneven topography of the encapsulant 130 provide. In some embodiments, a ratio of the thickness T1 the polymer layer to an average diameter of the fillers 130A to the thickness T1 of the polymer layer is at least about 0.5. In some embodiments, the thickness is T1 the polymer layer at least 10 microns. In some embodiments, the method may be to form the polymeric material 131 along the uneven topography of the encapsulant 130 used coating process cause an upper surface of the polymer material 131 is not plan. For example, portions of the upper surface of the polymeric material 131 directly over exposed hollow cores 130B (please refer 28B) be uneven.

Next will be in 31A and 31B openings 170 in the polymer material 131 structured to the vias 112 and the die connectors 126 expose. 31B shows a detailed cross-sectional view of the area 604 in 31A , The patterning may be accomplished by a suitable process, such as by exposing the polymeric material 131 with light when the dielectric layer is a photosensitive material, or by etching, for example, using anisotropic etching.

After structuring, a hardening process (eg, annealing) may be applied to the polymeric material 131 be applied. In embodiments where one or more of the integrated circuit dies 114A / 114B temperature sensitive (eg memory dies), the polymer material can 131 a low temperature polymer that is cured at a relatively low temperature (eg, less than about 300 ° C) such that the integrated circuit dies 114A / 114B not be damaged. In other embodiments, the polymeric material 131 be cured at any suitable temperature. The curing process can cure the polymer material to provide sufficient rigidity for subsequent processing steps (eg, planarization, see 32A . 32B and 32C) to enable. Although the curing process is described as following the patterning of the polymeric material 131 In other embodiments, curing of the polymeric material may be performed 131 before structuring the polymer material 131 be performed (if, for example, an etching process for structuring the polymer material 131 is used).

In 32A . 32B and 32C becomes a planarization process on the polymer material 131 applied. 32B and 32C show a detailed cross-sectional view of the area 604 in 32A , 32B corresponds to a planarization process that belongs to the package 504 (please refer 34A) according to some embodiments. 32C corresponds to a planarization process that belongs to the package 506 (please refer 34B) according to some alternative embodiments.

The planarization process provides a top surface with a high degree of flatness for forming additional features (eg, metallization structures) over the encapsulant 130 and the polymer material 131 ready. In some embodiments, the planarization process includes a CMP that uses a chemical suspension that is the polymeric material 131 at a higher rate than the encapsulant 130 selectively removed. For example, the chemical suspension may include silica, alumina, combinations thereof, or the like. The planarization may also be a timed process wherein an endpoint of the planarization process is determined by timing.

After planarization, sections of the polymer material may 131 remain, the pits and other depressions in the upper surface of the encapsulant 130 to fill. In some embodiments (see 32B) For example, the planarization process may include other portions of the polymeric material 131 Remove so that areas of the encapsulant 130 (eg area 130B in 32B) be exposed. For example, after planarization, top surfaces of the polymeric material may 131 , the encapsulant 130 , the dielectric material 128 to be essentially coplanar. In such embodiments, after planarization, a thickness of the polymeric material 131 vary and may range from 0 μm to about 0.1 μm across an upper surface of the encapsulant 130 and the dielectric material 128 lie.

In another embodiment (see 32C) The planarization process planarizes the polymer material 131 without leaving sections of the encapsulant 130 or the dielectric material 128 be exposed. For example, the polymer material covers 131 after planarization upper surfaces of the encapsulant 130 and the dielectric material 128 completely off. In such embodiments, after planarization, a thickness of the polymeric material 131 vary and may range from 0.1 μm to about 30 μm across an upper surface of the encapsulant 130 and the dielectric material 128 lie.

In addition, the planarization process can lead to a CMP backlog (for example, backlog 133 that also as pollution 133 referred to) on the upper surface of the polymer material 131 and / or the encapsulant 130 remains. The CMP residue (also referred to as a contaminant) is a different material than the polymeric material 131 and the CMP residue and may include a material of the chemical suspension used during the CMP. For example, if the chemical suspension comprises silica, alumina, combinations thereof, or the like, the CMP residue may equally comprise molecules of silicon, aluminum, oxygen, combinations thereof, or the like. In addition, a material of the CMP residue within a material composition of the polymer material 131 not found.

Next will be in 33A . 33B and 33C the metallization structure 138 directly on the polymer material 131 designed to be the die connector 126 Integrated Circuit Die 114A who have Die Connector 126 Integrated Circuit Die 114B and the vias 112 electrically connect with each other. 33B and 33C show a detailed cross-sectional view of the area 604 in 33A , 33B corresponds to the formation of a metallization structure, resulting in the package 504 (please refer 34A) according to some embodiments. 33C corresponds to the formation of a metallization structure, resulting in the package 506 (please refer 34B) according to some alternative embodiments.

In some embodiments (see 33B) forms the metallization structure 138 Interfaces with the encapsulant 130 , the dielectric material 128 and the polymer material 131 , In such embodiments, a CMP residue may be from planarizing the polymeric material 131 (shown as a residue 133 ) at the interface between the metallization structure 138 and the polymer material 131 and / or the interface between the metallization structure 138 and the encapsulant 130 be arranged. As discussed above, the CMP residue may comprise a material of the chemical suspension that may be present during the CMP of the polymeric material 131 is used. For example, if the chemical suspension comprises silica, alumina, combinations thereof, or the like, the CMP residue may equally comprise molecules of silicon, aluminum, oxygen, combinations thereof, or the like. 34A shows the completed package 504 after further processing, for example, by applying the same process steps as those described above with reference to FIG 12 to 25A were discussed. In other embodiments (eg similar 25B) can, especially if the optional back-side redistribution structure 110 and the vias 112 be omitted, the package 300 be omitted.

In some embodiments (see 33C) forms the metallization structure 138 Interfaces with the polymer material 131 without leaving interfaces with the encapsulant 130 or the dielectric material 128 be formed. In such embodiments, a CMP residue may be from planarizing the polymeric material 131 (shown as a residue 133 ) at the interface between the metallization structure 138 and the polymer material 131 be arranged. As discussed above, the CMP residue may comprise a material of the chemical suspension that may be present during the CMP of the polymeric material 131 is used. For example, if the chemical suspension comprises silica, alumina, combinations thereof, or the like, the CMP residue may equally comprise molecules of silicon, aluminum, oxygen, combinations thereof, or the like. 34B shows the completed package 506 after further processing, for example, by applying the same process steps as those described above with reference to FIG 12 to 25A were discussed. In other embodiments (eg similar 25B) can, especially if the optional back-side redistribution structure 110 and the vias 112 be omitted, the package 300 be omitted.

Various embodiments discussed above provide an additional polymeric material for filling and planarizing an uneven top surface of an encapsulant in a device package. The polymeric material is substantially free of fillers so that the polymer material can be planarized compared to the filler-containing encapsulant with improved topography. It has been found that by providing this polymeric material, manufacturing defects in subsequently formed features (e.g., conductive lines of metallization structures) can be reduced.

According to one embodiment, a method comprises encapsulating a semiconductor die in an encapsulant; Planarizing the encapsulant; Depositing a polymer material on the encapsulant; Planarizing the polymeric material; and forming a metallization structure on the polymeric material. The metallization structure electrically connects a die connector of the semiconductor die with a conductive feature disposed outside of the semiconductor die. In one embodiment, the encapsulant comprises a filler, and planarizing the encapsulant exposes a hollow core of the filler, and wherein depositing the polymeric material comprises filling the hollow core with the polymeric material. In an embodiment, the method further comprises forming a polymer layer between the polymeric material and the metallization structure. In an embodiment, forming the metallization structure comprises forming the metallization structure in physical contact with the polymeric material. In an embodiment, the method further comprises patterning a first opening through the polymeric material to expose the die connectors of the semiconductor die and patterning a second opening through the polymeric material to expose the conductive feature. Forming the metallization structure includes forming portions of the metallization structure in the first opening and the second opening. In one embodiment, the patterning of the first opening and the structuring of the second opening are performed prior to planarizing the polymeric material. In an embodiment, the method further comprises, prior to depositing the polymeric material, recessing the die of the semiconductor die below an upper surface of the encapsulant. In one embodiment, planarizing the polymeric material exposes a portion of the encapsulant.

According to one embodiment, a method comprises: arranging a first integrated circuit die adjacent to a second integrated circuit die; Capsules of the first integrated circuit die and the second integrated Circuit Die in a molding compound, wherein the molding compound comprises a plurality of fillers; and planarizing the molding compound to expose a first die connector of the first integrated circuit die and a second die connector of the second integrated circuit die. The planarization of the molding compound defines a plurality of depressions on an upper surface of the molding compound. The method further comprises depositing a polymeric material over the molding compound, wherein the polymeric material is disposed in the plurality of depressions on the upper surface of the molding compound; Planarizing the polymeric material; and forming a metallization structure over the polymeric material. The metallization structure electrically connects the first die connector to the second die connector. In one embodiment, the method further comprises depositing a polymer layer over the polymeric material, and forming the metallization structure comprises forming the metallization structure over the polymeric material. In an embodiment, forming the metallization structure comprises forming the metallization structure in physical contact with the polymeric material. In an embodiment, the method further comprises patterning the first die connector and the second die connector below an upper surface of the molding compound. In one embodiment, after planarization of the polymeric material, upper surfaces of the polymeric material, the molding compound, the first die connector, and the second die connector are coplanar.

According to one embodiment, a package includes an integrated circuit die comprising a die connector; an encapsulant disposed around the integrated circuit die; a polymeric material over at least a portion of the encapsulant; an impurity on an upper surface of the polymer material, wherein a material of the impurity is different from the polymer material; and a conductive line over the polymer material. The conductive line electrically connects the die connector to a conductive feature, and a portion of the encapsulant is disposed between the die connector and the conductive feature. In one embodiment, a polymer layer is disposed between the conductive line and the polymeric material, and the contaminant is disposed at an interface between the polymeric material and the polymeric layer. In one embodiment, the polymer layer further forms an interface with the encapsulant. In one embodiment, the polymer layer covers an entire top surface of the encapsulant. In one embodiment, the contaminant is disposed at an interface between the conductive line and the polymeric material. In one embodiment, an upper surface of the die connector is disposed below an upper surface of the encapsulant, and the polymeric material extends from the upper surface of the encapsulant to the upper surface of the die connector. In one embodiment, the contaminant comprises silicon, aluminum, or a combination thereof.

The foregoing outlines features of several embodiments so that one skilled in the art can better understand the aspects of the present disclosure. One skilled in the art should recognize that he may readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same objects and / or achieve the same advantages of the embodiments presented herein. One skilled in the art should also understand that such equivalent embodiments do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 62586558 [0001]

Claims (20)

Method, comprising: Capsules of a semiconductor die in an encapsulant, Planarizing the encapsulant, Depositing a polymer material on the encapsulant, Planarizing the polymeric material, and Forming a metallization structure on the polymer material, wherein the metallization structure electrically connects a die connector of the semiconductor die with a conductive feature disposed outside the semiconductor die. Method according to Claim 1 wherein the encapsulant comprises a filler, wherein planarizing the encapsulant exposes a hollow core of the filler, and wherein depositing the polymeric material comprises filling the hollow core with the polymeric material. Method according to Claim 1 or 2 further comprising forming a polymer layer between the polymeric material and the metallization structure. The method of any one of the preceding claims, wherein forming the metallization structure comprises forming the metallization structure in physical contact with the polymeric material. Method according to Claim 4 , further comprising: patterning a first opening through the polymeric material to expose the die connectors of the semiconductor die and patterning a second opening through the polymeric material to expose the conductive feature, wherein forming the metallization pattern comprises forming portions of the metallization structure in the first opening and the second opening. Method according to Claim 5 wherein the patterning of the first opening and the structuring of the second opening are performed prior to planarizing the polymeric material. The method of any one of the preceding claims, further comprising, prior to depositing the polymeric material, recessing the die of the semiconductor die below an upper surface of the encapsulant. The method of any one of the preceding claims, wherein planarizing the polymeric material exposes a portion of the encapsulant. Method, comprising: Depositing a first integrated circuit adjacent to a second integrated circuit die, Capsules of the first integrated circuit die and the second integrated circuit die in a molding compound, wherein the molding compound comprises a plurality of fillers, Planarizing the molding compound to expose a first die connector of the first integrated circuit die and a second die connector of the second integrated circuit die, wherein planarizing the molding compound defines a plurality of recesses on an upper surface of the molding compound; Depositing a polymeric material over the molding compound, wherein the polymeric material is disposed in the plurality of depressions on the upper surface of the molding compound, Planarizing the polymeric material, and Forming a metallization structure over the polymeric material, wherein the metallization structure electrically connects the first die connector to the second die connector. Method according to Claim 9 further comprising depositing a polymer layer over the polymeric material, wherein forming the metallization structure comprises forming the metallization structure over the polymeric layer. Method according to Claim 9 or 10 wherein forming the metallization structure comprises forming the metallization structure in contact with the polymeric material. Method according to one of the preceding Claims 9 to 11 further comprising patterning the first die connector and the second die connector below an upper surface of the molding compound. Method according to one of the preceding Claims 9 to 12 wherein after planarizing the polymeric material, upper surfaces of the polymeric material, the molding compound, the first die connector and the second die connector are coplanar. A package comprising: an integrated circuit die comprising a die connector, an encapsulant disposed about the integrated circuit die, a polymeric material over at least a portion of the encapsulant, an impurity disposed on an upper surface of the polymeric material wherein a material of the contaminant is different from the polymeric material, and a conductive line over the polymer material, wherein the conductive line electrically connects the die connector to a conductive feature, and Section of the encapsulant between the die connector and the conductive feature is arranged. Package after Claim 14 further comprising a polymer layer disposed between the conductive line and the polymeric material, the impurity being at an interface between the polymeric material and the polymeric layer. Package after Claim 15 wherein the polymer layer further forms an interface with the encapsulant. Package after Claim 15 or 16 wherein the polymer layer covers an entire top surface of the encapsulant. Package after one of the previous ones Claims 14 to 17 wherein the contaminant is at an interface between the conductive line and the polymeric material. Package after one of the previous ones Claims 14 to 18 wherein an upper surface of the die connector is disposed below an upper surface of the encapsulant, wherein the polymeric material extends from the upper surface of the encapsulant to the upper surface of the die connector. Package after one of the previous ones Claims 14 to 19 wherein the contaminant comprises silicon, aluminum or a combination thereof.

Images