DE102018003154A1 - Gate driver circuit for power transistor power loss control, junction temperature control system and method - Google Patents

Abstract

The invention relates to a gate driver circuit 10 for controlling the power loss of a power transistor 40, comprising: a control unit 12 having a control unit input 14 for receiving a control signal 16 and a control unit output 18 for outputting a control current to the gate of the power transistor 40; wherein the amount of control current from the control unit is variably adjustable and controls the switching speed of the power transistor 40. Furthermore, the invention relates to a junction temperature control system and a junction temperature control method.

Description

The invention relates to gate drive circuits for power dissipation control of power transistors, a junction temperature control system, and a method of reducing junction temperature variations.

In the field of power electronics, in addition to high energy efficiency and power density at low cost, the demands on reliability and service life are becoming increasingly important. Usually, the life of an entire power electronics application is limited by the life of the power transistors. The lifetime of power transistors depends largely on their thermal load. In particular, large temperature variations at the junction damage the power transistors. The reason for the occurring temperature fluctuations is due to the changing load conditions to which the power transistors are exposed. As a result of the changing load conditions, different power losses occur in the power transistors over time. Due to the different high power losses, the power transistors are heated to different degrees during operation and there are temperature fluctuations. There are power transistors of a variety of different material layers, these material layers have different thermal expansion coefficients. Temperature fluctuations thus cause a different expansion in their material layers. This leads to mechanical stress, which damages the power transistors and ultimately destroys them.

One way to increase the life of power electronics applications is thus to reduce the thermal stress on power transistors by a suitable junction temperature control system. In this case, a junction temperature control system must be able to reduce the thermal load on the power transistors by regulating the losses in power losses, in particular during load changes.

Previous control system solutions focus primarily on a reduction of the power loss peaks to equalize the average power loss. This is achieved, for example, by regulating the switching frequency of the power transistors or by using different modulation methods depending on the load condition. Another possibility is described by the use of additional reactive current at the load.

These control system solutions have several disadvantages. On the one hand, they offer little room for maneuver under low-load conditions, whereas in many control strategies, high additional power losses have to be generated. Furthermore, such control system solutions simultaneously affect the power dissipation of all of the power transistors used in a power electronics application. These control system solutions and gate driver circuits do not affect the output performance of the power electronics application. An individual and optimized control of the temperature at the individual power transistors is thus not possible.

It is therefore an object of the present invention to provide a junction temperature control system and components therefor, as well as a method of reducing junction temperature variations for power electronics applications that individually regulate the power transistors and enable high additional power dissipation under low load conditions.

This object is achieved by the subject matters of the independent claims. Advantageous embodiments are the subject of the dependent claims.

Unless otherwise stated, in the context of the present description, the term "connection" is always understood to mean electrical connection.

• - eine Steuereinheit mit einem Steuereinheitseingang zum Empfang eines Steuersignals und einem Steuereinheitsausgang zur Ausgabe eines Steuerstroms an das Gate des Leistungstransistors;

wobei die Höhe des Steuerstroms von der Steuereinheit variabel einstellbar ist und die Schaltgeschwindigkeit des Leistungstransistors steuert.A first independent aspect for achieving the object relates to a gate driver circuit for controlling the power loss of a power transistor, comprising:

• a control unit having a control unit input for receiving a control signal and a control unit output for outputting a control current to the gate of the power transistor;

wherein the height of the control current from the control unit is variably adjustable and controls the switching speed of the power transistor.

The main task of a junction temperature control system is the regulation of the power losses to reduce the thermal stress on power transistors. This task is essentially taken over by a control system component that is used to control the power loss of a power transistor. As power transistors in this case, to a large extent, power MOSFETs (metal oxide semiconductor field effect transistor) and IGBTs (insulated gate bipolar transistor) are used. Electrode), which are each controlled by their gate terminal. This control is realized in the present invention by gate driver circuits.

The power loss of a power transistor can be subdivided into four different loss mechanisms, which cause switching losses, conduction losses, blocking losses and additional saturation losses. These power losses can each be influenced by influences on the switching cycles. The amount of blocking losses is negligible.

Switching losses occur when the drain-source voltage and the drain current of a power transistor change at the same time. The switching losses are subdivided into switch- _on losses E _on and switch- _off losses E _off . Switch-on losses occur when the power transistor goes into a conductive state. In this case, the drain-source voltage from the reverse voltage falls to a forward voltage and the drain current increases from zero or the saturation current to the load current. During the change of these values, a certain amount of energy is converted into heat because the switching transition is not ideal. Turn-off losses occur when the power transistor switches from the conducting state to either the off state or the saturation state. Then, the drain-source voltage rises to the reverse voltage and the drain current drops to zero or to the saturation current. The total switching losses Psw result in: $$P_{sw}=\frac{1}{T_{PWM}}\cdot \left(e_{On}+e_{Off}\right)$$

The turn-on and turn-off losses can be determined with the double-pulse method.

The line losses are the product of the voltage drop V _{DS (on)} during the conduction time T _con and the drain current I _D flowing through the power transistor: $$P_{cOn}=\frac{1}{T_{PWM}}\cdot {\displaystyle \underset{T_{cOn}}{\int }{V}_{DS\left(On\right)}\left(t\right)\cdot I_D\left(t\right)\cdot dt}$$

The conduction time depends on the duty cycle of the corresponding switching cycles. The courses of the drain-source voltage _{VDS (on)} and the drain current I _D are difficult to calculate. The drain current is equal to the load current including the current ripple while the power transistor is conducting and adds to the superimposed saturation current of the other power transistors. The drain-source voltage depends on the drain current and the junction temperature. In addition, the voltage drop differs depending on whether the current flows through the power transistor or through its body diode. If the current ripple is small and the saturation current is much smaller than the load current, the line losses can P _con are approximated by the average value of the drain current and the line voltage _{VDS (on)} ,

Saturation losses are additional losses due to time _Sat depend in which the saturation current flows through the corresponding power transistor. The amount of saturation current I _sat depends on the junction temperature and the supply voltage V _sat the gate driver circuit, which is equal to the gate-source voltage in the saturation region. The additional losses add up to: $$P_{sat}=\frac{T_{sat}}{T_{PWM}}\cdot V_{DC}\cdot I_{sat}\left(V_{sat}\right)$$

The gate driver circuit comprises a control unit having at least one control unit input, a processing component and a control unit output. Hereby, the control unit receives a control signal at the control unit input, converts this control signal into a control current which can be used for the control of the power loss of the power transistor and provides this at the control unit output to the gate terminal of the power transistor.

The gate driver circuit of the first independent aspect uses the magnitude of the control current as a control quantity and thus controls the switching speed of the power transistor. In this case, the switching speed controls the power loss in the power transistor. The magnitude of the control current is variably adjustable by the processing component in the control unit of the gate drive circuit, thereby enabling variable switching speeds in the power transistor. Here, in power electronics applications, each power transistor may be individually controlled with a respective dedicated gate drive circuit.

In addition to the switching speed, the magnitude of the control current also affects the voltage and current drop in the power transistor during switching transitions. The amount of electromagnetic emission is significantly influenced. In addition, a steep current drop in the power transistor along with the parasitic inductance of the terminals causes overshoot while the power transistor turns off. Thus, the gate driver circuit can also be used to reduce electromagnetic emissions in the To reduce power electronics application or to prevent overshoot.

The switching speed and the voltage and current drops in the power transistor thus depend on the control current at the gate terminal, which is the gate capacitance C _G loading and unloading. The higher the control current in this case, the higher the switching speed and thereby also increase the voltage and current drops. When using a voltage controlled gate driver circuit, the control current is dependent I _G from the supply voltages V _CC . V _EE and from the gate resistor R _G from. With the simplifying assumption that the gate driver circuit is decoupled from the power path, the magnitude of the control current I _G calculated as follows: $$I_G\left(t\right)=\frac{V_{CC}+V_{ee}}{R_G}\cdot e^{-\frac{t}{R_G\cdot C_G}}$$

In a preferred embodiment, the control unit comprises a variably adjustable gate resistor at the control unit output and the variably adjustable gate resistor sets the magnitude of the control current.

The magnitude of the control current can be variably set by the processing component in the control unit of the gate drive circuit. In this case, either the gate series resistor or at least one of the supply voltages can be used as a manipulated variable. If the gate series resistor is selected as the manipulated variable, this results in a more complex circuit for the processing component than for the supply voltages as a manipulated variable. This results in a large resistance between the gate driver circuit and the gate terminal for a large gate series resistor. In order to prevent unwanted switching operations, disturbances to the gate connection must be minimized.

In a further preferred embodiment, the control unit provides a variably adjustable supply voltage at the control unit output and the variably adjustable supply voltage determines the magnitude of the control current.

When selecting the supply voltages as a control variable and a small resistance between the gate driver circuit and gate terminal, the gate-source voltage is almost equal to the corresponding supply voltage at all times. This allows a simpler circuit for the processing component in the control unit of the gate drive circuit. During operation, this results in a supply voltage which is equal to the gate-source voltage at the power transistor.

In a further preferred embodiment, the control unit further comprises a half-bridge circuit, through which a positive supply voltage and a negative supply voltage can be provided at the control unit output, wherein either the positive supply voltage is variably adjustable and the negative supply voltage is constant, or the positive supply voltage constant and the negative supply voltage variable is adjustable and wherein the height of the supply voltage at the control unit output determines the height of the control current.

To control the power transistor through its gate terminal, the gate driver circuit must provide at least two supply voltages at the output of its control unit so that the power transistor can be turned on and off. This is achieved for switching on by a positive supply voltage in sufficient height. To turn off a supply voltage is required, in which locks the power transistor. This is achieved for very small, but at least negative supply voltages. Therefore, for a variably adjustable amount of control current, the control unit of the gate drive circuit must provide either a variably adjustable positive supply voltage, or a variably adjustable negative supply voltage, or both a variably adjustable positive and negative supply voltage at the controller output.

Under this condition, the gate drive circuit can control the switching speed of the power transistor either at power-up, at power-off, or at power-on and power-off.

In another preferred embodiment, the magnitude of the control current, determined by the positive supply voltage, places the power transistor in a conducting state in linear operation, and blocks the magnitude of the control current, determined by the negative supply voltage, from the power transistor.

If the positive supply voltage at the gate terminal is set too low, the power transistor does not switch on at all or it operates in the saturation region of the power transistor, in which the power transistor is not fully switched on and additional power loss is generated.

In the currently described embodiment, however, the power transistor is to be operated in its linear operating state in which the power transistor is completely turned on. The lower the positive gate-source voltage of the power transistor is, the higher the resistance in the turned-on state of the power transistor and the higher its line losses. Thus, with a positive, variably adjustable supply voltage at the control unit output, the switching and line losses change in the same way. Due to the negative supply voltage, the power transistor can be completely blocked in each case. These properties are advantageous when using the gate driver circuit in a junction temperature control system with the supply voltage as the control variable. In contrast to the variation of the positive supply voltage, the variation of the negative supply voltage has no effect on the conduction losses of the power transistor.

In a further preferred embodiment, the control unit further comprises a step-down converter, which converts a constant positive supply voltage into the variably adjustable, positive supply voltage at the controller output, and / or a constant negative supply voltage into the variably adjustable, negative supply voltage at the controller output.

The duty cycle of the step-down converter results as the ratio between the output and input voltage of the step-down converter: $$D=\frac{V_{CC}}{V_{CC}^{\text{'}}}$$

The duty cycle of the buck converter can be changed at any time during the operation of the power electronics application to vary the supply voltage at the control unit output. The time required for a supply voltage change is in the millisecond range, which is sufficient for use in a junction temperature control system. The design for a variably adjustable positive and negative supply voltage by means of a buck converter is carried out in an analogous manner.

In a further preferred embodiment, a first, a second and a third supply voltage can be provided by the control unit at the control unit output, wherein the level of the supply voltage at the control unit output determines the magnitude of the control current.

In another preferred embodiment, the magnitude of the control current, as determined by the first supply voltage, places the power transistor in a conducting state in linear operation, and causes the magnitude of the control current, determined by the second supply voltage, to put the power transistor in a saturated state conducting condition. and blocks the magnitude of the control current determined by the third supply voltage, the power transistor.

In most voltage controlled gate driver circuits, as previously described, the controller provides two different supply voltages at the controller output to put the power transistor in a conducting and a blocking state. These two supply voltages are now supplemented by a further supply voltage, which puts the power transistor in a conductive state in the saturated mode.

• - jeweils einen Gate-Vorwiderstand und einen Schalter zum Bereitstellen der ersten, zweiten und dritten Versorgungsspannung am Steuereinheitsausgang;
• - eine Logik-Schaltung zum Bereitstellen der Schaltsignale für die Schalter;

wobei der Schalter zum Bereitstellen der zweiten Versorgungsspannung am Steuereinheitsausgang ein bidirektionaler Schalter ist.In a further preferred embodiment, the control unit further comprises:

• - Each a gate resistor and a switch for providing the first, second and third supply voltage at the control unit output;
• a logic circuit for providing the switching signals for the switches;

wherein the switch for providing the second supply voltage at the controller output is a bidirectional switch.

The gate driver circuit consists of a three-level voltage source and three switches to connect the different supply voltages at the control unit output to the gate terminal of the power transistor. These switches are driven by a logic circuit which converts an incoming two-bit control signal at the control unit input into the switching signals for the switches. A two-bit control signal is necessary because each power transistor should map three switching states (conducting, saturated, blocking). The second switch for switching the power transistor to a conducting state in saturated operation is a bidirectionally operating switch in order to prevent the supply voltage for the linearly conducting operation from being short-circuited to the supply voltage for the conducting operation in the saturated region. This bi-directional switch also makes it possible to charge and discharge the gate of the power transistor, depending on the state before saturation state adjustment. The gate driver circuit and its three supply voltages are connected via three gate series resistors at the gate terminal.

• - eine Steuereinheit mit einem Steuereinheitseingang zum Empfang eines Steuersignals und einem Steuereinheitsausgang zur Ausgabe eines Steuerstroms an das Gate des Leistungstransistors;

wobei der Tastgrad und die Totzeit des Steuerstroms von der Steuereinheit variabel einstellbar sind und die Verlustleistung des Leistungstransistors steuert.Another independent aspect for achieving the object relates to a gate driver circuit for controlling the power loss of a power transistor, comprising:

• - a control unit having a control unit input for receiving a control signal and a control unit output for outputting a control current to the gate of the power transistor;

wherein the duty cycle and the dead time of the control current from the control unit are variably adjustable and controls the power loss of the power transistor.

The use of dead time in conjunction with the duty cycle of a control current as a control variable in influencing the power loss in a power transistor, and thus to control the junction temperature, provides the opportunity to generate additional power loss during low load conditions. In this case, the dead time for shifting switching times within a duty cycle of the control current is used to generate a very short short circuit between the drain and source and thus additional power loss in the power transistor. Depending on the duration of the shift by the dead time, the duration of the short circuit can be varied and thus additional power loss can be set via this control variable. Parasitic inductive elements in the short circuit path prevent the current from rising too much during the short circuit.

Dead time as a control variable can only sensibly be used in power electronics applications that consist of power electronics half bridges with at least two active switching power transistors. Most converter topologies belong to this category.

Usually, in power electronics applications, dead time is used in the control of power electronics half-bridges to protect the power transistors from short circuits. Real power transistors have switching times greater than zero. This results in a transition period between the conducting state and the blocking state of the power transistor. In the case of no dead time, the two power transistors of the power electronics half-bridge have their transition period at the same time. This can lead to short circuits. The result is a very large increase in the current across the DC-Link voltage of the power electronics half-bridge through the two power transistors. This leads to large power losses, which can destroy the power transistors. Parasitic inductive elements L _σ limit the increase of the current: $$I=\frac{1}{L_{\mathrm{\sigma }}}\cdot {\displaystyle \int V_{DC}\cdot dt}$$

If the duration of the short circuit is very short, additional power dissipation occurs without destroying the power transistors.

• - mindestens ein Leistungstransistor, wobei mindestens einem Leistungstransistor jeweils eine Gate-Treiberschaltung nach einem der Ansprüche 1 bis 10 zugeordnet ist und wobei jeweils der Steuereinheitsausgang der Gate-Treiberschaltung mit dem Gate-Anschluss des zugeordneten Leistungstransistors verbunden ist;
• - eine Regelungseinheit zur Bereitstellung von Steuersignalen, wobei jeweils ein Steuersignal am Steuereinheitseingang jeweils einer Gate-Treiberschaltung anliegt und der Steuerstrom der Gate-Treiberschaltung die Verlustleistung des zugeordneten Leistungstransistors steuert;

wobei die Regelungseinheit die Verlustleistung im jeweiligen Leistungstransistor regelt, um die Temperaturschwankung in der Sperrschicht des Leistungstransistors zu minimieren.A further independent aspect for achieving the object relates to a junction temperature control system for reducing junction temperature fluctuations of at least one power transistor, comprising:

• - At least one power transistor, wherein at least one power transistor in each case a gate driver circuit according to one of claims 1 to 10 is assigned and wherein in each case the control unit output of the gate driver circuit is connected to the gate terminal of the associated power transistor;
• - A control unit for providing control signals, wherein in each case a control signal at the control unit input in each case a gate driver circuit is applied and the control current of the gate driver circuit controls the power loss of the associated power transistor;

wherein the control unit regulates the power loss in the respective power transistor in order to minimize the temperature fluctuation in the barrier layer of the power transistor.

The junction temperature control system comprises a control unit, at least one power transistor whose junction temperature is to be regulated, and a respectively associated with the power transistor gate driver circuit, as has been described in the preceding sections. In this case, both gate driver circuits can be used, which use as a control variable, the height of the control current to control the switching speed of the power transistor, and gate drive circuit with dead time as a control variable for controlling a short circuit within the power transistor. The control unit receives after a control cycle feedback whether the control has reduced the temperature fluctuation in the junction of the respective power transistors. By comparing actual value in the previous control cycle and the setpoint, the control unit then outputs the control signal to the respective control unit of the gate driver circuit.

In a preferred embodiment, the control unit increases the power loss in the respective power transistor when the load current drops at the respective power transistor.

As a feedback to the control unit, for example, the measurement of the load current in each control cycle in question. Exceeds a difference of the feedback value between the current and previous control cycle a predefined threshold value, the control unit increases the power loss in the respective power transistor. In the case of measuring the load current, the predefined threshold value is a negative value. Another possibility of the feedback is a temperature measurement at the junction of the power transistor in the respective control cycle.

In a further preferred embodiment, the junction temperature control further comprises two power transistors, each with associated gate drive circuit, wherein the two power transistors are connected to a half-bridge circuit with resistive and inductive load.

In a further preferred embodiment, the gate driver circuits according to one of the preceding embodiments are designed, and the control unit controls the duty cycle and the dead time of the respective control current of the two gate driver circuits such that both power transistors during the switching process for a period between 0 and 200ns are in a conducting state and the half bridge circuit is shorted.

The actual duration depends strongly on the structure and the transistors used. The above-mentioned duration of the common conducting state of the power transistors between 0 and 200 ns results from measurements on prototypes. This period can also be significantly higher for future prototypes.

• - Starten eines Regelungszyklus, umfassend;
• - Messen des aktuellen Laststroms in dem jeweiligen Leistungstransistor;
• - Ermitteln der Laststromdifferenz zwischen aktuellen und vorherigen Regelungszyklus für den jeweiligen Leistungstransistor;
• - Erhöhung der Verlustleistung im jeweiligen Leistungstransistor, falls die Laststromdifferenz einen negativen Schwellwert überschreitet;
• - Starten eines neuen Regelungszyklus

wobei die Erhöhung der Verlustleistung im jeweiligen Leistungstransistor über eine Reduktion der Schaltgeschwindigkeit oder über einen Kurzschlussstrom steuerbar ist.Another independent aspect for achieving the object relates to a method for reducing junction temperature fluctuations of at least one power transistor, comprising:

• - starting a control cycle, comprising;
• - measuring the current load current in the respective power transistor;
• - Determining the load current difference between the current and previous control cycle for the respective power transistor;
• - Increasing the power loss in the respective power transistor, if the load current difference exceeds a negative threshold;
• - Starting a new control cycle

wherein the increase in the power loss in the respective power transistor is controllable via a reduction of the switching speed or via a short-circuit current.

For the above-mentioned aspects and in particular for preferred embodiments thereof, the statements made above or below regarding the embodiments of the respective other aspects also apply.

In the following, individual embodiments for solving the problem will be described by way of example with reference to the figures. In this case, the individual embodiments described have in part features which are not absolutely necessary in order to carry out the claimed subject matter, but which provide desired properties in certain applications. Thus, embodiments are also to be regarded as falling under the described technical teaching, which does not have all the features of the embodiments described below. Further, in order to avoid unnecessary repetition, certain features will be mentioned only with respect to each of the embodiments described below. It should be noted that the individual embodiments should therefore be considered not only in isolation, but also in a synopsis. Based on this synopsis, those skilled in the art will recognize that individual embodiments may also be modified by incorporating one or more features of other embodiments. It should be understood that a systematic combination of the individual embodiments having single or multiple features described with respect to other embodiments may be desirable and useful, and therefore should be considered and also included within the description.

list of figures

• 1 shows a simplified representation of a gate drive circuit with a variable positive supply voltage.
• 2 shows an example of the conduction characteristic of a power transistor.
• 3 shows a schematic diagram of a gate drive circuit with variable adjustable positive supply voltage according to a preferred embodiment of the present invention.
• 4 shows a schematic diagram of a three-stage gate driver circuit with three supply voltages according to a preferred embodiment of the present invention.
• 5 shows a schematic diagram of a half-bridge circuit with resistive and inductive load.
• 6 a, b . c show duty cycle and dead times of control currents of a power electronics half-bridge circuit.
• 7 shows a simplified overview for the generation of control signals for a power electronics half-bridge circuit according to a preferred embodiment of the present invention.

Detailed description of the figures

The 1 shows a simplified illustration of a gate driver circuit 10 with variably adjustable positive supply voltage V ' _CC , The gate driver circuit 10 is only by its control unit 12 shown. The control unit 12 consists of a control unit input 14 at which a control signal 16 is applied, a half-bridge circuit 20 , a gate resistor R _G and a controller output 18 , The control signal in this case controls the half-bridge circuit, via which either a variably adjustable positive supply voltage V ' _CC or a constant negative supply voltage V _EE is applied via the gate resistor at the control unit output and thus the height of the control current is set at the control unit output. The control unit output of the gate drive circuit is finally connected to the gate terminal of a power transistor 40 connected.

The 2 shows an example of the conduction characteristic of a power transistor 40 (eg SCH2080KE, SiC MOSFET from Rohm). On the x-axis of the diagram is the drain-source voltage V _DS applied to the power transistor and on the y-axis is its drain current I _D , The individual graphs represent the functional relationship of both variables with different gate-source voltage V _GS on the power transistor. Assuming that the drain current in this example is always lower than 30A, the power transistor is for gate-to-source voltages V _GS between 0V and about 13V in a saturated state conducting state and between about 13V and 20V in a linear state conducting state.

The 3 shows a schematic diagram of a gate drive circuit with variable adjustable positive supply voltage according to a preferred embodiment of the present invention. The structure of the gate driver circuit corresponds to the circuit diagram 1 , wherein the variably adjustable positive supply voltage V ' _CC through a buck converter 28 is realized. The buck converter 28 converts the constantly positive supply voltage V _CC into the variably adjustable positive supply voltage V ' _CC around. The inductance L _BC in the order of 10μH and the capacity C _BC on the order of 100μF the variable adjustable positive supply voltage smoothes out V ' _CC , As an example, a conventional insulated gate driver 1EDI60N12AF from Infineon is used to form the half-bridge circuit of the buck converter 28 to realize. The switching frequency of such a step-down converter is 100 kHz. This leads to a voltage ripple of about 100mV, which is small enough to the switching behavior of a power transistor 40 not noticeably influence. The half-bridge circuit 20 is realized with the same component.

Due to the variably adjustable positive supply voltage V ' _CC , the height of the control current can be set variable and thus the switching speed of the power transistor 40 to be controlled.

The 4 shows a schematic diagram of a three-stage gate driver circuit 10 with three supply voltages V ₁ . V ₂ . V ₃ according to a preferred embodiment of the present invention. The three supply voltages V ₁ . V ₂ . V ₃ can do it over the three switches S ₁ . S ₂ . S ₃ with the control unit output 18 and connected to the gate terminal of the power transistor. The switches S ₁ . S ₂ . S ₃ be from a logic circuit 64 driven, which in this case an incoming two-bit control signal at the control unit input 14 in the switching signals for the switches S ₁ . S ₂ . S ₃ transforms. The second switch S ₂ For switching the power transistor in a conductive state in the saturated mode is in a bidirectional operating switch to prevent the first supply voltage V ₁ with the second supply voltage V ₂ shorted. The three-stage gate driver circuit is connected 10 over three gate resistors R ₁ . R ₂ . R ₃ at the gate terminal of the power transistor 40 ,

The 5 shows a schematic diagram of a power electronics half-bridge circuit 72 with resistive and inductive load as commonly implemented in power electronics applications. It will be to a voltage V _DC a first and a second power transistor 74 . 76 serially connected in series. Parallel to the second power transistor 76 a serial ohmic and inductive load is switched. The first power transistor 74 is doing from a first control signal SC ₁ controlled, the second power transistor 76 from a second control signal SC ₂ ,

t₁ , t₂ , t₃ und t₄ sind dabei die Zeitpunkte an denen die Steuersignale SC₁ und SC₂ an den Leistungstransistoren 74, 76 sich ändern. Wenn die Totzeit t_dead = 0s ist, ist das erste Steuersignal SC₁ immer invers zu dem zweiten Steuersignal SC₂ . (6a). Während die Totzeit positiv ist, sind die ansteigenden Flanken der Steuersignale SC₁ und SC₂ verzögert. So entsteht eine Zeitdauer, in welcher beide Leistungstransistoren 74, 76 ausgeschalten sind (6b). Wenn die Totzeit negativ ist, sind die abfallenden Flanken der Steuersignale SC₁ und SC₂ verzögert. Als Ergebnis entsteht eine Zeitdauer, in welcher beide Leistungstransistoren 74, 76 angeschaltet sind (6c). Diese Zeitdauer muss sehr kurz gewählt werden, damit der entstehende Kurzschlussstrom nicht zu stark ansteigt. Andernfalls werden die Leistungstransistoren 74, 76 beschädigt.The 6 a, b and c show duty cycle and dead times of control currents of a power electronics half-bridge circuit 72 , The dead time _dead is defined as follows: $$t_{\text{dead}}=t_2-{\mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102018003154A1\_0011.png,DE102018003154A1\_0012.png"\; state="\{\{state\}\}">t</figure-callout>}}_1=t_4-t_3$$

t ₁ . t ₂ . t ₃ and t ₄ are the times at which the control signals SC ₁ and SC ₂ at the power transistors 74 . 76 change. When the dead time _dead = 0s is the first control signal SC ₁ always inverse to the second control signal SC ₂ , ( 6a) , While the dead time is positive, the rising edges are the control signals SC ₁ and SC ₂ delayed. This creates a period of time in which both power transistors 74 . 76 are switched off ( 6b) , When the dead time is negative, the falling edges of the control signals SC ₁ and SC ₂ delayed. As a result, a period of time arises in which both power transistors 74 . 76 are turned on ( 6c ). This period of time must be very short so that the resulting short-circuit current does not increase too much. Otherwise, the power transistors will 74 . 76 damaged.

The 7 shows a simplified overview of the generation of control signals for a power electronics half-bridge circuit 72 according to a preferred embodiment of the present invention. To the power transistors 74 . 76 to control, the control signals must SC ₁ and SC ₂ from a control unit 78 to be generated. This will be within a gate driver circuit 10 from the control unit 12 caused by a programmable logic unit (CPLD). Therefore, the CPLD needs information about duty cycle and dead time. The control unit 78 transmits this information together with an activation signal to the CPLD. After generation, the control signals SC ₁ and SC ₂ to the power transistors 74 . 76 transmitted.

$$t_{\text{on},\text{S2}}=\left(1-\tau \right)\cdot t_{\text{PWM}}$$

If the enable signal is not set, no control signals will be generated SC ₁ and SC ₂ to the power transistors 74 . 76 transmitted. The duty cycle τ describes the conduction time t _{on, S1} from power transistor 74 in connection with the switching period t _PWM , It can be the times t _{on, S1} and t _{on, S2} at constant switching period t _PWM calculated to: $$t_{\text{on}.\text{S1}}=\tau \cdot t_{\text{PWM}}$$

$$t_{\text{on}.\text{S2}}=\left(1-\tau \right)\cdot t_{\text{PWM}}$$

The dead time becomes the control signals SC ₁ and SC ₂ added.

LIST OF REFERENCE NUMBERS

10

Gate drive circuit

12

control unit

14

Controller input

16

control signal

18

Control unit output

20

Half-bridge circuit

V ' _CC

variably adjustable positive supply voltage

V _EE

constant negative supply voltage

R _G

Gate series resistor

28

Buck converter

V _CC

constant positive supply voltage

V ' _EE

variably adjustable negative supply voltage

40

power transistor

V ₁

first supply voltage

V ₂

second supply voltage

V ₃

third supply voltage

S ₁

first switch

S ₂

second switch

S ₃

third switch

64

Logic circuit

R ₁

first gate resistor

R ₂

second gate resistor

R ₃

third gate resistor

72

Power electronic half-bridge circuit

74

first power transistor

76

second power transistor

78

control unit

SC ₁

first control signal

SC ₂

second control signal

Claims (15)

A gate driver circuit (10) for controlling the power dissipation of a power transistor (40), comprising: - A control unit (12) having a control unit input (14) for receiving a control signal (16) and a control unit output (18) for outputting a control current to the gate of the power transistor (40); wherein the amount of control current from the control unit is variably adjustable and controls the switching speed of the power transistor (40). Gate driver circuit (10) after Claim 1 wherein the control unit (12) comprises a variably adjustable gate resistor (R _G ) at the control unit output (18) and the variably adjustable gate series resistor (R _G ) determines the magnitude of the control current. Gate driver circuit (10) according to one of the preceding claims, wherein the control unit (12) provides a variably adjustable supply voltage (V ' _CC , V' _EE ) at the control unit output (18) and the variably adjustable supply voltage (V'cc, V ' _EE ) determines the magnitude of the control current. Gate driver circuit (10) according to one of the preceding claims, wherein the control unit (12) further comprises a half-bridge circuit (20), by which a positive supply voltage (V ' _CC , Vcc) and a negative supply voltage (V _EE , V' _EE ) can be provided at the control unit output, wherein either the positive supply voltage (V ' _CC ) is variably adjustable and the negative supply voltage (V _EE ) is constant, or the positive supply voltage (V _CC ) is constant and the negative supply voltage (V' _EE ) is variably adjustable, and wherein the magnitude of the supply voltage at the controller output (18) determines the magnitude of the control current. Gate driver circuit (10) after Claim 4 in which the magnitude of the control current, defined by the positive supply voltage (V ' _CC , V _CC ), puts the power transistor in a conducting state in linear operation, and wherein the magnitude of the control current determined by the negative supply voltage (V _EE , V' _EE ), the power transistor blocks. Gate driver circuit (10) after Claim 4 or 5 wherein the control unit (12) further comprises a buck converter (28) having either a constant positive supply voltage (V _CC ) in the variably adjustable, positive supply voltage (V ' _CC ) at the control unit output (18), and / or a constant negative supply voltage (V _EE ) to the variable adjustable negative supply voltage (V ' _EE ) at the control unit output. Gate driver circuit (10) according to one of Claims 1 to 3 in that a first, a second and a third supply voltage (V ₁ , V ₂ , V ₃ ) can be provided by the control unit (12) at the control unit output (18), and wherein the level of the supply voltage at the control unit output (18) is the height of the Control current sets. Gate driver circuit (10) after Claim 7 in that the magnitude of the control current, determined by the first supply voltage (V ₁ ), sets the power transistor (40) in a conducting state in linear operation, wherein the magnitude of the control current, determined by the second supply voltage (V ₂ ), the power transistor in a saturated state conductive state, and wherein the height of the control current, determined by the third supply voltage (V ₃ ), the power transistor blocks. Gate driver circuit (10) after Claim 8 , the control unit (12) further comprising: - in each case a gate series resistor (R ₁ , R ₂ , R ₃ ) and a switch (S ₁ , S ₂ , S ₃ ) for providing the first, second and third supply voltage (V ₁ , V ₂ , V ₃ ) at the control unit output (18); - A logic circuit (64) for providing the switching signals for the switches (S ₁ , S ₂ , S ₃ ); wherein the switch (S ₂ ) for providing the second supply voltage (V ₂ ) at the control unit output (18) is a bidirectional switch. A gate driver circuit (10) for controlling the power dissipation of a power transistor (40), comprising: - a control unit (12) having a control unit input (14) for receiving a control signal (16) and a control unit output (18) for outputting a control current to the gate of the power transistor; wherein the duty cycle and the dead time of the control current from the control unit (12) are variably adjustable and the power loss of the power transistor (40) controls. A junction temperature control system (80) for reducing junction temperature variations of at least one power transistor (40) comprising: - at least one power transistor (40), wherein at least one power transistor (40) comprises a gate driver circuit (10) according to any one of Claims 1 to 10 and wherein in each case the control unit output (18) of the gate driver circuit (10) is connected to the gate terminal of the associated power transistor (40); - A control unit (78) for providing control signals (16), wherein in each case a control signal (16) at the control unit input (14) each of a gate driver circuit (10) is applied and the control current of the gate driver circuit (10), the power loss of the associated power transistor controls; wherein the control unit (78) regulates the power loss in the respective power transistor to minimize the temperature variation in the junction of the power transistor (40). Junction temperature control system (80) according to Claim 11 , wherein the control unit (78) increases the power loss in the respective power transistor (40) when the load current drops at the respective power transistor (40). Junction temperature control system (80) according to Claim 12 . wherein the junction temperature control (80) further comprises two power transistors (74, 76) each having associated gate drive circuitry (10), and wherein the two power transistors (40) are coupled to a resistive and inductive load power electronics half-bridge circuit (72). Junction temperature control system (80) according to Claim 13 wherein the gate driver circuits (10) after Claim 10 and wherein the control unit (78) regulates the duty cycle and the dead time of the respective control current of the two gate driver circuits (10) such that both power transistors (74, 76) during the switching operation for a period of time between 0 and 200 ns in a conducting Condition are and the power electronics half-bridge circuit (72) is closed briefly. A method of reducing junction temperature variations of at least one power transistor (40), comprising: - starting a control cycle, comprising; - measuring the current load current in the respective power transistor (40); - determining the load current difference between the current and previous control cycle for the respective power transistor (40); - Increasing the power loss in each power transistor (40), if the load current difference exceeds a negative threshold; - Starting a new control cycle wherein the increase of the power loss in the respective power transistor (40) is controllable via a reduction of the switching speed or via a short-circuit current.

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