DE102017209426A1 - Error memory, in particular for a motor vehicle - Google Patents

Abstract

Device (1) for processing a plurality of possible input signals, comprising at least
a plurality of input registers (2), each of which may be in a first state or in a second state and which are each connectable to an input signal source (7), the state being changeable by an input signal from the input signal source (7),
at least one register (3, 4) in which information regarding the states of the input registers (1) can be stored,
the device (1) further comprising:
a memory circuit (9) which stores at least one value in the register (3, 4) when the state of one of the input registers (2) changes,
which represents at least the change of the state of the input register (2).

Description

State of the art

The invention relates to a fault memory, which is particularly suitable for use in a motor vehicle in the context of an OBD system (OBD = on-board diagnosis).

So far, hardware errors that occur in the vehicle while driving, stored in the hardware or hardware-related and read by a diagnostic software when accessing the vehicle via an OBD interface. By storage in the hardware or "hardware-related" storage is meant here that the errors are stored directly in the subsystems and subcomponents in which the errors occurred, for example in sub-controllers of these subsystems and subcomponents. Subsystems or subcomponents could be here, for example, a brake system with its own control unit or an airbag system with its own airbag control unit. In a motor vehicle usually exist a plurality of such subsystems.

The diagnostic software will normally have the option to clear the individual fault memories in the subsystems or subcomponents if the respective fault has been rectified. Thus, the motor vehicle can be converted back to normal operation after operation with errors, in which it can then be recognized that an error has occurred again, because previously all error memory again does not contain memory values that indicate an error or memory values on indicate a faultless operation.

The storage of the errors in the individual subsystems or the subcomponents, however, requires that it can not be recognized in which order errors have occurred if several errors have occurred in succession. Rather, each error is stored and read out individually. Accordingly, no statement can be made about the chronological order of the occurrence of the errors.

Disclosure of the invention

Described here are a device and a method with which, in particular, a particularly accurate and efficient diagnosis of highly dynamic errors is made possible. It has been found that often an initial error causes more errors. The diagnostic software should be successively given the opportunity to determine which error was the initial error or which error occurred first when several errors occur. If the initial error is known, the cause of the error can usually be determined faster and better. This is possible by reading out the first fault present.

To achieve this, a device is described which has a plurality of input registers. The input registers may each assume a first state or a second state, represented for example by 0 (first state) and 1 (second state) in the input register. The input registers may be implemented as hardware or as software. It is contemplated that input signals may alter the state of the input registers. The first state can also be referred to as (error-free) ground state. The second state may be referred to as an error condition.

Input signals come from input signal sources. Input signal sources are, for example, subsystems or subcomponents of a motor vehicle or control devices of such subsystems or subcomponents. Input signal sources are connected to the input registers, for example via signal lines. However, input signal sources can also be connected to the input registers by radio.

The input signals are in particular error signals from the input signal sources. If an input signal corresponds to a first state, there is no error. If an input signal corresponds to a second state, however, there is an error.

With the aid of the device described, additional information can be made available to software for diagnosis if the device is used to enable a diagnosis in a motor vehicle.

If the input signal sources are subsystems or sub-components or their control devices, then the device stores additional information about the course of the occurrence of an error or an error cascade. By the term "additional information" is meant information regarding the occurrence of the error, which results from the time of occurrence of the respective error and which would be lost if only the respective error memories of the subsystems or subcomponents were used. As the state of one of the input registers changes, additional information is stored in the register. This additional information may be helpful in diagnosing a fault because it indicates an order of occurrence of multiple faults.

Two different types of registers are proposed for the device, namely storage registers and output registers, which will be described below.

The memory register is characterized in particular by the fact that information of the states of all input registers can optionally be stored with additional information and essentially unchanged. The output register is characterized in particular by the fact that names of input registers can be stored therein. By storing designations of input registers in which state changes have occurred, information relating to the occurrence of state changes can also be subsequently reconstructed.

The memory register is filled by means of a memory circuit in response to changes in the states of the input registers. The memory circuit may be implemented as software or as hardware. The content of the memory register makes it possible to subsequently reconstruct the order of occurrence of individual state changes (and thus the occurrence of individual errors). This can be very helpful in the evaluation and diagnosis of errors (especially in the context of an on-board diagnosis).

The output register is also filled by means of an evaluation circuit in response to changes in the states of the input register. The evaluation circuit can also be implemented as software or as hardware. The content of the output register is an additional data source for the evaluation and diagnosis of errors.

The evaluation circuit differs from the memory circuit in that the memory circuit performs a pure storage of data while the evaluation circuit processes data and determines therefrom output values which are then stored by the evaluation circuit in the output register.

Particularly preferably, the evaluation circuit is set up such that the evaluation circuit checks whether a designation of an input register is already stored in the output register and stores a designation of the last changed input register in the output register only if no designation of an input register has yet been stored.

Further preferably, the evaluation circuit is set up such that it resorts to intermediate values which are made available to the evaluation circuit by the memory circuit.

When a plurality of state changes or errors occur immediately after one another, it is possible to save the sequence of these errors or the states of all error sources separately in different memory locations of the memory register. This further improves the possibilities for error diagnosis. Preferably, the memory register has as many memory locations as the input register device. Then, even when all possible input registers have undergone state changes, the states of all registers can be stored at each of the state changes made. A first memory location then stores the states upon the occurrence of the first state change (first error). A second memory location then stores the conditions upon the occurrence of the second state change (second error), etc.

Optionally, the memory register even has more memory locations than the input register device. Then, the memory register is also capable of fully mapping the state changes of the input registers when more state changes occur than the device has input registers. This can occur, for example, when at least one input register changes at least once from a first state to a second state and then back again to a first state.

Preferably, the memory circuit is arranged so that first of the totality of the states of the input registers, a common input parameter is formed, which assumes a first value, if all input registers in the first state and the second value assumes, if at least one of the input registers in the second state and so forth, starting from the first state (ground state), the states of the input registers are (for the first time) stored in the memory register as soon as the input parameter first changes from the first value to the second value.

It is particularly preferred if in each case a time stamp is stored when storing states in the memory register. The timestamp can be stored in a time memory, which can be part of the memory register. Particularly preferably, the memory register has a time memory for each memory location (for states), so that for each successive state changes in each case a time stamp is stored in a time memory which is assigned to the respective memory location or can be assigned. Thus, a statement can also be made (at a later date) as to the time interval between which the individual state changes (and thus the individual errors) occurred. This opens up further diagnostic options.

In a preferred application, the device is used (only) as a first error memory which ensures the occurrence of a first error. Then, the device may have as register only one output register according to the definition above and optionally no memory register.

The circuits described (the memory circuit and the evaluation circuit) may also be referred to as state machines. They automatically respond to state changes of the input registers and automatically perform operations (here, the calculation of input values for the memory register and the output register) in such state changes.

Most preferably, the device has a reset signal input, wherein at least the input and memory registers can be reset to a first state with a reset signal at the reset signal input. Preferably, via such a reset signal at the reset signal input, an output register is also reset to an output value when a corresponding output register is part of the device. The reset signal may also be referred to as a "clear signal" or as a "CLR signal". For example, the reset signal may be applied to the reset signal input if the device is to be reset after remedying a motor vehicle repair or repair in a workshop. A reset signal is transmitted to the device or to the reset signal input of the device, for example, by a diagnostic software after successful correction of the errors.

With the aid of the device, stored state changes (error signals) are stored in chronological order and subsequently made available for evaluation.

Particularly preferably, the device is equipped with a divisible by two number of input registers, for example with 16 Input registers. Most preferably, the device is equipped with a number of input registers having a power of 2 corresponds, for example 2 . 4 . 8th . 16 or 32 Input register and so on. The memory register, the output register and possibly also individual memory locations of the memory register can then each have four bits. In four bits can be encoded in which of 16 Input registers a state change has occurred. If the memory circuit writes values to the memory register whenever a state change has occurred in one of the input registers, then one can store in four bits in which of 16 Input registers the state change takes place. An output register therefore requires, for example, a width of only 4 bits in a device with 16 input registers.

It is also particularly preferred if in the memory register or in the memory locations in each case all states of all input registers are stored explicitly.

Particularly preferably, the memory circuit and the memory register are also set up so that, based on the memory register, it can subsequently also be recognized that a corresponding change in state has taken place from the second state to the first state in an input register. When the device is used to monitor faults in a motor vehicle for a subsequent diagnosis, such a state change corresponds to the case where the presence of a fault has fallen away again. This is a very valuable information for diagnosis.

The described device can be used in particular in a fault memory for a motor vehicle. The input registers of the device are then preferably connected to sources of error in the motor vehicle, which may be, for example, subsystems or subcomponents in the motor vehicle or control devices of such systems and components or, in particular, fault memory of such systems, components and control devices.

Also to be described here is a method for processing input registers, which can be carried out in particular with the described device. All the above-explained advantages and design features of the device can be transferred to the described method. The method is particularly useful for storing errors in a motor vehicle. step a ) and step b ) of the method are in particular carried out by a memory circuit which monitors the input registers and which, upon a change of state, determines a value which represents the states of all the input registers and stores them in the memory register.

step a ) is performed in particular by the fact that the device described permanently monitors the input signals or the input registers. State changes of each of the input registers are considered as events, the subsequent actions (in particular step b )) trigger. step b ) with a function stored in the device or with a circuit established in the device which is activated as a result of a state change in one of the input registers and then accesses all the input registers to determine the value representing the state of all the input registers. ,

A sub-step c ) in step b ) is preferably carried out by an evaluation circuit, which optionally intervenes for evaluation on intermediate variables that occur in the memory circuit and optionally alternatively or additionally directly accesses the input registers to determine the input register, which has first undergone a change of state.

In addition, a corresponding computer program and a machine-readable storage medium on which this computer program is stored are to be disclosed here.

• 1: Ein Kraftfahrzeug mit einer beschriebenen Vorrichtung, und
• 2: ein Ablaufdiagramm des beschriebenen Verfahrens:

The following figures further explain the disclosure. It should be noted that the features disclosed in connection with the figures may also be part of the disclosure independently of other features illustrated in the figures. Show it:

• 1 : A motor vehicle with a described device, and
• 2 : a flowchart of the described method:

1 shows a motor vehicle 6 comprising a device 1 that is part of a fault memory 5 of the motor vehicle 6 is. The motor vehicle has various subsystems 15 and subcomponents 16 , each with its own fault memory 17 exhibit. The device 1 or input register 2 the device 1 are about data connections 18 to this error memory 17 tethered. The error memory 17 form from the perspective of the device 1 Input sources 7 or sources of error 14 that from the device 1 be monitored. The device 1 know a memory circuit 9 as well as an evaluation circuit 10 on which the input registers 2 be monitored and depending on state changes in the input registers 2 Actions are performed. The memory circuit 9 When changing a state of one of the input registers, stores one value each in the memory register 3 representing the states of all input registers 2 represents.

Optionally, this storage takes place in different memory locations 8th of the memory register 3 , Optionally, the memory circuit determines 9 from a time source 12 still a current timestamp and also stores this timestamp in the memory register 3 , in particular in a designated time memory 11 , The evaluation circuit 10 stores at the first change of a state of one of the input registers 2 an output value in an output register 4 , wherein the output value is a designation of a first changed input register 2 is.

The memory circuit 9 works in particular as follows: All states (error signals) in the individual input registers 2 are combined via an AND operation into a signal (referred to below as sum error). If there is no stored error, the sum error is 1 ', if there is a stored error, is the sum error. . 0 '.

The evaluation circuit 10 then works as follows. The evaluation circuit 10 accesses the in the memory circuit 9 returned sum error. From the perspective of the memory circuit 9 this sum error is an intermediate value 19 , the evaluation circuit 10 further processed. The evaluation works in the manner of a state machine. As soon as the sum error reaches the value, 1 The evaluation circuit is activated and determines an output value which has the designation of a first changed input register and stores this value in the output register.

The device 1 has a reset signal input 13 wherein at least the input registers 2 and the storage register 3 with a reset signal at the reset signal input 13 can be reset to a first state.

2 shows a flowchart of the described method. Evident are the process steps a ) b ) and c ). Process step a) performs the monitoring of the input registers 2 from, wherein here several examples of input registers 2 shown as a box. If here a change of state in an input register 2 takes place, becomes step b ), which has at least one value in the memory register 3 stores which states of all input registers 2 represents. In addition, step c ), which is the one designation of the input register 2 in the output register 4 stores which has first undergone a state change. This step is taken c ) to intermediate values 19 back in the implementation of step b ) appeared.

Claims (12)

A device (1) for processing a plurality of possible input signals, comprising at least - a plurality of input registers (2), each of which may be in a first state or in a second state and which are each connectable to an input signal source (7), wherein the State can be changed by an input signal from the input signal source (7), at least one register (3, 4) in which information relating to the states of the input registers (1) can be stored, the device (1) further comprising: - a memory circuit (9) which, upon a change in the state of one of the input registers (2 ) stores at least one value in the register (3, 4) representing at least the change of the state of the input register (2). Device (1) according to Claim 1 , wherein as register (3,4) an output register (4) is provided, in which an output value can be stored and the device further comprises an evaluation circuit (10) which is arranged in the output register (4) a designation of an input register (2 ), which first has undergone a state change. Device (1) according to Claim 1 in which a memory register (3) having a plurality of memory locations (8) is provided as register (3, 4), wherein in successive changes of the state of one of the input registers (2) the states of all the input registers (2) in one of the memory locations (8 ) get saved. Device after Claim 3 in which the memory register (3) has at least one time memory (11), and the memory circuit (9) is set up to store the current time stamp in the time memory (11) when the state of one of the input registers (2) changes. Apparatus (1) according to any one of the preceding claims, wherein the apparatus (1) has a reset signal input (13), and wherein at least the input registers (2) and the register (3,4) are provided with a reset signal at the reset signal input (13) first state can be reset. A fault memory (5) for a motor vehicle (6) comprising at least one device (1) according to one of the preceding claims, wherein a plurality of possible fault sources (14) in the motor vehicle (6) are connected to a respective one of the input registers (2) as input signal sources (7). can be connected, wherein the respective input register (2) can be converted by the occurrence of the corresponding error from the first state to the second state. Fault memory (5) after Claim 6 , wherein as register (3,4) an output register (4) is provided, in which an output value can be stored and the device further comprises an evaluation circuit (10) which is adapted to the output register (4) a designation of a first changed input register (2) to store from output value, this designation indicating which of the possible errors was first incurred. A method of processing a plurality of possible input registers (2), which may represent a first state or a second state, wherein all input signals initially represent a first state, and wherein the method comprises at least the following steps: a) monitor for each of the input registers (2) whether a change of state occurs b) as soon as a change of state occurs, storing a value representing the states of all input registers (2) in a register (3, 4). Method according to Claim 8 in which the register (3, 4) is an output register (4) in which an output value can be stored and in step b) the following substep is additionally performed: c) determining a designation of an input register (2) which has first undergone a state change and storing this designation in the output register (4) as output value. Use of the method according to one of Claims 8 or 9 for storing error information in a motor vehicle. Computer program, which is set up, all steps of the procedure according to one of Claims 8 or 9 perform. Machine-readable storage medium on which the computer program is based Claim 11 is stored.

Images