DE102017129755B4 - Snubber network for damping the vibrations on a converter inductance of a voltage regulator and the associated process - Google Patents

Abstract

Snubber network (SN) for damping the oscillations on a converter inductance (L) of a voltage regulator (BSIC) - with a first snubber resistor (Rs) and - with a second snubber resistor (Rs) and - with a first switching transistor (M ) and- with a second switching transistor (M) and- with a first bias resistor (R) and / or with a second bias resistor (R) and- with a first bias diode (D) and / or with a second Bias diode (D) and - with a limiter element (D) and - with a passive discharge resistor (R) and - with a switch-off transistor (M), - the converter inductance (L) having a first connection and a second connection and - the converter inductance (L) being connected to the first connection with a first node (N1), which is in particular switching, and - the converter inductance (L) being connected to the second connection with a second node (N2)), which is in particular switching is, is connected and- wherein the snubber network (SN) has a first connection with which it is connected to the first connection (N1) of the converter inductance (L), and the snubber network (SN) has a second connection with which it is connected to the second connection (N2 ) the converter inductance (L) is connected, and- wherein the snubber network (SN) has a complex internal resistance (Z) between its first connection and its second connection and- wherein the snubber network (SN) has a control connection (enq) and- wherein the complex internal resistance (Z) of the snubber network (SN) depends on the state of the control connection (enq), wherein the state of the control connection (enq) can depend on a control logic and timer circuit (CLT) and- wherein the first Snubber resistor (Rs) is connected with its first connection to the first node (N1) and- wherein the first snubber resistor (Rs) is connected with its second connection to a fifth node (N5) and- wherein the second snubber- Resistor (Rs) is connected with its first connection to the second node (N2) and- wherein the second snubber resistor (Rs) is connected with its second connection to a sixth node (N6) and- wherein a series circuit, the sequence of which can be selected is, from the first bias resistor (R) and the first bias diode (D) is connected with their first connection to the first node (N1) and / or wherein the series circuit of the first bias resistor (R) and the first bias diode (D) is connected with its second connection to a third node (N3) and- wherein the cathode of the first bias diode (D) is oriented in the direction of the third node (N3) and- wherein a series circuit, the sequence of which can be selected, the second bias resistor (R) and the second bias diode (D) are connected with their first connection to the second node (N2) and / or the series circuit consisting of the second bias resistor (R ) and the second bias diode (D) with its second A. connection is connected to the third node (N3) and- wherein the cathode of the second bias diode (D) is oriented towards the third node (N3) and- wherein the control electrode of the first switching transistor (M) is connected to the third node ( N3) is connected and- wherein the control electrode of the second switching transistor (M) is connected to the third node (N3) and- wherein a first connection of the first switching transistor (M), which is not the control electrode of the first switching transistor (M), is connected to a fourth node (N4) is connected and- wherein a first terminal of the second switching transistor (M), which is not the control electrode of the second switching transistor (M), is connected to the fourth node (N4) and- wherein a second terminal of the first Switching transistor (M), which is not the control electrode of the first switching transistor (M) and not the first terminal of the first switching transistor (M), is connected to the fifth node (N5) and a second terminal de s second switching transistor (M), which is not the control electrode of the second switching transistor (M) and not the first connection of the second switching transistor (M), is connected to the sixth node (N6) and - the passive discharge resistor (R) with its first connection is connected to the fourth node (N4) and- wherein the second connection of the passive discharge resistor (R) is connected to the third node (N3) and- wherein the limiter element (D) has a first connection, in particular an anode , and a second connection, in particular a cathode, and- wherein the second connection of the limiter element (D) is connected to the third node (N3) and- wherein the first connection of the limiter element (D) is connected to the fourth node (N4) is connected and- wherein the control electrode of the switch-off transistor (M) is the control terminal (enq) and- wherein a first terminal of the switch-off transistor (M), which is not the control electrode of the switch-off transistor (M) is connected to a reference potential (GND) and- wherein a second connection of the turn-off transistor (M), which is not the control electrode of the turn-off transistor (M) and not the first connection of the turn-off transistor (M), is connected to the third node (N3) is connected.

Description

Generic term

The invention is directed to a snubber network (SN) for damping the oscillations in a converter inductance (L _boost ) of a voltage regulator (BSIC) and an associated method for damping the oscillations in the converter inductance (L _boost ) of the voltage regulator (BSIC).

General introduction

The aim of the proposal presented here is to reduce the electromagnetic emission at switching regulator nodes with high quality and the associated tendency to oscillate at the moment of switch-off. So-called snubber networks are known from the prior art.

Snubber networks for damping the tendency of the converter inductances of switched-mode power supplies to oscillate have been known for a long time, for example DE 602 12 463 T2 , EP 0 695 023 B1 , US 8,941,962 B2 , EP 1 500 181 B1 , EP 1413 039 B1 , US 6 333 861 B1 , and US 6 532 160 B2 known.

From the US 6 625 046 B2 is from theirs 14th a switch (reference number 1400 of US 6 625 046 B2 ) known that a pair of switches or IGBT's (reference numerals 1402 and 1403 of the US 6 625 046 B2 ) and a pair of diodes (reference numerals 1404 and 1405 of the US 6 625 046 B2 ) having. A diode (reference number 1404 of US 6 625 046 B2 ) of the two diodes (reference numerals 1402 and 1404 of the US 6 625 046 B2 ) is an anti-parallel diode to a first switch (reference number 1402 of US 6 625 046 B2 ). The other diode (reference number 1405 of US 6 625 046 B2 ) of the two diodes (reference numerals 1402 and 1404 of the US 6 625 046 B2 ) is an anti-parallel diode to a second switch (reference number 1403 of the US 6 625 046 B2 ). The two switch / diode combinations are connected in series, but reversed to each other and connected in opposite directions. The aim is, according to the description of the US 6 625 046 B2 to get a diode whose direction can be switched. This diode construction, which can be switched in direction, is used to smoothly switch the high-side transistor (reference number 1502 of FIG US 6 625 046 B2 ) or the low-side transistor (reference number 1504 of US 6 625 046 B2 ) memorize.

However, the techniques and methods described in these publications are not suitable for reducing switching energies in the converter inductances with low EMC radiation if the load is not constant. Rather, they are usually geared towards changing the phase position appropriately, e.g. to work optimally via capacitive or inductive networks with constant load.

Also from the US 2008/0 252 273 A1 , of the US 2009/0 115 388 A1 and the US 9 787 179 B1 subber networks are known. The specific solution for symmetrical control is not specified in any of these documents.

Object of the invention

The invention is therefore based on the object of creating a concrete solution which, on average, has lower losses during operation than the solutions from the prior art in the partial load range or in intermittent operation, that is to say with a non-constant load, and has further advantages.

This object is achieved by a device according to claim 1 and a method according to claim 4.

Solution of the task

A circuit is proposed with which the damping function of the external components can be implemented. The proposal is designed in such a way that decay processes are designed with as little radiation as possible while at the same time generating as little power as possible in a relief network, hereinafter referred to as a snubber network (SN). The basic idea is to incorporate an integrated relief or snubber network (SN) into a micro-integrated voltage regulator circuit (BSIC).

1. 1. ein erster Betriebsmodus mit einer hohen Dämpfung und hohen Verlusten und
2. 2. ein zweiter Betriebsmodus mit einer geringen Dämpfung und nur geringen Verlusten.

It is proposed that the necessary damping of the parasitic resonant circuit consisting of parasitic node capacitances (C _p ) and converter inductance (L _boost ) should be connected in parallel to this parasitic resonant circuit consisting of parasitic node capacitances (C _p ) as parallel damping in the form of a relief or snubber network (SN) and converter inductance (L _boost ) to be introduced into the overall circuit. In contrast to the prior art, it is now proposed to make the relief or snubber network (SN) and thus the damping of the parasitic resonant circuit from parasitic node capacitances (C _p ) and converter inductance (L _boost ) selectively switchable for power loss reasons. This creates two operating modes:

1. 1. a first operating mode with high damping and high losses and
2. 2. a second operating mode with low damping and only low losses.

The first operating mode is activated in the event of load and voltage changes, the second operating mode is activated in normal operation.

The special thing is that in the first operating mode the energy of the oscillation itself is used to keep the snubber network (SN) quasi passive: The transistors in the snubber network (SN) do not have to be actively driven by the circuit, but rather be driven Quasi passively controlled from the voltage difference as a result of the oscillating energy. For this purpose, in anticipation of the description of the characters 4th referenced, which represents a special implementation of a snubber network (SN). The wiring rectifies the voltage difference between the first connection node (N1) of the snubber network (SN) and the second connection node (N2) and uses it to control the control electrodes (gates) of the switching transistors (M _s ).

In 1 The drawings show an exemplary circuit structure of a switching regulator in the form of an exemplary integrated circuit of the boost converter (BSIC). The parasitic resonant circuit to be damped consists of the two parasitic node capacitances (C _p ) at the first node (N1) and the second node (N2) and the converter inductance (L _boost ).

The circuit of the exemplary integrated circuit of the boost converter (BSIC) of the 1 is supplied with electrical energy from the supply voltage (Vdd) and the reference potential (GND).

• Der elektrische Strom fließt über den typischerweise eingeschalteten High-Side-Transistor (T1) und die Konverterinduktivität (L_boost) durch die Freilaufdiode (FD) in die Boost-Kapazität (C_boost), die als Energiespeicher für die Last am Ausgang (out) des Spannungsreglers (BSIC) dient. Der Low-Side-transistor (T2) wird periodisch geschlossen. Hierdurch fließt ein Strom durch die Konverterinduktivität (L_boost) zum Bezugspotenzial (GND). Wird der Low-Side-transistor (T2) geöffnet, so wird das Potenzial am Knoten N2 über das Potenzial am Ausgang (out) durch Selbstinduktion der Konverterinduktivität (L_boost) angehoben und die Boost-Kapazität (C_boost) mit dem Strom der Konverterinduktivität (L_boost) geladen. Das Ein- und Ausschalten des High-Side-Transistors (T1) und des Low-Side-Transistors (T2) werden dabei durch eine Kontrolllogik- und Zeitgeberschaltung (CTL) gesteuert. Die Kontrolllogik- und Zeitgeberschaltung (CTL) erzeugt ein Treibereingangssignal (H_vT1) für den High-Side-Treiber (DR1) für den High-Side-Transistor (T1). Des Weiteren erzeugt die Kontrolllogik- und Zeitgeberschaltung (CTL) ein Treibereingangssignal (L_pwm) für den Low-Side-Treiber (DR2) des Low-Side-Transistors (T2). Der High-Side-Treiber (DR1) erzeugt aus dem einen Treibereingangssignal (H_vT1) für den High-Side-Treiber (DR1) ein Steuersignal (H_T1) für die Steuerelektrode des High-Side-Transistors (T1). Der Low-Side-Treiber (DR2) erzeugt aus dem Treibereingangssignal (L_pwm) für den Low-Side-Treiber (DR2) ein Steuersignal (L_T2) für die Steuerelektrode des Low-Side-Transistors (T2).

A load at the output (out) of the switching regulator (BSIC) is supplied with electrical energy as follows:

• The electrical current flows through the high-side transistor (T1), which is typically switched on, and the converter inductance (L _boost ) through the freewheeling diode (FD) into the boost capacitance (C _boost ), which _acts as an energy store for the load at the output (out) of the voltage regulator (BSIC). The low-side transistor (T2) is closed periodically. This causes a current to flow through the converter inductance (L _boost ) to the reference potential (GND). If the low-side transistor (T2) is opened, the potential at node N2 is raised above the potential at the output (out) through self-induction of the converter inductance (L _boost ) and the boost capacitance (C _boost ) with the current of the converter inductance (L _boost ) loaded. The switching on and off of the high-side transistor (T1) and the low-side transistor (T2) are controlled by a control logic and timer circuit (CTL). The control _logic and timer circuit (CTL) generates a driver input signal (H _vT1 ) for the high-side driver (DR1) for the high-side transistor (T1). Furthermore, the control _{logic and timing circuit} (CTL) generates a driver input _signal (L _pwm ) for the low-side driver (DR2) of the low-side transistor (T2). The high-side driver (DR1) generates a control signal (H _T1 ) for the control electrode of the high-side transistor (T1) from the one driver input _signal (H _vT1 ) for the high-side driver (DR1). The low-side driver (DR2) generates a control signal (L _T2 ) for the control electrode of the low-side transistor (T2) from the driver input _signal (L _pwm ) for the low-side driver (DR2).

A first current measuring device (M _v1 ) detects the current from the supply voltage (Vdd) into the high-side transistor (T1) as a high-side current actual signal (I _Hist ). A high-side overcurrent protection (HSOCP) evaluates the high-side current actual signal (I _Hist ) and generates a high-side overcurrent warning signal (W _H ) if a high-side maximum current threshold is exceeded. The control logic and timer circuit (CTL) evaluates the high-side overcurrent warning signal (W _H ) and switches off the high-side transistor (T1) in the event of an overcurrent. The voltage limiting diode (ZD1) takes over the current in this case. It should be mentioned here that the voltage limiting diode (ZD1) does not necessarily have to be a Zener diode if the reference number of the voltage limiting diode (ZD1) suggests this. On the contrary, a normal diode is completely sufficient at this point.

A second current measuring device (M _v2 ) detects the current into the reference potential (GND) out of the low-side transistor (T2) as a low-side current actual signal (I _List ). A low-side overcurrent protection (LSOCP) evaluates the low-side current actual signal (I _List ) and generates a low-side overcurrent warning signal (W _L ) when a low-side maximum current threshold is exceeded. An overcurrent warning suppression (BL) only generates an overcurrent warning in the form of an overcurrent signal (OCS) if enough time has passed after the low-side transistor (T2) has switched so as not to trigger an overcurrent warning due to current peaks during the actual switching process. For this purpose, the overcurrent _{warning suppression} (BL) evaluates the driver input _signal (L _pwm ) for the low-side driver (DR2) of the low-side transistor (T2) and the low-side overcurrent _{warning signal} (W _L ) and then generates the Overcurrent signal (OCS). The control logic and timer circuit (CTL) evaluates the overcurrent signal (OCS) and switches off the high-side transistor (T1) and the low-side transistor (T2) in the event of an overcurrent.

A relative voltage measuring device (RVM) records the boost voltage (V _boost ) at the output (out) of the voltage regulator and generates a voltage measurement signal (V _m ) as a function of this voltage. A regulator (REG) compares the voltage measurement signal (V _m ) with a reference voltage (V _ref ) and generates a control signal (V _reg ) as a function of the deviation - typically as a function of the voltage difference (V _ref -V _m ). The control logic and timer circuit (CTL) evaluates the control signal (V _reg ) and controls the switching state of the high-side transistor (T1) and depending on the control signal (V _reg ) and the time as well as depending on the aforementioned signals the switching state of the low-side transistor (T2). In normal operation, the high-side switch (T1) is essentially switched on, while at the same time the low-side transistor (T2) is preferably clocked with the same or higher frequency.

However, if the boost voltage (V _boost ) at the output reaches the target value, both the high-side transistor (T1) and the low-side transistor (T2) are switched off by the control logic and timer circuit (CTL) to save energy in order to save energy, since the converter inductance (L _boost ), the high-side switch (T1) and the low-side switch (T2) always have a loss resistance when a current flows ... Hig-Side-transistor (T1) through the voltage limiting diode (ZD1) the energy in the converter inductance (L _boost ) can be reduced quickly. This advantageously leads to a lower energy input at the output (out) beyond the target value of the boost voltage (V _boost ) aimed at by the regulation. If the boost capacity (C _boost ) is sufficiently charged, this flow of current is unnecessary and only leads to losses. Switching off the high-side transistor (T1) and the low-side transistor (T2) therefore leads to an oscillation of the parasitic resonant circuit made up of parasitic node capacitances (C _p ) and converter inductance (after the energy in the converter _{inductance has been reduced} ) (L _boost ) L _boost ). The control logic and timer circuit (CTL) therefore switches in this case between the first node (N1), which corresponds to the drain of the high-side transistor and a first connection, the converter inductance (L _boost ), and the second node (N2) , which corresponds to the drain of the low-side transistor and a second connection of the converter inductance (L _boost ), a damping network (subber network SN). This snubber network (SN) is advantageously controlled from the energy of the oscillation itself and subsequently works advantageously adaptively based on the amplitudes of the voltage difference between the nodes to be damped (N1, N2) and absorbs the energy in the converter inductance (L _boost ) and energy stored in the parasitic nodal capacitances (C _p ). During normal operation, the high-side transistor (T1) is switched on and the low-side transistor (T2) is switched on with a PWM by control _logic and timer _circuit (CTL) via the driver input _signal (L _pwm ) for the low-side driver ( DR2) of the low-side transistor (T2) is activated. For this normal operation, in contrast to the prior art, it is now proposed that the snubber network (SN) be in a high-resistance state with respect to the two connections of the snubber network (SN), which are connected to the first node (N1) and connected to the second node (N2) to switch. For this purpose, the control logic and timer circuit (CTL) generates the corresponding control signal (enq).

1. a. Spitzenströmen und Verlusten in einem Snubber-Netzwerk (SN) gegenüber
2. b. der erzielten Dämpfung.

In 2 the principle influence of the snubber network (SN) is shown together with the objective function. The 2a represents an excerpt from the 1 The snubber network (SN) is connected between the first node (N1) and the second node (N2). The parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ) is also connected in parallel between the first node (N1) and the second node (N2). The snubber network (SN) has a complex resistance (Z _SN ). For this complex resistance (Z _SN ) of the snubber network (SN), an optimum damping of the parasitic resonant circuit (C _p , L _boost ) is to be determined as a compromise between

1. a. Contrasting peak currents and losses in a snubber network (SN)
2. b. the attenuation achieved.

In 2 B the complex resistance (Z _SN ) of the snubber network (SN) is not adapted to the resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ). This is the case, for example, when the snubber network (SN) is switched to a high-resistance state by means of the control signal (enq), that is to say has a complex resistor (Z _SN ) with a high ohmic component.

In 2c the complex resistance (Z _SN ) of the snubber network (SN) is adapted to the resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ). This is the case, for example, when the snubber network (SN) is switched to a low-resistance state or a passive damping state by means of the control signal (enq), i.e. has a complex resistor (Z _SN ) with a low ohmic component. The complex resistance (Z _SN ) of the snubber network (SN) should preferably have the same ohmic real part as the parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ) between the first node (N1) and its second node (N2) at its resonance frequency (f _r ). As a result, the snubber network (SN) is then optimally adapted to the energy source, the parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ), and takes energy from this parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic ones at maximum speed Nodal capacities (C _p ). However, it has been shown that a certain mismatch makes sense. In a reference application that was used to develop the proposal, real parts were found in the resonance circuit of 1-4 ohms (DC resistance of the converter inductance (L _boost ) with direct voltage control. The resonance resistance was typically 3-4kOhm. In comparison, a switched Impedance with approx. 4kOhm introduced. This case is roughly in 2c shown. For rework, it is recommended to use simulations to determine the appropriate compromise between transient response, chip area and temperature load, depending on the application, according to the properties of the planned load and the intended converter inductance (L _boost ). As a result, the radiation of the circuit is massively improved and thus the EMC behavior is optimized.

The snubber network (SN) is therefore preferably designed in such a way that, in a state of the control connection (enq), the real part of the complex internal resistance (Z _SN ) of the snubber network (SN) is not more than 200% or not more than 150% or not more than 120% or not more than 110% or not more than 105% of the magnitude of the resonance resistance (R _r ) of the parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ) and the snubber network (SN) be designed so that in this state of the control connection (enq) the real part of the complex internal resistance (Z _SN ) of the snubber network (SN) is not less than 50% or not less than 75% or not less than 88% or not less than 95% or not less than 98% of the magnitude of the resonance resistance value (R _r ) of the parasitic resonant circuit composed of converter inductance (L _boost ) and parasitic node capacitances (C _p ).

When dimensioning the adaptation, however, the heat output must also be taken into account. Depending on the housing, a subpoptimal adaptation can therefore be useful in different ways, depending on application to application.

In 3 various stages of development of a snubber network (SN) are shown. 3a shows a snubber network (SN) according to the prior art. In the prior art, an RC filter is located at the first node (N1), for example, consisting of a capacitance (C _s ) and a resistor (R _s ) and, symmetrically to this, at the second node (N2) an RC filter of the same design (see FIG 3a) . The snubber network (SN) can also be implemented potential-free without a ground connection using an RC filter (C _s , R _s ) according to the state of the art ( 3b) . The snubber network (SN) in the prior art can also be used as a simple resistor ( 3c ) will be realized. According to the proposal, provision is now made to increase the resistance of the snubber network (SN) in normal operation as a function of a control signal (enq) of the snubber network (SN) and, if attenuation is necessary, to reduce it by means of this control signal (enq) ( 3d ). In the simplest case, the snubber network (SN) can be interrupted by a switch depending on the control signal (enq) of the snubber network (SN).

In 4th is for the sake of completeness a detailed, exemplary proposal for the implementation of a switchable snubber network (SN) accordingly 3d shown in simplified form in the integrated circuit of the boost converter (BSIC). The switch of the 3d is in the 4th realized by the two switching transistors (M _s ) in what is known as a back-to-back arrangement for opening and closing the connection between nodes N1 and N2. These are connected in series with the two actual snubber resistors (R _s ), in which the oscillation energy of the parasitic oscillating circuit (C _p , L _boost ) to be destroyed can be converted into heat when the device is switched off. It is suggested to build the snubber network (SN) in a highly symmetrical manner in order to maximize the damping and EMC effect. A limiter element (D _G ) (for example a Zener diode) is used to limit the maximum gate-source voltage (V _GS ) of the switching transistors (M _S ) of the proposed switchable snubber network (SN). One bias resistor (R _B ) per switching transistor (M _s ) is used to charge the respective control electrode (gate) of the respective switching transistor (M _s ) from the potential difference between nodes N1 and N2 and to limit the current in the limiter element (D _G ) a diode is provided. One bias diode (D _B ) is provided for rectifying the potential difference between N1 and N2. In addition, they advantageously allow the damping network with a suitable time constant, which is determined via the node capacitance at the third node (N3) and the passive discharge resistance (R _G ) for the gates of the switching transistors (M _S ), beyond the decay of the oscillation keep active. These bias diodes (D _B ) also prevent a cross current through the bias network between the first node (N1) and the second node (N2). It is also of interest here that control in this way can also take place implicitly above the available supply voltages, since it is a type of charge pump. The passive one Discharge resistor (R _G ) is used to discharge the gates of the switching transistors (Ms). This construction makes it possible to use a switch-off transistor (M _DIS ) to effectively activate the snubber network (SN) between the first node (N1) and the second node (N2), i.e. to switch it to low resistance, or to deactivate it, i.e. to high-resistance to switch. An advantageous property of this implementation of the snubber network (SN) is the low effort required to control the snubber network (SN), which in particular allows the integration effort within an integrated circuit to be reduced.

The proposed method of changing the internal resistance of the snubber network (SN) to a first internal resistance value (Z _SN1 ) for the case of normal operation and a second internal resistance value (Z _SN2 ) for the case that the target output voltage at the output (out) has been reached, can be used for switching regulators in general. The snubber network (SN) is preferably used in parallel to the energy-storing inductance in the relevant switching regulator construction. The approach shown can thus also be extended to other switching regulator circuits than the boost circuit shown with reference to the battery by a person skilled in the art. For example, the transmission to Buck converters, whose switching nodes and output nodes are usually part of the interface of an integrated circuit interfaces, can be used. In principle, the principle of using a switchable parallel attenuation circuit (snubber network) can also be used there.

A snubber network (SN) is therefore proposed for damping the vibrations at a converter inductance (L _boost ) of a voltage regulator (BSIC) with a controllable shunt resistance (Z _SN ). The converter inductance (L _boost ) has a first connection and a second connection, the converter inductance (L _boost ) being connected to the first connection to a first node (N1) and being connected to the second connection to a second node (N2) . The snubber network (SN) also has a first connection with which it is connected to the first connection (N1) of the converter inductance (L _boost ), and a second connection with which it is connected to the second connection (N2) of the Converter inductance (L _boost ) is connected. The snubber network (SN) has a complex internal resistance (Z _SN ) between its first connection and its second connection. The snubber network (SN) has a control connection (enq), the complex internal resistance (Z _SN ) of the snubber network (SN) depending on the state of the control connection (enq).

The converter inductance (L _boost ) and parasitic node capacitances (C _p ) at the first node (N1) and at the second node (N2) form a parasitic resonant circuit with a resonance frequency ( _fr ), the parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic Node capacitances (C _p ) at this resonance frequency ( _fr ) has a resonance resistance value (R _r ) between the first node (N1) and the second node (N2). This resonance resistance (R _r ) is very often between 3 and 4 kOhm. In a preferred variant of the proposal, the snubber network (SN) is designed such that in a first state of the control connection (enq) the real part of the complex internal resistance (Z _SN ) of the snubber network (SN) does not exceed 200% or better no more than 150% or better no more than 120% or better no more than 110% or better no more than 105% of the magnitude of the resonance resistance value (R _r ) of the parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ) and that in this first state of the control connection (enq) the real part of the complex internal resistance (Z _SN ) of the snubber network (SN) is not less than 50% or better not less than 75% or better not less than 88% or better not less than 95% or better not less than 98% of the magnitude of the resonance resistance value (R _r ) of the parasitic resonant circuit composed of converter inductance (L _boost ) and parasitic node capacitances (C _p ) be wearing.

Such a snubber network (SN, 4th ) comprises in a preferred variant of the proposal a first snubber resistor (Rs), a second snubber resistor (Rs), a first switching transistor (M _s ), a second switching transistor (M _s ), a first bias resistor (R _B ), a second bias resistor (R _B ), a first bias diode (D _B ), a second bias diode (D _B ), a limiter element (D _G ), a passive discharge resistor (R _G ) and a Switch-off transistor (M _DIS ). The first snubber resistor (Rs) is connected with its first connection to the first node (N1) and with its second connection and a fifth node (N5). The second snubber resistor (Rs) is connected with its first connection to the second node (N2) and with its second connection and a sixth node (N6). A series circuit comprising the first bias resistor (R _B ) and the first bias diode (D _B ) has its first connection connected to the first node (N1) and its second connection connected to a third node (N3). The cathode of the first bias The diode (D _B ) is oriented towards the third node (N3). A series circuit made up of the second bias resistor (R _B ) and the second bias diode (D _B ) has its first connection connected to the second node (N2) and its second connection connected to the third node (N3). The cathode of the second bias diode (D _B ) is oriented in the direction of the third node (N3). The control electrode of the first switching transistor (M _s ) is connected to the third node (N3) and the control electrode of the second switching transistor (M _s ) is connected to the third node (N3). A first connection of the first switching transistor (M _s ), which is not the control electrode of the first switching transistor (M _s ), is connected to a fourth node (N4). A first connection of the second switching transistor (M _s ), which is not the control electrode of the second switching transistor (M _s ), is connected to the fourth node (N4). A second connection of the first switching transistor (M _s ), which is not the control electrode of the first switching transistor (M _s ) and not the first connection of the first switching transistor (M _s ), is connected to the fifth node (N5). A second connection of the second switching transistor (M _s ), which is not the control electrode of the second switching transistor (M _s ) and not the first connection of the second switching transistor (M _s ), is connected to the sixth node (N6). The passive discharge resistor (R _G ) is connected with its first connection to the fourth node (N4) and with its second connection to the third node (N3). The limiter element (D _G ) has an anode and a cathode. The cathode of the limiter element (D _G ) is connected to the third node (N3) and the anode of the limiter element (D _G ) is connected to the fourth node (N4). The control electrode of the switch-off transistor (M _DIS ) is the control connection (enq) of the snubber network (SN). A first connection of the switch-off transistor (M _DIS ), which is not the control electrode of the switch-off transistor (M _DIS ), is connected to a reference potential (GND). A second connection of the switch-off transistor (M _DIS ), which is not the control electrode of the switch-off transistor (M _DIS ) and not the first connection of the switch-off transistor (M _DIS ), is connected to the third node (K3).

A method for damping the vibrations at a converter inductance (L _boost ) of a voltage regulator (BSIC) with an output (out) and a reference potential (GND) is therefore proposed. The converter inductance (L _boost ) has a first connection and a second connection. The converter inductance (L _boost ) is connected with the first connection to a first node (N1) and with the second connection with a second node (N2). A snubber network (SN) has a first connection with which it is connected to the first connection (N1) of the converter inductance (L _boost ), and a second connection with which it is connected to the second connection (N2) of the converter inductance (L _boost ) is connected. The snubber network (SN) has a complex internal resistance (Z _SN ) between its first connection and its second connection. The snubber network (SN) also has a control connection (enq). The complex internal resistance (Z _SN ) of the snubber network (SN) depends on the state of the control connection (enq) and can therefore be controlled via the control connection (enq). The method comprises the steps of energizing the converter inductance (L _boost ) with a current (I _boost ) that deviates from zero amperes in the time average, and switching the complex internal resistance (Z _SN ) of the snubber network (SN) to a first complex internal resistance value (Z _SN1 ) of the snubber network (SN) if the output voltage difference between the output (out) of the voltage regulator (BSIC) and the reference potential (GND) deviates from a specified reference value by more than a specified minimum voltage difference ΔV, and not energizing the converter inductance (L _boost ) and switching the complex internal resistance (Z _SN ) of the snubber network (SN) to a second complex internal resistance value (Z _SN2 ) of the snubber network (SN) if the output voltage difference between the output ( out) of the voltage regulator (BSIC) and the reference potential (GND) from a specified reference value by less than a specified minimum all voltage difference ΔV deviates in amount. The real part of the first complex internal resistance value (Z _SN1 ) of the snubber network (SN) is greater than the real part of the second complex internal resistance value (Z _SN2 ) of the snubber network (SN).

In a variant of the method, the properties of the vibrating element are used. The oscillations of the converter inductance (L _boost ) occur with a resonance frequency (f _r ) when they occur. The Konverterinduktivität (L _boost) and the vibration-causing parasitic components (C _p) have a resonance resistance value (R _r) on at this resonant frequency (f _r). The real part of the second complex internal resistance value (Z _SN2 ) of the snubber network (SN) is preferably not more than 200% or better not more than 150% or better not more than 120% or better not more than 110% or better not more than 105% of the amount of resonance resistance (R _r ) and not less than 50% or better not less than 75% or better not less than 88% or better not less than 95% or better not less than 98% of the amount of resonance resistance (R _r ).

Advantage of the proposal

Such a snubber network (SN) for damping the oscillations on a converter inductance (L _boost ) of a voltage regulator (BSIC) enables, at least in some implementations, on average lower losses than the solutions from the prior art when the load is not constant. The advantages are not limited to this.

A significant commercial advantage is that a possible integration into a microelectronic circuit avoids external component costs and thus increases the functional reliability. Added to this is the reduced installation space required due to the integration, which in turn is advantageous in terms of the interference emitted by the switching operation itself. At the same time, it is possible to save power loss by actively switching the snubber network (SN) inversely to the activity of the switching regulator. The snubber network (SN) is therefore preferably always switched to a low-resistance state when the switching regulator does not have to supply the boost capacitance (C _boost ) with energy. The snubber network (SN) is therefore also preferably switched to a high-resistance state whenever the switching regulator has to supply the boost capacitance (C _boost ) with energy.

List of reference symbols

BL

Overcurrent alarm suppression;

BSIC

integrated circuit of the boost converter;

C _boost

Boost capacity;

CLT

Control logic and timer circuit;

C _p

parasitic nodal capacitances;

C _s

Capacity of a snubber network (SN) with RC filter;

ΔV

predetermined voltage difference;

D _B

Bias diode for rectifying the potential difference between N1 and N2;

D _G

Limiter element (eg Zener diode) for limiting the maximum gate-source voltage (V _GS ) of the switching transistors (M _S );

DR1

High-side driver for the high-side transistor (T1);

DR2

Low-side driver for the low-side transistor (T2);

EMC

Electromagnetic compatibility;

enq

Control signal for switching the snubber network (SN) between a high-resistance and a low-resistance state based on the two connections of the snubber network (SN) which are connected to the first node (N1) and to the second node (N2);

FD

Freewheeling diode of the switching regulator between the boost voltage (V _boost ) and the second node (N2);

for _r

Resonance frequency of the parasitic resonant circuit (C _p , L _boost );

GND

Reference potential;

HSOCP

High-side overcurrent protection;

H _T1

Control signal for the control electrode of the high-side transistor (T1);

H _vT1

Driver input signal for the high-side driver (DR1) for the high-side transistor (T1);

I _hist

High-side current actual signal;

I _ust

Low-side current actual signal;

L _boost

Converter inductance;

L _pwm

Driver input signal for the low-side driver (DR2) of the low-side transistor (T2);

LSOCP

Low-side overcurrent protection;

L _T2

Control signal for the control electrode of the low-side transistor (T2);

M _DIS

Turn-off transistor for effectively deactivating the snubber network (SN) between nodes N1 and N2;

M _S

Switching transistor in what is known as a back-to-back arrangement for opening / closing the connection between nodes N1 and N2;

M _V1

first current measuring device;

M _V2

second current measuring device;

N1

first knot;

N2

second knot;

N3

third knot;

N4

fourth knot;

N5

fifth knot;

N6

sixth knot;

OCS

Overcurrent signal;

out

Voltage output of the switching regulator;

REG

Regulator;

R _B

Bias resistance for charging the gates from potential differences between nodes

N1 and N2

as well as limitation of the current in D _G ;

R _G

passive discharge resistor for the gates of the switching transistors M _S ;

R _pc

Precharge resistor;

R _R

Resonance resistance value that the resonant circuit has from the converter inductance (L _boost ) and the parasitic components (C _p ) causing the oscillation at the resonance frequency ( _fr ) between the first node (N1) and the second node (N2). The resonance resistance value is typically real at the resonance frequency ( _fr ) and typically has no imaginary part. The resonance resistance is often between 3 and 4 kOhm;

R _S

actual snubber resistance, responsible for the energy conversion in the moment of switch-off (between N1 / N2);

RVM

relative tension measuring device;

SdT

State of the art;

SN

Snubber network;

T1

High-side transistor;

T2

Low-side transistor;

SN

Snubber network;

V _boost

Boost voltage;

Vdd

Supply voltage;

V _GS

Gate-source voltage of the switching transistors (M _S );

V _m

Voltage measurement signal;

V _N1

Voltage at the first node N1 against the reference potential (GND);

V _N2

Voltage at the second node N2 against the reference potential (GND);

Vref

Reference voltage;

V _reg

Control signal;

W _H

High-side overcurrent warning signal;

W _L

Low-side overcurrent warning signal;

ZD1

Voltage limiting diode to limit the voltage between the reference potential (GND) and the first node (N1). The voltage limiting diode can also be a simple diode instead of a Zener diode. It is required for freewheeling. The upward clamping of the voltage is typically provided implicitly by the high-side transistor (T1) via its bulk diode .;

Z _SN

complex internal resistance value of the snubber network (SN) between the first node (N1) and the second node (N2);

Z _SN1

First complex internal resistance value of the snubber network (SN) between the first node (N1) and the second node (N2), which is preferably assumed by the snubber network (SN) if the output voltage difference between the output (out) of the voltage regulator ( BSIC) and the reference potential (GND) deviates from a predetermined reference value by more than a predetermined minimum voltage difference ΔV in terms of amount;

Z _SN2

second complex internal resistance value of the snubber network (SN) between the first node (N1) and the second node (N2), which is preferably through the snubber network

(SN)

it is assumed if the output voltage difference between the output (out) of the voltage regulator (BSIC) and the reference potential (GND) deviates from a predetermined reference value by less than a predetermined minimum voltage difference ΔV;

Claims (4)

Snubber network (SN) for damping the oscillations at a converter inductance (L _boost ) of a voltage regulator (BSIC) - with a first snubber resistor (Rs) and - with a second snubber resistor (Rs) and - with a first switching transistor ( M _s ) and - with a second switching transistor (M _s ) and - with a first bias resistor (R _B ) and / or with a second bias resistor (R _B ) and - with a first bias diode (D _B ) and / or with a second bias diode (D _B ) and - with a limiter element (D _G ) and - with a passive discharge resistor (R _G ) and - with a switch-off transistor (M _DIS ), - wherein the converter inductance (L _boost ) has a first connection and a second connection and - wherein the converter inductance (L _boost ) is connected to the first connection with a first node (N1), which is in particular switching, and - wherein the converter inductance (L _boost ) is connected to the second connection with a second node (N2)), which is in particular switching, and - the snubber network (SN) having a first connection with which it is connected to the first connection (N1) of the converter inductance ( L _boost ), and - wherein the snubber network (SN) has a second connection, with which it is connected to the second connection (N2) of the converter inductance (L _boost ), and - wherein the snubber network (SN) has a complex internal resistance (Z _SN ) between its first connection and its second connection and - wherein the snubber network (SN) has a control connection (enq) and - wherein the complex internal resistance (Z _SN ) of the snubber network (SN) depends on the state of the control connection (enq), wherein the state of the control connection (enq) can depend on a control logic and timer circuit (CLT) and - wherein the first snubber resistor (Rs ) is connected with its first connection to the first node (N1) and - wherein the first snubber resistor (Rs) is connected with its second connection to a fifth node (N5) and - the second snubber resistor (Rs) with its first connection is connected to the second node (N2) and - the second snubber resistor (Rs) is connected with its second connection to a sixth node (N6) and - a series circuit, the sequence of which is selectable, from the first Bias resistor (R _B ) and the first bias diode (D _B ) is connected with its first connection to the first node (N1) and / or wherein the series circuit of the first bias resistor (R _B ) and the first bias -Diode (D _B ) with her second en connection is connected to a third node (N3) and - wherein the cathode of the first bias diode (D _B ) is oriented towards the third node (N3) and - wherein a series circuit, the order of which is selectable, from the second Bias resistor (R _B ) and the second bias diode (D _B ) is connected with its first connection to the second node (N2) and / or wherein the series circuit of the second bias resistor (R _B ) and the second bias -Diode (D _B ) is connected with its second connection to the third node (N3) and - the cathode of the second bias diode (D _B ) is oriented towards the third node (N3) and - the control electrode of the first switching transistor (M _s ) is connected to the third node (N3) and - wherein the control electrode of the second switching transistor (M _s ) is connected to the third node (N3) and - wherein a first connection of the first switching transistor (M _s ), which is not the control electrode of the first switching tra nsistor (M _s ) is connected to a fourth node (N4) and - wherein a first connection of the second switching transistor (M _s ), which is not the control electrode of the second switching transistor (M _s ), is connected to the fourth node (N4) and - a second connection of the first switching transistor (M _s ), which is not the control electrode of the first switching transistor (M _s ) and not the first connection of the first switching transistor (M _s ), is connected to the fifth node (N5) and - wherein a second connection of the second switching transistor (M _s ), which is not the control electrode of the second switching transistor (M _s ) and not the first connection of the second switching transistor (M _s ), is connected to the sixth node (N6) and - wherein the passive discharge resistor (R _G ) is connected with its first connection to the fourth node (N4) and - wherein the passive discharge resistor (R _G ) is connected with its second connection to the third node (N3) and - wherein the limiter element (D _G ) has a first connection, in particular an anode, and a second connection, in particular a cathode, and - wherein the second connection of the limiter element (D _G ) is connected to the third node (N3) and - wherein the first connection of the limiter element (D _G ) is connected to the fourth node (N4) and - wherein the control electrode of the switch-off transistor (M _DIS ) is the control connection (enq) and - wherein a first connection of the switch-off transistor (M _DIS ), which is not the control electrode of the switch-off transistor (M _DIS ), is connected to a reference potential (GND) and - whereby a second connection of the switch-off transistor (M _DIS ), which is not the control electrode of the switch-off transistor (M _DIS ) and not the first Connection of the switch-off transistor (M _DIS ) is connected to the third node (N3). Snubber network Claim 1 - wherein the converter inductance (L _boost ) and parasitic node capacitances (C _p ) at the first node (N1) and at the second node (N2) form an oscillating circuit with a resonance frequency ( _fr ) and - wherein the parasitic oscillating circuit is composed of converter inductance (L _boost ) and parasitic node capacitances (C _p ) at the resonance frequency ( _fr ) has a resonance resistance value (R _r ) between the first node (N1) and the second node (N2) and - wherein the snubber network (SN) is designed such that in a state of the control connection (enq) the real part of the complex internal resistance (Z _SN ) of the snubber network (SN) not more than 200% or not more than 150% or not more than 120% or not more than 110% or not more than 105% of the amount of the resonance resistance (R _r ) of the parasitic resonant circuit made up of converter inductance (L _boost ) and parasitic node capacitances (C _p ) and - the snubber network (SN) is designed so that in this state d it control connection (enq) the real part of the complex internal resistance (Z _SN ) of the snubber network (SN) not less than 50% or not less than 75% or not less than 88% or not less than 95% or not less than 98% of the magnitude of the resonance resistance value (R _r ) of the parasitic resonant circuit comprising converter inductance (L _boost ) and parasitic node capacitances (C _p ). Method for damping the vibrations at a converter inductance (L _boost ) of a voltage regulator (BSIC) with an output (out) and a reference potential (GND) - the converter inductance (L _boost ) having a first connection and a second connection and - the converter inductance (L _boost ) is connected to the first connection to a first node (N1) and - the converter inductance (L _boost ) is connected to the second connection to a second node (N2) and - a snubber network (SN) after one of the Claims 1 or 2 has a first connection, with which it is connected to the first connection (N1) of the converter inductance (L _boost ), and - wherein the snubber network (SN) has a second connection with which it is connected to the second connection (N2) of the Converter inductance (L _boost ) is connected, and - wherein the snubber network (SN) has a complex internal resistance (Z _SN ) between its first connection and its second connection and - wherein the snubber network (SN) has a control connection (enq) and - wherein the complex internal resistance (Z _SN ) of the snubber network (SN) depends on the state of the control connection (enq) with the steps of - energizing the converter inductance (L _boost ) with a current (I _boost ) which is averaged over time of Deviates from zero amperes, and switching the complex internal resistance (Z _SN ) of the snubber network (SN) to a first complex internal resistance value (Z _SN1 ) of the snubber network (SN) when the output voltage difference between en the output (out) of the voltage regulator (BSIC) and the reference potential (GND) deviates from a predetermined reference value by more than the amount of a predetermined minimum voltage difference ΔV; - Not energizing the converter inductance (L _boost ) and switching the complex internal resistance (Z _SN ) of the snubber network (SN) to a second complex internal resistance value (Z _SN2 ) of the snubber network (SN) if the output voltage difference between the output ( out) of the voltage regulator (BSIC) and the reference potential (GND) deviates from a predetermined reference value by less than the amount of a predetermined minimum voltage difference ΔV, - the real part of the first complex internal resistance value (Z _SN1 ) of the snubber network (SN) in terms of amount is greater than the real part of the second complex internal resistance value (Z _SN2 ) of the snubber network (SN). Method according to the preceding claim - wherein the oscillations of the converter inductance (L _boost ) occur at a resonance frequency (f _r ) when they occur and - wherein the converter inductance (L _boost ) and the parasitic components (C _p ) causing the oscillation are at this resonance frequency ( f _r ) have a resonance resistance value (R _r ) and - the real part of the second complex internal resistance value (Z _SN2 ) of the snubber network (SN) • not more than 200% or not more than 150% or not more than 120% or not is more than 110% or not more than 105% of the magnitude of the resonance resistance value (R _r ) and • not less than 50% or not less than 75% or not less than 88% or not less than 95% or not less than 98% of the magnitude of the resonance resistance value (R _r ).

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