DE102017127209A1 - INTERMEDIATE METAL FILM WITH DIFFUSION IN SOURCE / DRAIN - Google Patents

Abstract

One method includes etching a substrate to form a first semiconductor strip. A first dummy gate structure is formed over a first channel region of the first semiconductor strip. First and second recesses are etched in the first semiconductor strip on both sides of a first dummy gate. An intermetal doping film is formed in the first recess and the second recess. A dopant of the intermetallic doping film is diffused in the first semiconductor strips near the pits. Source / drain regions are grown epitaxially in the wells. A device comprises semiconductor strips and a plurality of gate stacks. A first epitaxial source / drain region is disposed between two first ones of the plurality of gate stacks. A first dopant diffusion region surrounds the first epitaxial source / drain region and has a first concentration of a first dopant that is higher than a second concentration of the first dopant outside of the first dopant diffusion region.

Description

CLAIM OF PRIORITY AND CROSS-REFERENCES

This application claims the priority of the provisional US Application No. 62/527 698 entitled "Intermetallic Doping Film with Diffusion in Source / Drain," filed Jun. 30, 2017, which is hereby incorporated by reference.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers and semiconductor layers of various materials over a semiconductor substrate and patterning the various layers of material by lithography to form circuit components and elements thereon.

The semiconductor industry improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, minimizing the minimum feature size introduces additional issues that should be addressed.

list of figures

• 1 ist eine Perspektivansicht einer Fin-Feldeffekttransistor- („FinFET“) - Vorrichtung gemäß einigen Ausführungsformen.
• Die 2A bis 26A, 26B und 26C sind Querschnittsansichten von Zwischenstufen bei der Herstellung einer FinFET-Vorrichtung gemäß einigen Ausführungsformen.
• Die 27C, 28C und 29C sind Querschnittsansichten einer FinFET-Vorrichtung gemäß einigen Ausführungsformen.

Aspects of the present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It should be noted that various features are not drawn to scale according to industry standard practice. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.

• 1 FIG. 4 is a perspective view of a Fin Field Effect Transistor ("FinFET") device, in accordance with some embodiments.
• The 2A to 26A . 26B and 26C 12 are cross-sectional views of intermediate stages in the fabrication of a FinFET device according to some embodiments.
• The 27C . 28C and 29C FIG. 15 are cross-sectional views of a FinFET device according to some embodiments. FIG.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following disclosure provides many different embodiments or examples to implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course these are just examples and should not be limiting. For example, forming a first element over or on a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are interposed between the first element and the second element second element may be formed so that the first and the second element do not have to be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and in itself does not enforce any relationship between the various described embodiments and / or configurations.

Further, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like, for convenience of description, may be used to describe the relationship of one element or device to another element (FIG. en) or device (s) as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation) and the spatially relative terms used herein may also be interpreted accordingly.

Embodiments will be described with respect to a specific context, namely, a FinFET device and a method of forming the same. Various embodiments described herein allow the formation of source / drain regions of a FinFET device such that the dopant concentration in a well interface of the source / drain region is increased to reduce sheet resistance and increase carrier mobility. Various embodiments presented herein are described in the context of FinFETs formed using a gate-load method. In further embodiments, a gate-first method may be used. In addition, some embodiments contemplate aspects that appear in planar devices are used, such as. B. planar FETs.

1 shows an example of a fin field effect transistor (FinFET) 30 in a three-dimensional view. The FinFET 30 includes a fin 36 on a substrate 32 , The substrate 32 has isolation areas 34 on and the Finn 36 protrudes over adjacent isolation areas 34 and lies between them. A gate dielectric 38 is along sidewalls and over an upper surface of the fin 36 arranged and a gate electrode 40 is above the gate dielectric 38 arranged. Source / drain regions 42 and 44 are on opposite sides of the fin 36 with respect to the gate dielectric 38 and the gate electrode 40 arranged. 1 also shows reference cross sections used in the following figures. The cross section AA passes through a channel, the gate dielectric 38 and the gate electrode 40 of the FinFET 30 , The cross section CC lies in a plane parallel to the cross section AA and through the fin 36 is arranged outside the channel. The cross section BB is perpendicular to the cross section AA and lies along a longitudinal axis of the fin 36 and in the direction of, for example, a current flow between the source / drain regions 42 and 44 , The following figures refer to these reference cross sections for clarity.

The 2A to 26A-C FIG. 15 are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. FIG. In the 2A to 26A-C are figures that end with an "A" lettering along the in 1 shown reference cross section AA, except that there are several FinFETs and a plurality of fins per FinFET; Figures ending with a "B" bi-directional education are along the in 1 shown reference cross-section BB shown; and figures ending with a "C" bi-directional drift are along the in 1 shown cross-section CC shown. In some cases, cross-sectional views are omitted in certain steps, for example, if the omitted cross-section is not specifically described.

2A shows a substrate 50 , The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like, which may be doped or undoped (eg, with a p- or n-type dopant). The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 Silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

The substrate 50 may further include integrated circuit devices (not shown). As one of ordinary skill in the art will appreciate, a wide variety of integrated circuit devices, such as transistors, diodes, capacitors, resistors, or the like, or combinations thereof, may be incorporated in and / or on the substrate 50 be designed to meet the structural and / or functional design requirements for the resulting FinFETs. The integrated circuit devices may be formed using any suitable method.

In some embodiments, the substrate may be 50 a first area 100A and a second area 100B include. The first area 100A may serve to form n-type devices, such as n-type metal oxide semiconductor (nMOS) transistors, such as n-type FinFETs. The second area 100B may serve to form p-type devices, such as p-type metal oxide semiconductor (PMOS) transistors, such as p-type FinFETs. Accordingly, the first area 100A also as NMOS area 100A and the second area 100B also as a PMOS area 100B be designated.

2A further shows the formation of a mask 53 above the substrate 50 , In some embodiments, the mask 53 be used in a subsequent etching step to the substrate 50 to structure (see 3A) , As in 2A shown, the mask can 53 a first mask layer 53A and a second mask layer 53B include. The first mask layer 53A may be a hardmask layer. In some embodiments, the first mask layer 53A Silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like may be formed using any suitable method such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), a combination thereof, or the like. The first mask layer 53A can be used to etch the substrate 50 that under the first mask layer 53A is to prevent or minimize in the subsequent etching step (see 3A) , The second mask layer 53B may comprise a photoresist and may be used in some embodiments, the first mask layer 53A for use in the subsequent etching step described above. The second mask layer 53B can be formed using a spin coating technique and can be patterned using suitable photolithographic techniques. In some embodiments, the mask 53 comprise three or more mask layers.

3A shows the formation of semiconductor strips 52 in the substrate 50 , First, the mask layers 53A and 53B be structured, with openings in the mask layers 53A and 53B Areas of the substrate 50 expose where trenches 55 are formed. Next, an etching process is performed wherein the etching process includes trenches 55 in the substrate 50 through the openings in the mask 53 generated. The remaining sections of the substrate 50 under a textured mask 53 lie, form a plurality of semiconductor strips 52 , The etching may be any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process may be anisotropic. In some embodiments, the semiconductor strips may 52 a height H _o between about 50 nm and about 60 nm and a width W _o between about 6 nm and about 8 nm.

4A shows the formation of an insulating material in the trenches 55 (see 3A) between adjacent semiconductor strips 52 to isolation areas 54 train. The insulating material may be an oxide such as silicon oxide, a nitride such as silicon nitride, the like, or a combination thereof, and may be formed by a high density chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD). based material deposition in a remote plasma system and post-curing to convert it to another material such as an oxide), the like, or a combination thereof. Other insulation materials formed by any suitable method may also be used.

Furthermore, the isolation areas 54 in some embodiments, have a liner (not shown) attached to sidewalls and a bottom surface of the trenches 55 (see FIG 3A) is formed before the trenches 55 with an insulation material of the isolation areas 54 be filled. In some embodiments, the liner may be a semiconductor nitride (eg, a silicon nitride), a semiconductor oxide (eg, a silicon oxide), a thermal semiconductor oxide (eg, a thermal silicon oxide), a semiconductor oxynitride (eg, a silicon oxynitride ), a polymer dielectric, combinations thereof, and the like. Forming the liner may include any suitable method, such as ALD, CVD, HDP-CVD, PVD, a combination thereof, or the like. In some embodiments, the formation of the liner may result in a conformally deposited layer having horizontal portions and vertical (or non-horizontal) portions having substantially the same thickness, for example, the vertical thickness of the vertical portions of the liner and the horizontal thickness of the horizontal Sections of the lining have a difference of less than 20 Percent. In such embodiments, the liner may facilitate the diffusion of the semiconductor material from the semiconductor strips 52 (eg Si and / or Ge) into the surrounding isolation areas 54 during the subsequent annealing of the isolation areas 54 prevent (or at least reduce). For example, after the insulation material of the isolation areas 54 has been deposited, an annealing process on the insulation material of the isolation areas 54 be applied.

Further referring to 4A For example, a planarization process, such as chemical mechanical polishing (CMP), any excess isolation material of the isolation regions 54 remove, leaving the top surfaces of the isolation areas 54 and the upper surfaces of the semiconductor strips 52 (within process variances) are coplanar. In some embodiments, the CMP may also be the mask 53 remove. In further embodiments, the mask 53 be removed separately from the CMP using a wet cleaning process.

5A shows the depth of the isolation areas 54 to form shallow trench isolation (STI) regions 54. The isolation areas 54 become so engrossed that Finns 56 in the first area 100A and in the second area 100B between adjacent isolation areas 54 protrude. Furthermore, the upper surfaces of the isolation areas 54 have a flat surface as shown, a convex surface, a concave surface (such as cavities), or a combination thereof. The upper surfaces of the isolation areas 54 can be made flat, convex and / or concave by suitable etching. The isolation areas 54 can be made using a suitable etching process, for example, selective for the material of the isolation areas 54 is to be absorbed. For example, chemical removal of the oxide using a CERTAS® etch or a SICONI tool from Applied Materials or dilute hydrogen fluoride (dHF) acid may be used.

That in terms of 2A to 5A The method described is just one example of how the Finns 56 can be trained. In further embodiments, a dielectric Layer over an upper surface of the substrate 50 be formed; Trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer may be recessed so that the homoepitaxial structures project from the dielectric layer to form fins. In yet other embodiments, heteroepitaxial structures may be used for the fins. For example, the semiconductor strips 52 in 4 be deepened and a material that differs from the semiconductor strips 52 can be epitaxially grown in their place. In yet another embodiment, a dielectric layer may overlie a top surface of the substrate 50 be formed; Trenches can be etched through the dielectric layer; Heteroepitaxial structures can be epitaxially grown in the trenches using one of the substrate 50 different material are bred; and the dielectric layer may be recessed so that the heteroepitaxial structures protrude from the dielectric layer to form the fins 56 form. In some embodiments, in which homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials may be in situ doped during growth. In other embodiments, for example, homoepitaxial or heteroepitaxial structures may be doped using ion implantation after the homoepitaxial or heteroepitaxial structures have been epitaxially grown. Still further, it may be advantageous to have a material in the NMOS region 100A that is different from the material in the PMOS area 100B differs to epitaxially breed. In various embodiments, the fins may 56 Silicon germanium (Si _x Ge _1-x , where x is between about o and 1 silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, an II-VI compound semiconductor or the like. For example, the available materials for forming III-V compound semiconductors include, without limitation, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

In the 6A and 6B becomes a dummy dielectric layer 58 on the Finns 56 educated. The dummy dielectric layer 58 For example, it may be silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown (for example, using thermal oxidation or the like) according to appropriate techniques (for example, using CVD, PVD, a combination thereof, or the like). A dummy gate layer 60 is over the dummy dielectric layer 58 trained and a mask 62 gets over the dummy gate layer 60 educated. In some embodiments, the dummy gate layer 60 over the dummy dielectric layer 58 deposited and then planarized using, for example, a CMP method. The mask 62 can over the dummy gate layer 60 be deposited. The dummy gate layer 60 may be made of polysilicon, for example, although other materials have a high etch selectivity with respect to the material of the isolation regions 54 can also be used. The mask 62 may include one or more layers, for example, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or a combination thereof. In an embodiment, the mask comprises 62 a first mask layer 62A silicon nitride and a second mask layer 62B made of silicon oxide. In some embodiments, the first mask layer 62A a thickness between about 18 nm and about 22 nm and the second mask layer 62B have a thickness between about 50 nm and about 90 nm. In some embodiments, the dummy dielectric layer 58 a thickness between about 11 nm and about 15 nm and the dummy gate layer 60 have a thickness between about 50 nm and about 80 nm. In some embodiments, the dummy dielectric layer 58 be omitted.

Referring to the 6A and 6B In the embodiment shown, a single dummy dielectric layer will be used 58 , a single dummy gate layer 60 and a single mask 62 above that first area 100A and the second area 100B educated. In further embodiments, separate dummy dielectric layers, separate dummy gate layers, and separate masks may be in the first region 100A and the second area 100B be formed.

Referring to the 6A and 6B may be suitable doped wells (not shown) in the fins 56 , the semiconductor strip 52 and / or the substrate 50 be formed. Wells can be formed before or after the dummy gates 70 and 76 (hereinafter referred to as 7A . 7B and 7C described) are formed. In embodiments where wells are prior to forming the dummy gates 70 and 76 For example, the wells may be formed prior to forming the dummy dielectric layer 58 be formed. For example, a p-well may be in the first area 100A and an n-well in the second region 100B be formed. The different implantation steps for the different areas 100A and 100B can be performed using a photoresist or other masks (not shown). For example, take a photoresist over the fins 56 and the isolation areas 54 in the first area 100A and the second area 100B educated. The photoresist is patterned to the second area 100B of the substrate 50 , such as a PMOS region, while the first region 100A For example, an NMOS area is protected. The photoresist may be formed using a spin coating technique and may be patterned using suitable photolithographic techniques. Once the photoresist is patterned, n-type contaminants become the second region 100B implanted, and the photoresist can serve as a mask to substantially prevent n-type contaminants in the first area 100A be implanted. The n impurities may be phosphorus, arsenic or the like and may be in the second region 100B to a concentration 10 ¹⁸ cm ^-3 or less, such as in a range of about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 implanted. After the implantation procedure, the photoresist is removed using, for example, a suitable ashing process followed by a wet cleaning process.

After implanting the second area 100B is a second photoresist (not shown) over the fins 56 and the isolation areas 54 in the first area 100A and the second area 100B educated. The second photoresist is patterned to the first area 100A of the substrate 50 uncover while the second area 100B is protected. The second photoresist may be formed using a spin coating technique and patterned using appropriate photolithographic techniques. Once the second photoresist is patterned, p-type contaminants become the first region 100A implanted, and the second photoresist may serve as a mask to substantially prevent p-type impurities from entering the second region 100B be implanted. The p-type impurities may be boron, BF ₂ or the like and may be in the first range 100A to a concentration of 10 ¹⁸ cm ^-3 or less, such as in a range of about 10 ¹⁷ cm ^-3 to about 10 ¹⁸ cm ^-3 implanted. After the implantation process, the second photoresist is removed using, for example, a suitable ashing process followed by a wet cleaning process.

After implanting suitable contaminants in the first area 100A and the second area 100B For example, annealing may be performed to activate the p and n impurities that have been implanted. The implantation procedure may include a p-well in the first region 100A and an n-well in the second region 100B form. In some embodiments, where the fins are epitaxially grown, the cultured materials of the fins may be 56 be doped in situ during the growth process.

In the 7A . 7B and 7C can the mask 62 (see the 6A and 6B) be patterned using suitable photolithography and etching techniques to form a mask 72 in the first area 100A and a mask 78 in the second area 100B train. The structure of the masks 72 and 78 can then be applied to the dummy gate layer by a suitable etching technique 60 be transferred to dummy gates 70 in the first area 100A and dummy gates 76 in the second area 100B train. Optionally, the structure of the masks 72 and 78 similarly to the dummy dielectric layer 58 be transmitted. The structure of the dummy gates 70 and 76 covers associated channel areas of the fins 56 while the source / drain regions of the fins 56 exposed. The dummy gates 70 and 76 may also have a longitudinal direction which is substantially perpendicular to the longitudinal direction of the respective fins 56 is. A size of the dummy gates 70 and 76 and a pitch between the dummy gates 70 and 76 may depend on a range of a die in which the dummy gates are formed. In some embodiments, the dummy gates 70 and 76 may be larger and have a larger pitch when in an input / output region of a die (where, for example, input / output circuits are arranged) than when they are in a logic region of a die (where, for example, logic circuits are arranged). In some embodiments, the dummy gates 70 have a height between about 135 nm and about 175 nm and the dummy gates 76 may have a width between about 15 nm and about 27 nm.

In the 8A . 8B and 8C becomes a gate spacer layer 80 on exposed surfaces of the dummy gates 70 and 76 (see the 8A and 8B) and / or the dummy dielectric layer 58 over the Finn 56 (please refer 8C) educated. Any suitable methods of forming the gate spacer layer 80 can be used. In some embodiments, a deposition (such as CVD, ALD, or the like) may be used to form the gate spacer layer 80 be used. In some embodiments, the gate spacer layer 80 One or more layers include, for example, silicon nitride (SiN), silicon oxynitride, silicon carbonitride, silicon oxycarbonitride (SiOCN), a combination thereof, or the like. In some embodiments, the gate spacer layer 80 a first gate spacer layer 80A , a second gate spacer layer 80B over the first gate spacer layer 80A and a third gate spacer layer 80C above the second gate spacer layer 80B include. In an embodiment, the first gate spacer layer comprises 80A SiOCN, the second gate spacer layer 80B SiOCN and the third gate spacer layer 80C SiN. In some embodiments, the first gate spacer layer 80A a thickness between about 3 nm and about 5 nm, the second gate spacer layer 80B a thickness between about 3 nm and about 5 nm and the third gate spacer layer 80C a thickness between about 4 nm and about 6 nm.

With further reference to the 8A . 8B and 8C may after forming the first spacer layer 80A lightly doped source / drain (LDD) regions 75 and 79 in the substrate 50 in the first area 100A or the second area 100B be formed. Similar to the implantation method described above with reference to FIGS 7A . 7B and 7C A mask (not shown), such as a photoresist, may be over the first area 100A , z. As the NMOS area, while the second area 100B , z. For example, the PMOS region is exposed and p-type contaminants may be present in the exposed fins 56 in the second area 100B be implanted to the LDD areas 79 manufacture. During implantation of the LDD areas 79 can the dummy gate 76 act as a mask to prevent dopants from entering a channel region of the exposed fins 56 implanted (or at least reduced). So can the LDD areas 79 essentially in source / drain regions of the exposed fins 56 be formed. The mask can then be removed. Subsequently, a mask (not shown) such as a photoresist may be over the second area 100B be formed while the first area 100A exposed, and n-impurities can enter the exposed fins 56 in the first area 100A be implanted to the LDD areas 75 manufacture. During implantation of the LDD areas 75 can the dummy gate 70 act as a mask to prevent dopants from entering a channel region of the exposed fins 56 implanted (or at least reduced). So can the LDD areas 75 essentially in source / drain regions of the exposed fins 56 be formed. The second mask can then be removed. The n-type impurities may be any of the above-described n-type impurities, and the p-type impurities may be any of the above-described p-type impurities. The LDD areas 75 and 79 each may have an impurity concentration of about 10 ¹⁵ cm ^-3 to about 10 ¹⁶ cm ^-3 . An annealing process may be performed to activate the implanted contaminants.

Referring to the 9A . 9B . 9C . 10A . 10B and 10C For example, a patterning process is performed to remove excess portions of the spacer layer 80 in the first area 100A to remove. Any suitable patterning method may be used. Referring first to the 9A . 9B and 9C becomes a three-layer mask in some embodiments 120 over the first area 100A and the second area 100B educated. The three-layer mask 120 includes a lower layer 120A , a middle layer 120B above the lower layer 120A and an upper layer 120C above the middle layer 120B , In some embodiments, the lower layer 120A comprise an organic material such as a spin-on-carbon (SOC) material or the like, and may be formed using a spin coating, CVD, ALD or the like. The middle layer 120B may include an inorganic material, which may be a nitride (such as SiN, TiN, TaN or the like), an oxynitride (such as SiON), an oxide (such as silicon oxide) or the like, and may be formed by using CVD, ALD or be formed. The upper layer 120C may comprise an organic material such as a photoresist material and may be formed using a spin coating or the like. In some embodiments, the top layer becomes 120C the three-layer mask 120 structured to the first area 100A expose. The upper layer 120C can be patterned using suitable photolithographic techniques.

Referring to the 10A . 10B and 10C becomes an etching method using the structured three-layer mask 120 performed as a mask. The etching process may be anisotropic. After performing the etching process, lateral portions of the first spacer layer 80A , the second spacer layer 80B and the third spacer layer 80C over the LDD areas 75 and in the isolation areas 54 be removed to upper surfaces of the fins 56 and the masks 72 for the dummy gate stacks 70 expose. Portions of the first spacer layer 80A , the second spacer layer 80B and the third spacer layer 80C along side walls of the dummy gates 70 and the Finns 56 can remain and spacers 122 form. In further embodiments, the spacer layer 80 also from the side walls of the Finns 56 be removed. After structuring the spacer layer 80 can the three-layer mask 120 be removed using any suitable removal method.

The 11B to 21C show the formation of epitaxial source / drain regions 82 and 84 in the first area 100A and the second area 100B , In some embodiments, the epitaxial source / drain regions 82 (see the 21B and 21C) in the first area 100A be formed before the epitaxial source / drain regions 84 (see the 21B and 21C) in the second area 100B be formed. In further embodiments, the epitaxial source / drain regions 84 in the second area 100b prior to forming the epitaxial source / drain regions 82 in the first area 100a be formed.

The 11B to 14C show the formation of the epitaxial source / drain regions 82 in the first area 100A , During the formation of the epitaxial source / drain regions in the first region 100A , z. B. the NMOS area, the second area 100B , z. The PMOS area, may be masked (not shown).

Referring to the 11B and 11C becomes a first patterning process on the fins 56 performed to pits 124 in the source / drain regions of the fins 56 train. The first patterning method may be performed such that the pits 124 between adjacent dummy gates 70 (in inner areas of the Finns 56 , see, for. B. 13D) or between an isolation area 54 and the adjacent dummy gate 70 be formed (in end portions of the fins 56 , for example, as in the in 11B shown cross-section shown). In some embodiments, the first patterning method may include a suitable anisotropic dry etching method while the dummy gates 70 , the spacers 122 and / or the isolation areas 54 be used as a combined mask. The suitable anisotropic dry etching method may include reactive ion etching (RIE), neutral beam etching (NBE) or the like, or a combination thereof. In some embodiments, where the RIE is used in the first patterning process, process parameters such as a process gas mixture, bias voltage, and RF power may be selected such that the etch is predominantly performed using physical etching, such as etching. B. ion bombardment instead of chemical etching, such as radical etching is carried out by chemical reactions. In some embodiments, a bias voltage may be increased to increase the energy of ions used in the ion bombardment process, and thus to increase a rate of physical etching. Since the anisotropic physical etching and the chemical etching are isotropic in nature, such an etching method has a vertical etching rate larger than a lateral etching rate. In some embodiments, the anisotropic etch process may be performed using a process gas mixture comprising CH ₃ F, CH ₄ , HBr, O _2, Ar, a combination thereof, or the like.

In some embodiments, the first patterning process forms recesses 124 with U-shaped bottom surfaces. The wells 124 can also be called U-shaped depressions 124 be designated. In some embodiments, the U-shaped depressions 124 a depth D ₁ measured from an upper surface of the fins 56 , between about 45 nm and about 65 nm. As a result of the first patterning process, the pits can 124 have rough surfaces. In some embodiments, the etching process may be to form the U-shaped depressions 124 also an upper surface of the isolation areas 54 etching. The shape and profile of the U-shaped depressions 124 in relation to below 13D described following a thermal diffusion process.

The 12B and 12C show the formation of an intermetal doping film and the thermal diffusion of dopants into the fin 56 and the semiconductor strips 52 , A first intermetallic doping film 220 is above the device in the first area 100A and the second area 100B educated. The first intermetallic doping film 220 can also be used as the first doping film 220 be designated. The first doping film 220 may comprise a doped silicate glass. The dopant used may comprise any suitable group V n-contaminant, for example any of those previously described, such as phosphorus, arsenic, antimony or bismuth and so on, or combinations thereof. The first doping film 220 can be deposited by any suitable method such as ALD, CVD, plasma-enhanced CVD (PECVD), etc. (shown by the arrows 221 ) to make a thin film over the dummy gates 70 and 76 and in the U-shaped depressions 124 train.

A concentration of the dopant in the first doping film 220 can be adjusted by varying the ratio of gases in the process environment, such as a deposition chamber. For example, if phosphorus is used to make phosphosilicate glass (PSG), process gases may include tetraethylorthosilicate (TEOS) or silane SiH ₄ as the source of the silicate and PH ₃ or POCl ₃ as the source of phosphorus and other process gases (such as oxygen, nitrogen, hydrogen or argon ). The ratio of the phosphorus dopant source can be adjusted to incorporate more or less phosphorus in the formed PSG. For example, a ratio of PH ₃ to SiH _{4 may be} about 15% to about 45%. A ratio of the process gases can be adjusted similarly for other dopants. In some Embodiments may determine the resulting dopant concentration in the first doping film 220 between about 3.5 × 10 ¹⁹ cm ^-3 to about 8.5 × 10 ¹⁹ cm ^-3 . In some embodiments, the first doping film 220 deposited in a thickness between about 0.8 nm and about 2 nm. In further embodiments, the first doping film 220 in a thickness of less than about 0.8 nm or more than about 2 nm.

Still referring to the 12B and 12C may after forming the first doping film 220 a thermal diffusion method (shown by the arrows 223 ) are performed to the dopant of the first doping film 220 into the wells 224 surrounding fins 56 and semiconductor strips 52 to diffuse. The thermal diffusion process 223 may include any suitable thermal diffusion method, such as rapid thermal annealing (RTA), microwave annealing, furnace annealing, and the like. For example, an RTA may be at a temperature of between about 900 ° C to about 1000 ° C for about 3 to 6 Seconds, for example 5 Seconds, be performed.

In some embodiments, a mask (not shown) may overlay the second area 100B be formed to substantially prevent dopant from the first doping film 220 in structures of the second area 100B diffused. In some embodiments, one or more layers of the gate spacer layer 80 serve to prevent dopant into underlying structures of the second region 100B diffused. A compliant liner (not shown, see description in connection with 4A above) can between the isolation area 54 and the semiconductor strip 52 be formed to act as a diffusion barrier to a diffusion of dopant from the first doping layer 220 in the isolation areas 54 to prevent.

The diffusion of dopant from the first dopant layer 220 into the surrounding fin 56 and the semiconductor strips 52 provides an increased doping concentration to reduce sheet resistance and carrier mobility to the source / drain region in the first region 100A to improve the trained device. The concentration of dopant in the dopant diffusion region 227 the surrounding fin 56 and the semiconductor strip 52 is higher than the concentration of the same dopant outside the dopant diffusion region 227 For example, in an outer diffusion region, the at least part of the dopant diffusion region 227 in the surrounding fin 56 and the semiconductor strip 52 surrounds and adjoins this. The concentration of the dopant passing through the first dopant layer 220 in the dopant diffusion region 227 (see the 13B . 13C and 13D) may be between about 1.2 x 10 ¹⁹ cm ^-3 to about 6.2 x 10 ¹⁹ cm ^-3 . The resulting carrier mobility may be between about 15 cm ² / Vs to about 35 cm ² / Vs. The sheet resistance may be between about 200 Ωcm to about 1200 Ω-cm.

Referring to the 13B . 13C and 13D is after the thermal diffusion process 223 the first doping film 220 removed by any suitable method, for example by wet etching. The first dopant diffusion region 227 is in the Finns 56 and the semiconductor strip 52 educated.

13D shows an enlarged view of a part of 13B to details the dimensions of the opening 226 after doping by the intermetallic doping film. 13D shows the opening 226 that is between two adjacent dummy gates 70 is arranged. In some embodiments, the depth D ₃ of the dopant diffusion region 227 about 3 nm to about 18 nm. The depth D ₁ , measured from an upper surface of the fins 56 , may be between about 45 nm and about 65 nm. The surfaces 228 of the opening 226 , among other things, along the sides and the bottom of the opening 226 , are smoothed by the intermetal doping film method. A width W ₁ the opening 226 is measured at the top of the opening. A width W2 the opening 226 is measured at 50% of the depth (in the middle) of the opening. A width W ₃ the opening 226 is measured at 90% of the depth (90% from the top) of the opening. In some embodiments, a ratio of the widths W ₁ : W2 about 1.00: 1.13-1.22; a ratio of latitudes W ₁ : W ₃ may be about 1.00: 1.01-1.52; and a ratio of latitudes W ₂ W ₃ may be about 1.13-1.22: 1.01-1.52. In other words, the average width W2 may be about 13 to 22 Percent wider than the top width W ₁ his and the lower 90% width W ₃ can be about 1 until about 52 Percent wider than the top width W ₁ be.

The dopant diffusion region 227 leads to an increased dopant concentration in the semiconductor fins 56 and the semiconductor strip 52 which provides increased vehicle mobility. In some embodiments, the dopant diffusion region comprises 227 a part of the channel area under the dummy gate 60 , In other words, the dummy gate is 60 in some embodiments, vertically on a portion of the dopant diffusion region 227 aligned.

The smooth surfaces 228 of the opening 226 are advantageous for growing an epitaxial material therein, as described in more detail below is described. The smooth surfaces 228 result in an epitaxial structure of the source / drain regions having a corresponding smooth surface and a greater height and width than the epitaxial structure of the source / drain regions would have without the thermal diffusion doping process.

The 14B . 14C and 14D show the formation of the epitaxial source / drain regions 82 in the first area 100A , In some embodiments, the epitaxial source / drain regions become 82 epitaxially in the doped U-shaped recesses 226 (see the 13B and 13C) using metalorganic CVD (MOCVD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Gas Phase Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), a combination thereof, or the like. The epitaxial source / drain regions 82 may include any suitable material, such as any material suitable for n-type FinFETs. If, for example, the Finn 56 is made of silicon, the epitaxial source / drain regions 82 Silicon, SiC, SiCP, SiP or the like. The epitaxial source / drain regions 82 may have surfaces that are different from respective surfaces of the fins 56 are raised and may have facets. The epitaxial source / drain regions 82 are in the Finns 56 designed such that each dummy gate 70 between an associated adjacent pair of epitaxial source / drain regions 82 is arranged. In some embodiments, the epitaxial source / drain regions may become 82 about the Finns 56 out and into the semiconductor strips 52 extend as in 14B is shown.

The material of the epitaxial source / drain regions 82 in the first area 100A can be implanted with dopants, similar to the previously described method of forming the LDD regions 75 followed by a tempering (see the 8A . 8B and 8C and its description). The epitaxial source / drain regions 82 may have an impurity concentration in a range of about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . The n impurities for the source / drain regions in the first region 100A , z. The NMOS region may be any of the n-type impurities previously described. In further embodiments, the material of the epitaxial source / drain regions 82 be doped in situ during growth. In the embodiments shown, each of the source / drain regions 82 spatially from other source / drain regions 82 separated. In further embodiments, two or more adjacent source / drain regions 82 be united. Examples of such embodiments are in the 27C and 31C shown to have two or three adjacent source / drain regions 82 are united to form a common source / drain region. In some embodiments, more than two or three adjacent source / drain regions 82 be united.

Due to the film doping of the U-shaped recess 226 (see the 13B . 13C and 13D) , which provides a smooth sidewall profile of the recess, may include the epitaxial source / drain regions 82 be formed in a more uniform manner and produce a larger volume than would otherwise be produced without the film doping.

14D shows an enlarged part of the cross section, which in 14B is shown. The epitaxial source / drain regions 82 can have one or more layers 82A and 82B include. The layer 82A is a first set of one or more layers of epitaxial source / drain regions 82 , The layer 82B is a second set of one or more layers of epitaxial source / drain regions 82 , In some embodiments, the epitaxial source / drain regions 82 be formed of a single continuous layer. The first shift 82A can be formed using methods and materials as described above 14B are described. The second layer 82B can also be formed using methods and materials as described above 14B are described. The first shift 82A represents a first growth of epitaxial material in the epitaxial source / drain regions 82 ready. The second layer 82B represents a subsequent growth of epitaxial material in the epitaxial source / drain regions 82 ready. The first shift 82A may have a first lattice constant. The second layer 82B may have a second lattice constant. In some embodiments, the first lattice constant is equal to the second lattice constant. In some embodiments, the first lattice constant is different from the second lattice constant.

In some embodiments, the depth D ₆ of the epitaxial source / drain 82 , measured from the top surface of the fin 56 , be about 45 nm to about 65 nm. The depth D ₅ from an upper point of the epitaxial source / drain material 82 to the top surface of the fin 56 may be about 0.5 nm to about 3.0 nm. The depth D ₄ from the top surface of the fin 56 to a lower interface of the second layer 82B may be about 30 nm to about 50 nm. A width W ₄ the second layer 82b of the epitaxial source / drain material is measured at the top of the opening. A width W ₅ the second layer 82b of the epitaxial source / drain material becomes 50% of the depth (the middle) of the second layer 82B measured. A width W ₆ the second layer 82b The epitaxial source / drain material is measured at 90% of the depth (90% from the top) of the opening. In some embodiments, a ratio of the widths W ₄ : W ₅ about 1.00: 0.8-0.9; a ratio of latitudes W ₄ : W ₆ may be about 1.00: 1.02-1.61; and a ratio of latitudes W ₅ : W ₆ may be about 0.8-0.9: 1.02-1.61. In other words, the average width W ₅ about 80% to about 90% of the upper width W ₄ amount and the lower 90% width W ₆ can be about 2% to about 52% wider than the top width W ₄ be.

Referring to the in 13D described latitudes and ratios and the in 14D described widths and ratios, a ratio relationship between the opening 226 and the second layer 82B of the epitaxial source / drain material. A ratio of the upper width W ₁ the opening 226 to the upper width W ₄ the second layer 82B ( W ₁ : W ₄ ) may be about 1.14 to about 1.19: 1. A ratio of the middle width W2 the opening 226 to the upper width W ₅ the second layer 82B ( W ₂ : W ₅ ) may be about 1.52 to about 1.61. A ratio of the lower 90% width W ₃ the opening 226 to the upper width W ₆ the second layer 82B ( W ₃ : W ₆ ) may be about 1.02 to about 1.21. These ratios are examples of possible relationships in some embodiments. Other dimensions and ratios may be used.

Referring to the 15A . 15B . 15C . 16A . 16B and 16C For example, a patterning process is performed to remove excess portions of the spacer layer 80 in the second area 100B to remove. Any suitable patterning method may be used.

Referring first to the 15A . 15B and 15C becomes a three-layer mask in some embodiments 121 over the first area 100A and the second area 100B educated. The three-layer mask 121 includes a lower layer 121A , a middle layer 121B above the lower layer 121A and an upper layer 121C above the middle layer 121B , The three-layer mask 121 can be formed using methods and materials as described above with reference to FIGS 9A . 9B and 9C which are not repeated. In some embodiments, the top layer becomes 121C the three-layer mask 121 structured to the second area 100B expose. The upper layer 121C can be patterned using suitable photolithographic techniques.

In some embodiments, a mask layer 230 over the first area 100A be formed to protect the first area, while the second area 100B is processed. Any suitable methods for forming the mask layer 230 can be used. In some embodiments, a deposition (such as CVD, ALD or the like) or spin coating may be used to form the mask layer 230 be used. In some embodiments, the mask layer 230 one or more layers of, for example, a nitride (such as SiN, TiN, TaN, or the like), an oxynitride (such as SiON), a carbonitride (such as SiOCN), spin on carbon, a combination thereof, or the like. Although she before forming the three-layer mask 121 of the 15A . 15B and 15C is shown, the mask layer 230 in some embodiments, after removal of the three-layer mask 121 be formed.

Referring to the 16A . 16B and 16C becomes an etching method using the structured three-layer mask 121 performed as a mask. The etching process may be anisotropic. After performing the etching process, lateral portions of the first spacer layer 80A , the second spacer layer 80B and the third spacer layer 80C over the LDD areas 75 and over the isolation areas 54 be removed, leaving upper surfaces of the fins 56 and the masks 78 for the dummy gate stacks 76 be exposed. Parts of the first spacer layer 80A , the second spacer layer 80B and the third spacer layer 80C along the side walls of the dummy gate 78 and the Finns 56 remain and form spacers 122 , In further embodiments, the spacer layer 80 also from the side walls of the Finns 56 be removed. After structuring the spacer layer 80 can the three-layer mask 121 be removed using any suitable removal method.

The 17B to 21C show the formation of the epitaxial source / drain regions 84 in the second area 100B , During the formation of the epitaxial source / drain regions 84 in the second area 100B , z. As the PMOS area, the first area 100A , z. The NMOS region, through the mask layer 230 or masking another type of mask.

Referring to the 17B and 17C becomes a second structuring method on the fins 56 performed to pits 125 in source / drain regions of the fins 56 train. The wells 125 in the second area 100B can be made using similar methods and materials as the U-shaped depressions 124 in the first area 100A be formed as above with reference to the 11A . 11B and 11C has been described, and the description will not be repeated.

In some embodiments, the second patterning process forms recesses 125 with U-shaped bottom surfaces in the second area 100B out. The wells 125 can also be called U-shaped depressions 125 be designated. In some embodiments, the U-shaped depressions 125 a depth D ₁ , measured from an upper surface of the fins 56 , between about 45 nm and about 65 nm. As a result of the first patterning process, the pits can 125 have rough surfaces. In some embodiments, the etching process may be to form the U-shaped depressions 125 also an upper surface of the isolation areas 54 etching.

The 18B and 18C show the formation of a second intermetal doping film and the thermal diffusion of dopants into the fin 56 and the semiconductor strips 52 , A second intermetallic doping film 240 is above the device in the first area 100A and the second area 100B educated. The second intermetal doping film 240 can also be used as a second doping film 240 be designated. The second doping film 240 may comprise a doped silicate glass. The dopant used may comprise any suitable Group III p-type impurity, such as any of those previously described, for example, boron, aluminum, gallium or indium, and so forth, or combinations thereof. The second doping film 240 can be deposited by any suitable method such as CVD, spin coating, PECVD, etc. (shown by the arrows 241 ) to make a thin layer over the dummy gates 70 and 76 and in the U-shaped depressions 125 train.

A concentration of the dopant in the second doping film 240 can be adjusted by varying the ratio of gases in the process environment. For example, if boron is used to make borosilicate glass (BSG), the process gases may include silane SiH ₄ as the source of the silicate and B ₂ H ₆ as the source of the boron. The ratio of boron dopant source can be adjusted to incorporate more or less boron into the formed BSG. For example, a ratio of B ₂ H ₆ to SiH _{4 may be from} about 15% to about 45%. A ratio of the process gases can be adjusted similarly for other dopants. In some embodiments, the resulting dopant concentration in the second doping film 240 between about 2.5 × 10 ¹⁸ cm ^-3 to about 7.5 × 10 ¹⁸ cm ^-3 . In some embodiments, the thickness of the second doping film 240 between about 0.8 nm and about 2 nm. In some embodiments, the thickness of the second doping film 240 less than about 0.8 nm thick or thicker than about 2 nm.

Still referring to the 18B and 18C may after forming the second doping film 240 a thermal diffusion method (shown by the arrows 243 ) to the dopant of the second dopant film 240 in the Finns 56 and the semiconductor strips 52 that the wells 125 surrounded, to diffuse. The thermal diffusion process 243 can be carried out by methods described above in relation to the thermal diffusion method 223 of the 12B and 12C which are not repeated.

The mask 230 substantially prevents the dopant from the second doping film 240 into the source / drain regions 82 of the first area 100A diffused. A compliant liner (not shown, see description in connection with 4A above) can between the isolation area 54 and the semiconductor strip 52 be formed to act as a diffusion barrier to a diffusion of dopant from the second doping film 240 in the isolation areas 54 to prevent.

The diffusion of dopant into the surrounding fin 56 and the semiconductor strips 52 provides an increased doping concentration to reduce the sheet resistance and the carrier mobility in the source / drain region in the second region 100B to improve the trained device. The concentration of dopant in the dopant diffusion region 247 is greater than the concentration of the same dopant outside the dopant diffusion region 247 For example, in an outer diffusion region, the at least part of the dopant diffusion region 227 in the surrounding fin 56 and the semiconductor strip 52 surrounds and adjoins this. The concentration of the dopant passing through the first dopant layer 220 in the dopant diffusion region 227 (see the 19B and 19C) may be between about 2.5 x 10 ¹⁹ cm ^-3 to about 7.5 x 10 ¹⁹ cm ^-3 . The resulting support mobility may be between about 8 cm ² / Vs to about 20 cm ² / Vs. The sheet resistance may be between about 150 Ω-cm to about 190 Ω-cm.

With reference to the 19B and 19C is after the thermal diffusion process 243 the second doping film 240 removed by any suitable method, for example by wet etching. A second dopant diffusion region 247 is in the Finns 56 and the semiconductor strip 52 educated.

The dimensions and characteristics of the opening 125 and the thermal diffusion region 247 agree with those above regarding the opening 124 and the thermal diffusion region 227 from 13D have been described and will not be repeated.

The 20B and 20C show the formation of epitaxial source / drain regions 84 in the second area 100B , In some embodiments, the epitaxial source / drain regions become 84 in the second area 100B epitaxially grown in the wells using MOCVD, MBE, LPE, VPE, SEG, a combination thereof, or the like. The epitaxial source / drain regions 84 may include any suitable material, such as any material suitable for p-type FinFETs. If, for example, the Finn 56 is made of silicon, the epitaxial source / drain regions 84 SiGe, SiGeB, Ge, GeSn or the like. The epitaxial source / drain regions 84 may have surfaces that are different from respective surfaces of the fins 56 are raised and may have facets. The epitaxial source / drain regions 84 are in the Finns 56 designed such that each dummy gate 76 between an associated adjacent pair of epitaxial source / drain regions 84 is arranged. In some embodiments, the epitaxial source / drain regions may become 84 about the Finns 56 out and into the semiconductor strips 52 extend as in 20B is shown.

The material of the epitaxial source / drain regions 84 in the second area 100B can be implanted with dopants similar to the previously described method of forming the LDD regions 79 followed by a tempering (see the 8A . 8B and 8C) , The source / drain regions 84 may have an impurity concentration in a range of about 10 ¹⁹ cm ^-3 to about 10 ²¹ cm ^-3 . The p-type impurities for the source / drain regions 84 in the second area 100B , z. The PMOS region may be any of the p-type impurities previously described. In other embodiments, the epitaxial source / drain regions 84 be doped in situ during growth. In the embodiments shown, each of the source / drain regions 84 spatially from other source / drain regions 84 separated. In further embodiments, two or more adjacent source / drain regions 84 be united. Examples of such embodiments are in the 27C and 31C shown to have two or three adjacent source / drain regions 84 are united to form a common source / drain region. In some embodiments, more than two adjacent source / drain regions 84 be united.

Due to the film doping of the U-shaped recess 246 (see the 20B and 20C) , which provides a smooth sidewall profile of the recess, may include the epitaxial source / drain regions 84 be formed in a uniform manner and produce a larger volume than would be produced without the film doping.

The dimensions and properties of the epitaxial source / drain regions 84 may be similar to those above with respect to the epitaxial source / drain regions 82 from 14D have been described and will not be repeated.

Referring to the 21A . 21B and 21C becomes the mask 230 that the first area 100A protects, using any suitable technique removed.

The 22A to 25C show the replacement of the dummy gates 70 in the first area 100A and the dummy gates 76 in the second area 100B through a replacement gate structure. In some embodiments, the replacement gate structure may be a metal gate, as described below. As mentioned above, although a gate-load method has been shown and described, it will be understood by those skilled in the art that a gate-first method may also be used.

Referring to the 22A . 22B and 22C become an etch stop layer 87 and an interlayer dielectric (ILD) 88 over the dummy gates 70 and 76 and over the source / drain regions 82 and 84 deposited. In one embodiment, the ILD 88 a flowable film formed by a flowable CVD. In some embodiments, this is the ILD 88 formed of a dielectric such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG) or the like, and can be deposited by any suitable method such as CVD, PECVD, a combination thereof or the like. In some embodiments, the etch stop layer becomes 87 used as a stop layer while the ILD 88 is patterned to form openings for subsequently formed contacts. Accordingly, a material for the etching stopper layer 87 be chosen so that the material of the etch stop layer 87 a lower etch rate than the material of the ILD 88 having.

Referring to the 23A . 23B and 23C For example, a planarization method, such as a CMP, may be performed around the top surface of the ILD 88 with the top surfaces of the dummy gates 70 and 76 to level. After the planarization process, the top surfaces of the dummy gates 70 and 76 through the ILD 88 exposed. In In some embodiments, the CMP may also use the masks 72 and 78 or parts of it on the dummy gates 70 and 76 remove.

Referring to the 24A . 24B and 24C become remaining portions of the masks 72 and 78 and the dummy gates 70 and 76 removed in one or more etching steps, so that depressions 90 be formed. Each of the wells 90 defines a channel area of an associated fin 56 free. Each channel region is between an adjacent pair of epitaxial source / drain regions 82 in the first area 100A or between an adjacent pair of epitaxial source / drain regions 84 in the second area 100B arranged. In some embodiments, during removal, the dummy dielectric layer may 58 used as etch stop layer and exposed when the dummy gates 70 and 76 be etched. The exposed dummy dielectric layer 58 can then after removing the dummy gates 70 and 76 be removed. In some embodiments, portions of the dummy dielectric layer 58 that by the method of removing the dummy gates 70 and 76 have not been uncovered, remain as in 24B shown.

Referring to the 25A . 25B and 25C become gate dielectric layers 92 and 96 and gate electrodes 94 and 98 for the replacement gates in the first area 100A or the second area 100B educated. The gate dielectric layers 92 and 96 be in the wells 90 formed, for example, on the upper surfaces and the side walls of the fins 56 , on sidewalls of the gate spacers 122 respectively. 130 and on an upper surface of the ILD 88 , In some embodiments, the gate dielectric layers become 92 and 96 deposited in an opaque deposited layer. In some embodiments, the gate dielectric layers include 92 and 96 Silicon oxide, silicon nitride or multilayers thereof. In other embodiments, the gate dielectric layers include 92 and 96 a high-k dielectric, and in these embodiments, the gate dielectric layers 92 and 96 have a k value of greater than about 7.0, and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The manufacturing processes of the gate dielectric layers 92 and 96 may include molecular beam deposition (MBD), ALD, CVD, PECVD, a combination thereof, or the like. In some embodiments, forming may result in a conformally deposited layer having horizontal sections and vertical (or non-horizontal) sections of substantially the same thickness, for example, the vertical thickness of the vertical sections of the dielectric layers 92 and 96 and the horizontal thickness of the horizontal portions of the dielectric layers 92 and 96 a difference of less than 20 Percent. In some embodiments, the gate dielectric layers may be 92 and 96 thermally grown as above with respect to the dummy dielectric layer 58 is described.

Next are the gate electrodes 94 and 98 over the gate dielectric layers 92 respectively. 96 deposited and fill the remaining portions of the wells 90 out. The gate electrodes 94 and 98 may be made of a metal-containing material such as TiN, TaN, TaC, TiC, TiO, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, combinations thereof or multilayers thereof. After filling the gate electrodes 94 and 98 For example, a planarization process such as a CMP may be performed to eliminate the excess portions of the gate dielectric layers 92 and 96 and the gate electrodes 94 and 98 removing these excess portions above the top surface of the ILD 88 lie. The resulting remaining material portions of the gate electrodes 94 and 98 and the gate dielectric layers 92 and 96 thus form spare gates of the resulting FinFETs.

Although not shown, the gate electrodes may be 94 and 98 a sequence of one or more stacked layers (not shown). The stacked layers can be in the wells 90 over sidewalls and bottoms of the gate electrodes 94 and 98 and above the upper surface of the ILD 88 be deposited. The stacked layers may be formed by a blanket deposition process such as ALD or CVD and have a substantially uniform thickness within process variances. In some embodiments, forming the gate electrodes 94 and 98 result in conformally deposited layers having horizontal sections and vertical (or non-horizontal) sections having substantially the same thickness, for example the vertical thickness of the vertical sections of the layers and the horizontal thickness of the horizontal sections being less than 20 Percent. The stacked layers may include a diffusion barrier layer and one or more work function layers over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN) or thallium nitride. The one or more work function layers determine the work function of the gate and may include at least one layer or a plurality of layers of different materials. The specific material of the work function layer may be selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, if the FinFET is an n-FinFET, the work function layer may be an AlTiC layer include. If the FinFET is a p-type FinFET, the work function layer may comprise an AlTiN and / or an AlTiC layer. After depositing the one or more work function layers, a barrier layer (not shown), which may be another TiN layer, may be formed.

In some embodiments, forming the gate dielectric layers 92 and 96 occur simultaneously so that the gate dielectric layers 92 and 96 made of the same materials, and the formation of the gate electrodes 94 and 98 can be done simultaneously, so that the gate electrodes 94 and 98 made of the same materials. However, in other embodiments, the gate dielectric layers may 92 and 96 be formed by different methods, so that the gate dielectric layers 92 and 96 can be made of different materials, and the gate electrodes 94 and 98 can be formed by different methods, so that the gate electrodes 94 and 98 can be made of different materials. Various masking steps can be used to mask and expose appropriate areas when using separate methods.

The 26A . 26B and 26C show the FinFET device after forming contacts to the source / drain regions 82 and 84 and the gates 94 and 96 , A second ILD 102 will be over the ILD 88 isolated, contacts 104 and 106 be through the ILD 102 and the ILD 88 trained and contacts 108 and 110 be through the ILD 102 educated. In one embodiment, the ILD 102 using similar materials and procedures as the ILD 88 , referring to the above 22A . 22B and 22C has been described, and the description will not be repeated. In some embodiments, these are the ILD 102 and the ILD 88 made of the same material. In other embodiments, these are the ILD 102 and the ILD 88 made of different materials.

Openings for the contacts 104 and 106 be through the ILDs 88 and 102 and the etch stop layer 87 educated. Openings for the contacts 108 and 110 be through the ILD 102 and the etch stop layer 87 educated. These openings can all be formed simultaneously in a same process or in separate processes. The openings may be formed using suitable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesive layer or the like, and a conductive material are formed in the openings. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel or the like. A planarization process, such as a CMP, can be performed to remove excess materials from an upper surface of the ILD 102 to remove. Remaining lining and conductive material form the contacts 104 . 106 . 108 and 110 in the openings. An annealing process may be performed to form a silicide (not shown) at the interface between the epitaxial source / drain regions 82 and 84 and the contacts 104 respectively. 105 train. The contacts 104 are spatial and electrical with the epitaxial source / drain regions 82 connected to the contacts 106 are spatial and electrical with the epitaxial source / drain regions 84 connected, the contact 108 is spatial and electrical with the gate electrode 94 connected and the contact 110 is spatial and electrical with the gate electrode 98 connected.

27C shows a cross-sectional view of a FinFET device, the in the 26A . 26B and 26C similar FinFET device shown, wherein like elements are designated by like reference numerals. In some embodiments, the FinFET device of FIG 27C using similar materials and methods as the FinFET device of FIG 26A . 26B and 26C be formed, with reference to the above 1-26C have been described and the description will not be repeated. In the embodiment shown, two adjacent source / drain regions are 82 and two adjacent source / drain regions 84 so that they form respective common source / drain regions. In further embodiments, more than two adjacent source / drain regions 82 and more than two adjacent source / drain regions 84 united (see for example 29C) ,

The 28C and 29C 10 show enlarged portions of a cross section of an epitaxial source / drain region of a device showing various arrangements of the epitaxial materials according to some embodiments. The sectional views of 28C and 29C correspond to a FinFET device that in the 26A . 26B and 26C similar FinFET device shown, wherein like elements are provided with the same reference numerals. In some embodiments, the FinFET devices may be the 28C and 29C using similar materials and methods as the FinFET device of FIG 26A . 26B and 26C be formed, with reference to the above 1-26C have been described and the description will not be repeated.

In 28C may be a single epitaxial source / drain region 82 / 84 a part of a FinFET with a single fin or may be a single fin of a FinFET with a plurality of fins. Due to the dopant diffusion method ( 13B . 13C . 13D . 19B and 19C) may be the shape of the epitaxial materials in the source / drain regions 82 / 84 smoother, larger and more defined than without the doping. The epitaxial source / drain 82 / 84 can be a first epitaxial structure 82Y / 84Y and a final layer of epitaxial material 82Z / 84Z include that on the first epitaxial structure 82Y / 84Y formed using methods and materials similar to those described above with respect to FIGS 14B . 14C . 14D . 20B and 20C have been described. The first epitaxial structure 82Y / 84Y can consist of several layers of epitaxial material. A width W ₇ corresponds to the width of the first epitaxial structure 82Y / 84Y , In some embodiments, the width W ₇ about 29 nm to about 39 nm amount. A width W ₈ corresponds to the width of the epitaxial source / drain region 82 / 84 , the final layer of epitaxial material 82Z / 84Z includes. In some embodiments, the width W ₈ about 38 nm to about 50 nm. A distance D7 corresponds to the height of the first epitaxial structure 82Y / 84Y , In some embodiments, the distance D ₇ be about 36 nm to about 48 nm. A distance D ₈ corresponds to the height of the epitaxial source / drain regions 82 / 84 that the final layer of epitaxial material 82Z / 84Z include. In some embodiments D ₈ about 43 nm to about 54 nm. A distance D ₉ corresponds to the thickness of the final layer of epitaxial material 82Z / 84Z , In some embodiments D ₉ about 3.5 nm to about 7.5 nm.

The profile of the epitaxial source / drain regions 82 / 84 may have a larger volume and a greater height with better defined facets as a result of the intermetallic dopant diffusion method described herein (see US Pat 12B . 12C . 18B and 18C and the accompanying description).

In 29C can be a triple epitaxial source / drain region 82 / 84 be part of the fins of a FinFET showing a crown-shaped structure with a unified epitaxial structure. Due to the dopant diffusion method ( 13B . 13C . 13D . 19B and 19C) may be the shape of the epitaxial materials in the source / drain regions 82 / 84 smoother, larger and more defined than without the doping. The epitaxial source / drain regions 82 / 84 can be a first united epitaxial structure 82Y / 84Y and a final layer of epitaxial material 82Z / 84Z include, on the first united epitaxial structure 82Y / 84Y formed using methods and materials such as those described above with respect to 14B . 14C . 14D . 20B and 20C are described. The first epitaxial structure 82Y / 84Y can consist of several layers of epitaxial material. A distance D ₁₀ corresponds to the height of the first epitaxial structure 82Y / 84Y , In some embodiments, the distance D ₁₀ be about 51 nm to about 58 nm. A distance D ₁₁ corresponds to the height of the epitaxial source / drain regions 82 / 84 that the final layer of epitaxial material 82Z / 84Z include. In some embodiments, the distance D ₁₁ about 53 nm to about 64 nm. The distance D ₉ corresponds to the thickness of the final layer of epitaxial material 82Z / 84Z , In some embodiments, the distance D ₉ about 3.5 nm to about 7.5 nm.

Embodiments of the present disclosure provide an increased concentration of dopant impurities in the source / drain regions of an n-FinFET, p-FinFET or both (as in a complementary configuration). The increased dopant concentration provides improved carrier mobility and reduces sheet resistance in the source / drain regions. An additional advantage of the method of using the thermal diffusion of a doped silicate glass to provide the dopant is that the profile of the recessed fin in the source / drain regions (prior to forming an epitaxial source / drain region) has smoother surfaces. The smoother surfaces provide an epitaxial structure in the source / drain regions (the epitaxial source / drain regions described above), which has a more defined faceted profile of greater height, width and volume.

One embodiment is a method that includes etching a substrate to form a first semiconductor stripe. A first dummy gate structure is formed over a first channel region of the first semiconductor strip, wherein the first dummy gate is perpendicular to the first semiconductor strip. A first recess is etched in the first semiconductor strip on a first side of the first dummy gate. A second recess is etched in the first semiconductor strip on a second side of the first dummy gate. A first intermetal doping film is formed in the first recess and the second recess. A first dopant of the intermetal dopant film is diffused in the first semiconductor strip near the first recess and in the first semiconductor strip near the second recess. A source / drain region is epitaxially grown in the first well and the second well.

Another embodiment is a method comprising etching a first set of pits in a source / drain region of a first region of a FinFET device and depositing a first intermetal dopant film in the first set of pits. The first intermetal doping film is annealed to diffuse the dopant of the first intermetal doping film adjacent to the first set of wells. A first epitaxial source / drain region is grown in one or more wells of the first set of wells. The method also includes etching a second set of pits in a source / drain region of a second region of a FinFET device and depositing a second intermetal dopant film in the second set of pits, the second intermetal dopant film being different from the first Intermetallic doping film is different. The second intermetal doping film is annealed to diffuse the dopant of the second intermetal doping film adjacent to the second set of wells. A second epitaxial source / drain region is grown in one or more wells of the second set of wells.

One embodiment is a semiconductor device that includes a plurality of semiconductor strips and an isolation region formed between the plurality of semiconductor strips, wherein the isolation region has an upper surface that is lower than an upper surface of the plurality of semiconductor strips. The device also includes a plurality of gate stacks formed over a first channel region of the plurality of semiconductor strips, wherein the plurality of gate stacks are perpendicular to the plurality of semiconductor strips. A first epitaxial source / drain region is disposed between two first ones of the plurality of gate stacks, wherein the first epitaxial source / drain region is formed in a first opening in a first strip of the plurality of semiconductor strips. A first dopant diffusion region surrounds the first epitaxial source / drain region and has a first concentration of the first dopant. A first outer diffusion region surrounds and adjoins at least a portion of the first dopant diffusion region and has a second concentration of the first dopant. The first concentration of the first dopant is greater than the second concentration of the first dopant.

While this invention has been described with reference to exemplary embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments and other embodiments of the invention will be apparent to those skilled in the art upon reference to the specification. It is therefore intended that the appended claims encompass any such modifications or embodiments.

QUOTES INCLUDE IN THE DESCRIPTION

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Cited patent literature

• US 62527698 [0001]

Claims (20)

Method, comprising: Etching a substrate to form a first semiconductor strip; Forming a first dummy gate structure over a first channel region of the first semiconductor strip, the first dummy gate structure being perpendicular to the first semiconductor strip; Etching a first recess in the first semiconductor strip on a first side of the first dummy gate structure; Etching a second recess in the first semiconductor strip on a second side of the first dummy gate structure; Forming a first intermetallic doping film in the first recess and the second recess; Diffusing a first dopant of the first intermetal doping film into the first semiconductor strip near the first recess and in the first semiconductor strip near the second recess; epitaxially growing a source / drain region in the first recess; and epitaxially growing a source / drain region in the second recess. Method according to Claim 1 wherein the first dopant is selected from the group consisting of phosphorus, arsenic, antimony, bismuth or a combination of two or more thereof. Method according to Claim 1 wherein the first dopant is selected from the group consisting of boron, aluminum, gallium, indium, or a combination of two or more thereof. The method of any one of the preceding claims, wherein diffusing the first dopant comprises thermally annealing the first intermetal doping film between 900 and 1000 degrees Celsius for 3 to 6 seconds. The method of any one of the preceding claims, wherein forming the first intermetal dopant film comprises: Providing a first process gas having a first concentration, wherein the first process gas is a source of silicon, and Providing a second process gas having a second concentration, wherein the second process gas is a source of the first dopant, wherein a ratio of the second concentration to the first concentration determines a concentration of the first dopant in the first intermetal doping film. Method according to Claim 5 wherein the first process gas comprises: tetraethylorthosilicate (TEOS) or silane (SiH ₄ ), and wherein the second process gas comprises: PH ₃ , POCl ₃ or B ₂ H ₆ . The method of any one of the preceding claims, further comprising: Forming a second dummy gate structure over a second channel region of the first semiconductor strip, the first channel region being separated from the second channel region by an isolation structure; Etching a third recess in the first semiconductor strip on a first side of the second dummy gate structure; Etching a fourth recess in the first semiconductor strip on a second side of the second dummy gate structure; Forming a second intermetal doping film in the third recess and the fourth recess; Diffusing a second dopant of the second intermetal doping film into the first semiconductor strip near the third recess and in the first semiconductor strip near the fourth recess, the second dopant being different from the first dopant; and epitaxially growing a source / drain region in the third depression and a source / drain region in the fourth recess. Method according to Claim 7 , further comprising: etching the substrate to form a second semiconductor strip parallel to the first semiconductor strip, wherein the first dummy gate structure is formed over a first channel region of the second semiconductor strip, and wherein the second dummy gate structure is formed over a second channel region of the second semiconductor strip ; Depositing an insulating material between the first and second semiconductor strips; Diffusing the first dopant of the first intermetal doping film into the second semiconductor strip; and diffusing the second dopant of the second intermetal dopant film into the second semiconductor stripe. A method, comprising: etching a first set of pits into a source / drain region of a first region of a FinFET device; Depositing a first intermetal dopant film in the first set of wells; Annealing the first intermetal doping film to diffuse the dopant of the first intermetal doping film adjacent to the first set of wells; Removing the first intermetallic doping film; Growing a first epitaxial source / drain region in one or more wells of the first set of wells; Etching a second set of pits into a source / drain region of a second region of a FinFET device; Depositing a second intermetal doping film different from the first intermetal doping film in the second set of depressions; Annealing the second intermetal dopant film to diffuse the dopant of the second intermetal dopant film adjacent to the second set of wells; Removing the second intermetallic doping film; and growing a second epitaxial source / drain region in one or more wells of the second set of wells. Method according to Claim 9 wherein the dopant of the first intermetal dopant film is selected from a list consisting of phosphorus, arsenic, antimony, bismuth, or a combination of two or more thereof, and wherein the dopant of the second intermetallic dopant film is selected from a list is boron, aluminum, gallium, indium, or a combination of two or more thereof. Method according to Claim 9 wherein the first intermetal doping film is a first doped silicate glass and wherein the second intermetal doping film is a second doped silicate glass. Method according to Claim 11 wherein the annealing of the first intermetallic doping film comprises annealing the first doped silicate glass between 900 and 1000 degrees Celsius for 3 to 6 seconds. Method according to one of the preceding Claims 9 to 12 further comprising forming a first dummy gate structure perpendicular to and over one or more semiconductor fins, wherein the first set of recesses in the one or more semiconductor fins is etched on opposite sides of the first dummy gate structure. Method according to one of the preceding Claims 9 to 13 wherein the first epitaxial source / drain region comprises a plurality of epitaxial structures combined into a single faceted structure. Method according to Claim 13 further comprising: replacing the first dummy gate structure with a first replacement gate structure, the first replacement gate structure including a gate electrode; Forming a first dielectric layer over the first replacement gate structure; and forming a contact through the first dielectric layer to the gate electrode. Method according to one of the preceding Claims 9 to 15 wherein: depositing the first intermetallic dopant film comprises: providing a first process gas at a first concentration, wherein the first process gas is a source of silicon; and providing a second process gas at a second concentration, the second process gas being a source for the first Dopant is; and depositing the second intermetal dopant film comprises: providing a third process gas having a third concentration, wherein the third process gas is a source of silicon; and providing a fourth process gas having a fourth concentration, wherein the fourth process gas is a source of the second dopant , A semiconductor device, comprising: a plurality of semiconductor strips; an isolation region formed between the plurality of semiconductor strips, the isolation region having an upper surface lower than an upper surface of the plurality of semiconductor strips; a plurality of gate stacks formed over respective channel regions of the plurality of semiconductor strips, the plurality of gate stacks being perpendicular to the plurality of semiconductor strips; a first epitaxial source / drain region disposed between first two of the plurality of gate stacks, the first epitaxial source / drain region being formed in a first opening in a first strip of the plurality of semiconductor strips; a first dopant diffusion region surrounding the first epitaxial source / drain region, the first dopant diffusion region having a first concentration of a first dopant; and a first outer diffusion region surrounding and contiguous with at least a portion of the first dopant diffusion region, the first outer diffusion region having a second concentration of the first dopant, wherein the first concentration of the first dopant is greater than the second concentration of the first dopant. Semiconductor device according to Claim 17 wherein the first opening has a lower surface that is lower than the upper surface of the isolation region. Semiconductor device according to Claim 17 or 18 , further comprising: a second epitaxial source / drain region disposed between second two of the plurality of gate stacks, the second epitaxial source / drain region being formed in a second opening in the first strip of the plurality of semiconductor strips; and a second dopant diffusion region surrounding the second epitaxial source / drain region, the second dopant diffusion region having a first concentration of a second dopant; and a second outer diffusion region surrounding and contiguous with at least a portion of the second dopant diffusion region, the second outer diffusion region having a second concentration of the second dopant, the first concentration of the second dopant being greater than the second concentration of the second dopant and the first dopant is an n-type impurity and the second dopant is a p-type impurity. Semiconductor device according to one of the preceding Claims 17 to 19 , further comprising: a third epitaxial source / drain region disposed between the first two of the plurality of gate stacks, wherein the third epitaxial source / drain region is formed in a third opening in a second strip of the plurality of semiconductor strips the second strip is adjacent to the first strip, the third epitaxial source / drain region being associated with the first epitaxial source / drain region, the combined epitaxial source / drain region having a faceted epitaxial structure having an upper surface, which is at least about 2 nm higher than an upper surface of the first strip.

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