DE102017122454A1 - Flexible crown-shaped bump for flip-chip mounting - Google Patents

Abstract

In various embodiments, a chip assembly is provided comprising a chip body (310), at least one chip termination region (320), at least one passivation layer (330) partially adjacent to the die connection region (320), the passivation layer (330) having an opening (332 ) by means of which at least part of the chip connection region (320) is exposed, a substrate (340) having a substrate connection region (342), and an electromechanical connection structure (350) having a cavity (352) in the interior. At least one wall (354) of the connection structure (350) is disposed on the passivation layer (330) and on the substrate connection region (342). The electromechanical connection structure (350) electrically connects the chip connection region (320) to the substrate connection region (342). The cavity (352) has a depth (d1) that is greater than a depth (d2) of the opening (332).

Description

Various embodiments generally relate to the mounting of chip arrays, for example, in flip-chip-on-substrate (FCOS) technology.

In the field of electronic device development, demands on the electronic components provided in an integrated circuit have been greatly increased in recent years. In particular, the increasing miniaturization of the structures further requires an adaptation of the manufacturing process in order, for example, to achieve a reduction of the structure size and thus also a reduction of the thicknesses of the required layers. However, a reduction in the layer thickness means that in particular insulating layers with a smaller thickness have poorer insulating properties.

For this reason, it is increasingly necessary to use for the insulating layers materials that isolate particularly well. For this purpose, offer materials with a low dielectric constant, for example, "low-k" - or "ultra low-k" materials, which still have sufficient insulating despite a small thickness, for example, to ensure the necessary capacity in capacitor structures.

However, the use of these particularly well-insulating materials presents further problems due to other properties of the materials which are unfavorable for the production of the chips.

A characteristic feature of ultra-low dielectric constant substrates (referred to as ULK substrates in the following) in integrated circuit (IC) chips or in the production of integrated circuit (IC) chips is, for example, the low mechanical stability of the insulating layers formed therefrom. When direct mechanical force, such as compressive force, acts on the ULK substrate, these layers may be damaged.

The principle of FCOS mounting is based on a pressure contact. For this purpose, the terminals of the ICs are provided with bumps, for example so-called stud bumps made of gold, which are relatively soft, or nickel-gold bumps, which are formed by means of electroless plating. During assembly, the IC is then placed upside down on the corresponding opposite substrate, which also has an adhesive that picks up and fixes the chip. The bumps are then pressed onto the substrate lines or substrate terminals, with a slight deformation of the bumps compensating for any height differences of the many bumps on a chip. In this position, the adhesive is cured, typically by heat. After the adhesive is cured, the chip is fixed on the substrate and there is an electrically conductive connection between the chip and the substrate.

The problem with this assembly method when used with ULK chips is the direct application of force when pressing the stud bumps onto the substrate leads or substrate leads. This direct-acting force can damage or destroy the ULK layers under the pad metal of the terminal of the chip, as in 1 shown.

1 Fig. 12 shows a stage of FCOS mounting a chip on a substrate using a stud bump according to the related art.

As in 1 has a chip equipped with low-dielectric-constant structures (also referred to as low-k structures hereinafter) 110 on his first page 116 , the main processing side and the front side, respectively (hereinafter referred to as a pad) terminal 120 of a pad metal at least partially disposed on the low-k structures. On the pad 120 is a stud-bump 112 , for example, made of gold, and next to the pad 120 is a chip passivation 130 For example, of polyimide, deposited.

The chip 110 comes with the first page 116 down to a substrate 140 applied, the substrate 140 Tracks or lines or connections 142 and a thermosetting adhesive 160 having.

The chip 110 is in a further sub-process on the substrate 140 Pressed so that the stud bump 112 through the glue 160 through to one of the substrate terminals 142 is pressed. This subprocess will put so much pressure on the chip body 110 and the substrate 140 exercised that the stud bumps 112 firmly on the substrate lines 142 be pressed, so that by means of a deformation of the stud bumps 112 over the surface of the first page 116 of the chip 110 existing height differences of the stud bumps are compensated. At the same time between the respective substrate line 142 and the corresponding stud-bump 112 each formed a reliable electrically conductive connection. After pressing the chip 110 on the substrate 140 becomes the glue 160 cured, for example by means of heat.

As already stated, this production method with FCOS assembly has the disadvantage that the one for the secure contacting of all stud bumps 112 with the substrate connections 142 necessary pressure when pressing on the chip 110 on the substrate 140 a force impact on the pad metal 120 and thus to the underlying low-k structures (or low-k layers, ULK structures and / or ULK layers) of the chip 110 includes. By looking at the low-k structures of the chip 110 acting force when compressing the chip 110 and the substrate 140 These low-k structures may be damaged, for example, by cracks or cracks in the area 114 The low-k layers or ULK layers arise because the layers of such materials are usually very brittle.

According to various embodiments, bump shapes are provided which can reduce or possibly even prevent direct application of pressure to the low-k material or ULK material of the structures in the chip during assembly.

The crown-bump shapes described in various embodiments preserve the effect of conventional gold stud bumps, by means of deformation of the bumps to compensate for a height difference of the bumps arranged on the chip. The crown bump shapes described in various embodiments may be configured to have deformable portions.

However, the particular shape of the crown bump embodiments described herein ensures that no direct pressure or direct force is exerted on the chips' low-k or ULK structures during the FCOS assembly process. Instead, in various embodiments, the crown bumps are configured to capture the pressure applied during the FCOS assembly process from the softer passivation layer deposited on top of the chip.

For this purpose, the new bumps are shaped so that the pressure-collecting parts of the bumps are arranged above the passivation layer. Because the passivation layer is softer than the pad metal, the passivation layer may be deformed so that the force applied during the process of compressing the chip and the substrate is captured and thus distributed by the passivation and not to the brittle ones present in the chip Low-k or ULK materials is passed.

Furthermore, the various embodiments of the new crown bumps described herein are shaped to ensure reliable contacting of the substrate lines on one side and the terminal pads of the chip on the other side.

According to various embodiments, a design of the bumps on the chip, which can avoid the application of a direct force on the structures of low-k or ULK material of the chip and still height differences of the structures to be contacted on the opposite surfaces of the chip or . of the substrate can compensate and thereby ensure a reliable electrical contacting of the chip terminals with the substrate lines.

In various embodiments, a chip arrangement is provided which has a chip body, at least one chip connection region on the chip body and at least one passivation layer. In this case, the passivation layer is partially arranged next to the chip connection region and has an opening, by means of which at least part of the chip connection region is exposed. The chip arrangement further comprises a substrate with a substrate connection region and an electromechanical connection structure. The electromechanical connection structure has a cavity in the interior, wherein at least one wall of the connection structure is arranged on the passivation layer and on the substrate connection region and connects the chip connection region to the substrate connection region in an electrically conductive manner. The cavity in the interior of the connection structure has a depth that is greater than a depth of the opening.

In various embodiments, the electromechanical connection structure of the chip arrangement may be a flip-chip connection structure. In other words, the connection structure may be formed so as to be suitable for mounting a chip body on a substrate in flip-chip-on-substrate (FCOS) technology. For this purpose, the connection structure may be designed such that it is suitable for pressure contact during FCOS mounting, such that, for example, deformable bumps are formed as a connection structure on the chip body. When the chip body is connected to the substrate, the chip body with the upper side, ie with the side having the chip connection region and the connection structure, can be applied to the oppositely disposed substrate which has the substrate connection region and adhesive. The deformable bumps can then be pressed onto the substrate and the substrate connection area in such a way that a slight deformation of the bumps, possibly existing height differences of the bumps on the chip body can be compensated. The adhesive can subsequently be cured, for example by means of heat, whereby the chip body can be mechanically fixed on the substrate and by means of the bumps an electrically conductive connection can be formed between the chip connection region and the substrate connection region.

The connection structure may have at least a bottom and a wall. The connection structure may also consist of a bottom and at least one wall.

In various embodiments, the wall may be annular. Alternatively, the wall may have a rectangular shape.

The wall may also be formed such that it is self-contained. Alternatively, the wall may be divided into a plurality of sections. In other words, the wall can be segmented. In this case, gaps between the sections may be formed.

In various embodiments, the wall may be segmented into four sections or any other number of sections. The portions and gaps between the portions may be made to be evenly distributed on the circumference of the wall or unevenly distributed on the circumference of the wall. In other words, the sections and the gaps may be the same size or the sections and the gaps may have different sizes.

In various embodiments, the bottom of the interconnect structure may contact the die pad area. The bottom of the connection structure may be configured to contact the chip termination region through the opening of the passivation layer.

In various embodiments, the chip body may include a chip body substrate. In various embodiments, the chip body substrate may include or consist essentially of at least one of silicon, silicon carbide, germanium, gallium phosphide, gallium arsenide, and gallium nitride.

In various embodiments, the chip body may further include structures of a material having a predetermined dielectric constant. For example, the dielectric constant of the material of the structures in the chip body may be less than 3.9. For example, the dielectric constant of the structures may be less than 2.4.

In various embodiments, the material of the structures of one of the group consisting of inorganic materials (hydrogen silsesquioxane (HSQ, HSSQ), amorphous carbon, carbon-doped silica), hybrids (Si-OC polymers), organic materials (polyimides, parylene) N, benzocyclobutenes (BCB), fluorinated polyimides, aromatic polyethers (PAE), polyaryls, parylene-F4, fluoropolymers (egPTFE)) and porous materials (organic materials, porous CDO, silicatic xerogels, silicatic aerogels, mesoporous organosilicates, porous HSSQ / MSSQ, mesoporous silicate glasses SiO2) or essentially consist thereof.

In various embodiments, the passivation layer may include or consist essentially of one of the group consisting of polyimide, polybenzoxazole (PBO), silicon nitride, and silicon dioxide.

In various embodiments, the interconnect structure may comprise or consist essentially of at least one of copper, nickel, palladium, nickel-palladium, gold, nickel-palladium-gold, nickel-phosphorous-palladium-gold, silver, and aluminum.

The connection structure may have a copper structure coated with a nickel-palladium layer in a thickness of about 3 μm. Alternatively, the interconnect structure may have a copper structure coated with a palladium layer in a thickness of approximately 300 nm. The interconnect structure may alternatively have a copper structure coated with a gold layer in a thickness of about 50 nm. Furthermore, the connection structure may have a copper structure which is coated with a nickel-palladium-gold layer in a thickness of less than 3 microns.

In various embodiments, the connection structure may have a diameter in a range of about 50 μm to about 150 μm, optionally in a range of about 70 μm to about 140 μm, optionally in a range of about 100 μm to about 120 μm.

In various embodiments, the chip termination region may have an area in a range of about 90 × 90 μm ² to about 25 × 25 μm ² , optionally in a range of about 80 × 80 μm ² to about 40 × 40 μm ² , optionally in one Range from about 70 × 70 μm ² to about 50 × 50 μm ² . The chip connection region can be designed as a connection pad. The chip connection region may be formed as a pad metallization.

In various embodiments, the chip body may further include a redistribution layer connected to the chip termination region exhibit. The redistribution layer may connect the chip termination region to the connection structure. The redistribution layer may be disposed in a plane with the bottom of the connection structure. The redistribution layer may be arranged to contact the chip pad region through the opening in the passivation layer.

In various embodiments, there is further provided a method of making a chip assembly, the method comprising forming an opening in at least one passivation layer. The passivation layer is partially arranged next to a chip connection region of a chip body, so that at least part of the chip connection region is exposed by means of the opening. The method further comprises forming an electromechanical interconnect structure between the die pad region and a substrate pad region of a substrate. The electromechanical connection structure has a cavity in the interior, such that at least one wall of the connection structure is arranged on the passivation layer and on the substrate connection region. The cavity further has a depth that is greater than a depth of the opening. The method further comprises fixing the electromechanical connection structure such that the chip connection region and the substrate connection region are connected to one another in an electrically conductive manner.

In various embodiments of the method, the electromechanical connection structure may be a flip-chip connection structure. In other words, the connection structure may be formed to be suitable for mounting a chip body on a substrate in flip-chip-on-substrate (FCOS) technology.

In various embodiments of the method, forming the connection structure may include at least forming a bottom and forming at least one wall. For example, the connection structure may be formed such that the floor of the connection structure is formed on the chip body and the wall is formed on the floor such that the floor and the wall form a mechanical, electrically conductive unit. In this case, the bottom can be formed at least partially over the chip connection region and contact it.

In various embodiments of the method, the wall may be formed annular. In other words, the wall can be formed in a ring shape. Alternatively, the wall may be formed in a rectangular shape. The wall can be closed in itself. In other words, the wall can form a self-contained ring on the floor.

In various embodiments of the method, the wall may be formed segmented. In other words, the wall may be formed to have a number of sections with gaps therebetween. For example, the wall may be formed to have a portion with a gap (for example, a slit), two sections having two gaps, three sections having three gaps, or four sections having four gaps. The wall can also be formed in various embodiments of the method so that it is subdivided into any other number of sections. In other words, the wall may be formed to be segmented into one, two, three, four, or any other number of sections. In various embodiments of the method, the sections may be formed such that the gaps between the sections are formed as narrow slots. In various embodiments of the method, the sections may be formed such that the sections and gaps between the sections are uniformly distributed around the circumference of the wall. In other words, the sections and the gaps can be made the same size. For example, the wall may be formed to be segmented into four sections.

In various embodiments, the chip body may include a chip body substrate. In various embodiments, the chip body may further include structures of a material having a predetermined dielectric constant. For example, the dielectric constant of the structures may be less than 3.9. Alternatively, the dielectric constant of the structures may be less than 2.4.

In various embodiments of the method, forming the interconnect structure may include forming a seed layer on the passivation layer and in the opening such that at least a portion of the exposed portion of the chip termination region is covered, forming a copper layer over the seed layer, forming a copper structure the copper layer, then removing exposed areas of the seed layer.

Further, the method of forming the interconnect structure may include forming a seed layer on the passivation layer and in the opening of the passivation layer such that at least a portion of the one of the opening exposed portion of the chip terminal area is covered by the seed layer; Forming a first mask over at least a portion of the seed layer; Forming a copper layer over the seed layer in regions exposed from the first mask; Removing the first mask; Forming a second mask over the copper layer and exposed areas of the seed layer; Forming a copper structure on exposed portions of the copper layer; Removing the second mask; subsequently removing exposed areas of the seed layer.

In various embodiments of the method, the copper layer and the copper structure may be formed such that together they form the connection structure. In this case, for example, the bottom of the connection structure can be formed by means of the formation of the copper layer, and by forming the copper structure, the wall of the connection structure can be formed. In other words, the copper layer can form the bottom of the connection structure, while the copper structure can form the wall of the connection structure. In this case, the copper layer can be formed such that it contacts the chip connection region.

In various embodiments of the method, the formation of the copper layer and the copper structure can be galvanic. Alternatively, the copper layer and the copper structure may be deposited by PVD.

Alternatively, the formation of the copper layer and the copper structure may be done by CVD.

In various embodiments of the method, the copper structure may be formed in a ring shape. Alternatively, the wall may be formed to have a rectangular shape.

The wall can be formed such that it forms a self-contained wall, for example a self-contained ring. Alternatively, the wall may be formed to be divided into a plurality of sections. In other words, the copper structure can be formed in segments, wherein the segments and gaps between the segments can be the same size. In other words, the portions of the copper structure and the gaps therebetween may be formed to be evenly distributed around the circumference of the copper structure.

In various embodiments, the copper structure may be coated with a nickel-palladium layer in a thickness of approximately 3 μm. Further, the copper structure may be coated with a palladium layer in a thickness of about 300 nm. The copper structure may be further coated with a gold layer in a thickness of about 50 nm. The copper structure may also be coated with a nickel-palladium-gold layer in a thickness of less than 3 μm.

In various embodiments of the method, the chip body may include structures of a material having a predetermined dielectric constant. For example, the dielectric constant of the structures may be less than 3.9. For example, the dielectric constant of the structures may be less than 2.4.

In various embodiments, the material of the structures of one of the group consisting of inorganic materials (hydrogen silsesquioxane (HSQ, HSSQ), amorphous carbon, carbon-doped silica), hybrids (Si-OC polymers), organic materials (polyimides, parylene) N, benzocyclobutenes (BCB), fluorinated polyimides, aromatic polyethers (PAE), polyaryls, parylene-F4, fluoropolymers (egPTFE)) or porous materials (organic materials, porous CDO, silicatic xerogels, silicatic aerogels, mesoporous organosilicates, porous HSSQ / MSSQ, mesoporous silicate glasses SiO2) or essentially consist thereof.

In various embodiments of the method, the chip body may comprise a chip body substrate comprising or consisting essentially of one of the group consisting of silicon, silicon carbide, germanium, gallium phosphide, gallium arsenide, and gallium nitride.

In various embodiments of the method, the passivation layer may be formed or substantially formed of at least one of the group consisting of polyimide, polybenzoxazole (PBO), silicon nitride, and silicon oxide.

In various embodiments of the method, the interconnect structure may be formed or substantially formed of at least one of the group consisting of copper, nickel, palladium, nickel-palladium, gold, nickel-palladium-gold, silver, and aluminum.

In various embodiments of the method, the interconnect structure may be formed in a diameter in a range of about 50 μm to about 150 μm, optionally in a range of about 70 μm to about 140 μm, optionally in a range of about 100 μm to about 120 μm ,

In various embodiments, the chip termination region may range in area from about 90 × 90 μm ² to about 25 × 25 μm ² , optionally in a range from about 80 × 80 μm ² to about 40 × 40 μm ² , optionally in FIG a range of about 70 × 70 μm ² to about 50 × 50 μm ² . The chip connection region can be formed as a connection pad. The chip connection region can be formed as a pad metallization.

In various embodiments, the method may further include: forming a redistribution layer connected to the chip pad region on the chip body. The redistribution layer may connect the chip termination region to the connection structure. The redistribution layer may be formed to be disposed in a plane with the bottom of the connection structure. The redistribution layer may be formed to contact the die pad region through the opening in the passivation layer.

In various embodiments, a chip arrangement may be provided with a plurality of integrated circuits having a plurality of connection structures, wherein the chip arrangement may have the above-mentioned features.

In various embodiments, a chip arrangement may be provided that includes a chip body, at least one chip termination region, and at least one passivation layer partially adjacent to the die connection region. In this case, the passivation layer may have an opening, by means of which at least part of the chip connection region is exposed. The chip assembly may further comprise a substrate having a substrate connection region and an electromechanical connection structure having a cavity therein. In this case, at least one wall of the connection structure may be arranged on the passivation layer and on the substrate connection region, wherein the electromechanical connection structure connects the chip connection region to the substrate connection region in an electrically conductive manner. In a region of the electromechanical connection structure, which is in contact with the chip connection region, there may be a tensile stress.

In various embodiments, a method for manufacturing a chip arrangement may be provided, wherein the method comprises various sub-processes. For example, a sub-process may be forming an opening in at least one passivation layer that is partially disposed adjacent a chip termination region of a chip body such that at least a portion of the chip termination region is exposed. In a further sub-process, an electromechanical connection structure can be formed between the chip connection region and a substrate connection region of a substrate. In this case, the electromechanical connection structure can be formed such that it has a cavity in the interior, such that at least one wall of the connection structure is arranged on the passivation layer and on the substrate connection region. Then, a force may be applied to the electromechanical connection structure such that a torque is generated by the wall of the electromechanical connection structure in a portion of the electromechanical connection structure in contact with the chip connection portion, and that the chip connection portion and the substrate Connection area are electrically connected to each other.

In various embodiments of the method, the chip body and the substrate may be compressed such that the connection structure forms an electrically conductive contact between the chip connection region and the substrate connection region. In other words, the connection structure can form a pressure contact between the chip connection region and the substrate connection region. In other words, by means of force application, a pressure contact can be formed between the chip connection region and the substrate connection region. In this case, the bottom of the connection structure can electrically conductively contact the chip connection region, and the wall of the connection structure can contact the substrate connection region in an electrically conductive manner. At the same time, the chip body and the substrate can be mechanically connected to each other by means of the connection structure, wherein adhesive which can be arranged between the substrate and the chip body can stabilize the connection.

In various embodiments of the method, when the chip body and the substrate are compressed, the copper structure may be deformed such that differences in height of structures on the surface of the chip body and on the surface of the substrate are compensated.

The chip arrangement described here or the method for producing a chip arrangement provides a connection structure by means of which it is possible to avoid the low-k structures or ULK structures arranged in the chip body substrate under the chip connection area during the FCOS process. Damage assembly process. Connection structures with a Crown bump design (in other words, a crown-shaped bump) according to various embodiments or a form of crown bumps according to various embodiments may be provided to redirect the pressure locally applied during the FCOS assembly process to the passivation layer deposited adjacent to the die pad area in that damage to the brittle low-k or ULK structures of the chip body is prevented. The shape of the crown bumps described here as a connection structure according to various embodiments can ensure that height differences of the structures to be contacted on the opposite surfaces of the chip or the substrate can be compensated and thereby a reliable electrical contacting of the chip terminals with the substrate lines can be provided.

The avoidance of direct application of force to the chip connection region and thus to the low-k or ULK structures of the chip body arranged underneath can be ensured, for example, by forming the crown bumps in such a way that they have a wall and a bottom. In this case, the bottom of the crown bumps can be designed so that the good contact of the chip connection area can be ensured. Furthermore, the wall of the crown bumps may be formed to be annular, wherein the diameter of the ring may be larger than the area of the chip termination area, so that it can be ensured that upon application of a force on the ring this force does not affect the chip connection area. In addition, the wall of the crown bumps may be formed so as to ensure that the crown bumps have a cavity over the chip termination region, wherein the cavity may have a sufficiently large depth, so that even during a force application during the FCOS assembly occurring deformation of the crown bump wall can be ensured that no force is exerted on the chip connection area. The depth of the cavity defined over the height of the wall of the crown bump can furthermore ensure that possibly existing height differences of the structures to be contacted on the surface of the chip or on the surface of the substrate are compensated for by means of a differently pronounced deformation of the crown bumps can. In sum, the embodiments of the chip arrangement provided here by means of the forms of the electromechanical connection structure described here, a simple FCOS assembly with good contact while avoiding damage to the present in the chip body sensitive low-k or ULK structures can be ensured.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

• 1 ein Stadium der herkömmlichen FCOS-Montage eines Chips auf einem Substrat unter Verwendung eines Stud-Bumps;
• 2 eine schematische Darstellung einer Draufsicht auf eine Chipanordnung gemäß verschiedenen Ausführungsbeispielen;
• 3 eine schematische Querschnittdarstellung einer Chipanordnung gemäß verschiedenen Ausführungsbeispielen;
• 4A und 4B vergrößerte schematische perspektivische Darstellungen einer Verbindungsstruktur einer Chipanordnung gemäß verschiedenen Ausführungsbeispielen;
• 5 ein Ablaufdiagramm eines Verfahrens zum Herstellen einer Chipanordnung gemäß verschiedenen Ausführungsbeispielen;
• 6 eine schematische Darstellung von Teilprozessen zum Bilden der Verbindungsstruktur in verschiedenen Ausführungsbeispielen des Verfahrens;
• 7A und 7B eine schematische Darstellung von zwei Teilprozessen der FCOS-Montage des Verfahrens gemäß verschiedenen Ausführungsbeispielen;
• 8 eine vergrößerte schematische Darstellung eines FCOS-Montage-Teilprozesses des Verfahrens gemäß verschiedenen Ausführungsbeispielen;
• 9 ein Ablaufdiagramm eines Verfahrens zum Herstellen einer Chipanordnung gemäß weiteren verschiedenen Ausführungsbeispielen;
• 10 eine vergrößerte schematische perspektivische Darstellung einer Verbindungsstruktur einer Chipanordnung mit einer Umverdrahtungsschicht gemäß verschiedenen Ausführungsbeispielen;
• 11 vergrößerte Ansichten eines Chipkarten-ICs, der eine Mehrzahl von Verbindungsstrukturen gemäß verschiedenen Ausführungsbeispielen aufweist.

Show it

• 1 a stage of conventional FCOS mounting of a chip on a substrate using a stud bump;
• 2 a schematic representation of a plan view of a chip arrangement according to various embodiments;
• 3 a schematic cross-sectional view of a chip arrangement according to various embodiments;
• 4A and 4B enlarged schematic perspective views of a connection structure of a chip arrangement according to various embodiments;
• 5 a flow chart of a method of manufacturing a chip arrangement according to various embodiments;
• 6 a schematic representation of sub-processes for forming the connection structure in various embodiments of the method;
• 7A and 7B a schematic representation of two sub-processes of the FCOS assembly of the method according to various embodiments;
• 8th an enlarged schematic representation of an FCOS assembly sub-process of the method according to various embodiments;
• 9 a flowchart of a method for manufacturing a chip arrangement according to further various embodiments;
• 10 an enlarged schematic perspective view of a connection structure of a chip arrangement with a redistribution layer according to various embodiments;
• 11 are enlarged views of a smart card IC having a plurality of interconnect structures according to various embodiments.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "front", "rear", etc. is used with reference to the orientation of the described figure (s). There For purposes of illustration, components of embodiments may be positioned in a number of different orientations, the directional terminology is illustrative and is in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be understood that the features of the various exemplary embodiments described herein may be combined with each other unless specifically stated otherwise. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

As used herein, the terms "connected," "connected," and "coupled" are used to describe both direct and indirect connection, direct or indirect connection, and direct or indirect coupling. In the figures, identical or similar elements are provided with identical reference numerals, as appropriate.

2 shows a schematic representation of a plan view of a chip arrangement according to various embodiments.

In various embodiments, components, materials, effects, dimensions, distances, etc., of devices or parts thereof may be used in conjunction with 3 to 11 described correspond to those associated with the 2 are described correspond. Repetition may therefore be dispensed with, and the components, materials, effects, dimensions, distances, etc. may be given the same reference numerals. It should also be noted that the list of said materials of all elements described is not exhaustive, but other materials may be used if their use makes sense.

As in 2 shown, a chip arrangement 200 According to various embodiments, a chip body 210 have on which a chip connection area 220 can be arranged. The chip body 210 may comprise a chip body substrate. The chip body 210 may further comprise structures that may be formed of a material having a low dielectric constant (hereinafter also referred to as low-k material or as low-k structures), or may be formed of a material that is an ultra having low dielectric constant (hereinafter also referred to as ULK material or as ULK structures).

In various embodiments, the chip body substrate may include or consist essentially of one of the group consisting of silicon, silicon carbide, germanium, gallium phosphide, gallium arsenide, and gallium nitride.

The chip body can furthermore be arranged on a system carrier, the system carrier being designed, for example, as a printed circuit board, lead frame or other chip carrier material. For example, the leadframe may comprise or consist essentially of any of these materials or a mixture thereof, silicon, chip substrates, flex polyimide, polyesters, other thermoplastic materials, fiber reinforced epoxy, or other fiber reinforced thermoset materials.

The low-k material (or the low-k structures) can be, for example, inorganic materials (hydrogen silsesquioxane (HSQ, HSSQ), amorphous carbon, carbon-doped silicon oxide), hybrids (Si-OC polymers) or organic materials ( Polyimides, parylene-N, benzocyclobutenes (BCB), fluorinated polyimides, aromatic polyethers (PAE), polyaryls, parylene-F4, fluoropolymers (eg PTFE)), or consist essentially of one of these materials or a mixture thereof. The ULK material (or the ULK structures) may include, for example, porous materials (organic materials, porous CDO, silicic xerogels, silicate aerogels, mesoporous organosilicates, porous HSSQ / MSSQ, mesoporous silicate glasses SiO 2), or substantially of any of these materials consist of a mixture of them.

The chip connection area 220 For example, in various embodiments, aluminum, copper, aluminum-copper, aluminum-silicon, aluminum-silicon-copper, nickel, nickel-phosphorus, nickel-palladium-gold or nickel-gold may comprise or substantially consist of one of these materials or of a mixture consist of it. The chip connection area 220 can be designed as a connection pad. The chip connection area 220 may be formed as a pad metallization. The chip termination region may, for example, have an area in a range of about 90 × 90 μm ² to about 25 × 25 μm ² , optionally in a range of about 80 × 80 μm ² to about 40 × 40 μm ² , optionally in a range of about 70 × 70 μm ² to about 50 × 50 μm ² .

At least on one surface of the chip body 210 can in different Embodiments, a passivation layer 230 be arranged. The passivation layer 230 can on a region of the surface of the chip body 210 be deposited, on which the chip connection area 220 is trained. The passivation layer 230 may be deposited such that it contacts the chip termination area 220 borders. The passivation layer 230 may be formed such that it the chip connection area 220 at least partially covered. The passivation layer 230 may be formed such that it the chip connection area 220 overlaps. The passivation layer 230 can be so on a portion of the surface of the chip body 210 be arranged that they have the chip connection area 220 completely covered.

The passivation layer 230 For example, it may comprise polyimide, polybenzoxazole (PBO), silicon nitride, and silicon oxide, or may consist essentially of one of these materials, a mixture thereof, or a layer combination of these materials. The passivation layer 230 For example, it may be deposited in a thickness in a range of about 4 μm to about 12 μm, optionally in a range of about 5 μm to about 10 μm, optionally in a range of about 6 μm to about 8 μm.

The passivation layer 230 may be an opening in various embodiments 232 have, wherein the opening 232 at least partially on the chip connection area 220 is arranged. The opening 232 may be formed such that it at least a portion of the chip connection area 220 exposes. This can be the opening 232 have a depth that is deep enough that at least a portion of the surface of the chip termination area 220 is exposed. The opening 232 can also be arranged such that the chip connection area 220 through the opening 232 can be contacted through.

The opening can be 232 have a diameter in a range of about 10 μm to about 70 μm, optionally in a range of about 20 μm to about 60 μm, optionally in a range of about 30 μm to about 45 μm. In addition, the opening 232 have a depth in a range of about 4 μm to about 12 μm, optionally in a range of about 5 μm to about 10 μm, optionally in a range of about 6 μm to about 8 μm.

In various embodiments, the chip arrangement 200 Furthermore, an electromechanical connection structure 250 exhibit. The electromechanical connection structure 250 may be formed such that it has a cavity 252 having. The connection structure 252 For example, it may be configured to form a floor 256 and a wall 254 having.

The floor 256 the connection structure 250 may be arranged in various embodiments such that it is on the chip connection area 220 is arranged. The floor 256 may further be formed such that it the chip connection area 220 through the opening 232 in the passivation layer 230 contacted through.

The floor 256 For example, it may have a thickness in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm.

The wall 254 the connection structure 250 may be arranged in various embodiments such that they are connected to the ground 256 together the cavity 252 forms. The cavity 252 may be arranged to overlie at least a portion of the chip termination area 220 is positioned. The cavity 252 may also be arranged such that it over at least a portion of the opening 232 in the passivation layer 230 is positioned. Furthermore, the cavity 252 be formed so that it completely over the passivation layer 230 is arranged (not shown). In this case, the cavity 252 be positioned so that it does not over the chip termination area 220 is arranged (not shown).

The wall 254 the connection structure 250 may have an outer diameter in a range of about 70 microns to about 160 microns, optionally in a range of about 90 microns to about 140 microns, optionally in a range of about 110 microns to about 120 microns. This can be the wall 254 the connection structure 250 a thickness in a range of about 5 μm to about 15 μm, optionally in a range of about 7 μm to about 13 μm, optionally in a range of about 9 μm to about 11 μm.

This allows the cavity 352 For example, have a radius in a range of about 20 microns to about 70 microns, optionally in a range of about 30 microns to about 60 microns, optionally in a range of about 40 microns to about 50 microns.

Besides, the wall can 254 the connection structure 250 a height in a range of about 10 μm to about 30 μm, optionally in a range of about 15 μm to about 25 μm, optionally in a range of about 18 μm to about 22 μm.

The connection structure 250 may be arranged in various embodiments such that at least part of the connection structure 250 on the passivation layer 230 is arranged. The wall 254 the connection structure 250 may be arranged such that at least a portion of the wall 254 on the passivation layer 230 is localized. The wall 254 may be arranged such that it the chip connection area 220 surrounds and completely on the passivation layer 230 is arranged, optionally the wall 254 the opening 232 the passivation layer 230 completely encloses. In other words, the opening 232 the passivation layer 230 completely inside the wall 254 be arranged. In other words, the opening can be 232 completely inside the cavity 252 the connection structure 250 be arranged.

The connection structure 250 For example, in various embodiments, at least one of the group consisting of copper, nickel, palladium, nickel-palladium, gold, nickel-palladium-gold and nickel-phosphorus-palladium-gold may comprise or be substantially formed.

In various embodiments, the connection structure 250 have a copper structure coated with a nickel-palladium layer in a thickness of about 3 μm. In various embodiments, the connection structure 250 have a copper structure coated with a palladium layer in a thickness of about 300 nm. In various embodiments, the connection structure 250 have a copper structure coated with a gold layer in a thickness of about 50 nm. In various embodiments, the connection structure 250 have a copper structure which is coated with a nickel-palladium-gold layer in a thickness of less than 3 microns.

3 shows a schematic cross-sectional view of a chip arrangement according to various embodiments.

As in 3 shown, a chip arrangement 300 According to various embodiments, a chip body 310 have on which a chip connection area 320 can be arranged. The chip body 310 may comprise a chip body substrate, which may further comprise structures which may be formed of a material having a low dielectric constant (hereinafter also referred to as low-k material or low-k structure), or consisting of a Material may be formed, which has an ultra-low dielectric constant (hereinafter also referred to as ULK material or ULK structure).

As related to above 2 As already stated, the chip body may comprise a chip body substrate, wherein the chip body substrate in various embodiments may comprise or consist essentially of one of the group consisting of silicon, silicon carbide, germanium, gallium phosphide, gallium arsenide and gallium nitride.

The chip body may be arranged on a system carrier, which may be designed, for example, as a printed circuit board, lead frame or other chip carrier material. For example, the leadframe may comprise or consist essentially of any of these materials or a mixture thereof, silicon, chip substrates, flex polyimide, polyesters, other thermoplastic materials, fiber reinforced epoxy, or other fiber reinforced thermoset materials.

The low-k material (or the low-k structures) may, for example, comprise carbon-doped silicon oxide or diamond-like carbon (DLC) or consist essentially of one of these materials or of a mixture thereof. The ULK material (or the ULK structures) may include, for example, porous materials (organic materials, porous CDO, silicic xerogels, silicate aerogels, mesoporous organosilicates, porous HSSQ / MSSQ, mesoporous silicate glasses SiO 2), or substantially of any of these materials consist of a mixture of them.

The chip connection area 320 For example, in various embodiments, it may be aluminum, copper, aluminum-copper, aluminum-silicon or aluminum-silicon-copper, or it may consist essentially of one of these materials or a mixture thereof. The chip connection area 320 can be designed as a connection pad, for example as a chip pad. The chip connection area 320 may be formed as a pad metallization.

The chip connection area 320 For example, an area in a range of about 90 × 90 μm ² to about 25 × 25 μm ² , optionally in a range of about 80 × 80 μm ² to about 40 × 40 μm ² , optionally in a range of about 70 × 70 ² μm to about 50 × 50 μm ² .

At least on one surface of the chip body 310 For example, in various embodiments, a passivation layer 330 be arranged. The passivation layer 330 can on a region of the surface of the chip body 310 be deposited, on which the chip connection area 320 is trained. The passivation layer 330 may be deposited such that it contacts the chip termination area 320 borders. The passivation layer 330 may be formed such that it the chip connection area 320 at least partially covered. The passivation layer 330 may be formed such that it the chip connection area 320 overlaps. The passivation layer 330 can be so on a portion of the surface of the chip body 310 be arranged that they have the chip connection area 320 completely covered.

The passivation layer 330 For example, it may comprise polyimide, polybenzoxazole (PBO), silicon nitride, and silicon oxide, or may consist essentially of any of these materials, a mixture thereof, or a combination of layers. In this case, the passivation layer 330 be formed of a material that is photostructurable or laser structurable. The passivation layer 330 may also be deposited, for example, in a thickness of 4 microns to about 12 microns, optionally in a range of about 5 microns to about 10 microns, optionally in a range of about 6 microns to about 8 microns.

In various embodiments, the passivation layer 330 an opening 332 have, wherein the opening 332 at least partially on the chip connection area 320 is arranged. The opening 332 may be formed such that it at least a portion of the chip connection area 320 exposes. This can be the opening 332 have a depth d2 sufficient that at least a portion of the surface of the chip terminal portion 320 is exposed. The opening 332 can also be arranged such that the chip connection area 320 through the opening 332 can be contacted through.

The opening can be 332 have a diameter in a range of about 10 μm to about 70 μm, optionally in a range of about 20 μm to about 60 μm, optionally in a range of about 30 μm to about 45 μm. In addition, the depth d2 of the opening 323 in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm.

In various embodiments, the chip arrangement 300 Furthermore, an electromechanical connection structure 350 exhibit. The electromechanical connection structure 350 may be formed such that it has a cavity 352 having. The connection structure 350 For example, it may be configured to form a floor 356 and a wall 354 having. Furthermore, the connection structure 350 be a flip-chip connection structure.

The floor 356 the connection structure 350 may be arranged in various embodiments such that it is on the chip connection area 320 is arranged. The floor 356 may further be formed such that it the chip connection area 320 through the opening 332 in the passivation layer 330 contacted through. This can be the soil 356 For example, have a thickness in a range of about 3 microns to about 10 microns, optionally in a range of about 4 microns to about 8 microns, optionally in a range of about 5 microns to about 7 microns.

The floor 356 the connection structure 350 can be so over the opening 323 over the chip connection area 320 and the one to the opening 323 adjacent area of the passivation layer 330 be formed that the ground 356 a dent above the chip connection area 320 having. In other words, the ground can 356 the opening 323 at least partially fill and thereby the chip connection area 320 and can also connect to the chip connection area 320 adjacent area of the passivation layer 330 overlap, so that the dent is formed. For example, the dimple may have a depth in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm.

The wall 354 the connection structure 350 may be arranged in various embodiments such that they are connected to the ground 356 together the cavity 352 forms. The cavity 352 may be arranged to overlie at least a portion of the chip termination area 320 is positioned. The cavity 352 may also be arranged such that it over at least a portion of the opening 332 in the passivation layer 330 is positioned. Furthermore, the cavity 352 be formed so that it completely over the passivation layer 330 is arranged (not shown). In this case, the cavity 352 be positioned so that it does not over the chip termination area 320 is arranged (not shown).

The wall 354 the connection structure 350 may have an outer diameter in a range of about 70 microns to about 160 microns, optionally in a range of about 90 microns to about 140 microns, optionally in a range of about 110 microns to about 120 microns. This can be the wall 354 the connection structure 350 a thickness in a range of about 5 microns to about 15 microns, optionally in a range of about 7 microns to about 13 microns, optionally in a range of about 9 microns to about 11 microns.

This allows the cavity 352 For example, have a radius in a range of about 20 microns to about 70 microns, optionally in a range of about 30 microns to about 60 microns, optionally in a range of about 40 microns to about 50 microns.

The cavity 352 may in various embodiments have a depth d1 which is greater than the depth d2 of the opening 332 in the passivation layer 330 , The cavity 352 may have a depth d1 in a range of about 10 μm to about 30 μm, optionally in a range of about 15 μm to about 25 μm, optionally in a range of about 18 μm to about 23 μm.

Here, the ratio of the thickness of the wall 354 to the depth of the cavity 352 in a range of about 0.3 to about 0.7, optionally from about 0.4 to about 0.6. In addition, the ratio of the thickness of the wall 354 to the thickness of the soil in a range of about 1.5 to about 2.5, optionally in a range of about 1.7 to 2.0.

The wall 354 the connection structure 350 Further, it may have a height in a range of about 10 μm to about 30 μm, optionally in a range of about 15 μm to about 25 μm, optionally in a range of about 18 μm to about 22 μm.

The connection structure 350 may be arranged in various embodiments such that at least part of the connection structure 350 on the passivation layer 330 is arranged. The wall 354 the connection structure 350 may be arranged such that at least a portion of the wall 354 on the passivation layer 330 is localized. The wall 354 may be arranged such that it the chip connection area 320 surrounds and completely on the passivation layer 330 is arranged, optionally the wall 354 the opening 332 the passivation layer 330 completely encloses. In other words, the opening 332 the passivation layer 330 completely inside the wall 354 be arranged. In other words, the opening can be 332 the passivation layer 330 completely below the ground 356 be arranged. In other words, the opening can be 332 completely below the cavity 352 the connection structure 350 be arranged.

The connection structure 350 For example, in various embodiments, at least one of the group consisting of copper, nickel, palladium, nickel-palladium, gold and nickel-palladium-gold may comprise or be substantially formed.

In various embodiments, the connection structure 350 have a copper structure coated with a nickel-palladium layer in a thickness of about 3 μm. In various embodiments, the connection structure 350 have a copper structure coated with a palladium layer in a thickness of about 300 nm. In various embodiments, the connection structure 350 have a copper structure coated with a gold layer in a thickness of about 50 nm. In various embodiments, the connection structure 350 have a copper structure which is coated with a nickel-palladium-gold layer in a thickness of less than 3 microns.

According to various embodiments, the chip arrangement 300 furthermore, a substrate 340 (hereinafter also referred to as chip array substrate 340 designated).

The substrate 340 may comprise at least one of, for example, polyimide, polyester or other thermoplastic materials, fiber-reinforced epoxies or other thermoset materials or may consist essentially of any of these materials or a blend thereof. Alternatively, the substrate may include or consist essentially of, for example, at least one of the group consisting of silicon, silicon carbide, germanium, gallium phosphide, gallium arsenide, and gallium nitride.

The substrate 340 For example, in various embodiments, a substrate termination region may be included 342 exhibit. The substrate 340 For example, in various embodiments, a plurality of substrate connection areas 342 exhibit. The substrate connection area 342 may be formed in various embodiments as a substrate connection. Furthermore, the substrate connection area 342 be formed in various embodiments as a connection pad. The substrate connection area 342 may be formed in various embodiments further as a substrate line.

The substrate connection area 342 For example, aluminum, copper, nickel, nickel-phosphorus, nickel-palladium-gold, nickel-gold or nickel-iron alloys, or may consist essentially of one of these materials or a mixture thereof. The substrate terminal region may have an area in a range of approximately 200 .mu.m.times.200 .mu.m.

The substrate 340 may in various embodiments of the chip arrangement 300 be arranged such that it is the chip body 310 is arranged opposite. The substrate 340 can also be arranged such that at least one wall 356 the connection structure 350 on an area of the substrate terminal area 342 is arranged. The substrate 340 may be arranged such that at least one wall 356 the connection structure 350 the substrate connection area 342 contacted. Furthermore, the substrate 340 in the chip arrangement 300 be arranged such that the electromechanical connection structure 350 the chip connection area 320 with the substrate connection area 342 electrically conductive connects.

4A and 4B show enlarged schematic perspective views of a connection structure of a chip arrangement according to various embodiments.

As in the view 400 of the 4A shown, may be an electromechanical connection structure 450 a chip arrangement be formed such that it has a cavity 452 has, as already described above. The connection structure 450 For example, it may be configured to include a floor (not shown) and a wall 454 having. The wall 454 the connection structure 450 may be formed so that they (not shown) together with the bottom of the cavity 452 forms.

As in 4A shown, the wall can be 454 be formed, for example, annular. In other words, the wall can 454 be formed such that the cavity 452 is completely enclosed in the direction of its circumference. In other words, the wall can be 454 and the bottom (not shown) may be barrel-shaped, ie they may be the cavity 452 like a barrel.

In this case, the connection structure 450 in various embodiments may be configured to have a diameter in a range of about 50 μm to about 150 μm, optionally in a range of about 70 μm to about 140 μm, optionally in a range of about 100 μm to about 120 μm.

The connection structure 450 For example, at least one of the group consisting of copper, nickel, palladium, nickel-palladium, gold, nickel-palladium-gold, and nickel-phosphorus-palladium-gold may comprise or may be formed substantially therefrom.

In various embodiments, the connection structure 450 have a copper structure coated with a nickel-palladium layer in a thickness of about 3 μm. The connection structure 450 For example, it may have a copper structure coated with a palladium layer in a thickness of about 300 nm. Furthermore, the connection structure 450 have a copper structure coated with a gold layer in a thickness of about 50 nm. The connection structure 450 may have a copper structure which is coated with a nickel-palladium-gold layer in a thickness of less than 3 microns.

The bottom (not shown) of the connection structure 450 For example, it may have a thickness in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm.

The wall 454 the connection structure 450 may have an outer diameter in a range of about 70 microns to about 160 microns, optionally in a range of about 90 microns to about 140 microns, optionally in a range of about 110 microns to about 120 microns. This can be the wall 454 the connection structure 450 a thickness in a range of about 5 μm to about 15 μm, optionally in a range of about 7 μm to about 13 μm, optionally in a range of about 9 μm to about 11 μm.

This allows the cavity 452 For example, have a radius in a range of about 20 microns to about 70 microns, optionally in a range of about 30 microns to about 60 microns, optionally in a range of about 40 microns to about 50 microns.

Besides, the wall can 454 the connection structure 450 a height in a range of about 10 μm to about 30 μm, optionally in a range of about 15 μm to about 25 μm, optionally in a range of about 18 μm to about 22 μm.

As in the view 405 of the 4B shown, may be an electromechanical connection structure 450 a chip arrangement be formed such that it has a cavity 452 has, as already described above. The connection structure 452 For example, it may be configured to include a floor (not shown) and a wall 454 having. The wall 454 the connection structure 450 For example, it may be formed such that it together with the bottom (not shown) the cavity 452 forms.

In this case, the connection structure 450 in various embodiments may be configured to have a diameter in a range of about 50 μm to about 150 μm, optionally in a range of about 70 μm to about 140 μm, optionally in a range of about 100 μm to about 120 μm.

The connection structure 450 For example, at least one of the group consisting of copper, nickel, palladium, nickel-palladium, gold, nickel-palladium-gold, and nickel-phosphorus-palladium-gold may comprise or may be formed substantially therefrom.

In various embodiments, the connection structure 450 have a copper structure coated with a nickel-palladium layer in a thickness of about 3 μm. The connection structure 450 For example, it may have a copper structure coated with a palladium layer in a thickness of about 300 nm. Furthermore, the connection structure 450 have a copper structure coated with a gold layer in a thickness of about 50 nm. The connection structure 450 may have a copper structure coated with a nickel-palladium-gold layer in a thickness of less than 3 microns.

The bottom (not shown) of the connection structure 450 For example, it may have a thickness in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm.

As in 4B shown, the wall can be 454 for example, be formed segmented. In other words, the wall can 454 be formed such that they have a plurality of segments 458 or sections 458 having. For example, the wall 454 be formed so that it has four segments 458 having. For example, the wall 454 be formed such that the sections 458 and gaps 459 between the sections 458 evenly distributed. In other words, the sections 458 and the gaps 459 be the same size, ie, for example, have an equal length or each occupy a same arc. In other words, the wall can be 454 in the view 405 be formed as a segmented barrel wall.

The wall 454 the connection structure 450 may have an outer diameter in a range of about 70 microns to about 160 microns, optionally in a range of about 90 microns to about 140 microns, optionally in a range of about 110 microns to about 120 microns. This can be the wall 454 the connection structure 450 a thickness in a range of about 5 μm to about 15 μm, optionally in a range of about 7 μm to about 13 μm, optionally in a range of about 9 μm to about 11 μm.

This allows the cavity 452 For example, have a radius in a range of about 20 microns to about 70 microns, optionally in a range of about 30 microns to about 60 microns, optionally in a range of about 40 microns to about 50 microns.

Besides, the wall can 454 the connection structure 450 a height in a range of about 10 μm to about 30 μm, optionally in a range of about 15 μm to about 25 μm, optionally in a range of about 18 μm to about 22 μm.

By training the wall 454 in segments according to an embodiment, as in FIG 4B can be ensured that in the FCOS assembly of the chip assembly air through the gaps 459 between the wall sections 458 through from the cavity 452 can escape, leaving the entire cavity 452 filled with adhesive (not shown). As a result, a higher mechanical stability of the chip arrangement can be achieved.

It should be noted that in all of the embodiments described in this application, the wall of the connection structure can be designed as an annular closed wall or divided into sections, even if this is not expressly mentioned in the description of each embodiment shown in the figures ,

5 FIG. 12 shows a flowchart of a method of manufacturing a chip device according to various embodiments.

As in 5 According to various embodiments, a method of manufacturing a chip arrangement may include: forming an opening in at least one passivation layer that is partially disposed adjacent a chip termination region of a chip body such that at least a portion of the chip termination region is exposed 510; Forming an electromechanical connection structure between the chip connection region and a substrate connection region of a substrate, which has a cavity inside, such that at least one wall of the connection structure is arranged on the passivation layer and on the substrate connection region, wherein the cavity has a depth greater than a depth of the opening, 520; and Fixing the electromechanical connection structure such that the chip connection region and the substrate connection region are connected to one another in an electrically conductive manner 530.

In this case, in the method for producing a chip arrangement, the electromechanical connection structure may be, for example, a flip-chip connection structure.

In the method of manufacturing a chip assembly, forming the interconnect structure may include at least the sub-processes of forming a bottom and forming at least one wall. In other words, the connection structure can be formed in a plurality of partial processes, wherein the bottom of the connection structure is formed in one partial process and the wall of the connection structure is formed in a further partial process. The wall of the connection structure can be formed annularly, for example. Furthermore, the wall of the connection structure can be formed segmented. In this case, the wall can be formed such that it is segmented, for example, into four sections. For example, the sections and gaps between the sections may be arranged to be evenly distributed or, for example, may be arranged to be unevenly distributed. In other words, the portions of the segmented wall and the gaps may be made equally large or may be formed as portions of the wall with narrow slots therebetween.

The chip body may include a chip body substrate. In addition, the chip body may, for example, have structures that at least partially comprise or may be formed substantially from a material having a dielectric constant that is less than 3.9. In other words, the structures of the chip body may include or be formed substantially from a material having a dielectric constant less than 3.9. Alternatively, the structures of the chip body may include or may be formed substantially of a material having a dielectric constant less than 2.4.

6 shows a schematic representation of steps for forming the connection structure in various embodiments of the method.

In various embodiments of the method, forming the interconnect structure as in FIG 6 represented, the sub-processes 601 to 609 exhibit. It should be noted that in 6 merely represents and describes the principle of the manufacturing process of a connection structure. That means that related to 6 not all sub-processes for producing the connection structure are shown and described. The subprocesses presented here are explained in order to provide a basic understanding of the method. However, to simplify the illustration in 6 Subprocesses of the manufacturing process have been omitted.

In 601 becomes a passivation layer 630 on a chip body 610 , which has a chip connection area 620 formed, wherein the passivation layer 630 over the chip connection area 620 an opening 632 having. The opening can be 632 in the passivation layer 630 be formed so that they at least a part of the chip connection area 620 exposes.

In this case, the passivation layer 630 , the chip body 610 , the chip connection area 620 and the opening 632 For example, have the materials and are formed in the dimensions, as described in connection with other figures, for example, in connection with the passivation layer 330 , the chip body 310 , the chip connection area 320 and the opening 332 of the 3 ,

When making the opening 632 in the passivation layer 630 can the size of the opening 632 in the passivation layer 630 be chosen such that they the size of the contact surface between the connection structure and the chip connection area 620 Are defined. In other words, the opening 632 in the passivation layer 630 be formed so that a sufficiently large contact area between the connection structure and the chip connection area 620 can be provided.

The opening can be 632 have a diameter in a range of about 10 μm to about 70 μm, optionally in a range of about 20 μm to about 60 μm, optionally in a range of about 30 μm to about 45 μm. In addition, the depth (d2 in 3 ) of the opening 623 in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm.

In 602 of the 6 becomes a germ layer 631 on the passivation layer 630 and in the opening 632 the passivation layer 630 formed such that at least the passivation layer 630 and the one by means of the opening 632 uncovered area of the chip connection area 620 from the germ layer 631 is covered.

The seed layer deposited in 602 631 can be applied, for example, by sputtering or by PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition). The germ layer 631 For example, it can be formed from a thin barrier layer, such as titanium-tungsten (TiW) as a diffusion barrier and additionally copper as the substantially conductive layer for electroplating or titanium nitride as a diffusion barrier and additionally copper as the substantially conductive layer for electroplating. In this case, the germ layer 631 in a thickness in a range of about 50 nm for the diffusion barrier, and in a thickness in a range of about 100 nm to about 300 nm for the copper layer.

In 603 becomes a first mask layer 633 over the germ layer 631 educated. The first mask layer 633 can be formed, for example, by a first resin layer on the seed layer 631 is deposited and patterned, such that the first mask 633 is formed. Here, the first mask 633 be formed such that portions of the seed layer 631 be exposed. Furthermore, the first mask 633 be formed such that the first resin layer has a gap over the chip connection region 620 and over one to the chip connection area 620 adjacent area of the passivation layer 630 having. In other words, the first mask 633 the germ layer 631 on the chip connection area 620 and on to the chip connection area 620 adjacent areas of the passivation layer 630 is arranged, uncover. In other words, the first mask 633 the germ layer 631 over the opening 632 the passivation layer 630 and over to the opening 632 adjacent areas of the passivation layer 630 uncover.

The first resin layer may be formed by, for example, depositing photosensitive paints. The first resin layer may be deposited by spin-on (spin-on-wafer), dry-film lamination, printing or spraying. The first resin layer may be for forming the first mask 633 For example, be structured by photolithography, laser irradiation or direct production by structured printing.

Alternatively, the germ layer 631 also in a sub-process after forming the mask 633 be formed, such that the seed layer 631 also on the side walls of the first mask 633 is deposited.

As in further 6 For example, at 604, a first copper layer is formed 653 on the areas of the germ layer 631 not from the first mask 633 covered, formed. In this case, for example, the first copper layer 653 on the areas of the germ layer 631 deposited by the first mask 633 are exposed. In other words, the first copper layer 653 over the chip connection area 620 and over to the chip connection area 620 adjacent areas of the passivation layer 630 deposited. Alternatively, instead of the first copper layer 653 a first layer 653 of gold, nickel or nickel-phosphorous on the exposed areas of the chip body 610 deposited.

The deposition of the first copper layer 653 can be done, for example, by plating copper material. The deposition of the first copper layer 653 can also be done, for example, galvanic or chemical. The formation of the first copper layer 653 may also include forming a redistribution layer. The formation of the first copper layer 653 may further include underbump metallization (UBM) metallization. The first copper layer 653 can be formed such that it the chip connection area 620 in the opening 632 the passivation layer 630 electrically conductive contacted. The first copper layer 653 can also be formed so that they the ground 656 forms the electromechanical connection structure.

For this, the first copper layer 653 for example, in a thickness in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm.

In 605 of the 6 is the structured first resin layer, which is the first mask 633 forms, removed. In this case, the first resin layer can be removed, for example, by means of stripping by means of chemicals or a plasma process or by ashing.

In addition, 605 becomes a second mask layer 635 or a second mask 635 formed on the chip body. The second mask layer 635 can be formed, for example, by a second resin layer on the chip body 610 , which is the passivation layer 630 , the germ layer 631 and the first copper layer 653 has formed. It can the second mask 635 be formed such that portions of the first copper layer 653 be exposed. Furthermore, the second mask 635 be formed such that the second resin layer has a gap over the to the chip connection area 620 adjacent areas of the passivation layer 630 has, wherein the gap may be annular. In other words, the second mask 635 be formed such that the first copper layer 653 via the to the chip connection area 620 adjacent areas of the passivation layer 630 is exposed. In other words, the second mask 635 over the chip connection area 620 be formed so that they over the chip connection area 620 has no gap. That is, portions of the second resin layer in forming the second mask 635 remain so that the first copper layer 653 over the chip connection area 620 not exposed.

The second resin layer 635 can be formed, for example, by means of deposition of photosensitive paints. The second resin layer 635 For example, it may be deposited by a spin-on process (spin-on-wafer), a dry film lamination, a printing process, or a spray process. The second resin layer may be used to form the second mask 635 For example, be structured by means of photolithography or irradiation with laser light.

In 606 of the 6 becomes a second copper layer 657 on the areas of the chip body 610 not from the second mask 635 covered, formed. For example, a second copper layer 657 on the areas of the first copper layer 653 deposited by (in other words, by means of) the second mask 635 are exposed. The deposition of the second copper layer 657 can be done, for example, by plating copper material. The deposition of the second copper layer 657 can be done for example by means of electroplating or chemically (electroless).

Alternatively, a second layer 657 made of gold, nickel or nickel-phosphorous on the not of the second mask 635 covered, ie on the exposed areas of the chip body 610 , isolated.

The second copper layer 657 can be formed such that it the first copper layer 653 electrically conductive contacted. The second copper layer 657 can also be formed such that it the wall 654 forms the electromechanical connection structure. The second copper layer 657 can be formed so that it is higher than the depth of the opening 632 in the passivation layer 630 , In other words, the second copper layer 657 be formed such that a wall formed thereby 654 the connection structure is higher than the depth of the opening 632 , The wall 654 The connection structure can be formed annular or segmented. The wall 654 may be formed to substantially over the passivation layer 630 is arranged.

The wall 654 The interconnect structure may be formed to have an outer diameter in a range of about 70 μm to about 160 μm, optionally in a range of about 90 μm to about 140 μm, optionally in a range of about 110 μm to about 120 μm having. Besides, the wall can 654 of the connecting structure are formed in a thickness in a range of about 5 μm to about 15 μm, optionally in a range of about 7 μm to about 13 μm, optionally in a range of about 9 μm to about 11 μm. Furthermore, the wall can 654 of the interconnect structure at a height in a range of about 10 μm to about 30 μm, optionally in a range of about 15 μm to about 25 μm, optionally in a range of about 18 μm to about 22 μm.

As in 6 When forming the connection structure in FIG. 607, the second resin layer forming the second mask is formed 635 forms, removed. In this case, the second resin layer can be removed, for example, by means of stripping by means of chemicals or by means of a plasma process or by ashing. The first copper layer 653 and the second copper layer 657 can when removing the second mask layer 635 persist in such a way that they cover the ground 656 , the wall 654 and the cavity 652 the connection structure 650 form. It can reduce the depth of the cavity 652 greater than the depth of the opening 632 in the passivation layer 630 ,

As described above in connection with other embodiments, the cavity may 652 characterized in that it has, for example, a radius in a range of about 20 microns to about 70 microns, optionally in a range of about 30 microns to about 60 microns, optionally in a range of about 40 microns to about 50 microns.

In 608 of in 6 The method shown is the seed layer 631 away. In this case, the germ layer 631 be removed by chemical etching or by a plasma process. In this case, the germ layer 631 be removed in exposed areas. In this case, the germ layer 631 that under the first copper layer 653 is arranged to be preserved. In other words, that can be under the ground 656 the connection structure 650 arranged germ layer 631 remain.

In 609 of the 6 becomes a coating 651 on the connection structure 650 educated. In this case, the coating 651 be applied for example by means of chemical deposition (elektroless).

The application of the coating 651 on the connection structure 650 can by means of separation for example, one of the group consisting of nickel, palladium, nickel-palladium, gold and nickel-phosphorus-palladium-gold on the first copper layer 653 and the second copper layer 657 be deposited. In other words, the coating may be deposited by depositing, for example, one of the group of nickel, palladium, nickel-palladium, gold and nickel-phosphorus-palladium-gold on the bottom 656 and the wall 654 the electromechanical connection structure 650 be deposited.

This may be the type of coating 651 in other words, the coating material of the layer 651 , are selected based on the particular requirements of a specific chip arrangement, for example, to increase the corrosion resistance of the connection structure 650 or as a diffusion barrier. A typical coating 651 can be done, for example, by means of ENIG coating or by ENEPIG coating, ie by chemical deposition of nickel and subsequent gold immersion (Electroless Nickel - Immersion Gold) or chemical deposition of nickel, subsequent chemical deposition of palladium and subsequent gold Immersion (Electroless Nickel - Electroless Palladium - Immersion Gold).

In this case, in 609, those for forming the connection structure 650 formed first copper layer 653 and second copper layer 657 form a copper structure, wherein in various embodiments, the copper structure with a nickel-palladium layer 651 coated in a thickness of about 3 microns. In various embodiments, the copper structure with a palladium layer 651 be coated in a thickness of about 300 nm. Alternatively, the copper structure in various embodiments with a gold layer 651 coated in a thickness of about 50 nm. Furthermore, the copper structure in various embodiments with a nickel-palladium-gold layer 651 be coated in a thickness of less than about 3 microns.

In an alternative method, after forming the connection structure 650 an additional passivation layer (not shown) on the surface of the chip body 610 such that the additional passivation layer (not shown) forms part of the cavity 652 fills the connection structure. For this purpose, for example, a polyimide layer as an additional passivation layer on the chip body 610 be formed.

It should be noted that the list of said materials of all elements described is not exhaustive, but other materials may be used if their use makes sense.

7 shows a schematic representation of two sub-processes of the FCOS assembly of the method according to various embodiments.

As in 7A In Figure 700, the FCOS assembly becomes a chip body 710 as he is in 2 and 3 is shown and described and the one with a chip connection area 720 , a passivation layer 730 and an electromechanical connection structure 750 is equipped with the flip chip on a substrate 740 applied, being on the substrate 740 a substrate connection area 742 is arranged. In other words, the one with the chip connection area 720 , the passivation layer 730 and the connection structure 750 provided chip body 710 such on the substrate 740 applied that connection structure 750 the substrate connection area 742 of the substrate 740 touched.

In an in 7B presented sub-process 705 the FCOS assembly becomes the chip body 710 and the substrate 740 pressed together so that the connection structure 750 an electrically conductive connection to the substrate connection area 742 forms. In this case, the chip body 710 and the substrate 740 be pressed against each other with a pressure such that the connection structure 750 is deformed. In other words, the at least one wall 754 the connection structure 750 by means of the applied pressure during compression of the chip body 710 and the substrate 740 be deformed. It can at the the substrate connection area 742 facing sides of the wall 754 a deformation 755 (in other words, a deformation 755 ) occur.

By means of deforming the wall 754 in other words, by means of the occurrence of deformations 755 (in other words, the deformations 755 ) may be present height differences of possibly on the entire surface of the chip body 710 arranged plurality of connection structures 750 be compensated. This is due to the occurrence of deformations 755 ensures that by means of connecting structures 750 over the entire surface of the chip body 710 a secure electrical connection between the chip connection area 720 of the chip body 710 and the substrate connection area 742 of the substrate 740 is trained.

Like from the 7B can be seen, according to the present embodiments, a connecting structure 750 be provided, in which the compression of the chip body 710 and the substrate 740 during FCOS mounting, pressure can be distributed substantially to areas outside of the die pad area. In other words, when applying a force during FCOS mounting on the chip body 710 and the substrate 740 at least part of this force by means of the wall 754 the electromechanical connection structure 750 from the chip connection area 720 be routed away.

As stated above, the cavity can 752 a depth d1 (see 3 ), which is greater than the depth d2 (see 3 ) of the opening in the passivation layer 730 , whereby it can be ensured that when compressing the chip body 710 and the substrate 740 no pressure on the chip connection area 720 and the underlying portions of the chip body substrate is applied. This can further ensure that low-k materials or ULK materials in the chip body substrate are not damaged.

In this case, the deformability of the wall material, for example by means of the thickness of a coating (for example, the coating 651 out 6 ) are adjusted such that the deformability of the wall 754 to compensate for any height differences is guaranteed.

In further embodiments, it may not be necessary that deformations 755 at the substrate connection area 742 facing sides of the wall 754 (or the wall segments 754 ) occur during the FCOS assembly subprocess. In specific applications, it may be possible to deform 755 omitted, for example, in the 2-contact antenna mounting, in which only one LA and one LB contact are needed.

The substrate 740 can be provided with an adhesive (not shown) during FCOS assembly, wherein the interconnect structure 750 through the adhesive (not shown) to the substrate connection area 742 can be contacted. The adhesive (not shown) may be a thermal adhesive that is cured by heat or may be a UV-curing adhesive. By providing the adhesive (not shown) after curing, a reliable and stable mechanical connection between the chip body 710 and the substrate 740 be guaranteed. In other words, the electromechanical connection structure 750 a reliable electrical connection between the chip connection area 720 and the substrate connection area 742 and a reliable mechanical connection between the chip body 710 and the substrate 740 ensure that is stabilized by the adhesive (not shown).

8th shows an enlarged schematic representation of an FCOS assembly sub-process of the method according to various embodiments. More specifically shows 8th an enlarged schematic representation of the second sub-process of the FCOS assembly according to the method for producing a chip arrangement in various embodiments.

At the in 8th shown second sub-process of FCOS assembly of the chip assembly 700 can the chip body 810 and the substrate 840 with a force F1 be pressed against each other. In this case, the chip body 810 a chip connection area 820 , a passivation layer 830 and an electromechanical connection structure 850 while the substrate 840 a substrate connection area 842 can have. The chip body 810 and the substrate 840 can be pressed onto each other in such a way that the connection structure 850 the chip connection area 820 and the substrate connection area 842 can connect electrically conductive. As related to above 7B described, while the substrate 840 an adhesive (not shown) through which the connection structure 850 the substrate connection area 842 contacted, whereby after curing of the adhesive mechanical stability of the chip assembly 800 can be guaranteed.

The connection structure 850 can in the chip arrangement 800 according to the illustrated embodiment, a floor 856 such that over the chip connection area 820 may be arranged to contact this electrically conductive. Furthermore, the connection structure 850 a wall 854 have in one to the chip connection area 820 adjacent area above the passivation layer 830 can be arranged. The chip body 810 and the substrate 840 can be pressed onto each other in this assembly sub-process such that at least one wall 854 or part of the wall 854 on the substrate connection area 842 is pressed.

When compressing the chip body 810 and the substrate 840 with the power F1 can be a force F2 on the wall 854 the connection structure 850 Act. The power F2 can at the passivation layer sites 830 and the substrate connection area 842 act on which the wall 854 on the passivation layer 830 and pushes the substrate connection area. This can be the wall 854 by means of force F2 such on the substrate connection area 842 of the substrate 840 and the passivation layer 830 of the chip body 810 pressed be that deformation 855 on the wall 856 is trained. As already stated above, by means of the deformation 855 Height differences that occur over the entire surface of the elements to be contacted across, can be compensated. For example, the deformations 855 the Wall 854 Height differences between different connection structures 850 the plurality of connection structures 850 Balancing over the chip body. Thereby, by means of the connection structure 850 a stable and secure mechanical and electrical connection of the chip body 810 with the substrate 840 be guaranteed.

Furthermore, during compression of the chip body 810 and the substrate 840 with the power F1 in the cavity 852 the connection structure one on the ground 856 the connection structure 650 Acting force F3 occur. The power F3 may be due to the specific arrangement of the soil 856 and the wall 854 the connection structure 850 that the cavity 852 form, occur. It can be when squeezed on the wall 854 Acting force F2 cause in that with the chip connection area 820 connected ground 856 the connection structure 850 a torque M occurs. Possible locations of the occurrence of the torque M are in the 8th marked by asterisks.

By the occurrence of the torque M in the ground 856 the connection structure 850 Further, in the chip connection area 820 contacting area of the soil 856 a force F3 occur. The power F3 can due to the occurring torque M in the direction of the cavity 852 be directed. In other words, that can be on the ground 856 the connection structure 850 Acting force F3 as tensile stress, in the direction of the cavity 852 the connection structure 850 is directed, act. The appearance of the force F3 This can be due to the special structure of the connection structure 850 be allowed, whose cavity 852 has a greater depth than the depth of the over the chip connection area 820 provided opening in the passivation layer 830 (S. 3 ).

In this case, the cavity 852 As noted above, in various embodiments, a depth d1 (see 3 ), which is greater than a depth d2 (see 3 ) of the opening in the passivation layer 830 , The cavity 852 For example, the depth d1 may range from about 10 microns to about 30 microns, optionally ranging from about 15 microns to about 25 microns, optionally ranging from about 18 microns to about 23 microns. The aperture may further have the depth d2 in a range of about 3 μm to about 10 μm, optionally in a range of about 4 μm to about 8 μm, optionally in a range of about 5 μm to about 7 μm. This can ensure that when compressing the chip body 810 and the substrate 840 no pressure on the chip connection area 820 and the underlying portions of the chip body substrate is applied. This can further ensure that low-k materials or ULK materials in the chip body substrate are not damaged.

In other words, by means of the specific configuration of the connection structure 850 in the chip arrangement 800 Accordingly, according to various embodiments, it is ensured that during the compression of the chip body 810 and the substrate 840 during FCOS mounting no pressure on the under the chip connection area 820 arranged areas of the chip body 810 be exercised. Therefore, in the chip arrangement 800 ensure that in the presence of low-k structures or ULK structures in the chip body (or the chip body substrate) no direct mechanical force in the direction of the under the chip connection area 820 arranged chip body substrate is applied. In other words, the particular embodiment of the connection structure described here 850 ensure that low-k or ulk structures in the chip body 810 will not be damaged during FCOS assembly due to applied pressure.

In contrast to the conventional pressure contact during FCOS assembly, due to the specific configuration of the connection structure 850 in the resulting chip arrangement 800 according to the present application in the area of the chip connection area 820 one of the sensitive chip body substrate of the chip body 810 gone force F3 occur. In other words, in the chip arrangement 800 according to various embodiments in the area of the chip connection area 820 one on the floor 856 acting tension F3 occur. The tension can be F3 from the chip connection area 850 away and towards the cavity 852 the connection structure 850 be directed.

As described above, the chip body becomes 810 and the substrate 840 pressed together so that an interposed adhesive (not shown) after curing stabilizes the mechanical connection. This means that after the curing of the adhesive (not shown) due to the specific configuration of the connection structure 850 in the finished chip arrangement 800 Even after the FCOS assembly still a tension can exist, the force F3 of the 8th equivalent.

9 FIG. 12 shows a flowchart of a method for producing a chip arrangement according to further various exemplary embodiments.

As in 9 1, a method of fabricating a chip device according to further embodiments may include: forming an opening in at least one passivation layer that is partially disposed adjacent a chip termination region of a chip body such that at least a portion of the chip termination region is exposed, 910; Forming an electromechanical connection structure between the chip connection region and a substrate connection region of a substrate, which has a cavity inside, such that at least one wall of the connection structure is arranged on the passivation layer and on the substrate connection region, wherein the cavity has a depth greater than a depth of the opening, 920; Applying a force to the electromechanical connection structure such that a torque is generated by means of the wall of the electromechanical connection structure in a region of the electromechanical connection structure that is in contact with the chip connection region, and that the chip connection region and the substrate connection region are electrically conductively connected, 930.

In this case, in the method for producing a chip arrangement, the electromechanical connection structure may be, for example, a flip-chip connection structure.

In the method of manufacturing a chip assembly, forming the interconnect structure may include at least the sub-processes of forming a bottom and forming at least one wall. In other words, the connection structure can be formed in a plurality of partial processes, wherein the bottom of the connection structure is formed in one partial process and the wall of the connection structure is formed in a second partial process. The wall of the connection structure can be formed annularly, for example. Furthermore, the wall of the connection structure can be formed segmented. In this case, the wall can be formed such that it is segmented into four or any other number of sections. For example, the portions and gaps between the portions may be arranged to be evenly distributed or unevenly distributed. In other words, the sections of the segmented wall and the gaps can be made equally large or the gaps between the sections of the segmented wall can be formed as narrow slots.

For example, the chip body may include structures that may be at least partially formed of a material that has a dielectric constant that is less than 3.9. In other words, structures in the chip body may include or be formed substantially from a material having a dielectric constant less than 3.9. Alternatively, the structures in the chip body may include or be formed substantially from a material having a dielectric constant less than 2.4.

10 shows an enlarged schematic perspective view of a connection structure of a chip arrangement with a redistribution layer according to various embodiments.

In the in 10 displayed view 1000 can be a first page 1016 a chip body 1010 a chip connection area 1020 and a connection structure 1050 have, wherein the connection structure 1050 not above the chip connection area 1020 is arranged. In other words, the connection structure 1050 on another area of the chip body 1010 be arranged as the chip connection area 1020 ,

For contacting the connection structure 1050 with the chip connection area 1020 can the chip body 1010 therefore, as in 10 also shown a redistribution layer 1070 (in other words, a redistribution layer (RDL) 1070) overlying the first page 1016 of the chip body 1010 is arranged such that it the chip connection area 1020 with the connection structure 1050 electrically conductive connects. In other words, on the first page 1016 of the chip body 1010 a redistribution layer 1070 be formed with the chip connection area 1020 and the connection structure 1050 can be connected. In this case, the rewiring layer 1070 be formed such that they the chip connection area 1020 contacted through the opening (not shown) in the passivation layer (not shown). Furthermore, the floor can 1056 the connection structure 1050 in a layer with the redistribution layer 1070 be educated. The wall 1054 or the wall segments 1058 The connection structure may be designed such that it is above the passivation layer (not shown) on the first side of the chip body 1010 is arranged or are.

11 11 shows enlarged views of a smart card IC having a plurality of interconnect structures (in other words, a plurality of crown bumps) according to various embodiments.

As in the left part of the 11 shown has a smart card IC 1180 (ie, a smart card integrated circuit) a chip body 1110 and a plurality of connection structures 1150 in other words, a plurality of crown bumps 1150 , According to various embodiments. Here are the majority of connection structures 1150 on the chip body 1110 typically arranged at a distance from each other for FCOS mounting.

In the right part of the 11 is an enlarged detail view of a connection structure 1150 of the chip card IC 1180 shown. In other words, an enlarged detail view of a crown bump 1150 on the chip card IC 1150 shown. Here are in 11 connecting structures 1150 shown having a segmented wall. However, the configuration of the connection structures 1150 not limited thereto, but the connection structures 1150 may also have an annular closed wall (not shown). The connection structures 1150 can also, as in 11 represented according to their function on the chip card IC 1180 be labeled.

A chip card IC 1180 , as in 11 can be provided for the chip card security control for mounting in the FCOS assembly. Furthermore, adjustments to the arrangement of the connection structures 1150 on the chip card IC 1180 to the respective application possible. For example, it may be necessary to have individual connection structures 1150 on the chip card IC 1180 to connect with each other. In other words, a chip body 1110 also with an interconnect or a plurality of interconnects (not shown) between interconnect structures 1150 be provided, for example, in the bare chip assembly (English: bare the assembly), for example in the application at ePassports, eDriverLicense etc.

An electromechanical interconnect structure for a chip assembly intended for FCOS mounting in which the interconnect structure has a cavity of sufficient depth has the following advantages: When applying force during FCOS assembly, the pressure acts on the wall or wall segments the connection structure such that a good electrical connection to the substrate connection region of the chip body oppositely arranged substrate can be ensured. In this case, however, no pressure is exerted on the bottom of the connection structure, which is arranged on the chip connection region and / or electrically conductively connected to it, such that sensitive low-k or ULK structures in the chip body under the chip connection region are protected from damage.

Due to the specific configuration of the wall and the bottom of the connection structure, by means of the forces acting on the wall, torques can occur in the bottom of the connection structure such that a tensile force acts on the region of the base connected to the chip connection region. As a result, brittle low-k or ULK structures in the chip body can be protected from damage.

Further, upon compression of the chip body and the substrate during FCOS mounting, the wall of the interconnect structure may redirect the applied pressure to the softer passivation layer adjacent to the die pad area, such that low-k or ULK structures in the chip body do not to be damaged.

Furthermore, the wall of the connection structure can be deformed during compression of the chip body and the substrate during the FCOS assembly by means of the applied pressure, whereby occurring differences in height of distributed on the surface of the chip body arranged plurality of connection structures can be compensated.

Furthermore, the bottom of the connection structure can ensure a reliable electrical connection to the chip connection region, while the wall of the connection structure ensures a reliable electrical connection to the substrate connection region.

Claims (26)

Chip arrangement, comprising A chip body (310); At least one chip connection region (320); At least one passivation layer (330) partially adjacent to the die pad region (320), the passivation layer (330) having an opening (332) by which at least a portion of the die pad region (320) is exposed; A substrate (340) having a substrate attachment region (342); An electromechanical interconnect structure (350) having a cavity (352) therein, wherein at least one wall (354) of the interconnect structure (350) is disposed on the passivation layer (330) and on the substrate interconnect region (342) electromechanical connection structure (350) electrically connecting the chip termination region (320) to the substrate attachment region (342); Wherein the cavity (352) has a depth (d1) greater than a depth (d2) of the opening (332). Chip arrangement according to Claim 1 wherein the electromechanical connection structure (350) is a flip-chip connection structure. Chip arrangement according to Claim 1 or 2 wherein the wall (354) is annular. Chip arrangement according to one of Claims 1 to 3 wherein the chip body (310) has structures of a dielectric constant less than 3.9. Chip arrangement according to one of Claims 1 to 4 wherein the chip body has structures of a dielectric constant less than 2.4. Chip arrangement according to one of Claims 1 to 5 wherein the chip body comprises a chip body substrate, wherein the chip body substrate comprises or substantially consists of one of the group consisting of silicon, silicon carbide, germanium, gallium phosphide, gallium arsenide and gallium nitride. Chip arrangement according to one of Claims 1 to 6 wherein the passivation layer (330) comprises or consists essentially of one of the group consisting of polyimide, polybenzoxazole (PBO), silicon nitride and silicon dioxide. Chip arrangement according to one of Claims 1 to 7 wherein the interconnect structure (350) comprises, or consists essentially of, at least one of copper, nickel, palladium, nickel-palladium, gold, nickel-palladium-gold, and nickel-phosphorus-palladium-gold. Chip arrangement according to one of Claims 1 to 8th wherein the connection structure (350) has a diameter in a range of about 50 μm to about 150 μm, optionally in a range of about 70 μm to about 140 μm, optionally in a range of about 100 μm to about 120 μm. Chip arrangement according to one of Claims 1 to 9 wherein the chip body (1010) further comprises a redistribution layer (1070) connected to the chip termination region (1020). A method of manufacturing a chip device comprising the method Forming an opening (332) in at least one passivation layer (330) that is partially disposed adjacent a chip termination region (320) of a chip body (310) such that at least a portion of the chip termination region (320) is exposed (510) ; Forming an electromechanical interconnect structure (350) between the die pad region (320) and a substrate pad region (342) of a substrate (340) having a void (352) therein such that at least one wall (354) is the one Connecting structure (350) is arranged on the passivation layer (330) and on the substrate connection region (320) (520), Wherein the cavity (352) has a depth (d1) greater than a depth (d2) of the opening (332); and • Fixing the electromechanical connection structure (350), so that the chip connection region (320) and the substrate connection region (342) are electrically connected to each other (530). Method according to Claim 11 wherein the electromechanical connection structure (350) is a flip-chip connection structure. Method according to Claim 11 or 12 wherein the wall (354) is annular. Method according to one of Claims 11 to 13 wherein the chip body (310) has structures of a dielectric constant less than 3.9. Method according to one of Claims 11 to 14 wherein forming the interconnect structure (650) comprises: forming (602) a seed layer (631) on the passivation layer (630) and in the opening (632) such that at least a portion of the exposed portion of the chip termination region (620) is covered; Forming (604) a copper layer (653) over the seed layer (631); Forming (606) a copper structure (657) on the copper layer (653); Subsequent removal (608) of exposed areas of the seed layer (631). Method according to Claim 15 wherein the copper structure (657) is formed as a ring shape. Method according to one of Claims 11 to 16 wherein the chip body (310) has structures of a dielectric constant less than 3.9. Method according to one of Claims 11 to 17 wherein the chip body (310) has structures of a dielectric constant less than 2.4. Method according to one of Claims 11 to 18 wherein the substrate (340) comprises or consists essentially of one of the group consisting of polyimide, polyester, thermoplastic materials, fiber reinforced epoxies, or thermoset materials. Method according to one of Claims 11 to 18 wherein the substrate (340) comprises or consists essentially of one of the group consisting of silicon, silicon carbide, germanium, gallium phosphide, gallium arsenide and gallium nitride. Method according to one of Claims 11 to 20 wherein the passivation layer (330) comprises or consists essentially of one of the group consisting of polyimide, polybenzoxazole (PBO), silicon nitride and silicon oxide. Method according to one of Claims 11 to 21 wherein the interconnect structure (350) comprises, or consists essentially of, at least one of copper, nickel, palladium, nickel-palladium, gold, nickel-palladium-gold, and nickel-phosphorus-palladium-gold. Method according to one of Claims 11 to 22 wherein the connection structure (350) is formed in a diameter in a range of about 50 μm to about 150 μm. Method according to one of Claims 11 to 23 , further comprising: forming a redistribution layer (1070) on the chip body (1010) connected to the chip termination region (1020). Chip arrangement, comprising A chip body (810); • at least one chip connection area (820); At least one passivation layer (830) partially adjacent the chip termination region (820), the passivation layer (830) having an opening (832) by means of which at least a portion of the chip termination region (820) is exposed; A substrate (840) having a substrate attachment region (842); An electromechanical interconnect structure (850) having a cavity (852) therein, wherein at least one wall (854) of the interconnect structure (850) is disposed on the passivation layer (830) and on the substrate interconnect region (842) electromechanical connection structure (850) electrically connecting the chip termination region (820) to the substrate attachment region (842); Wherein a tensile stress exists in a portion of the electromechanical connection structure (850) in contact with the chip connection portion (820). A method of manufacturing a chip device comprising the method Forming an opening (832) in at least one passivation layer (830) disposed partially adjacent a chip termination region (820) of a chip body (810) such that at least a portion of the chip termination region (820) is exposed; Forming an electromechanical interconnect structure (850) between the die pad region (820) and a substrate pad region (842) of a substrate (840) having a void (852) therein such that at least one wall (854) is the one of the vias Connecting structure (850) is disposed on the passivation layer (830) and on the substrate connecting region (842); and Applying a force to the electromechanical connection structure (850) such that by means of the wall (854) of the electromechanical connection structure (850) in a region of the electromechanical connection structure (850) in contact with the chip connection region (820) Torque (M) is generated, and that the chip connection region (820) and the substrate connection region (842) are electrically connected to each other.

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