DE102017117802B4 - Semiconductor component and method - Google Patents

Abstract

Semiconductor device comprising:a substrate (123);a first RDL (131) over a first side (123U) of the substrate (123);one or more semiconductor dies (111, 113, 115) over the first RDL (131) are arranged and are electrically connected to it; an encapsulating material (133, 135) over the first RDL (131) and around the one or more semiconductor dies (111, 113, 115); terminals (125) which are on a second side (123L) of the substrate (123) opposite the first side (123U), the terminals (125) being electrically connected to the first RDL (131); anda polymer layer (129) on the second side (123L) of the substrate (123), wherein the connections (125) protrude from the polymer layer (129) over a first surface of the polymer layer (129) which is away from the substrate (123). is, wherein a first part of the polymer layer (129), which contacts the connections (125), has a first thickness (H4) and a second part of the polymer layer (129) between adjacent connections (125) has a second thickness (H3), which is smaller than the first thickness (H4).

Description

Background of the invention

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density is due to repeated reductions in the smallest feature width (e.g. shrinking the semiconductor process node to a sub-20 nm node), allowing more components to be integrated into a given area. As the demand for size reduction, higher speed and bandwidth, as well as lower power consumption and shorter delay time has become stronger, a need for more creative packaging methods for semiconductor dies has arisen.

As semiconductor technologies continue to advance, stacked and bonded semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits, such as logic, memory, processor circuits, and the like, are at least partially fabricated on separate substrates and then physically and electrically connected to form a functional device. Due to differences in the coefficients of thermal expansion (CTE) of different materials used in the stacked semiconductor device, deformation of the stacked semiconductor device may occur, which may affect the functionalities of the semiconductor device. If severe deformation of the semiconductor component is not compensated for, it can lead to component failure and/or negatively influence the yield of the semiconductor manufacturing process. A semiconductor device is off the record US 2012/0080786 A1 known. Other semiconductor devices are also known from the publications US 2012/0153498 A1 , US 2016/0148887 A1 , US 2016/0181218 A1 , US 2007/0020916 A1 or US 2014/0367867 A1 .

Brief description of the drawings

• Die 1A und 1B zeigen eine Draufsicht bzw. eine Schnittansicht eines Halbleiter-Bauelements gemäß einigen Ausführungsformen.
• 1C zeigt eine vergrößerte Darstellung eines Bereichs von 1B.
• 1D zeigt eine Schnittansicht eines Halbleiter-Bauelements gemäß einer Ausführungsform.
• Die 2A bis 2D zeigen Schnittansichten eines Halbleiter-Bauelements auf verschiedenen Herstellungsstufen gemäß einer Ausführungsform.
• Die 3A bis 3C zeigen Schnittansichten eines Halbleiter-Bauelements auf verschiedenen Herstellungsstufen gemäß einer Ausführungsform.
• 4 zeigt eine vergrößerte Darstellung eines Bereichs von 3C.
• Die 5A bis 5C zeigen Schnittansichten eines Halbleiter-Bauelements auf verschiedenen Herstellungsstufen gemäß einer Ausführungsform.
• 6 zeigt eine vergrößerte Darstellung eines Bereichs von 5C.
• 7 zeigt die Leistung eines Halbleiter-Bauelements gemäß einigen Ausführungsformen.
• 8 zeigt ein Ablaufdiagramm eines Verfahrens zur Herstellung eines Halbleiter-Bauelements gemäß einigen Ausführungsformen.

For a better understanding of the present invention and its advantages, the present invention will be described in more detail below in connection with the accompanying drawings.

• The 1A and 1B show a top view or a sectional view of a semiconductor component according to some embodiments.
• 1C shows an enlarged view of an area of 1B .
• 1D shows a sectional view of a semiconductor component according to an embodiment.
• The 2A until 2D show sectional views of a semiconductor component at various manufacturing stages according to one embodiment.
• The 3A until 3C show sectional views of a semiconductor component at various manufacturing stages according to one embodiment.
• 4 shows an enlarged view of an area of 3C .
• The 5A until 5C show sectional views of a semiconductor component at various manufacturing stages according to one embodiment.
• 6 shows an enlarged view of an area of 5C .
• 7 shows the performance of a semiconductor device according to some embodiments.
• 8th shows a flowchart of a method for producing a semiconductor component according to some embodiments.

Detailed description

The description below provides many different embodiments or examples for implementing various elements of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present invention. For example, as described below, fabrication of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements the second element can be designed so that the first and second elements are not in direct contact.

In addition, spatially relative terms, such as “located below”, “below”, “lower”/“lower”, “located above”, “upper”/“upper” and the like, can be used here for easy purposes Description of the relationship of an element or structure to one or more other elements or structures shown in the figures can be used. The spatially relative terms are intended to represent other orientations of the in. in addition to the orientation shown in the figures Component in use or in operation. The device can be oriented differently (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein can also be interpreted accordingly.

1A is a top view of a semiconductor device 100 according to some embodiments. In 1A a semiconductor die 111 is attached to a first side of a first substrate 123. One or more semiconductor dies (e.g., 113, 113A, 115, 115A) are attached to the first side of the first substrate 123 and adjacent to the semiconductor die 111. As in 1A As shown, the semiconductor die 111 is disposed over a central region of the first substrate 123, and the semiconductor dies 113, 113A, 115, and 115A are disposed over edge regions (e.g., regions near the outer boundaries) of the first substrate 123 arranged. The semiconductor dies 111, 113, 113A, 115 and 115A may be suitable dies such as logic dies, DRAM dies, SRAM dies, combinations thereof, or the like. The semiconductor dies 111, 113, 113A, 115, and 115A may be the same type of device (e.g., all dies may be DRAM dies), or alternatively, they may be different types of dies. For example, semiconductor die 111 may be a logic die, such as a system-on-chip (SoC) die, and semiconductor dies 113, 113A, 115, and 115A may be memory dies, such as HBM dies. This (HBM: High Bandwidth Memory), be. The semiconductor dies 111, 113, 113A, 115 and 115A may also include a stack of multiple dies. Alternatively, any suitable combination of semiconductor dies and any number of semiconductor dies may be used. It should be noted that for clarity, the underfill material 133 and the molding material 135 (see 1B) in 1A are not shown.

1B is a sectional view of the semiconductor device 100 along the line A - A of 1A . As in 1B As shown, the semiconductor device 100 has an interposer 150 comprising: a first substrate 123, a first redistribution layer (RDL) 131 on a first side 123U of the first substrate 123, external terminals 125 on a second side 123L of the first Substrate 123, and current paths 121 [e.g. B. electrically conductive paths, such as substrate vias (TSVs)] in the first substrate 123 that electrically connect the first RDL 131 to the external terminals 125.

The semiconductor dies 111, 113 and 115 (and the semiconductor dies 113A and 115A shown in the sectional view of 1B are not visible) are physically and electrically connected to the first RDL 131 via connectors (which may also be referred to as external contacts) 117 (e.g. 117A, 117B and 117C). An underfill material (which may also be referred to as an underfill) 133 may fill a gap between the semiconductor dies 111, 113 and 115 and the first RDL 131. As in 1B As shown, a molding material 135 is deposited over the first side 123U of the first substrate 123 and around the semiconductor dies 111, 113 and 115 and the underfill material 133. The underfill material 133 and the molding material 135 may be collectively referred to as an encapsulating material. In embodiments in which only the underfill material 133 or only the molding material 135 is used, the underfill material 133 or the molding material 135 may be referred to as an encapsulating material.

In 1B a polymer layer 129 is produced on the second side 123L of the first substrate 123. While polymer layer 129 will be used as an example in the discussion below, it will be appreciated that other suitable dielectric layers may be used in place of polymer layer 129. The polymer layer 129 is selectively formed over the second side 123L of the first substrate 123 (e.g., between adjacent external terminals 125) without covering the top surfaces (e.g., the top surfaces having solder 127) of the external terminals 125 . For example, although the polymer layer 129 contacts side walls of the external terminals 125, it does not contact or cover the tops of the external terminals 125. In the illustrated embodiment, the external terminals 125 protrude over the bottom of the polymer layer 129, which is away from the first substrate 123 is.

Above the second side 123L of the first substrate 123, e.g. B. between the first substrate 123 and the external terminals 125, a dielectric layer (e.g. a passivation layer) can be produced, but in 1B is not shown. This dielectric layer may be used to prevent or reduce diffusion of metals (e.g., diffusion of the metal of the external terminals 125) into the first substrate 123 and may include suitable dielectric materials such as silicon oxide, silicon nitride , low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, combinations thereof, or the like. In some embodiments, the dielectric layer may comprise a polymeric material such as cryogenic polyimide (PI), polybenzoxazole (PBO), combinations thereof, or the like. Any suitable manufacturing method can be used to produce the dielectric layer, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD).

Details of the semiconductor device 100 will be described below. The semiconductor die 111 may include: a second substrate 111S, first electrical components (not shown individually) on the second substrate, first metallization layers (shown in 1B are represented by a single layer with reference symbol 112), a first passivation layer (not shown), and first external contacts 117A (shown in 1B are shown as already bonded to conductive pads 132 of the interposer 150 and will be explained in more detail later). In one embodiment, the second substrate 111S may comprise doped or undoped bulk silicon or an active layer of a silicon-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that can be used are multilayer substrates, gradient substrates or hybrid orientation substrates.

The first electrical components include various active devices (e.g., transistors) and passive devices (e.g., capacitors, resistors, and inductors) and the like that are used to meet the structural and functional requirements of the semiconductor die design 111 can be used. The first electrical components may be fabricated in or otherwise on the second substrate 111S using suitable methods.

The first metallization layers 112 are formed over the second substrate 111S and the first electrical components and are designed to connect the various first electrical components into a functional circuit. In one embodiment, the first metallization layers 112 consist of alternating layers of a dielectric and a conductive material and may be formed using a suitable process (such as deposition, single damascene process, dual damascene process, etc.). In one embodiment, four metallization layers separated from the second substrate 111S by at least one interlayer dielectric (ILD) layer may be used, but the exact number of first metallization layers 112 depends on the design of the semiconductor die 111.

The first passivation layer (not shown) may be formed over the first metallization layers 112 to provide some protection to the structures underneath. The first passivation layer may be made from one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, combinations of it or something like that. The first passivation layer may be formed using a suitable method such as chemical vapor deposition (CVD), but any suitable method may be used.

The conductive pads 102 may be fabricated over and in electrical contact with the first metallization layer 112. The conductive pads 102 may comprise aluminum, but alternatively other materials such as copper may be used. The conductive pads 102 may be formed using a deposition process such as sputtering or plating to form a layer of material (not shown), and then portions of the layer of material may be removed using a suitable process (such as photolithographic masking and etching) to form the to produce conductive pads 102. However, another suitable method for producing the conductive pads 102 can also be used.

The first external contacts 117A may be formed on the conductive pads 102 to provide conductive areas for contact between the first metallization layers 112 and e.g. B. the first RDL 131 on the first substrate 123 to provide. In one embodiment, the first external contacts 117A may contact bumps, such as microbumps, and may comprise a material such as tin, or other suitable materials such as silver or copper. In an embodiment where the first external contacts 117A are tin solder bumps, the first external contacts 117A may be formed by first forming a layer of tin using a suitable method, such as evaporation, electroplating, printing, solder transfer, and ball placement. After a layer of tin has been formed on the structure, reflow is performed to form the material into the desired bump shape with a diameter of e.g. B. about 10 µm to 100 µm, although any suitable size can alternatively be used.

However, as one of ordinary skill in the art would recognize, the first external contacts 117A referred to above as microbumps are intended to be illustrative only. Rather, any suitable type of external contacts can alternatively be used, such as C4 contact bumps (C4: controlled collapse chip connection; chip connection with controlled collapse), copper pillars, a copper layer, a nickel layer, a connection-free layer (LF layer), an ENEPIG Layer (ENEPIG: Electro less Nickel Electroless Palladium Immersion Gold), a Cu/LF layer, a Sn/Ag layer, a Sn/Pb layer, combinations thereof or the like. Any suitable external terminal and method of making external terminals may be used for the first external contacts 117A.

The semiconductor die 113 may include: a third substrate 113S, second electrical components (the in 1B are not shown individually), second metallization layers (which are in 1B are represented by a single layer with the reference symbol 114), a second passivation layer (not shown), and second external contacts 117B. In one embodiment, the third substrate 113S, the second electrical components, the second metallization layers 114, the second passivation layer, and the second external contacts 117B may be the second substrate 111S, the first electrical components, the first metallization layers 112, the first passivation layer, and the first external contacts, respectively 117A, although they may alternatively be made of other materials that may be made using other methods. For example, the exact placement and fabrication of the various components and layers are at least partially dependent on the desired functionality of the semiconductor die 113.

The semiconductor die 115 may include: a fourth substrate 115S, third electrical components (the in 1B are not shown individually), third metallization layers (which are in 1B are represented by a single layer with the reference symbol 116), a third passivation layer (not shown), and third external contacts 117C. In one embodiment, the fourth substrate 115S, the third electrical components, the third metallization layers 116, the third passivation layer, and the third external contacts 117C may be the second substrate 111S, the first electrical components, the first metallization layers 112, the first passivation layer, and the first external contacts, respectively 117A, although they may alternatively be made of other materials that may be made using other methods. For example, the exact placement and fabrication of the various components and layers are at least partially dependent on the desired functionality of the semiconductor die 115.

Let's consider the interposer 150. The first substrate 123 can e.g. B. be a doped or undoped silicon substrate or an active layer made of a silicon-on-insulator (SOI) substrate. Alternatively, the first substrate 123 may be a glass substrate, a ceramic substrate, a polymer substrate, or another substrate that can provide suitable protection and/or connection functionality. These and other suitable materials may alternatively be used for the first substrate 123.

In some embodiments, the first substrate 123 may include electrical components such as resistors, capacitors, signal distribution circuits, combinations thereof, or the like. These electrical components can be active or passive components or a combination thereof. In other embodiments, the first substrate 123 is free of active and passive electrical components.

Additionally, in some embodiments, the first substrate 123 at this stage of the manufacturing process is a semiconductor wafer, such as a twelve-inch semiconductor wafer. The first substrate 123 can, for example, via the in 1B extend beyond the limits shown and have further parts, e.g. B. also include TSVs for the production of other structures. Therefore, if semiconductor dies, e.g. B. the semiconductor dies 111, 113 and 115, are bonded to the first substrate 123, the combined structure is a CoW configuration (chip-on-wafer configuration).

The current paths 121 may be TSVs or other suitable current paths. In embodiments where the current paths 121 are TSVs, the TSVs may be fabricated by first fabricating electrically conductive paths partially through the first substrate 123 and then thinning the first substrate 123 to expose the electrically conductive paths. In other embodiments, the current paths 121 pass through the first substrate 123 as they are manufactured, and the first substrate 123 does not need to be thinned. The current paths 121 may be formed by forming an appropriate photoresist layer or hardmask on the first substrate 123, patterning the photoresist or hardmask, and then etching the first substrate 123 to form openings (e.g., TSV openings). to create.

After the openings for the current paths 121 have been made, the openings can z. B. with a top layer (in 1B not shown separately), a barrier layer (in 1B also not shown separately) and filled with a conductive material. In one embodiment, the cover layer may be comprised of a dielectric material such as silicon nitride, silicon oxide, a dielectric polymer, combinations thereof, or the like, prepared using a process such as chemical vapor deposition, oxidation, physical Vapor deposition, atomic layer deposition or the like is deposited.

The barrier layer may comprise a conductive material such as titanium nitride, but other materials may also be used such as tantalum nitride, titanium, another dielectric, or the like. The barrier layer can be manufactured using a CVD process such as plasma enhanced chemical vapor deposition (PECVD). However, other processes can also be used, such as sputtering or metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). The barrier layer can be made to outline the shape of the opening for the current paths 121 underneath.

The conductive material may include copper, but alternatively other suitable materials may be used, such as aluminum, tungsten, alloys, doped polysilicon, combinations thereof, and the like. The conductive material can be made by depositing a seed layer and then electroplating copper onto the seed layer so that the openings for the current paths 121 are filled and overfilled. After the openings for the current paths 121 have been filled, excess portions of the barrier layer and excess conductive material outside the openings may be removed using an abrasive process such as chemical mechanical polishing (CMP), but any suitable removal method may be used.

After the current paths 121 are formed, the first RDL 131 may be formed on the first side 123U of the first substrate 123 to establish a connection between the current paths 121, the external contacts 117A and the semiconductor dies 111, 113 and 115. The first RDL 131 has electrically conductive structural elements (conductive lines and/or vias) which are arranged in one or more dielectric layers of the first RDL 131. The conductive structural elements of the first RDL 131 can be manufactured using conventional methods for producing interconnect structures in integrated circuits. In one embodiment, the conductive features of the first RDL 131 include at least one conductive layer made of a metal such as aluminum, copper, tungsten, titanium, or combinations thereof. The at least one conductive layer may be formed by forming a seed layer, covering the seed layer with a patterned photoresist (not shown), and then plating the metal on the seed layer in the openings of the photoresist. The photoresist and portions of the seed layer located beneath the photoresist are then removed, leaving behind the at least one conductive layer, which may have a thickness of about 0.5 μm to about 30 μm and a width of about 5 μm . The one or more dielectric layers of the first RDL 131 may include silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, combinations thereof, or the like. and may be manufactured using a process such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), or other suitable deposition process.

After the first RDL 131 is fabricated, an optional fourth passivation layer (not shown) may be fabricated over the first RDL 131, and vias may be fabricated through the fourth passivation layer to provide electrical access to the first RDL 131. In one embodiment, the fourth passivation layer may consist of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide , low temperature polyimide (PI), polybenzoxazole (PBO), combinations thereof or the like. The fourth passivation layer may be formed using a suitable method such as chemical vapor deposition (CVD), spin coating, and/or lithography, but another suitable method may also be used.

After the first RDL 131 (and optional fourth passivation layer) are fabricated, conductive pads 132 may be fabricated over and in electrical connection with the first RDL 131 on the first side 123U of the first substrate 123. The conductive pads 132 may include aluminum, but other materials such as copper may also be used. The conductive pads 132 may be formed using a deposition process such as sputtering to form a layer of material (not shown), and then portions of the material layer may be removed using a suitable process (such as photolithographic masking and etching) to form the conductive pads 132 to produce. However, another suitable method for producing the conductive pads 132 can also be used.

A second RDL can be placed above the second side 123L of the first substrate 123, but in 1B is not shown, are manufactured and z. B. via the current paths 121 electrically with the first th RDL 131 can be connected. Additionally, a fifth passivation layer (not shown) may be fabricated over the second RDL. The materials and manufacturing processes for the second RDL and the fifth passivation layer may be similar to those for the first RDL 131 and the fourth passivation layer, respectively, and therefore details are not repeated here.

Then external connections 125 can be made over the second side 123L of the first substrate 123 and e.g. B. be electrically connected to the first RDL 131 via current paths 121. In cases where a second RDL and a fifth passivation layer are formed over the second side 123L of the first substrate 123, the external terminals 125 are formed over the fifth passivation layer and are electrically connected to the second RDL, which in turn is e.g. B. is connected to the first RDL 131 via the current paths 121. The external connections 125 can be z. B. physically and electrically connected to another substrate (not shown) by reflow to produce a chip-on-wafer-on-substrate (CoWoS) structure. In the illustrated embodiment, the external terminals 125 are copper columns having a height of about 20 μm to about 70 μm, such as about 40 μm, and a width of about 40 μm to about 170 μm, such as about 80 μm. As in 1B As shown, a solder 127 is deposited on the tops of the external terminals 125, which may have a height of about 10 μm to about 50 μm. The aforementioned dimensions of the external terminals 125 and solder 127 are merely examples, and other suitable dimensions for the external terminals 125 and solder 127 are possible.

In another embodiment, the external terminals 125 may be bumps, such as C4 bumps, and may comprise a material such as tin or other suitable materials such as silver or copper. In an embodiment where the external terminals 125 are tin solder bumps, the external terminals 125 may be formed by first forming a layer of tin using a suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. After the layer of tin has been formed on the structure, reflow is carried out to form the material into the desired bump shape with a diameter of e.g. B. to bring about 80 µm.

However, as one of ordinary skill in the art would recognize, the external terminals 125 referred to above as C4 bumps are intended to be illustrative only. Rather, any suitable type of external contacts can alternatively be used, such as microbumps, copper pillars, a copper layer, a nickel layer, a terminal-free layer (LF layer), an ENEPIG layer, a Cu/LF layer, a Sn/Ag layer , an Sn/Pb layer, combinations thereof, or the like. Any suitable external terminal and any suitable method of making external terminals can be used for the external terminals 125.

The semiconductor dies 111, 113 and 115 can then be used, for example. B. bonded to the interposer 150 using a bonding process. In an embodiment where the first external contacts 117 are solder microbumps, the bonding process may be performed such that the first external contacts 117 are first aligned with their respective conductive pads 132 and then brought into physical contact with the conductive pads 132. After contact is made, reflow may be performed to melt the first external contacts 117, thereby bonding the first external contacts 117 to the conductive pads 132.

After bonding, the underfill material 133 may be injected or otherwise deposited into the space between the interposer 150 and the semiconductor dies 111, 113 and 115. The first underfill material 133 may be, for example, a liquid epoxy resin that is distributed between the semiconductor dies 111, 113 and 115 and the first substrate 123 and then cured. This first underfill material 133 can be used to prevent cracking in the first external contacts 117, where cracks are normally caused by thermal stresses.

As in 1B is shown, the underfill material 133 can also be column 119 (see 1A) between side walls of adjacent semiconductor dies. The size (e.g., width) of column 119 may range from about 30 μm to about 300 μm and may be adjusted for various design requirements and considerations. For example, a smaller gap size allows for higher integration density and results in a smaller size of the semiconductor device 100, but requires the use of the underfill material 133 (which is more expensive than the mold material 135) to fill the gap 119. Conversely, larger gaps enable use of the mold material 135 to fill the gaps 119, but they can also result in larger device size and can cause more deformation of the semiconductor device 100, as will be discussed in more detail below.

Depending on the size of the gap 119, the underfill 133 may extend to the tops of the semiconductor dies 111, 113 and 115 due to the capillary force based on the size of the gap 119, as in the example of 1B is shown. In a further embodiment, the underfill 133 can extend below the tops of the semiconductor dies 111, 113 and 115 due to the wider gap 119 (and thus the weaker capillary force). Compared to the molding material 135, the underfill material 133 has a greater flow rate and a homogeneous and void-free flow structure, and it hardens faster. In addition, the underfill material 133 can contain gaps (e.g., the gap 119 or the gap between the interposer 150 and the semiconductor dies 111, 113, and 115) with small gap sizes (e.g., gaps ranging in size from about 10 μm to 60 µm) that the mold material 135 may not be able to fill.

Then, the molding material 135 is deposited on the first side 123U of the first substrate 123 (e.g., over the first RDL 131). The molding material 135, in some embodiments, encloses the semiconductor dies 111, 113, and 115 and the underfill material 133. The molding material 135 may, for example, be an epoxy resin, an organic polymer, a polymer with or without an added silica-based filler, or glass filler or include other materials. In some embodiments, the molding material 135 includes a liquid molding compound (LMC) that is a gel liquid when applied. The molding material 135 may be a liquid or a solid when applied. Alternatively, the molding material 135 may include other insulating and/or capping materials. The molding material 135 is deposited using a wafer-level molding process in some embodiments. The molding material 135 may be formed, for example, by compression molding, injection molding, mold underfilling (MUF), or other methods.

Then, in some embodiments, the mold material 135 is hardened using a curing process. The curing process may include heating the mold material 135 to a specified temperature for a specified period of time using an annealing process or other heating process. The curing process may also include exposure to UV light, exposure to infrared (Ir) energy, combinations thereof, or a combination thereof with a heating process. Alternatively, the mold material 135 may be hardened using other methods. In some embodiments, no curing process is used.

1B 12 shows the underfill material 133 filling the gap between the interposer 150 and the semiconductor dies 111, 113 and 115, but instead of the underfill material 133, the mold material 135 can also be used to fill the gap if the gap is large (e.g. B. larger than 10 µm). Likewise, if the gaps 119 are large (e.g., greater than 40 μm), the molding material 135 may be used to fill the gaps 119 instead of the underfill material 133 (in 1B not shown). Other combinations of the underfill material 133 and the molding material 135 are possible.

Due to the difference between the CTEs of the molding material 135, the underfill material 133, and/or other materials used in the semiconductor device 100, deformation of the semiconductor device 100 may occur. For example, the CTE of the underfill material 133 may be in the range of about 15 parts per million parts per °C (ppm/°C) to about 200 ppm/°C, such as 120 ppm/°C, and the CTE of the Molding material 135 may range from about 4 ppm/°C to about 80 ppm/°C, such as 26 ppm/°C. In the example of 1B is the molding material 135 in the edge regions 103 (e.g., the regions near the outer boundaries of the interposer 150, such as the regions in which the semiconductor dies 113 and 115 are disposed) of the interposer 150 and around the underfill material 133 arranged. Therefore, at high temperatures (e.g., higher than 200° C.), the underfill material 133 expands more than the molding material 135, which may cause the edge regions 103 of the interposer 150 to move downward toward the central region 101 (e.g. B. the area near the center of the interposer 150, such as the area in which the semiconductor die 111 is arranged) of the interposer 150 bend. During subsequent reflow to connect the external terminals 125 of the semiconductor device 100 to corresponding conductive features (e.g., conductive pads or connectors) of another substrate (in 1B not shown) to produce a CoWoS structure, the deformation described above can result in cold solder joints in the central region 101 and/or solder bridges (e.g. solder that connects adjacent external connections 125, so that an electrical short circuit occurs). the edge areas 103 lead. Cold solder joints and solder bridges affect the reliability of the CoWoS structure and reduce the yield of semiconductor manufacturing. As discussed above, the polymer layer 129 is manufactured to reduce the deformation of the semiconductor device 100 and to avoid or reduce cold solder joints and/or solder bridges.

Let's stay with it 1B . The polymer layer 129 is produced on the second side 123L of the first substrate 123. The polymer layer 129 is selectively over the second side 123L, e.g. B. between adjacent external terminals 125, without covering the top surfaces (e.g. the surfaces with the solder 127) of the external terminals 125. The polymer layer 129, in some embodiments, includes polyimide (PI), polybenzoxazole (PBO), resin, epoxy resin, acrylic polymer, combinations thereof, or the like. In some embodiments, the polymer layer 129 includes a molding material, such as an epoxy resin, with a filler (e.g., silicon oxide). In one embodiment, the polymer layer 129 includes an underfill material. The polymer layer 129 may be in a liquid state when distributed on the second side 123L of the first substrate 123. A suitable metering device or method (e.g., ejection, distribution) can be used to produce the polymer layer 129.

The composition, location, thickness and/or volume of the polymer layer 129 may be adjusted to achieve a specified CTE and/or stress level to counteract the deformation of the semiconductor device 100. For example, in embodiments in which the volume of the underfill material 133 dominates the total volume of the underfill material 133 and the molding material 135 (e.g., occupies more than about 60% of the total volume), the CTE and/or the stress level of the polymer layer 129 may be adjusted so (e.g., by changing the composition, location, thickness and/or volume of the polymer layer 129) to match the CTE and/or the stress level of the underfill material 133 to compensate for the deformation of the semiconductor device 100. In some embodiments, the volume or thickness of the polymer layer 129 is adjusted (e.g., increased) to compensate for the deformation of the semiconductor device 100. As another example, if the volume of the polymer layer 129 is less than the volume of the underfill material 133, the CTE and/or the stress level of the polymer layer 129 may be adjusted to be higher than the CTE and/or the stress level of the underfill material 133 in order to achieve sufficient compensation to reduce the deformation of the semiconductor component 100. As yet another example, if the molding material 135 is used instead of the underfill material 133, the CTE and/or the stress level of the polymer layer 129 may be adjusted to match the CTE and/or the stress level of the molding material 135.

1C shows an enlarged view of an area 105 of 1B . In the example shown, due to the wetting of the polymer layer 129 on the external terminals 125, a first part of the polymer layer 129, which contacts the side walls of the external terminals 125, has a height H2 (which is also referred to as a thickness H2 of the polymer layer 129), and a second portion of the polymer layer 129 remote from the external terminals 125 (e.g., midway between adjacent external terminals 125) has a height H1 (also referred to as a thickness H1 of the polymer layer 129). The height H2 is greater than the height H1, and the bottom 129U of the polymer layer 129, remote from the first substrate 123, may have a round profile near the external terminals 125, as in the example of 1C is shown. The values for height H1 and height H2 may depend on various design factors, such as: B. the size of the external connections 125, the wettability of the polymer layer 129 and the extent of the deformation to be compensated for by the polymer layer 129. For example, in an embodiment where the height (measured along the same direction as H2) of the external terminals 125 is about 40 μM, the height H1 is about 2 μm to about 40 μm, and the height H2 is about 10 μm to about 70 µm. Other dimensions for height H1 and height H2 are possible and are intended to be within the scope of the present invention.

Although the height H2 in the example of 1C greater than the height H1, depending on the material of the polymer layer 129 and the wettability of the polymer layer 129 on the external connections 125, the height H2 can be equal to the height H1 (e.g. the polymer layer 129 has a constant thickness) , and in some embodiments, the polymer layer 129 may have a flat top surface 129F (see dashed line) that contacts the sidewalls of the external terminals 125.

In 1B the polymer layer 129 is arranged on the second side 123L of the first substrate 123 in the middle region 101 and the edge region 103. 1D shows a further embodiment of a semiconductor component 180, which is the semiconductor component 100 of 1B is similar, but the polymer layer 129 has different positions. In particular, the polymer layer 129 of the semiconductor device 180 is arranged over a first part of the second side 123L of the first substrate 123, and a second part of the second side 123L is not covered (exposed) by the polymer layer 129. For example, in 1D the middle region 101 does not have the polymer layer 129 (it is not covered by it), and the polymer layer 129 is made in the edge regions 103. These and other changes and/or modifications to the polymer layer 129 are possible and are intended to be within the scope of the present invention.

The thickness (e.g. the height H1 in 1C ) and the positions (e.g. middle area 101 and/or edge areas 103 in the 1B and 1C ) of the polymer layer 129, in some embodiments, determine the volume of the polymer layer 129. The composition, thickness, and/or volume of the polymer layer 129 may be changed to achieve a target stress level to counteract the stress, e.g. B. caused by the underfilling 133 and the molding material 135. In embodiments in which the polymer layer 129 is arranged both in the central region 101 and in the edge regions 103 of the interposer 150 (see 1B) , the thickness (e.g. the height H1 in 1C ) of the polymer layer 129 can be 2 μm to 40 μm, and the stress level (e.g., elastic modulus) of the polymer layer 129 can be 1 GPa to about 10 GPa. In embodiments in which the polymer layer 129 is arranged in the edge regions 103 of the interposer 150 (see 1D ), the thickness (e.g. the height H1 in 1C ) of the polymer layer 129 can be 2 μm to 40 μm, and the stress level (e.g., elastic modulus) of the polymer layer 129 can be 1 GPa to about 10 GPa.

The 2A until 2D show sectional views of a semiconductor structure 200 at various manufacturing stages according to one embodiment. The elements or structures that are the same as in 1B are, are in the 2A until 2D designated with the same reference symbols, and in the 2A until 2D A reference symbol with the suffix M denotes a component or structure that contains multiple copies of a respective element of the structure 1B includes those that do not have the suffix M. For example, the interposer has 150M of 2A a plurality of areas 202, 204 and 206, each area being assigned to the interposer 150 1B corresponds.

In 2A An Interposer 150M is provided. The interposer 150M includes a substrate 123M, an RDL 131M, current paths 121 (e.g., TSVs or other current paths), and external terminals 125 (e.g., C4 bumps). As will be explained in more detail later, after a subsequent isolation process (see 2D ) each of the regions (e.g. 202, 204 and 206) of the semiconductor structure 200 to a semiconductor device, such as the semiconductor device 100 of 1B .

Over a second side 123L of the first substrate 123M, e.g. B. between the first substrate 123M and the external terminals 125, a dielectric layer (e.g. a passivation layer) can be produced, but in 2A is not shown. This dielectric layer may be used to prevent or reduce diffusion of metals (e.g., diffusion of the metal of the external terminals 125) into the first substrate 123M. Details of the materials and manufacturing methods for this dielectric layer are similar to those discussed above with reference to 1B have been described and will therefore not be repeated here.

To fabricate the semiconductor structure 200, in each of the regions (e.g., 202, 204, and 206) of the interposer 150M, semiconductor dies 111, 113, and 115 are physically and electrically connected to a corresponding part via connectors 117 (e.g., microbumps). connected to the RDL 131M. The gap between the interposer 150M and the semiconductor dies 111, 113 and 115 is filled with the underfill 133. The mold material 135 is deposited over the RDL 131 and around the semiconductor dies 111, 113 and 115 and the underfill 133. Details of the materials and manufacturing methods for the underfill 133 and the molding material 135 are similar to those discussed above with reference to 1B have been described and will therefore not be repeated here.

In 2 B For example, a polymeric material 129' is selectively deposited over the substrate 123M (e.g., between adjacent external terminals 125), excluding the top surfaces (e.g., the surfaces of the external terminals 125 remote from the substrate 123M) of the external terminals 125 to cover. The composition of the polymer material 129' may be similar to that of the polymer layer 129 described above 1B has been described and the details will therefore not be repeated here. The polymeric material 129' is distributed using a metering device 201. In some embodiments, the metering device 201 has built-in heating elements so that the polymeric material 129' is in a liquid state when deposited. In some embodiments, the dispenser 201 has a built-in UV light source so that the polymer material 129' is in a liquid state when deposited.

The deposited polymer material 129' forms the polymer layer 129 over the substrate 123M, as shown in 2C is shown. Depending on the wettability of the polymer layer 129 on the external terminals 125, the polymer layer 129 may have a flat top 129U remote from the substrate 123M, the flat top 129U contacting the sidewalls of the external terminals 125, as shown in FIG 2C is shown. In other embodiments, the top of the polymer layer 129 may have a round profile near the external terminals 125, e.g. B. the in 1C is similar. The polymer layer 129 may have a first height H1 in a first part from the external terminals 125 (e.g., midway between adjacent external terminals 125), and have a second height H2 in a second portion proximate (e.g., in contact with the sidewalls) of the external terminals 125 , where H2 is greater than H1. The dimensions of the height H1 and the height H2 are above with reference to 1C have been discussed and therefore details will not be repeated here.

After the polymer layer 129 is produced, a curing process is performed to fully cure the polymer layer 129. In some embodiments, the curing process is a heat curing process performed at a temperature of about 130°C to about 250°C, such as 180°C, and for a period of time of about 30 minutes to about 4 hours, such as 90 minutes becomes. In other embodiments, a UV curing process is performed to cure the polymer layer 129. The UV curing process can be performed using UV light with a wavelength of about 300 nm to about 396 nm, and the time period for the UV curing process can be about 5 seconds to about 180 seconds. The foregoing curing processes are merely examples, and other curing processes and methods are also possible and are intended to be within the scope of the present invention.

In other embodiments, a curing process is performed to partially cure the polymer layer 129. For example, a UV curing process is performed to partially cure the polymer layer 129. The partial UV curing process may use the same wavelength as, but a different time period than, the full UV curing process described above. For example, the time period for the UV curing process can be adjusted (e.g., shortened) to achieve different levels of curing (e.g., full cure or partial cure). Likewise, a thermosetting process can be used to partially harden the polymer layer 129. The temperature and/or duration of the full heat curing process discussed above may be modified (e.g., lower temperature and/or shorter duration) to achieve different levels of curing. The partially hardened polymer layer 129 can be further hardened in a subsequent reflow process (e.g. a reflow process for bonding the outer connections 125 of the semiconductor component 100 to another substrate in order to produce a CoWoS structure), so that the polymer layer 129 after can be completely hardened by the subsequent melting process.

Then in 2D After the curing process, the semiconductor structure 200 along boundaries of various areas (e.g. 202, 204 and 206 in 2A) singulated using a singulation device 205, which may be, for example, a singulation knife or a laser singulation device. After the separation process, a large number of semiconductor components 100 (see also 1B) manufactured. Note that in various embodiments, the polymer layer 129 is formed only after the external terminals (e.g., 125 in 1B , 305 in 3B and 507 in 1C ) of the interposer (e.g. the interposer 150) have been produced and before the interposer is attached to the further substrate (e.g. to produce a CoWoS structure).

2D shows that the polymer layer 129 is arranged over the central region and the edge regions of each semiconductor device 100. Similar to in 1D In some embodiments, the polymer layer 129 may be disposed over the edge regions of each semiconductor device 100, and the central region of each semiconductor device 100 is free of (ie, not covered by) the polymer layer 129. These and other variations and/or modifications of the polymer layer 129 are possible and are intended to be within the scope of the present invention.

The 3A until 3C show sectional views of a semiconductor component 300 at various manufacturing stages according to one embodiment. For the sake of simplicity, they show 3A until 3C only one semiconductor component 300, it being clear that several tens, hundreds or even thousands of the semiconductor components 300 can be produced on an interposer and can then be separated into a large number of semiconductor components 300. The elements or structures that are the same as in 1B are, are in the 3A until 3C designated with the same reference symbols. Unless otherwise indicated, elements or structures with the same reference symbols are made from the same material and using the same manufacturing processes and therefore details are not repeated.

In 3A a semiconductor component 300 is produced. The semiconductor component 300 is the semiconductor component 100 from 1B similar, except that in 3A external connections 305 are made of solder and the polymer layer 129 is not produced. The external connections 305 can be made by first placing a photoresist (not shown) over the second side 123L of the first substrate 123 depositing, patterning the photoresist to form openings at positions where the external terminals 305 are to be formed, and depositing solder in the openings using a suitable deposition method, such as plating. In the example shown, the external terminals 305 each have flat (ie, straight) sidewalls 305S, and therefore a distance remains between two opposite sides 305S of an external terminal 305 from a first end of the sidewalls 305S contacting the first substrate 123 up to one second end of the sidewalls 305S, which is distant from the first substrate 123, is substantially the same.

As in 3A As shown, a polymer material 129' is selectively distributed over the second side 123L of the first substrate 123 using the metering device 201, without tops 305T of the external terminals 305, e.g. B. between adjacent external connections 305 and / or next to the external connections 305 to cover. The deposited polymer material 129' forms the polymer layer 129, as shown in 3B is shown.

Then, as in 3B is shown, the polymer layer 129 is cured (e.g. completely or partially) with a curing process 303. In some embodiments, the curing process 303 is a UV curing process that is performed to fully cure the polymer layer 129. The UV curing process may be performed using UV light having a wavelength of about 300 nm to about 396 nm and a time period of about 5 seconds to about 180 seconds to fully cure the polymer layer 129. In other embodiments, a UV curing process is performed to partially cure the polymer layer 129 and a subsequent reflow process completes the curing of the polymer layer 129. The partial UV curing process can use the same wavelength as, but a different time period than, the full UV curing process. For example, the time period for the UV curing process can be adjusted (e.g., shortened) to achieve different levels of curing (e.g., full cure or partial cure). After the curing process 303 (a partial UV curing process or a full UV curing process), the polymer layer 129 is cured and provides a support and/or boundary for the external terminals 305 during a subsequent reflow process. UV curing is used as an example of the curing process 303 in the discussion above. Other suitable curing processes may also be used, which are intended to be within the scope of the present invention.

Then in 3C a melting process 307 is carried out. During the melting process 307, the external connections 305 (which consist of solder in the example shown) are melted. Due to the surface tension of the melted solder, first parts 305B (the parts that protrude beyond the polymer layer 129) of the external connections 305 have a round profile after the end of the melting process 307 (e.g. they have the shape of spheres or spherical parts). Note that due to the constraint provided by the (e.g., partially or fully) cured polymer layer 129, second portions 305A (the portions of the external terminals 305 between the first portions 305B and the first substrate 123) of the external connections 305 maintain the flat (ie straight) side walls after the melting process 307 has ended. In embodiments in which the polymer layer 129 is partially cured with the curing process 303, the reflow process 307 also completes the curing process, and thus after the reflow process 307 the polymer layer 129 is completely cured.

The 3B and 3C show that the polymer layer 129 is fabricated over the second side 123L of the first substrate 123 and covers the central region and the edge regions of the semiconductor device 300. Similar to in 1D In other embodiments (not shown), the polymer layer 129 is produced in the edge regions of the semiconductor component 300, and the central region of the semiconductor component 300 is free of the polymer layer 129. These and further variations and / or modifications of the polymer layer 129 are possible and are intended to be within the scope of the present invention.

4 shows an enlarged view of an area 309 of 3C . As in 4 As shown, the first parts 305B of the external terminals 305 have a width W2 that is larger than a width W1 of the second parts 305A of the external terminals 305. In some embodiments, the width W2 is in the range of about 80 μm to about 120 μm and the width W1 is in the range of about 40 μm to about 80 μm.

In the example of 4 Due to the wetting of the polymer layer 129 on the outer terminal 305, a first part of the polymer layer 129 that contacts the side walls of the outer terminal 305 has a height H4 (which is also referred to as a thickness H4 of the polymer layer 129), and a second part The polymer layer 129, which is remote from the external terminals 305 (e.g., midway between adjacent external terminals 305), has a third height H3 (also referred to as a Thickness H3 of the polymer layer 129 is referred to). The height H4 is greater than the height H3, and the bottom of the polymer layer 129, remote from the first substrate 123, may have a round profile near the external terminals 305, as in the example of 4 is shown. The values for height H3 and height H4 may depend on various design factors, such as: B. the size of the external connections 305, the wettability of the polymer layer 129 and the extent of the deformation to be compensated for by the polymer layer 129. For example, in an embodiment where the height (measured along the same direction as H3) of the external terminals 305 is about 70 μm, the height H3 is about 2 μm to about 40 μm, and the height H4 is about 10 μm to about 70 µm. Other dimensions for height H3 and height H4 are possible and are intended to be within the scope of the present invention.

Although the height H4 in the example of 4 greater than the height H3, depending on the material of the polymer layer 129 and the wettability of the polymer layer 129 on the external terminals 125, the height H4 may be equal to the height H3, and in some embodiments, the polymer layer 129 may have a flat top surface 129F ( see dashed line) that contacts the side walls of the external connections 305.

The 5A until 5C show sectional views of a semiconductor component 500 at various manufacturing stages according to some embodiments. For the sake of simplicity, they show 5A until 5C only one semiconductor component 500, whereby it is clear that several tens, hundreds or even thousands of the semiconductor components 500 can be produced on an interposer and can then be separated into a large number of semiconductor components 500. The elements or structures that are the same as in 1B are, are in the 5A until 5C designated with the same reference symbols. Unless otherwise indicated, elements or structures with the same reference symbols are made from the same material and using the same manufacturing processes and therefore details are not repeated here.

In 5A a semiconductor component 500 is produced. The semiconductor component 500 is the semiconductor component 300 from 3A similarly before the polymer material 129' is distributed, and details will not be repeated here.

Then in 1B a melting process 501 is carried out. Through the reflow process 501, the external terminals 305, which are made of solder, melt and solidify again after the reflow process is completed. Due to the surface tension of the molten solder, the profile of the external connections 305 changes into a round profile (e.g. into spheres or spherical parts) after the melting process 307. Below, the external connections 305 after the reflow process 501 are referred to as external connections 507.

Then, as in 5C 12, the polymeric material 129' is shown selectively distributed over the second side 123L of the first substrate 123 using the metering device 201, excluding tops 507T of the external terminals 507, e.g. B. between adjacent external connections 507 and / or next to the external connections 507 to cover. The deposited polymer material 129' forms the polymer layer 129.

After the polymer layer 129 has been prepared, a curing process, such as UV curing or heat curing, may be performed to cure the polymer layer 129. In some embodiments, the curing process is a heat curing process performed at a temperature of about 130°C to about 250°C, such as 180°C, and for a period of time of about 30 minutes to about 4 hours, such as 90 minutes becomes. In other embodiments, a UV curing process is performed to cure the polymer layer 129. The UV curing process can be performed using UV light with a wavelength of about 350 nm to about 396 nm, and the time period for the UV curing process can be about 5 seconds to about 180 seconds. The foregoing curing processes are merely examples, and other curing processes and methods are also possible, which are also intended to be within the scope of the present invention.

5C shows that the polymer layer 129 is fabricated over the second side 123L of the first substrate 123 and covers the central region and the edge regions of the semiconductor device 500. Similar to in 1D In other embodiments (not shown), the polymer layer 129 is produced in the edge regions of the semiconductor device 500, and the central region of the semiconductor device 500 is free of the polymer layer 129 (it is not covered by it). These and other variations and/or modifications of the polymer layer 129 are possible and are intended to be within the scope of the present invention.

6 shows an enlarged view of an area 505 of 5C . As in 6 is shown has due to the wetting of the polymer layer 129 on the outer terminal 507, a first part of the polymer layer 129 which contacts the side walls of the outer terminal 507, a height H6, and a second part of the polymer layer 129 which is away from the outer terminals 507 (e.g. in the middle between two adjacent external connections 507) has a height H5. The height H6 is greater than the height H5, and the bottom of the polymer layer 129, which is away from the substrate 123, may have a round profile near the external terminals 507, as in the example of 6 is shown. The values for height H5 and height H6 may depend on various design factors, such as: B. the size of the external connections 507, the wettability of the polymer layer 129 and the extent of the deformation to be compensated for by the polymer layer 129. For example, in an embodiment in which the height (measured along the same direction as H2) of the external terminals 507 is about 70 μm, the height H5 is about 2 μm to about 40 μm, and the height H6 is about 10 μm to about 70 µm. Other dimensions for height H5 and height H6 are possible and are intended to be within the scope of the present invention.

Although the height H6 in the example of 6 129F ( see dashed line) which contacts the side walls of the external connections 507.

7 shows a performance comparison between a conventional semiconductor component without the polymer layer 129 and a component according to the invention that has the polymer layer 129. In particular, a curve 601 corresponds to the conventional device, and a curve 603 corresponds to the device according to the invention (e.g. the semiconductor device 100, 300 or 500) with the polymer layer 129. The x-axis represents the temperature (from room temperature to 258 °C and then drops back to room temperature), and the y-axis represents the amount of deformation in micrometers (µm). A positive deformation value indicates that the edge parts of the semiconductor device (e.g. parts of the semiconductor component 100 in the areas 103 of 1B) with respect to the central part of the semiconductor device (e.g. the part of the semiconductor device 100 in the region 101 of 1B) bend upwards. Conversely, a negative deformation value indicates that the edge parts of the semiconductor device bend downwards in relation to the central part of the semiconductor device. The deformation value can be determined by measuring the distance between the tops of the external terminals in the central region 101 and the edge regions 103. Out of 7 shows that both at room temperature and at a high temperature (e.g. about 258 ° C) the component according to the invention has a lower deformation than the conventional component. In 7 the greatest deformation (e.g. the maximum of the absolute value of the measured deformation) is approximately 60 µm. The reduced deformation of the device according to the invention indicates that the stress applied to the semiconductor device is lower, the failure rate of the devices is lower and the device performance is better. Cold solder joints and/or bridging of solder joints are reduced or avoided.

8th shows a flowchart of a method 1000 for producing a semiconductor component according to some embodiments. It should be clear that the method according to the invention, which is in 8th is shown is merely an example of numerous possible methods according to the invention. One of ordinary skill in the art would recognize numerous variations, alternatives and modifications. For example, various steps included in 8th shown, added, omitted, rearranged and repeated.

In 8th an interposer is provided in step 1010. The interposer includes a first redistribution layer (RDL) over a first side of a substrate and a plurality of external terminals attached to a second side of the substrate opposite the first side. In step 1020, a plurality of dies are attached to the first RDL. In step 1030, a space between the plurality of dies and the first RDL is filled with an underfill material. In step 1040, a molding material is deposited over the first RDL and around the plurality of dies and the underfill material. In step 1050, the stress of the underfill material and the molding material is neutralized by distributing a polymeric material on the second side of the substrate without covering the tops of the plurality of external terminals remote from the substrate. In step 1060, the polymer material is cured.

One of the advantages of the present invention is the reduction of deformation in semiconductor components. The reduced deformation prevents cold solder joints and/or bridging of solder joints. Device reliability is improved and semiconductor processing yield is increased.

The invention relates to a semiconductor component, comprising: a substrate; a first redistribution layer (RDL) over a first side of the substrate; one or more semiconductor dies disposed above and electrically connected to the first RDL; and an encapsulating material over the first RDL and around the one or more semiconductor dies. The semiconductor device further includes terminals attached to a second side of the substrate opposite the first side, the terminals being electrically connected to the first RDL. The semiconductor component further has a polymer layer on the second side of the substrate, with the connections protruding from the polymer layer over a first surface of the polymer layer that is remote from the substrate, with a first part of the polymer layer that contacts the connections, has a first thickness and a second portion of the polymer layer between adjacent terminals has a second thickness that is smaller than the first thickness.

The invention further relates to a method comprising: receiving an interposer, the interposer having a first substrate, a first redistribution layer (RDL) over a first side of the first substrate and a plurality of external terminals on a second side of the first substrate, which the first side, wherein the plurality of external terminals are electrically connected to the first RDL. The method further includes: attaching a plurality of dies to the first RDL of the interposer; filling a gap between the interposer and the plurality of dies with a first dielectric material; and distributing a second dielectric material on the second side of the first substrate without covering tops of the plurality of external terminals before attaching the interposer to a second substrate, the distributing occurring after the plurality of external terminals on the second side of the first substrate was formed.

In yet another embodiment, a method includes including an interposer having a first redistribution layer (RDL) over a first side of a substrate and a plurality of external terminals on a second side of the substrate opposite the first side. The method further includes: attaching a plurality of dies to the first RDL, wherein after attaching the plurality of dies, the first RDL is between the substrate and the plurality of dies; filling a space between the plurality of dies and the first RDL with an underfill material; and depositing a molding material over the first RDL and around the plurality of dies and the underfill material. The method further includes: distributing a polymeric material on the second side of the substrate without covering tops of the plurality of external terminals remote from the substrate; and curing the polymer material.

Claims (20)

Semiconductor device with: a substrate (123); a first RDL (131) over a first side (123U) of the substrate (123); one or more semiconductor dies (111, 113, 115) disposed above and electrically connected to the first RDL (131); an encapsulation material (133, 135) over the first RDL (131) and around the one or more semiconductor dies (111, 113, 115); terminals (125) attached to a second side (123L) of the substrate (123) opposite the first side (123U), the terminals (125) being electrically connected to the first RDL (131); and a polymer layer (129) on the second side (123L) of the substrate (123), the connections (125) protruding from the polymer layer (129) over a first surface of the polymer layer (129) which is away from the substrate (123). is, wherein a first part of the polymer layer (129), which contacts the connections (125), has a first thickness (H4) and a second part of the polymer layer (129) between adjacent connections (125) has a second thickness (H3), which is smaller than the first thickness (H4). Semiconductor device according to Claim 1 , wherein the polymer layer (129) comprises a material selected from a group consisting essentially of polyimide, polybenzoxazole, resin, epoxy resin, acrylic polymer, an underfill material, a molding material, or combinations thereof. Semiconductor device according to Claim 1 or 2 , wherein the polymer layer (129) is arranged in edge regions of the substrate (123) and a central region of the substrate (123) is free of the polymer layer (129). A semiconductor device according to any one of the preceding claims, wherein the encapsulation material (133, 135) comprises: an underfill material (133) in a gap between the substrate (123) and the one or more semiconductor dies (111, 113, 115); and a molding material (135) over the first side of the substrate (123) and around the one or more semiconductor dies (111, 113, 115). Semiconductor device according to one of the preceding claims, wherein a first part of the connections (305B) extends further from the substrate (123) than the first surface of the polymer layer (129) and a second part of the connections (305B) between the substrate (123) and the first part of the connections (305B), the second part of the connections (305A) having flat side walls and the first part of the connections (305B) having curved side walls. Semiconductor device according to Claim 5 , wherein a first width (w2) of the first part of the connections (305B) is greater than a second width (w1) of the second part of the connections (305A). Procedure with the following steps: Receiving an interposer (150), the interposer (150) comprising: a first substrate (123), a first RDL (131) over a first side (129U) of the first substrate (123), and a plurality of external terminals (125) formed on a second side (123L) of the first substrate (123) opposite the first side (123U), the plurality of external terminals (125) being electrically connected to the first RDL (131) is connected; attaching a plurality of dies (111, 113, 115) to the first RDL (131) of the interposer (150); filling a gap between the interposer (150) and the plurality of dies (111, 113, 115) with a first dielectric material (133); and Distributing a second dielectric material (135) on the second side (123L) of the first substrate (123) without covering tops of the plurality of external terminals (125) before attaching the interposer (150) to a second substrate (111S). , wherein the distributing is performed after the plurality of external terminals (125) are formed on the second side (123L) of the first substrate (123). Procedure according to Claim 7 , further comprising performing a reflow process to bond the plurality of external terminals (125) to respective conductive features (112) of the second substrate (123). Procedure according to Claim 7 or 8th , wherein a polymer material (129) has a first part contacting the plurality of external terminals (125) and a second part remote from the plurality of external terminals (125), the first part having a first thickness (H4 ) which is greater than a second thickness (H3) of the second part. Procedure according to one of the Claims 7 until 9 , wherein the polymer material (129) has a constant thickness. Procedure according to one of the Claims 7 until 10 , wherein the distribution comprises distributing the polymer material (129) in edge regions of the interposer (150) and keeping a central region of the interposer (150) free of the polymer material (129). Procedure according to one of the Claims 7 until 11 , further comprising curing the polymeric material (129) after distribution. Procedure according to Claim 12 , wherein the curing comprises partial curing of the polymer material (129). Procedure according to Claim 12 or 13 , further comprising performing a reflow process after curing the polymer material (129), wherein the reflow process modifies a profile of a first portion (305B) of one of the plurality of external terminals (125) which extends over a first surface of the second dielectric material (135) which is removed from the substrate (123). Procedure according to Claim 14 , wherein the first part (305B) of the one of the plurality of external terminals (125) has a first width (w2) and the second part (305a) of the one of the plurality of external terminals (125) which is between the first substrate (123 ) and the first part (305B), has a second width (w1), wherein the first width (w2) is greater than the second width (w1). Procedure with the following steps: Receiving an interposer (150), the interposer having a first RDL (131) over a first side (123U) of a substrate (123) and a plurality of external terminals (125) attached to a second side (123L) of the substrate (123U) 123) opposite the first side (123U); Attaching a plurality of dies (111, 113, 115) to the first RDL (131), wherein after attaching the plurality of dies (111, 113, 115), the first RDL (131) is between the substrate (123) and the variety of dies (111, 113, 115); filling a space between the plurality of dies (111, 113, 115) and the first RDL (131) with an underfill material (133); forming a molding material (135) over the first RDL (131) and around the plurality of dies (111, 113, 115) and the underfill material (133); distributing a polymeric material (129) on the second side (123L) of the substrate (123) without covering tops of the plurality of external terminals (125) remote from the substrate (123); and Hardening the polymer material (129). Procedure according to Claim 16 , further comprising physically and electrically connecting the plurality of external terminals (125) of the interposer (150) to conductive features (112) of another substrate (111S). Procedure according to Claim 16 or 17 , wherein a first portion of the polymeric material (129) contacting the plurality of external terminals (125) extends further from the substrate (123) than a second portion of the polymeric material (129) extending from the plurality of external terminals (125 ) is removed. Procedure according to one of the Claims 16 until 18 , wherein the plurality of external terminals (125) consists of solder (127), and wherein the method further comprises performing a reflow process to modify profiles of the plurality of external terminals (125) before distributing the polymeric material (129). Procedure according to one of the Claims 16 until 19 , wherein the curing includes an ultraviolet curing process or a hot curing process.

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