DE102017115056B3 - Method for checking safety-relevant register or memory cells for stuck at fault during operation - Google Patents

Abstract

A method for checking memory or register cells of an integrated circuit for stuck-at errors during the operation of this integrated circuit is proposed in which parts of the data to be stored in the memory or register cells are stored inverted, sometimes not inverted, during operation become. Information about the inversion is included so that the information can be reconstructed. If an error occurs due to a stuck-at error of a single bit, the memory cell can be further used in an emergency mode by suitable inversion of the data to be stored and the corresponding information about the inversion. Another advantage is that this can clearly identify the defect class "Stuck-At". Specifically, the error detection is performed by storing the data, then reading the data and comparing the data to be stored with the read data.

Description

preamble

Methods for checking memory or register cells of an integrated circuit for stuck-at errors during operation of this integrated circuit are proposed.

General introduction

In the field of safety-related integrated circuits, latent errors in memory or register cells, which occur during operation, e.g. due to degradation, etc. This applies, for example, to calibration registers with virtually static content. In addition, there is a desire register to keep usable in a single error.

State of the art

From the state of the art, register protection via redundant data such as CRC checksums or parity bits is known. However, if a parity error occurs, the register is no longer usable. This can in some cases lead to failures.

Both mechanisms alone find a stuck-at error only with actual variation of all bits. A registry with security relevant content would thus have the potential to obscure latent errors (e.g., crash data such as pressure or acceleration, which typically have no significant variation in content in normal operation without a crash).

From the patent US Pat. No. 9,075,742 B2 For example, a method for checking memory or register cells of an integrated circuit for faults during operation of this integrated circuit is already known. In the process of US Pat. No. 9,075,742 B2 By means of additional data information, a first part of the data to be stored, depending on the status of the additional data information, is stored either inverted as a whole or not inverted. From the process of US Pat. No. 9,075,742 B2 It is known that the inverting reading of the first part of the memory or register cells and the non-inverting reading of a second part of the memory or register cells leads to a reading result. The reading result is represented by the first and the second part of the read data.

A similar prior art is also known from the published patent application DE 10 2013 215 055 A1 known.

Task of the proposed method

The task is thus to allow a check for stucco-at faults in registers of security-relevant ICs with quasi-static content or even to keep them usable despite the fault. For this purpose, a method for finding potentially unchangeable content ("stucco-at" error) is necessary. An emergency mode with reduced performance should be possible.

This object is achieved by the method according to claim 1.

Solution of the task

A method is proposed for checking memory or register cells of an integrated circuit for stuck-at errors and possibly bridging faults during the operation of this integrated circuit. The method begins by providing the data to be stored in the memory or register cells to be checked. These data to be stored can be divided at least into a first and a second part. It is conceivable to divide the data into more than two parts and treat them differently. For example, a third part of the data can not be secured. Here, however, it is assumed that both parts are protected by a parity bit or a CRC checksum, for example, whereby only the memory and register cells of the first part are subjected to a functional test. The first part of the data to be stored and the second part of the data to be stored are non-overlapping. This means that a datum (and hence the associated register or memory cell) belongs to either the first part or the second part but never to both parts. The first part can include all data to be stored. The second part can not include any data. The first part should contain at least one date, at least one bit. For this data to be stored, a check information is added. This check information can take place before or after the subsequent partial or total inversion of the data to be stored. In the reading process, this process must then be reversed only in the reverse order. Preferably, the check information is part of the data to be stored. The memory and register cells for this test information are then also subjected to the test itself. The addition of a check information, in particular a CRC checksum to the data to be stored is thus an important part of the method. As a result, this check information is part of the data to be stored. In the following, this data to be stored will then become secured data to be stored. It typically follows the definition of whether and which first part of this protected data to be stored inverted in the memory or register cells to be stored. In this case, it may be provided, for example, to invert all bits of this data before storage or only certain data or a specific pattern, for example every other bit etc. The provision of patterns with regard to inversion before storage has the advantage that not only stucco At-fault can be detected, but that short circuits between lines can be detected. It is particularly advantageous if the patterns to be used are precalculated due to the previously known at the time of production of the integrated electronic circuit topology of the lines of the integrated microelectronic circuit. Because of this topology, only certain shorts are actually likely or possible.

Also, pattern sequences can be calculated in this way, which should be successively written into the memory cells. The great advantage of the present proposal is that it provides a test method that allows such test patterns to be generated as inverted patterns of payload without interrupting use during operation.

These test patterns can be used to detect bridging faults.

Together with the subsequent filing of the data to be stored in the memory and / or register cells, the filing takes place at least one corresponding additional data information that marks whether and which parts of the protected stored data are to be inverted or not inverted as the first part of the saved stored data or are inverted when they are stored. This additional data information is preferably stored so that its register bits can also be subjected to a check. For example, it is possible to provide three bits, two of which must always include the inverse of the third bit. Now you can invert the third of these bits while reading and check whether all bits have the same value. If this is not the case, this additional data information itself is faulty. This value thus determined can then be used to detect whether a first part of the read data information has been inverted or not. The additional data information should therefore have at least a first status if the first part of the saved stored data is not to be stored inverted or not inverted and has a second status if the first part of the saved stored data is to be inverted or inverted was filed. When storing the data to be stored in the relevant register and / or memory cells, this information is taken into account. This additional data information is modified between different writes to these memories or register cells. Preferably, the net information comprises only one bit, which indicates whether the data to be stored or the stored data should be inverted or are inverted. In that case, the additional data information is inverted between write accesses to the register and / or memory cells. A particular variant provides for a regeneration of the additional data information for each write access to the register and / or memory cells. Here, for example, this regeneration can also be done by a random principle in a random number generator. Depending on the logical content of the additional data information, a non-inverted filing of the first part of the protected data to be stored takes place in a first part of the memory or register cells corresponding to the first part of the protected data to be stored, if the additional data information has a first status and an inverted storage of the first part of the data to be saved to be stored in a first part of the memory or register cells corresponding to the first part of the data to be backed up, if the additional data information has a second status. For the second part of the data to be stored, a non-inverted filing of the second part of the protected data to be stored takes place in a second part of the memory or register cells corresponding to the second part of the protected data to be stored. This second part of the data is not inverted. Thus, no check of the associated second part of the memory and register cells takes place for this second part of the data. These memory and register cells, these second part of the memory and register cells, are different from the memory and register cells of the first part of the memory and register cells.

At a typically later time, the reading of the at least one additional data information from the first and second part of the memory and register cells takes place as read additional data information. On the basis of this read additional data information it is now determined whether and which first part of the saved stored data has been stored inverted in the memory or register cells. Depending on this, the non-inverting reading of a first part of the memory or register cells, which corresponds to the first part of the data of the memory or register cells, then takes place if the read additional data information contains a first state to obtain the first part of the read data or the inverting reading of the first part of the memory or register cells corresponding to the first part of the data of the memory or register cells, if the read additional data information has a second status, to get the first part of the read data. In addition, the non-inverting reading of a second part of the memory or register cells corresponding to the second part of the data of the memory or register cells takes place in order to obtain the second part of the read data. This is then followed by the extraction of the check information from the first part and / or the second part of the read data and the execution of a check of the data for correctness with the aid of this extracted check information. Particularly advantageous is the use of a CRC checksum, which is stored with the data as part of the same, so that at this point in the process a CRC check (CRC check) is performed. The output or processing or provision of an error message occurs when an error occurs during this check.

The proposed method described above has the advantage that the check always takes place and no additional expenditure of time arises up to the gate run times of the additional logic stages. However, it is conceivable to perform a similar test without stored test information such as parity bits or CRC checksums. Instead of the overhead of additional memory and register cells, the overhead is then shifted to the overhead for writing the memory and register cells. The number of memory and register cells required thereby decreases. On the other hand, the test takes place only at the time of writing. Tilting the logical contents of memory and register cells can then not be easily observed. Instead of storing a check information, a written information is verified by reading as soon as possible after the storage of the data in the memory and register cells.

Therefore, a method variant for checking memory or register cells of an integrated circuit for stuck-at errors during operation of this integrated circuit is proposed, which begins as before with the provision of data to be stored. The data to be stored can be divided again into a first part and a second part. This first part and this second part should not overlap. Incidentally, the first part of the data to be stored may completely include the entirety of the data to be stored. In that case, the second part of the data contains no data. The second part of the data to be stored can therefore not include any data. The storage of at least one additional data information in the memory or register cells for marking the first part of the data to be stored is performed as being inverted or inverting during storage. The additional data information again has at least a first status if the first part of the data to be stored of the memory or register cells should not be inverted or is not inverted. The additional data information has at least a second status if the first part of the data of the memory or register cells is to be inverted or inverted. Furthermore, the non-inverted filing of the first part of the data to be stored in a first part of the memory or register cells corresponding to the first part of the data to be stored follows if the additional data information has the first status and the inverted filing of the first part of the data to be filed in the first part of the memory or register cells corresponding to the first part of the data to be stored, if the additional data information has the second status. For the second part of the data to be stored, the non-inverted filing of the second part of the data to be stored takes place in a second part of the memory or register cells corresponding to the second part of the data to be stored. In this case, the first part of the memory or register cells does not overlap with the second part of the memory or register cells. However, in contrast to the method described above, checking for compliant behavior is now not done by checking check information. The check begins again with the reading of the at least one additional data information as read additional data information. It is suggested to determine subsequently whether and which first part of the saved stored data has been stored inverted in the memory or register cells. The proposed method comprises non-inverting reading of a first part of the memory or register cells corresponding to the first part of the data of the memory or register cells when the read additional data information has a first status to obtain the first part of the read data inverting the first portion of the memory or register cells corresponding to the first portion of the data of the memory or register cells when the read additional data information has a second status to obtain the first portion of the read data. As before, the non-inverting reading of a second part of the memory or register cells, corresponding to the second part of the data of the memory or register cells, also takes place in order to obtain the second part of the read data. At least the first part of the read data and the second part of the read data represent the first reading result. Unlike before, however, now does not take place a check of a check information. The writing process is not yet completed, so the first part and the second part of the data to be stored are still known. Therefore, instead of the check information evaluation taking advantage of this fact in this variant of the proposed method, a comparison of the first part and the second part of the data to be stored with the first Reading result with determination of a comparison result. Therefore, the method variant can not be used if this knowledge has already been deleted. The issuance or processing or provision of an error message when an error occurs when the comparison result represents a second reading result deviating from the first part and the second part of the data to be stored is the last step of this method variant to be mentioned here.

The third variant of the method now provides that the write / read cycle described in the preceding variant is performed with a first further data information as the first read / write cycle and then subsequently with a second further data information, which is different from the first further data information, a second time is carried out. In the first write / read cycle, a first reading result is obtained. In the second write / read cycle, a second reading result is obtained. The first and second read results should match. If this is not the case, the output or processing or provision of an error message occurs when such an error occurs. By changing the further data information between the first write / read cycle and the second write / read cycle, other data components are stored inverted in the first write / read cycle than in the second read / write cycle. This is a test effect states.

The basic idea of the proposed method is therefore to store the data content of the memory and register cells to be stored temporally and / or optionally alternately from memory or register cell to memory cell to register cell in an inverted and non-inverted manner. Such storage of the data content to be stored takes place together with the additional data information about the inversion itself. In this case, this additional data information is preferably added to the data content to be stored, that is to say the data to be stored, and thus even subject to this inversion. However, the addition can also be made after the inversion, but this has the disadvantage that the corresponding memory and register cells are not subject to this test as well.

The proposed method can therefore be characterized, for example, by the additional storage of at least one additional bit for displaying completely or partially inverted data. These bits are advantageously included in the CRC / Parity generation. A stucco-at-fault becomes recognizable.

Up to this point, the methods have been described so that memory and register cells could be treated equally. Typically, however, register cells in integrated circuits control state machines or provide data internally used internally within the integrated circuit concerned. Thus, they can typically be used in two directions: on the one hand they can be read from the bus side and on the other hand they can be read from the side of the integrated circuit subcircuit to be controlled. It is therefore advantageous if, even when reading a register from the side of the subcircuit of the integrated circuit to be controlled, the additional data information is evaluated and the information stored in the corresponding register cell is not inverted, ie in the intended polarity, to the subsequent subcircuit to be controlled the integrated circuit is output.

The possible emergency operation results for a single error without the use of test patterns for inversion. As a single error here is considered a memory or register cell whose logical value is fixed to a logical value by a damage and can not be modified as intended by at least one of the scheduled regular procedures in operation and thus is defective. Since the inversion possibility of access to the data content of this single faulty memory or register cell, the polarity of the filing of the binary data can be set in this single faulty memory or register cell, after finding a fault, the additional data information in the memory and register cells always so that the correct logical value for the correct data content of this faulty memory or register cell is always supplied. Thus, the storage of the information originally stored in the individual defective memory or register cell is shifted to the memory locations provided for storing the additional data information. This can be ensured in a single faulty memory or register cell emergency.

Advantage of the invention

A bit in the memory or register cells which can not be changed by one of the above-described methods due to damage to the relevant memory or register cell thus leads, at an early stage, to violation of the integrity check, e.g. through the described CRC check and can thus be displayed or cause further action by a higher-level system.

Advantageously, then the memory and register cells can be used as an emergency function to maintenance in the meantime so that the faulty bit has no effect. The inversion can be used purposefully, that the register would only be inverted, depending on the content to be dropped, if it remains usable!

Optionally, by attempting to store the data with or without inversion, the memory and register cells can be further used in at least one of the two states, which represents a considerable advantage over the prior art.

glossary

Stuck-At Errors and Bridging Faults (source Wikipedia)

1. A) Stuck-at-Faults (dt. Haftfehler) sind Fehler, bei denen Gatter an einem Eingang oder Ausgang auf einem bestimmten Wert feststecken. Je nach dem Wert unterscheidet man Stuck-at-1 oder Stuck-at-O-Fehler.
2. B) Als Bridging-Faults werden Kurzschlüsse zwischen zwei Leitungen bezeichnet. Daraus entstehen neue Funktionen der betroffenen Gatter. Input-Output-Bridging bedeutet, dass Ein- und Ausgänge der Schaltung miteinander verbunden sind (Rückkopplung). Dies führt zu zeitabhängigen Verhalten, z.B. zu oszillierenden Schaltungen.

Physical errors in digital circuits are divided into several classes.

1. A) Stuck-at-faults are faults where tags are stuck at an input or output at a certain value. Depending on the value, a distinction is made between stucco-at-1 or stuck-at-o errors.
2. B) Bridging faults are short circuits between two lines. This results in new functions of the affected gates. Input-output bridging means that the inputs and outputs of the circuit are interconnected (feedback). This leads to time-dependent behavior, eg to oscillating circuits.

Especially with transistors, stucco-off faults (transistor always off), stuck-on faults (transistor always on) and gate-delay faults, as well as path-delay faults, cause signal processing delays.

Claims (3)

A method of checking memory or register cells of an integrated circuit for stuck-at-failure during operation of this integrated circuit, comprising the steps of: - Provision of data to be filed, which can be split into a first part and a second part, and • where this first part and the second part do not overlap and • where the first part of the data to be filed may comprise the entirety of the data to be stored, and • where the second part of the data to be filed can not contain data and Storage of at least one additional data information in the memory or register cells for marking the first part of the data to be stored as inverted, • wherein the additional data information has at least a first status, if the first part of the data to be stored of the memory or register cells should not be inverted, and Wherein the additional data information has at least a second status if the first part of the data of the memory or register cells is to be inverted; non-inverted filing of the first part of the data to be stored in a first part of the memory or register cells corresponding to the first part of the data to be stored, if the additional data information has the first status; - Inverted storage of the first part of the data to be stored in the first part of the data to be stored corresponding first part of the memory or register cells, when the additional data information has the second status; non-inverted filing of the second part of the data to be stored in a second part of the memory or register cells corresponding to the second part of the data to be stored, - wherein the first part of the memory or register cells does not overlap with the second part of the memory or register cells; Reading the at least one additional data information as read additional data information; - determining whether and which first part of the saved stored data has been stored inverted in the memory or register cells; non-inverting reading of a first part of the memory or register cells corresponding to the first part of the data of the memory or register cells when the read additional data information has a first status to obtain the first part of the read data; - inverting the first part of the memory or register cells corresponding to the first part of the data of the memory or register cells, if the read additional data information has a second status to obtain the first part of the read data; non-inverting reading of a second part of the memory or register cells, corresponding to the second part of the data of the memory or register cells, to obtain the second part of the read data; - wherein at least the first part of the read data and the second part of the read data represent the first reading result; - Comparison of the first part and the second part of the data to be stored with the first reading result with determination of a comparison result; - Issuing or processing or providing an error message when an error occurs when the comparison result is a different from the first part and the second part of the data to be stored second reading result. Method according to Claim 1 - Wherein the additional data information contains information about which memory and / or register cells contain an inverted information and which memory and / or register cells contain non-inverted information, in particular with which pattern (inversion pattern) the information in the memory and / or Register cells is inverted. Method according to Claim 2 - Bridging faults are detected by using different inversion patterns at different times.