DE102017109759A1 - Magnetic field sensitive device with a sub-device superconducting at room temperature - Google Patents

Abstract

It is proposed a magnetic field sensitive device with a superconducting sub-device at room temperature. It has at least one sub-device, which comprises a first substrate (GSUB) consisting of at least two layer regions (GR, GB). The first layer region (GB) and the second layer region (GR) are arranged one above the other and have a common interface (GF). The first layer area (GB) consists of graphite with Bernal crystal structure (graphite-2H) with at least 3 atom layers with a respective thickness of exactly one atom. The second layer region (GR) consists of graphite with rhombohedral crystal structure (English rhombohedral, graphite-3R). The interface (GF) has an orientation of its surface normal (nF) parallel to the hexagonal symmetry axis (c) of the crystal lattice of the first layer region (GB) and also an orientation of its surface normal (nF) parallel to the hexagonal symmetry axis (d) of the crystal lattice of the second layer region ( GR). The interface (GF) has superconducting properties. The interface (GF) has a critical temperature (TC) higher than -195 ° C and / or higher than -100 ° C and / or higher than 360 K, and / or a critical magnetic flux density (Bk) at 77K which is higher than 1T and / or 50T. Usually, these boundary layers are superconducting at room temperature. The first substrate (Gsub) is patterned so that the outer edge of the interface (GF) in at least a portion of the first substrate (Gsub) is changed by machining. The interface (GF) has at least one electrical contact provided or adapted to electrically connect the interface (GF) to an electrical conductor. Use in microelectronic integrated circuits, MEMS, MOEMS, etc. is discussed and suggested.

Description

State of the art

Methods for graphite production have long been known from the patent literature. To name here, for example, the US 836 355 A . CA 764 889 A . CA 702 962 A . CA 238 795 A . CA 717 458 A . CA 632 113 A , From the DE 3 602 330 A1 and the CN102 800 382 B the production of graphite fibers is known. The use of graphite for electrical components has long been known. It is reminiscent of Edison's light bulb here.

From the US Pat. No. 8,964,491 B2 a graphene-based memory cell is known. A graphene stack is exposed to various electrical conditions. From this document it is also known that the bandgap of the different graphene stackings (see 3 of the US Pat. No. 8,964,491 B2 and corresponding description in the US Pat. No. 8,964,491 B2 ) may have significantly different band gaps.

This document is the unpublished at the time of application writings DE 10 2017 004 103.2 . DE 10 2017 003 537.7 and DE 10 2017 107 597.6 whose content and disclosure content is fully part of this disclosure. The priority of DE 10 2017 004 103.2 from 07.04.2017 is claimed in this disclosure.

Object of the invention

The invention has for its object to provide a method for producing an electrical, electronic, magnetic or optical component having at least one magnetic field sensitive sensor element / a magnetic field sensitive device, which has at least one sub-structure superconducting at room temperature.

This object is solved by the devices of the claims.

Explanations for the solution of the task

In order to make the reworking possible, a general method for producing an electrical or magnetic or electronic component is first proposed, which should have at least one superconducting component at room temperature. As a material for the superconducting sub-device, the combination of two different graphite modifications is proposed, which in a first process step by providing ( 1 ) of a first substrate (GSub) consisting of at least two layer regions (GB, GR) is achieved. Each of these two layer regions (GB, GR) preferably represents a graphite modification. The first layer region (GB) and the second layer region (GR) are arranged one above the other and have a common interface (GF). The first layer region (GB) consists, for example, of graphite with Bernal crystal structure (graphite 2H) with at least 3 atom layers with a respective thickness of exactly one atom per atomic layer and the second layer region (GR) of graphite with rhombohedral crystal structure ( English rhombohedral, graphite-3R) with at least 3 atomic layers with a respective thickness of exactly one atom per atomic layer. The term first and second layer area can be reversed in reality. The interface (GF) preferably has an orientation of its surface normals ( nF ) parallel to the hexagonal axis of symmetry ( c ) of the crystal lattice of the first layer region (GB). Parallel in the sense of this disclosure means that the orientation of the surface normals ( nF ) of the interface (GF) relative to the hexagonal axis of symmetry ( c ) of the crystal lattice of the first layer region (GB) has a tilt angle of less than 45 °, better less than 20 °, better less than 10 °, better less than 5 °, better less than 2 °, better less than 1 °, better less than 0.5 °, better less than 0.25 °. For the Exact range could so far still no exact investigation be accomplished. For the rework it is therefore recommended to carry out own statistical investigations for the respective graphite source in order to narrow down the area. It is certain that the observed effect occurs with a perfect match. In this respect, production tests are to be provided for a production which sort out non-functioning substrates (GSub). Resistance measurements and measurements with a Magnetic Force Microscope have proven particularly useful. Furthermore, the boundary surface (GF) should have an orientation of its surface normals ( nF ) also parallel to the hexagonal axis of symmetry ( d ) of the crystal lattice of the second layer region (GR). With regard to the tolerances of this parallelism, the prediction also applies here.

The use of these properties of the interfaces between graphene layers of different stacks and the corresponding methods of utilization are not known in the art for use in electrical, electronic, optical or magnetic devices.

It was observed in the preparation of the proposal that the interface (GF) has superconducting properties and the interface (GF) has a critical temperature (T _c ) which is higher than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or a critical magnetic flux density ( B _k In particular, it has been found that the configuration described herein with a boundary layer on two crystals of different graphite modifications appears to have a transition temperature TC of 370 ° K +/- 7 ° K , With the help of a MAFM it could be documented that a once impressively impressed electric current remained constant for weeks. This can only be explained by superconducting effects. This is thus an essential feature of the prior art distinction from which no room temperature superconductivity is known and has been proven beyond doubt at the time of filing this disclosure. In order to produce an electronic, electrical, optical or magnetic component, it makes sense to structure the substrate (GSub) ( 8th ). This can be done in particular by wet-chemical etching (eg dissolved in concentrated sulfuric acid in the potassium di-chromate). One problem of wet-chemical etching is the aggressiveness of the chemicals that are necessary for etching. Therefore structuring by ion or particle beam etching is very useful. This can be done, for example, in an oxygen plasma or in an argon plasma. Another possible and very successful method for producing very small structures is the focussed ion beam etching, which can be carried out reactively using chemically etching atoms and molecules and / or the use of gases which produce a purely mechanical etching (eg argon, etc .). Also a plasma etching is possible. Both RIE methods and DRIE methods can be used here. A wet-chemical etching can be assisted by applying a voltage to the substrate (GSub) to an electrode in the etching bath. Such an electrochemical etching is thus another possibility of structuring such a superconducting graphite substrate (GSub). In addition to these chemical structuring methods, also a cutting shaping by means of one or more chisels with cutting comes into question. Therefore, the structuring can also be done by milling, scribing, turning, grinding, cutting, piercing to produce chips. It is conceivable that several substrates can be combined by pressing and / or sintering into a larger whole. One variant of plasma etching that is possible is spark erosion. By amorphizing, for example by means of a carbon ion beam or an ion beam from another element or from molecules, the crystal structure can be locally destroyed, whereby the interface as such is destroyed and the superconducting region is limited or patterned. In order to be able to connect the substrate later, it is provided with electrical contacts in at least one further method step. It is therefore a process step of providing ( 13 ) of contacts of the interface (GF).

In the preparation of the proposed method, it has been found that it makes sense to align them before processing the substrates (GSub). Therefore, an improved method of making a proposed device includes the Step of ascertaining ( 2 ) the orientation of the surface normals ( nF ) of the interface (GF) within the substrate (GSub). This orientation can be done for example by means of an X-ray diffraction analysis. Other methods are conceivable. Thus, graphite can preferably be split along the atomic layers. Such an orientation step can therefore also take the form that some atomic layers are split off on one side of the graphite layer package. The remaining surface is then preferably perpendicular to the surface normal of the interface.

It has been shown in the use of natural graphite that not all graphite substrates have the desired room temperature superconductivity. In the case of sheet-like samples, to determine the superconducting region at room temperature, the sample was first heated and then magnetized with the aid of a sufficiently strong permanent magnet. This resulted in a circular current, which by means of a Magnetic Force Microscope ( MFM ) could be detected.

It is therefore advantageous, by means of such a measuring means in the process step ( 2 ) the position of the superconducting region of the interface ( G _F ) within the substrate (GSub) by means of a Magnetic Force Microscope ( MFM ) or another suitable measuring means for the distribution of a magnetic flux density or field strength and to identify the superconducting region.

In general, the substrate (GSub) is not present in the desired shape. Therefore, it is advantageous to thin the layer regions (GR, GB). Such a process step of thinning ( 3 ) of a layer region (GB, GR), hereinafter the "relevant layer region", and the creation of a lower boundary surface (FIG. UGF ) parallel to the interface (GF) is therefore a preferred component of the proposed method. The minimum thickness of the relevant layer area, which is thinned out, should not be less than three atomic layers. Better is a thinning on more than 6, better 10, better 20, better 50, better 100 atomic layers. The thinning can be done, for example, with the methods that are also used in structuring. These would be, for example, but not limited to, wet-chemical etching, ion or particle beam etching, focussed ion beam etching, plasma etching with RIE and / or DRIE etching, electrochemical etching, machining and spark erosion. The procedural possibilities of thinning are not limited to this but certainly. Particularly noteworthy here would be particularly precise methods such as lapping and electrochemical polishing and polishing with hot metal discs, in which carbon dissolves in the metal during contact with the graphite.

Now that one of the layer regions (GR, GB) has been thinned to such an extent that it can be further structured, for example, by photolithographic processes, the substrate (GSub) is now proposed in a variant of the method for producing the electrical component after thinning out the relevant layer region the two layer areas (GR, GB) with the resulting, typically almost ideally smooth surface in a further step on the surface ( OF ) of a carrier ( 1 ) or to place. It is therefore the process step of application ( 4 ) of the thinned substrate (GSub) on the surface ( OF ) of a carrier ( 1 ).

Provided that the surface of the substrate (GSub) produced during the thinning was ideally polished, and the surface ( OF ) of the carrier ( 1 ) is also ideal, can already Van-der-Valsche forces between these surfaces act and lead to a welding of the surfaces. In this case, it would be a fixing ( 5 ) of the thinned substrate (GSub) on the surface ( OF ) of the carrier ( 1 ) act by adhesion. However, it has been found that, as a rule, the outlay for achieving this precision of the surface treatment is too great and / or the work result is too unreliable. Therefore, it usually makes sense in a process step of fastening ( 5 ) of the thinned substrate (GSub) on the surface ( OF ) of the carrier ( 1 by forming a carbide (by temperature treatment in an oven and choice of a carbide-forming material of the carrier ( 1 ) make the connection more reliable. Also, the formation of a eutectic is conceivable instead. Finally, gluing or welding, in particular laser welding, come into question. In the latter case, the use of a shielding gas or working in a vacuum, as in all temperature treatments of graphite is indicated.

After the respective layer region of the layer regions (GR, GB) has been thinned, it now mostly makes sense to also thin out the not yet thinned layer region of the two layer regions (GB, GR). The proposed method is therefore preferred by a further process step of thinning ( 6 ) of the other layer area (GR, GB), hereinafter the "other layer area", which is not the layer area concerned, extended. This results in the creation of an upper interface ( OGF ) parallel to the interface (GF). Again, the same minimum thickness of the other layer area should be adhered to as in the layer area concerned. The minimum thickness of the other layer area, which is also thinned, should not fall below three atomic layers. Better is a thinning on more than 6, better 10, better 20, better 50, better 100 atomic layers. Thinning can be done, for example, again with the methods that are also used in the structuring. Again, such as, but not limited to, wet chemical etching, ion or particle beam etching, focussed ion beam etching, plasma etch with RIE and / or DRIE etch, electrochemical etch, machining and spark erosion , The procedural possibilities of thinning the other layer area are not limited thereto. Particularly noteworthy here are again particularly precise methods such as lapping and electrochemical polishing and polishing with hot metal discs, in which carbon dissolves in the metal during contact with the graphite.

• • spanerzeugende Formgebung und/oder
• • Polieren und/oder
• • Schleifen und/oder
• • Elektrochemisches Polieren und/oder
• • Chemisch mechanisches Polieren (CMP) und/oder
• • Nasschemisches Ätzen und/oder
• • Ionenätzung
• • Teilchenstrahlätzung
• • Chemische Ätzung
• • Plasmaätzung

In general, process variants are characterized in that process steps for thinning out layer regions (GR, GB) by using at least one of the following processes include:

• • chip-forming design and / or
• • Polishing and / or
• • grinding and / or
• Electrochemical polishing and / or
• • chemical mechanical polishing ( CMP ) and or
• Wet-chemical etching and / or
• • Ion etching
• • particle beam etching
• • Chemical etching
• • Plasma etching

It has now been recognized that it makes sense that such a created electrical, electronic, optical or magnetic device can be combined with conventional circuits. For example, it may be useful to provide a conventional circuit in the form of deployment ( 7 ) of a second substrate ( SUB ) for this combination. This second substrate ( SUB ) may be electrically insulating or electrically normal conducting or electrically semiconducting of the p-type or electrically semiconducting of the n-type or electrically be metallically conductive. The second substrate ( SUB ) can with the carrier ( 1 ) be identical. The carrier ( 1 ) but also, for example, again on the second substrate ( SUB ) by gluing etc. are attached. Of course, this process variant also comprises carrying out the process as described above. In this case, the sequence of the method steps may in particular be what the provision of the second substrate ( SUB ), be amended. If it is a completely or partially semiconducting substrate, for example an integrated circuit, it makes sense if the second substrate (sub) comprises at least one semiconductive electronic component. For example, but not limited to:

Wires, Contacts, Through-Through-Vias, TSV ), Junctions, insulating layers, diodes, PN diodes, Schottky diodes, ohmic resistors, transistors, PNP and / or PNP bipolar transistors, n- or p-channel MOS transistors, diacs, triacs, pip, - or nin or pin diodes, solar cells, etc.

The substrate ( SUB ) may also include more complex structures such as logic gates, amplifiers, filters, operational amplifiers, multipliers, analog-to-digital converters, reference voltage and current sources, current mirrors, differential amplifiers, digital-to-analog converters, comparators, memories, microcomputers, oscillators etc. have. In addition to these purely electronic and microelectronic subdevices, the second substrate ( SUB ) may also be modified in a different way simultaneously or alternatively, so that it has fluidic and / or microfluidic and / or optical and / or micro-optical sub-devices. For example, it is conceivable to take advantage of the MHD effect in such a device. Furthermore, it may be that the second substrate ( SUB ) another electronic and / or electrical component, in particular but not limited thereto, a flat coil or a capacitor, which in microstructure on the second substrate or in this second substrate ( SUB ) is made. In order to produce a wiring or contacting, it is initially appropriate to apply by means of 9 ) at least one electrically conductive layer on the first substrate (GSUB) or second substrate ( SUB ) to make the contacts. In this case, the electrically conductive layer may be electrically normal-conducting or electrically semiconducting of the p-type conductivity or electrically semiconducting of the n-type conductivity or electrically conductive metal. In particular, it can also be an amorphous or polycrystalline semiconductor, for example silicon or germanium or diamond or diamond-like layers ( DLC ) act. It is conceivable to embed in such a semiconducting layer semiconducting electronic components such as diodes, transistors and resistors. Parts of such a semiconductive layer may therefore have a different doping and thus a different conductivity type than other parts of the same semiconducting layer. Also, the resistivities and / or the mobility and / or the carrier density and / or the dopant density and / or the density of the traps may vary within such a semiconductive layer. In order to be able to wire the components well, it is expedient to structure them in particular by means of photo and / or ion beam lithographic methods. From the prior art, these methods are well known, which is why a further description is omitted here. Thus, the proposed method in this case also includes the structuring ( 10 ) of at least one electrically conductive, in particular electrically normal conductive layer, for example, to produce interconnects. It should be noted here that conductor tracks can also be produced from highly doped semiconductor material. In order not to short-circuit these conductor tracks through the first substrate (GSub), it is expedient if it is electrically insulated from the graphite body of the first substrate (GSub). For this purpose, it is useful before applying the normal conductive layer, the application ( 11 ) to perform at least one electrically insulating layer on the first or second substrate or on an electrically normal conductive layer. For this purpose, for example, silicon dioxide or other insulating materials, such as silicon nitride are suitable. It is also conceivable to use preferably photolithographically structurable plastics such as polyimide for this purpose. Typically, the opening of the electrical contacts is then necessary. This can be done by structuring ( 12 ) of the at least one insulating layer.

Around the In order to actually make electrical contact, it is typically necessary for the electrically conductive layer to be in direct mechanical contact with the first substrate (GSub) at at least one location. Preferably, this should not only be a mechanical, but also an electrical contact. Also, the insulating layer must be mechanically supported by the first substrate (GSub). The electrically insulating layer is therefore in direct mechanical contact with the first substrate (GSub) at at least one location. The structuring ( 9 . 11 ) of the insulating layer, such as that of the electrically conductive or semiconducting layer, preferably photolithographically and / or wet-chemically and / or by plasma etching and / or ion and particle beam bombardment and / or amorphization and / or e-beam irradiation and / or laser irradiation and / or mechanical cutting processes and / or forming processes, which in a structuring, the Structuring of the interface includes, combined with a tearing of the interface (GF).

As a result of the exemplary manufacturing process described above results in an electrical or optical or magnetic or electronic device comprising at least one sub-device comprising a first substrate (GSub) consisting of at least two layer regions (GR, GB), wherein the first layer region (GB ) and the second layer region (GR) are arranged one above the other and have a common interface (GF). When talking about each other in this disclosure, it is meant that with appropriate orientation of the overall package, the respective layer areas are superimposed. Therefore, the overall package may also be rotated to other orientations without departing from the disclosure and claim content of this disclosure due to this different orientation. The first layer area (GB) of the subassembly consists of graphite with Bernal crystal structure (graphite-2H) with at least 3 atomic layers with a respective thickness of exactly one atom. The second layer region (GR) of the sub-device consists of graphite with rhombohedral crystal structure (English rhombohedral, graphite-3R) with at least 3 atom layers with a respective thickness of exactly one atom. The interface (GF) preferably again has an orientation of its surface normals ( nF ) parallel to the hexagonal axis of symmetry ( c ) of the crystal lattice of the first layer region (GB). The interface (GF) furthermore has an orientation of its surface normals (n _F ) parallel to the hexagonal axis of symmetry (FIG. d ) of the crystal lattice of the second layer region ( G _R ) on. The interface (GF) has in contrast to the prior art superconducting properties. The interface (GF) has a transition temperature ( T _C ) which is higher than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or a critical magnetic flux density ( B _k ) at 77 K, which is higher than 1T and / or 50T. In order to make it possible to contact the interface, the first substrate (GSub) is structured in such a way that the outer edge of the interface (GF) is modified by machining in at least one subregion of the first substrate (GSub). Preferably, this edge region of the first substrate (GSub) is changed so that, for example, by bevels the interface ( G _F ) is open and can be contacted by Metalldeposition. In order to connect the component, it is useful if the interface ( G _F ) has at least one electrical contact with which is provided or suitable, the interface ( G _F ) electrically connect to an electrical conductor.

In order to obtain a suitable signal from the component, the component is supplied with electrical energy by means of a method for operating an electrical or optical or magnetic or electronic component. For this purpose, the proposed electrical or magnetic or electronic component is provided. The proposed method for operating a proposed electrical or optical or magnetic or electronic component is characterized inter alia by the fact that the component has a superconducting partial device with a transition temperature ( T _C ) which is higher than -196 ° C and / or a critical magnetic flux density ( B _k ) at 77 K, which is higher than 1T and / or 50 T. By energizing the electrical component at a temperature ( T ), which is above -196 ° C, an electric current flow is caused in the electrical or optical or magnetic or electronic component. In this case, it is advantageous for the component to be initially at a temperature above the critical temperature ( T _C ) and then to operate below the critical temperature, but still above -195 ° C. In this case, then occurs within the superconducting layer, the interface (GF), a current flow. On the basis of such a superconducting at room temperature layer can thus define an electrical component, which is characterized in that it comprises at least one sub-device having an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77K higher than 1T and / or 50T. Preferably, it has as electrical superconductor carbon, preferably in crystalline form, preferably in rhombohedral crystal structure (graphite 3R) and / or in Bernal crystal structure (graphite 2H). It is preferably provided in a first intended operating state at a working temperature ( Ta ) above the transition temperature (Tc) and in a second intended operating condition at a working temperature ( Ta ) below the transition temperature (Tc).

Such a superconducting device can be realized by utilizing the critical temperature ( T _C ) can be used as a temperature sensor. A proposed temperature sensor is accordingly characterized in that it comprises an electrical component as previously proposed, which has at least one superconductive subdevice as described above. In such a proposed electrical device, its conductivity depends on an external magnetic field. This dependence can abruptly by exceeding the critical magnetic field strength ( B _k ) or by slow penetration of the magnetic flux lines into the superconductor. Of particular interest are annular and / or spiral Structures in particular in connection with flat coils and / or Josephson contacts. Such structures are characterized in that the superconducting substructure of such a device has a topological gender greater than zero. This means that the superconducting structure has at least one hole completely surrounded by the superconductor. For the purposes of this disclosure, therefore, for example, annular superconductors are included, which are interrupted, for example, at one or two or more points, for example, by tunneling for charge carriers. Even such constructions should be covered by the topological gender 0.

The simplest electronic component that can be realized by the method outlined above is that of an electrical lead. For this purpose, for example, the first substrate (GSub), as described on both sides thinned and on a second substrate ( SUB ) mounted as a carrier. The crystal edges are worked parallel to the line direction left and right of the center line of the line through the structuring so that preferably only the line as such on the second substrate ( SUB ) remains. Possibly. the line is connected at its two ends as described above by means of metal deposition and subsequent preferably photolithographic structuring of this metal. Of course, it is also conceivable, for example, to machine a first substrate mechanically such that, for example, an elongated rod results, wherein the vector of the bar direction is parallel to a plane vector of the interface (GF) which is parallel to this interface (GF), whereby the rod is split in half, the first layer region ( G _B ) and the second layer area ( G _R ) is shared. The electrical contacts can also be made in such a case by metal caps, which are placed on the rod at its respective ends.

Since a magnetic field occurs during the current flow, it is possible by means of a first such line, when it is guided at a distance to a second such line, to change electrical properties of the first line by the current flow in the second line. In this case, the second line may also be a subsection of another proposed device comprising a room temperature superconductor as a functional sub-device. Instead of a ring structure, it is conceivable not to produce the component in planar technology. The production of graphite with a high proportion of rhombohedral graphite is known, for example, from the patent families of AU 2015 234 343 A1 , of the EP 2 982 646 A1 and the JP 5 697 067 B1 known.

It is particularly advantageous if, based on the proposed device, a line superconducting at room temperature is produced. This should then preferably be cylindrical and be graphitized all around. In such a line, at least one superconducting substructure should preferably be cylindrical.

Such a proposed electrical component with a sub-structure superconducting at room temperature, for example, but not just an electrical coil or in special cases a flat coil. Two such coils can be combined to form a superconducting signal and / or energy superconducting at room temperature. If a cylinder with bernal and rhombohedral graphite is alternately coated circumferentially and, for example, a spiral trench is milled into the resulting graphite layer package, which electrically cuts it, then a room-temperature superconducting cylindrical coil is obtained.

From microwave technology microstrip lines are known. It is therefore proposed to produce such microstrip lines by means of superconducting partial structures at room temperature. The practicable method has been described above. In many applications, no transformer is needed, but an efficient antenna or other RF device that works as lossless as possible. It is therefore proposed to produce resonators, in particular microwave resonator and / or THz resonators and / or antennas, and / or an oscillator with at least partial devices from a superconducting material at room temperature. Here, for example, the above-mentioned method can be used.

Furthermore, it is proposed to use the use of such at room temperature superconducting sub-devices as components of electrical capacitors. For example, the leads and / or the capacitor plates may be made from the room temperature superconducting material described above.

A device can now be made to freeze a given magnetic flux. If it is combined with a sensor for evaluating the magnetic flux, the component has a bistable behavior.

A particularly important component in this context is a Josephson diode. To produce such a Josephson diode, for example, a superconducting conductor at room temperature is cut by means of a focused ion beam or electron beam and the separation point is filled with a few atomic layers of an insulator. The layers are so close to each other that tunneling of the charge carriers is still possible. Such a structure has a bistable behavior. From the DE 2 434 997 It is known that on the basis of such Josephson diodes Josephson memory can be produced.

On the basis of such a room temperature superconducting device quantum register bits can be produced.

On the basis of what has been said so far, it is also possible to produce optical components which have at least one sub-device which has an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C. and / or higher than -100 ° C. and / or higher than -100 ° C. 50 ° C and / or higher than 360 ° K and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77K higher than 1T and / or 50T.

Likewise, magnetic components are proposed here, which have at least one sub-device, each having at least one electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C. and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77K higher than 1T and / or 50T.

It is intended, at a temperature below the critical temperature (T _c ) and / or at an external magnetic field below the critical magnetic flux density ( B _k ) to be operated. When used as intended, the proposed magnetic component has a permanent magnetic field with a magnetic flux density ( B ) of more than 5μT.

One such proposed magnetic device is a flux quantum generator. In this context, be on the DE 28 43 647 directed.

Such a device can also be used in electrical machines. In particular, such components can be used for measuring the magnetic field and thus for determining the rotor position. It is therefore proposed an electric machine, which may be a rotating machine or a linear motor having at least one sub-device - for example, an electromagnetically operating sensor for rotor position determination - which itself has a sub-device, which is an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77 K is higher than 1T and / or 50 T, whereby the electrical machine in question also has this property. The sensor and thus the superconducting sub-device may be part of a rotor and / or a rotor or a stator of the machine.

Such magnetic sensors, with at least one at room temperature superconducting sub-device, an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77K higher than 1T and / or 50T, are of particular interest to medical technology due to their sensitivity. For example, they can be used as sensors and antennas for NMR Plants etc. are used.

For the same reason, it is proposed to equip mobile devices with such sensors. The proposed mobile device therefore has at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher as 360 ° K and / or the critical magnetic flux density ( B _k ) at 77 K is higher than 1T and / or 50T. However, such a sub-device can also be, for example, an energy store for the mobile device.

Therefore, an energy storage is proposed, the energy stores, for example in the form of a superconducting circulating current. Such an energy store is characterized in that it comprises at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C. and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77 K is higher than 1T and / or 50T.

Description of the Hall component

The Hall component is an electronic component with a Hall measurement structure. Advantageously, recourse can be had to semiconductor semiconducting structures available in the prior art. For the purposes of this proposal, it is possible to replace the Hall device with another magnetic field-sensitive electronic component, such as a GMR resistor or an AMR sensor. More generally, therefore, an electronic component is proposed which has an electronic sub-device which changes an electrical parameter as a function of a magnetic field size or of another parameter of the electromagnetic field and thus can serve as a magnetic field sensor.

On this sub-device, so for example, the said Hall structure, the above-described superconducting substrate is applied at room temperature. This can be, for example, but not only by sticking or clamping with a non-magnetic material. As a result, the electronic component, preferably in its immediate vicinity at least one sub-device, which is an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or and / or higher than 360 ° K. Another equality may be that the critical magnetic flux density ( B _k ) at 77 K is higher than 1T and / or 50T. Preferably, the device described above is manufactured by using the previously described graphite structure. In that case, the first sub-device is then a first substrate ( G _sub ) consisting of at least two layer regions ( G _B . G _R ), wherein the first layer region ( G _B ) and the second layer area ( G _R ) are arranged one above the other and have a common interface ( G _F ) and wherein at least the first layer region (GB) or the second layer region ( G _R ) is disposed above the Hall measurement structure. In the case of the use of another magnetic field-sensitive electronic component instead of a Hall structure, for example a GMR resistor or an AMR sensor, then at least the first layer region (GB) or the second layer region (FIG. G _R ) is disposed above or near the magnetic field sensitive substructure of the other magnetic field sensitive electronic device used in place of a Hall structure. Nearby means that a magnetic field of the room-temperature superconducting structure can act on the magnetic field-sensitive substructure of the other magnetic field sensitive electronic component used in place of a Hall structure, such that one electric of the other for Magnetic fields of sensitive electronic component, which is used in place of a Hall structure, is measurably changed as a function of or in correlation with the magnetic field of the room temperature superconducting structure.

The first layer area ( G _B ) then again consists of graphite with Bernal crystal structure (graphite-2H) with at least 3 atomic layers with a respective thickness of exactly one atom per atomic layer and the second layer region ( G _R ) of graphite with rhombohedral crystal structure (English rhombohedral, graphite-3R) with at least 3 atom layers with a respective thickness of exactly one atom per atomic layer.

The interface ( G _F ) preferably has an orientation of its surface normal (n _F ) parallel to the hexagonal axis of symmetry ( c ) of the crystal lattice of the first layer region ( G _B ) on.

The interface ( G _F ) preferably has an orientation of its surface normal (n _F ) parallel to the hexagonal axis of symmetry ( d ) of the crystal lattice of the second layer region ( G _R ) on.

The interface ( G _F ) then again has at least partially superconducting properties and wherein the interface ( G _F ) at least partially has a transition temperature (T _c ) which is higher than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or critical magnetic flux density (Bk) at 77 K, which is higher than 1T and / or 50 T.

Experiments have shown that it may be sufficient if the electronic component has at least one subdevice that has an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C. and / or higher than -100 ° C. and / or higher than -50 ° C and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) is greater than 1T and / or 50T at 77K and this first subdevice is a first substrate ( G _sub ) consisting of at least two layer regions ( G _B . G _R ). The first layer area ( G _B ) and the second layer area ( G _R ) are arranged one above the other and have a common interface ( G _F ) on. At least the first layer area ( G _B ) or the second layer area ( G _R ) are arranged above the Hall structure or the. In certain cases, it is sufficient if the first layer region (GB) is a carbon crystal having a first crystal structure and the second layer region (GR) is a second carbon crystal having a first or second crystal structure and between the first crystal and the second Crystal an interface (GF) is formed. It has been found that doping, in particular with boron, and / or partial graphitization may in some cases lead to the interface ( G _F ) has at least partially superconducting properties and the interface ( G _F ) at least partially has a transition temperature (TC) which is higher than -195 ° C or higher than -100 ° C and higher than -50 ° C and / or higher than 360 ° K and / or a critical magnetic flux density (TC). Bk) at 77K, which is higher than 1T and / or 50T. However, the reproducibility was low at the time of disclosure. The doping with boron serves for the electrical connection of the boundary layer. At least the first layer area ( G _B ) or the second layer area ( G _R ) is preferably arranged above or in the vicinity of a Hall measurement structure or another magnetic field sensitive sensor or sensor element. In this case proximity means that a magnetic field is caused by a current in the interface ( G _F ) or the first layer area ( G _B ) or the second layer area ( G _R ), a parameter, in particular a measurement signal, the Hall measurement structure or the other magnetic field sensitive sensor or sensor element can change.

It will be apparent to those skilled in the art that, based on this basic principle disclosed herein, any prior art integrated circuit may be combined with the room temperature superconducting substrate described above. For this purpose, the above-described, at room temperature superconducting substrate is applied to the integrated circuit. This can happen, for example, but not only by sticking or clamping with a non-magnetic material. As a result, the integrated electronic circuit, at least one sub-device, which has an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77 K is higher than 1T and / or 50T. This is advantageous, for example, when the signal of the Hall element is to be amplified. Preferably, the device described above is manufactured by using the previously described graphite structure. In that case, the first sub-device is then a first substrate ( G _sub ) consisting of at least two layer regions ( G _B . G _R ), wherein the first layer region ( G _B ) and the second layer area ( G _R ) are arranged one above the other and have a common interface ( G _F ) and wherein at least the first layer region (GB) or the second layer region ( G _R ) is disposed on a surface of the integrated circuit.

Advantage of the invention

The proposed methods and devices, the energy loss free use of superconducting electrical conductors at room temperature together with magnetic sensitive sensor elements is possible. The advantages are not limited to this. For example, such a device can be used as an information store. In this case, the superconducting partial device stores the information, while the magnetic field-sensitive sensor element can read the information.

Description of the figures

The figures represent schematically simplified Prinziskizzen.

FIG. 1

1 shows for an exemplary proposed manufacturing method the first step of deployment ( 1 ) of a substrate (GSub).

FIG. 2

2 shows the third step of thinning ( 3 ) of a "relevant" layer area (GB, GR), here the first layer area (GB) and creation of a lower boundary area ( UGF ) parallel to the interface (GF) after already determined ( 2 ) the orientation of the surface normals ( nF ) of the interface (GF) within the substrate (GSub).

FIG. 3

3 the step of fixing ( 5 ) of the preferably thinned substrate (GSub) on the surface ( OF ) of the carrier ( 1 ) after application ( 4 ) of the preferably thinned substrate (GSub) onto the surface ( OF ) of a carrier ( 1 ).

FIG. 4

4 shows the thinning ( 6 ) of the other layer region (GR, GB), which is not the relevant layer region, here the second layer region (GR).

FIG. 5

5 shows the exemplary structuring ( 8th ) of the first substrate (GSub).

FIG. 6

5 shows the exemplary structuring ( 8th ) of the first substrate (GSub) with exemplary beveling of the etched edges by a suitable choice of the process parameters.

FIG. 7

5 shows the exemplary application ( 9 ) at least one electrically conductive layer ( ELS ) on the first substrate (GSub) to make the contacts.

FIG. 8

8th shows the exemplary structuring ( 10 ) of the at least one electrically conductive layer ( ELS ).

FIG. 9

9 shows the exemplary application ( 11 ) at least one electrically insulating layer ( IS ) on the first substrate (GSub) or the carrier ( 1 ) or the electrically, in particular normally conductive layer ( ELS ).

FIG. 10

10 shows the exemplary structuring ( 12 ) of the at least one insulating layer ( IS ) eg for opening the contacts or vias.

FIG. 11

• Bereitstellen (1) eines ersten Substrats (GSub) bestehend aus zumindest zwei Schichtbereichen (GB, GR);
• Feststellens (2) der Orientierung der Flächennormalen (nF) der Grenzfläche (GF) innerhalb des Substrats (GSub);
• Abdünnen (3) eines „betreffenden“ Schichtbereiches (GB, GR) und Schaffung einer unteren Grenzfläche (UGF) parallel zur Grenzfläche (GF);
• Aufbringen des vorzugsweise abgedünnten Substrats (GSub) auf die Oberfläche (OF) eines Trägers (Sub1);
• Befestigen des vorzugsweise abgedünnten Substrats (GSub) an der Oberfläche (OF) des Trägers (Sub1);
• Abdünnen des anderen Schichtbereiches (GR, GB), der nicht der betreffende Schichtbereich ist;
• Bereitstellung eines zweiten Substrates (SUB), beispielsweise in Form einer mikroelektronischen Schaltung;
• Strukturierung des ersten Substrats (GSub);
• Aufbringen mindestens einer elektrisch leitenden Schicht auf das erste Substrat (GSub) oder auf das zweite Substrat (SUB), beispielsweise um die Kontakte herzustellen;
• Strukturierung der mindestens einen elektrisch leitenden Schicht;
• Aufbringen mindestens einer elektrisch isolierenden Schicht auf das erste Substrat (GSub) oder zweite Substrat (SUB) oder den Träger (Sub1) oder auf eine elektrisch, insbesondere normal, leitende Schicht durchzuführen;
• Strukturierung der mindestens einen isolierenden Schicht z.B. zum Öffnen der Kontakte oder von Durchkontaktierungen;
• Bereitstellen der Kontakte der Grenzfläche (GF).

11 shows an exemplary sequence of steps for the preparation of the proposed devices:

• Provide ( 1 ) of a first substrate (GSub) consisting of at least two layer regions (GB, GR);
• Ascertaining 2 ) the orientation of the surface normals ( nF ) of the interface (GF) within the substrate (GSub);
• Thinning ( 3 ) of a 'relevant' stratum (GB, GR) and creation of a lower interface ( UGF ) parallel to the interface (GF);
• Application of the preferably thinned substrate (GSub) to the surface ( OF ) of a carrier ( 1 );
• Attaching the preferably thinned substrate (GSub) to the surface ( OF ) of the carrier ( 1 );
• Thinning of the other layer area (GR, GB), which is not the layer area concerned;
• Provision of a second substrate ( SUB ), for example in the form of a microelectronic circuit;
• Structuring of the first substrate (GSub);
• Applying at least one electrically conductive layer to the first substrate (GSub) or to the second substrate ( SUB ), for example, to make the contacts;
• Structuring the at least one electrically conductive layer;
• Applying at least one electrically insulating layer to the first substrate (GSub) or second substrate ( SUB ) or the carrier ( 1 ) or on an electrically, in particular normal, conductive layer perform;
• Structuring of the at least one insulating layer, eg for opening the contacts or plated-through holes;
• Providing the contacts of the interface (GF).

FIG. 12

12 shows a Josephson diode in cross section. The exemplary first substrate (GSub) from 4 is through the tunneling element (TU), for example, a few atomic layers thick oxide, cut through.

FIG. 13

13 shows the exemplary electrical device based on the Josephson contact 12 in the supervision. The first substrate (GSub) is structured so that an annular structure results. The two branches are interrupted by a respective Josephson diode (TU1, TU2). With current flow (I), the voltage drop depends on the magnetic field perpendicular to the image surface.

FIG. 14

14 shows a schematic, simplified cross section through an integrated microelectronic circuit with a Hall structure ( HL ), which is part of the integrated circuit as a magnetic field sensitive part device. The Hall structure ( HL ) is manufactured in a semiconducting carrier (Sub ₁ ). The Hall structure ( HL ) is protected by an isolator ( OX ) protected. Other insulators are conceivable. Also, whole metal / oxide stacks are used as insulator ( OX ) conceivable. Various wiring systems for integrated circuits are known in the prior art.

The Hall structure is in this example via contacts ( K1 . K2 ) contactable. By means of an adhesive ( GL ), the superconducting layer package, the first substrate ( G _sub With G _B . G _R . G _F ) with the actually superconducting interface on the carrier (Sub ₁ ) with the Hall structure ( HL ) attached. On this sub-device, so for example, the said carrier (Sub ₁ ) with the said Hall structure ( HL ) is thus the above-described, at room temperature superconducting first substrate ( G _B . G _R . G _F ) Was applied. This can, for example, but not only by sticking or clamping with a non-magnetic material, here the adhesive ( GL ) happen. As a result, the Hall structure ( HL ) as a magnetic field sensitive electronic component, in its immediate vicinity at least one sub-device, which is an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or the critical magnetic flux density ( B _k ) at 77 K is higher than 1T and / or 50T. The superconducting layer package ( G _sub ) consists, as before, of at least two layer regions ( G _B . G _R ), wherein the first layer region ( G _B ) and the second layer area ( G _R ) are arranged one above the other and have a common interface ( G _F ) and wherein at least the first layer region (GB) or the second layer region ( G _R ) above the Hall structure ( HL ) is arranged. The first layer area ( G _B ) and the second layer area ( G _R ) can change their position.

The first layer area ( G _B ) then again consists of graphite with Bernal crystal structure (graphite-2H) with at least 3 atomic layers with a respective thickness of exactly one atom per atomic layer and the second layer region ( G _R ) of graphite with rhombohedral crystal structure (English rhombohedral, graphite-3R) with at least 3 atom layers with a respective thickness of exactly one atom per atomic layer.

The interface ( G _F ) preferably has an orientation of its surface normal (n _F ) parallel to the hexagonal axis of symmetry ( c ) of the crystal lattice of the first layer region ( G _B ) on.

The interface ( G _F ) preferably has an orientation of its surface normal (n _F ) parallel to the hexagonal axis of symmetry ( d ) of the crystal lattice of the second layer region ( G _R ) on.

The interface ( G _F ) then again has at least partially superconducting properties. The interface ( G _F ) then typically at least partially has a critical temperature (T _c ) higher than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or a critical magnetic flux density (Bk) at 77 K, which is higher than 1T and / or 50 T.

It has been shown in laboratory experiments that thinning of the graphite layers is not always necessary depending on the starting material.

By a first contact doping (KD1) and a second contact doping (KD2) is in the example of the Hall structure ( HL ) of the 14 this Hall structure ( HL ) electrically via the first contact ( K1 ) and the second contact ( K2 ) contacted. These dopants of the substrate of the carrier ( 1 ) are usually carried out with a very high dopant concentration in order to avoid ohmic contacts ( K1 . K2 ). Is the semiconducting substrate of the support ( 1 ) of a first conductivity type, for example a p-doped silicon substrate, as is common in CMOS circuits, the Hall structure ( HL ), if not placed in a separate well, of a second conductivity type opposite to the first conductivity type, eg, a weakly n-doped silicon structure within the semiconductive substrate of the support ( 1 ). In this case, the contact dopants (KD1, KD2) are likewise of a second conductivity type, which is opposite to the first conductivity type, ie, for example, highly n-doped silicon structures within the semiconductive substrate of the support (FIG. 1 ) in contact with the Hall structure (HK) and the metal of the contacts ( K1 . K2 ) stand. It will be apparent to those skilled in the art that prior to application of the substrate (G _sub ) to the support ( 1 ) the carrier may have been subjected to a microtechnical process, wherein on or in the carrier microelectronic circuits and / or micromechanical devices and / or micro-optical devices and / or microfluidic devices may have been manufactured.

FIG. 15

15 based on 14 , In contrast to 14 shows 15 now an exemplary more complex metallization stack. This consists of a first insulating layer, preferably a first oxide ( OX1 ), which is preferably a gate oxide, and a second insulating layer ( OX2 ), preferably a second oxide. Between the first insulation layer ( OX1 ) and the second insulation layer ( OX2 ) are two exemplary tracks ( L1 . L2 ). Now there is an interaction between the current flow in the interconnects ( L1 . L2 ) and the room temperature superconducting interface G _F of the substrate G _sub , The inductance coating of the printed conductors ( L1 . L2 ) is changed by the proximity of the room temperature superconducting substrate (G _sub ).

FIG. 16

16 equals to 15 with the difference that the substrate ( G _sub ) now via a third line ( L3 ) is photolithographically connected. This prevents the substrate ( G _sub ) can charge statically.

FIG. 17

17 schematically shows an exemplary combined microfluidic / micromechanical devices with an exemplary semiconductor substrate as a carrier (Sub ₁ ). The metallization stack of 15 is now performed more complex to run in this example, the micromechanical and microfluidic devices in the metallization stack. It is known from the prior art that the implementation of micromechanical / microfluidic components can also take place in the substrate of the carrier (Sub ₁ ). For example, the metallization stack may include layers of metals such as titanium, tungsten, gold, platinum, aluminum, iron, niobium, vanadium, manganese, etc., insulators such as silicon nitride, silicon oxide, etc., of amorphous or polycrystalline semiconductor layers, such as polycrystalline ones Silicon - also called poly - or amorphous silicon or crystalline silicon or other corresponding semiconductor materials. This layer stack can therefore be generated at least in part by bonding different substrates to one another. In the example of 17 are a first insulator layer ( OX1 ), a second insulator layer ( OX2 ) and a third insulator layer ( OX3 ) and a polycrystalline silicon layer ( PLY ) intended. In the example of 17 The polycrystalline silicon layer in subregions of the surface of the device below the third insulator layer is then (by surface micromechanical methods) ( OX3 ) away. This can be done for example by gaseous etching gases, as known in the art. With suitable structuring, a micromechanical beam ( BE ), which on the one hand electrostatically, for example via the Hall structure ( HL ) or the exemplary tracks ( L1 . L2 ) can be excited to vibrate. It is known from the prior art that such a beam has a quality of vibration that depends on the pressure of the residual gas in its environment. However, the vibrational behavior also depends on the interaction between the superconducting substrate at room temperature ( G _sub ) and the other electrically conductive subdevices ( L1 . L2 . HL , Sub ₁ ). The beam is therefore also a microfluidic element which interacts with the gaseous fluid of its environment. Its efficiency is reduced in liquids, but works there in principle. The use in conjunction with a pressure cell in a pressure sensor, in particular an absolute pressure sensor is therefore also conceivable. For this, the cavity (CAV) of the 17 only be completed all around by the exemplary poly-silicon. this shows 18 ,

FIG. 18

18 equals to 17 with closed cavity (CAV), for example for an absolute pressure sensor or a microfluidic component.

FIG. 19

19 equals to 15 with the difference that an optically active layer ( OA ), exhibiting an electro-optic effect associated with the magnetic field of the superconducting substrate ( G _sub ) interacts. This interaction can be observed optically or for the modification of optical radiation which is incident on the optically active layer (FIG. OA ) and reflected there will be used. In the latter case, it is expedient to use a reflection layer between optically active layer ( OA ) and the room temperature superconducting substrate ( G _sub ).

FIG. 20

20 corresponds to 19 with the difference that the optically active layer ( OA ) is now designed as an electro-optically active section of an optical waveguide. The figure shows this section schematically as a schematic diagram in cross section. The light is guided perpendicular to the image plane in the optical waveguide. In this way, it is possible to construct a magneotoptic switch which, by means of the Kerr effect, modulates an optical waveguide section, which is embodied in the form of an electro-optically active section, the phase position of the light in the optical waveguide or the transit time of the light through this section of the optical waveguide. The special feature is that the superconducting substrate at room temperature can generate a magnetic field that can influence this section of the optical waveguide. As a result, light switches can be built, which only need a short-term control for switching.

glossary

graphs

Graphite layer, benzene rings, etc. Graphene is the common name for a modification of carbon with a two-dimensional structure, in which each carbon atom is surrounded at an angle of 120 ° by three others, so that a honeycomb-shaped pattern is formed.

Graphene layer

For the purposes of this disclosure, a graphene layer is at least at one point of a benzene ring, more preferably the concatenation of at least two or more than two benzene rings.

Microstructure Technology / Microtechnology

Microtechnology (also known as microstructure technology) deals with processes used to fabricate bodies and geometric structures with dimensions in the micrometer range (0.1-1000 μm). Structure sizes of less than 100 nanometers are indeed called nanotechnology. However, they are included in the terms of this disclosure by the terms microstructure technology and microtechnology.

microelectronic circuits

Microelectronic circuits in the sense of this disclosure are electrical circuits and devices which have been produced at least partially by microstructure / microtechnology / nanotechnology techniques.

micromechanical devices

Micromechanical devices in the sense of this disclosure are mechanical devices that have been produced at least partially by microstructure / microtechnology / nanotechnology techniques.

micro-optical devices

Micro-optical devices in the sense of this disclosure are optical devices that have been produced at least partially by microstructure / microengineering / nanotechnology techniques.

microfluidic devices

Microfluidic devices in the sense of this disclosure are in the broadest sense micromechanical devices which serve the transport, modification or other treatment of at least partially gaseous and / or at least partially liquid fluids and which have been produced at least partially by microstructure / microengineering / nanotechnology techniques.

LIST OF REFERENCE NUMBERS

1

Provide ( 1 ) of a first substrate (GSub) consisting of at least two layer regions (GB, GR);

2

Ascertaining 2 ) the orientation of the surface normals ( nF ) of the interface (GF) within the substrate (GSub);

3

Thinning ( 3 ) of a 'relevant' stratum (GB, GR) and creation of a lower interface ( UGF ) parallel to the interface (GF);

4

Application of the preferably thinned substrate (GSub) to the surface ( OF ) of a carrier ( 1 );

5

Attaching the preferably thinned substrate (GSub) to the surface ( OF ) of the carrier ( 1 );

6

Thinning of the other layer area (GR, GB), which is not the layer area concerned;

7

Provision of a second substrate ( SUB ), for example in the form of a microelectronic circuit;

8th

Structuring of the first substrate (GSub);

9

Applying at least one electrically conductive layer to the first substrate (GSub) or to the second substrate ( SUB ), for example, to make the contacts;

10

Structuring the at least one electrically conductive layer;

11

Applying at least one electrically insulating layer to the first substrate (GSub) or second substrate ( SUB ) or the carrier ( 1 ) or on an electrically, in particular normal, conductive layer perform;

12

Structuring the at least one insulating layer, e.g. for opening the contacts or vias;

13

of providing ( 13 ) the contacts of the interface (GF);

B

magnetic flux density;

BE

micromechanical beams;

B _k

critical magnetic flux density;

c

Sixfold symmetry axis of the hexagonal unit cell of the graphite 2H structure;

CMP

chemical-mechanical polishing;

d

hexagonal axis of symmetry ( d ) of the crystal lattice of the second layer region (GR);

DLC

diamond like carbon (diamond-like layers);

ELS

electrically conductive layer;

G _A

first graph location;

G _B

first layer region of graphite with Bernal crystal structure (graphite 2H) with at least 3 atom layers (graphene layers) with a respective thickness of exactly one atom per atomic layer;

G _F

Interface between the first layer region (GB) and the second layer region (GR);

GL

Adhesive for bonding the superconductive layer package to the carrier (Sub ₁ );

G _R

second layer region of graphite with rhombohedral crystal structure (English rhombohedral, graphite-3R) with at least 3 atom layers (graphene layers) with a respective

Thickness of exactly one atom per atomic layer;

gs

Graphite substrate;

G _sub

Substrate ( G _sub ) consisting of at least two layer regions (GB, GR) and an interface ( G _F );

HL

Hall structure. This is an exemplary Hall structure in cross section.

IS

electrically insulating layer;

K1

first contact

K2

second contact

L1

first trace. The first printed conductor is preferably produced by means of photolithographic etching processes from a first metallization layer in the course of the manufacturing process. The first metallization layer is deposited on the first insulator layer ( OX1 ) applied. In the area of contacts ( K1 . K2 ), the first metallization is applied directly to the semiconductor substrate of the carrier (Sub ₁ ).

L2

second trace. The second interconnect is preferably produced by means of photolithographic etching processes from a first metallization layer during the manufacturing process. The first metallization layer is deposited on the first insulator layer ( OX1 ) applied. In the area of contacts ( K1 . K2 ), the first metallization is applied directly to the semiconductor substrate of the carrier (Sub ₁ ).

L3

third trace. The third interconnect is preferably produced by means of photolithographic etching processes from a second metallization layer in the course of the manufacturing process. The second metallization layer is deposited on the second insulator layer ( OX2 ) applied. In the area of contacts ( K1 . K2 ), but not necessarily the second metallization is applied directly to the first metallization.

MFM

Magnetic Force Microscopy

nF

Surface normal of the surface ( OF );

NMR

nuclear magnetic resonance;

OA

optically active layer, (e.g., layer having an electro-optic effect, for example

the

Kerr effect shows.);

OF

Surface of the carrier ( 1 ). If a Hall element is to be realized, it is preferred if the carrier is made of semiconducting material. The carrier may also include an integrated circuit;

OGF

upper interface ( OGF ) of the substrate (Gsub) parallel to the interface (GF) after preferential thinning;

OX

Insulator, typically SiO2 or silicon nitrite or silicon nitride. Other insulators, such as e.g. Polyimide are conceivable;

OX1

first insulator layer, typically SiO2 or silicon nitrite or silicon nitride. Other insulators, such as e.g. Polyimide are conceivable. Particularly preferred is the use of a gate oxide as the first insulator layer;

OX2

second insulator layer, typically SiO 2 or silicon nitride or silicon nitride. Other insulators, such as e.g. Polyimide are conceivable .;

OX3

third insulator layer, typically SiO2 or silicon nitride or silicon nitride. Other insulators, such as e.g. Polyimide are conceivable;

PLY

polycrystalline silicon layer. In the example of 17 the polycrystalline silicon layer must be selected from its material so as to be selective with respect to the second insulator layer ( OX2 ) and the third insulator layer ( OX3 ) is etchable;

1

Carrier;

SUB

second substrate, which may be a microelectronic circuit, for example. The second substrate ( SUB ) can with the carrier ( 1 ) be identical;

T

Temperature;

Ta

Working temperature;

T _C

Critical temperature;

TSV

Through silicon via;

UGF

thinned lower interface of the substrate (GSub) parallel to the interface (GF);

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

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Claims (12)

Electronic component - having a Hall-effect sensing structure or other electrical device in which at least one electrical parameter is dependent on the magnetic flux density or magnetic field strength penetrating this other electrical device, characterized in that it comprises at least one subdevice having a electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or with a critical magnetic flux density (B _k ) at 77 K higher than 1T and / or 50T. Electronic component according to Claim 1 Wherein the first sub-device is a first substrate (GSub) consisting of at least two layer regions (G _B , G _R ), wherein the first layer region (G _B ) and the second layer region (G _R ) are arranged one above the other and a common interface ( G _F ) and wherein at least the first layer region (G _B ) or the second layer region (G _R ) is arranged above the Hall measurement structure. • wherein the first layer region (G _B ) consists of graphite with Bernal crystal structure (graphite-2H) with at least 3 atom layers with a respective thickness of exactly one atom per atomic layer and • wherein the second layer region (G _R ) of Graphite with rhombohedral crystal structure (English rhombohedral, graphite-3R) with at least 3 atomic layers with a respective thickness of exactly one atom per atomic layer exists and • where the interface (G _F ) an orientation of their surface normal (n _F ) parallel to hexagonal axis of symmetry (c) of the crystal lattice of the first layer region (G _B ) and - the interface (G _F ) having an orientation of its surface normal (n _F ) parallel to the hexagonal axis of symmetry (d) of the crystal lattice of the second layer region (G _R ), wherein the interface (G _F ) has at least partially superconducting properties and wherein the interface (G _F ) at least partially has a transition temperature (T _C ) which is higher is greater than -195 ° C and / or greater than -100 ° C and / or greater than -50 ° C and / or has a critical magnetic flux density (B _k ) at 77K greater than 1T and / or 50T is. Electronic component - with at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or the critical magnetic flux density (B _k ) at 77 K is higher than 1T and / or 50T, said first sub-device being a first Substrate (G _Sub ) consisting of at least two layer regions (G _B , G _R ), - wherein the first layer region (G _B ) and the second layer region (G _R ) are arranged one above the other and have a common interface (G _F ) and wherein the first layer region (G _B ) is a carbon crystal having a first crystal structure, and wherein the second layer region (G _R ) is a second carbon crystal having a first or second crystal structure, and wherein between the first crystal and the second crystal an interface (G _F ) is formed and - wherein the interface (G _F ) has at least partially superconducting properties and wherein the interface (G _F ) at least partially a transition temperature (T _C ) which is higher than -195 ° C and / or higher as -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or a critical magnetic flux density (B _k ) at 77 K, which is higher than 1T and / or 50 T. , Device after Claim 3 - wherein at least the first layer region (G _B ) or the second layer region (G _R ) is arranged above or in the vicinity of a Hall measurement structure or other magnetic sensitive sensor or sensor element, - proximity means that a magnetic field that by a current in the interface (G _F ) or the first layer region (G _B ) or the second layer region (G _R ) is generated, a parameter, in particular a measurement signal, the Hall measurement structure or the other magnetic sensitive sensor or sensor element can change. Electronic component - comprising an electronic sub-device which changes an electrical parameter as a function of a magnetic field magnitude or of another parameter of the electromagnetic field, characterized in that it comprises at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or an electric superconductor having a critical magnetic flux density (B _k ) at 77 K higher is 1T and / or 50T. Electronic component according to Claim 5 - Wherein the first sub-device is a first substrate (G _Sub ) consisting of at least two layer regions (G _B , G _R ), • wherein the first layer region (G _B ) and the second layer region (G _R ) are arranged one above the other and a common interface (G _F ), and wherein at least the first layer region (G _B ) or the second layer region (G _R ) is arranged above the Hall measurement structure. • wherein the first layer region (G _B ) consists of graphite with Bernal crystal structure (graphite-2H) with at least 3 atom layers with a respective thickness of exactly one atom per atomic layer and • wherein the second layer region (G _R ) of Graphite with rhombohedral crystal structure (English rhombohedral, graphite-3R) with at least 3 atomic layers with a respective thickness of exactly one atom per atomic layer exists and • wherein the interface (G _F ) an orientation of their surface normals (n _F ) parallel to hexagonal axis of symmetry (c) of the crystal lattice of the first layer region (G _B ) and - the interface (G _F ) having an orientation of its surface normal (n _F ) parallel to the hexagonal axis of symmetry (d) of the crystal lattice of the second layer region (G _R ), wherein the interface (G _F ) has at least partially superconducting properties and wherein the interface (G _F ) at least partially has a transition temperature (T _c ) which is higher is as -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or wherein the interface (G _F ) at least partially a critical magnetic flux density (B _k ) at 77K higher than 1T and / or 50T. Microelectronic circuit, in particular integrated circuit, characterized in that it comprises at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than - 50 ° C and / or higher than 360 ° K and / or an electrical superconductor having a critical magnetic flux density (B _k ) at 77 K higher than 1 T and / or 50 T. Micromechanical device, characterized in that it comprises at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or an electrical superconductor with a critical magnetic flux density (B _k ) at 77 K higher than 1 T and / or 50 T. Microoptical device, characterized in that it comprises at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or an electrical superconductor with a critical magnetic flux density (B _k ) at 77 K higher than 1 T and / or 50 T. Micro-optical device according to Claim 9 characterized in that it comprises at least one optical waveguide section which is suitable or provided so that its optical properties depend, at least temporarily, on a magnetic field generated by said sub-device. Optical waveguide characterized in that - it is combined with a sub-device to a total device comprising an electrical superconductor with a transition temperature (T _c ) greater than - 195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or an electrical superconductor having a critical magnetic flux density (B _k ) at 77 K higher than 1 T and / or 50 T, and - that at least one interaction between the sub-device and the optical waveguide measurable is. Microfluidic device, characterized in that it comprises at least one sub-device comprising an electrical superconductor with a transition temperature (T _c ) greater than -195 ° C and / or higher than -100 ° C and / or higher than -50 ° C and / or higher than 360 ° K and / or an electrical superconductor with a critical magnetic flux density (B _k ) at 77 K higher than 1 T and / or 50 T.

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