DE102017108216A1 - Control system and method of memory access - Google Patents

Abstract

A method includes associating an associated processor address register with a predetermined operation, invoking an instruction that includes a reference to a referenced processor address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.

Description

TECHNICAL AREA

Various embodiments generally relate to a memory access control system and method.

BACKGROUND

A measuring device detects a control unit variable of a control unit program executed by a control unit processor in a control device. The control device may be a motor control for a motor vehicle, an embedded system, or the like, which may be used to control actuators, for example, electric motors, controls, or the like. The control processor uses a memory data connection with detection means for detecting data transmitted on the memory data connection. The detection device is, for example, a temperature sensor, a measuring transducer or the like, which is connected to the control device. The control unit processor executes a control program to monitor, for example, the actuator, control injection quantities of an internal combustion engine, or the like.

The control unit processor is connected to a control unit memory of the control unit in order to store, for example, control parameters and other variables used, measured and / or calculated. Thus, the control unit processor writes the control unit variable into a control unit memory. The control unit variable is, for example, a measured value, a temporary control value, an output value at an actuator, or the like. The variable may also include a program variable used by a program function.

The measuring device comprises a buffer memory into which the measuring device in a process, which in the present case is also referred to as recording or tracing, writes the data which has been transferred in memory access operations, i. H. when the memory data connection is used for transmission to an image memory, also referred to herein as a mirror memory. The mirror memory is thus intended to hold a memory map of at least part of the control unit memory.

The recording of the memory access operations of the controller processor can be achieved in several ways. In the case of microprocessors without internal peripherals and memory, it is common practice to record the external address / data bus and some control signals. The prerequisite for this so-called bus trace method is a physical access to the memory interface of the control device. Adapters that branch the signals either directly from the controller processor or directly from the memory module are typically used herein. The signals may also be dropped on the path between the controller processor and memory using press adapters for trace pads or connectors. If a physical connection is possible in this manner, all memory access operations can be recorded and the program flow and all data access operations can be determined therefrom.

There are limitations if the controller processor is equipped with a cache or internal RAM. In this case, the situation may occur in which no bus cycle on the external bus interface occurs for a long period of time, since all the required data is already present in the internal memory and executed there. In this case, a trace tool can not record anything and program behavior remains hidden.

However, ever-increasing integration densities and price pressures have resulted in a processor core, cache, peripherals, flash and RAM memory being integrated into a single chassis in many processors (system-on-chip). These processors often no longer have an external memory interface. The bus trace method can not be used in this case. Therefore, some processor architectures provide a special on-chip trace interface in addition to the debug interface. This trace interface can be used to make the program flow and the data trace visible to the outside in compressed form.

A trace bus having a width of 4, 8, or 16 bits and capable of being used to transmit program flow data and / or data access operations with a bus frequency of up to 400 MHz in compressed form is commonly used as the trace interface. Other options include high-speed gigabit / s serial interfaces with differential signaling with low voltage fluctuations. In this case, the information on the address bus / data bus is transferred in the manner in which they occur directly in the CPU core with address and data values. This means that operations to access peripheral devices, an on-chip flash or RAM memory - especially cached operations - can also be recorded.

However, a disadvantage of this trace method is the high bandwidth required to transmit the Trace data is needed. The problem is compounded in multi-core systems because the bandwidth required increases linearly with the number of processors.

SUMMARY

The following presents a simplified summary to provide a basic understanding of one or more aspects of the invention. This summary is not a comprehensive overview of the invention and is not intended to identify key elements or critical elements of the invention, nor to limit the scope of protection thereof. Rather, the main purpose of the summary is to present some concepts of the invention in a simplified form as an introduction to the more detailed description presented later.

In one aspect, a method includes associating at least one processor address register with a predetermined operation, invoking an instruction that includes a reference to an address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.

In one aspect, a control system includes an associated processor address register associated with a predetermined operation and a first processor configured to invoke an instruction that includes a reference to a referenced processor address register. The control system is configured, if the referenced processor address register is the associated processor address register, to perform the predetermined operation.

In another aspect, a first processor is configured to be coupled to a second processor. The first processor includes a counter configured to be incremented with a transmission of a process datum to the second processor. In an alternative other aspect, a first processor is configured to be coupled to a second processor, the first processor comprising a counter configured to be decremented with a transfer of a process datum to the second processor.

This summary is provided with the understanding that it is not used to interpret or limit the scope or meaning of the claims. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid to determining the scope of the claimed subject matter. Other methods, devices and systems are also disclosed. Additional features and advantages will become apparent to those skilled in the art upon reading the following detailed description and upon considering the accompanying drawings.

list of figures

• 1 stellt ein Blockdiagramm dar, das eine Vorrichtung gemäß manchen Ausführungsformen veranschaulicht.
• 2A, 2B und 2C stellen Tabellen dar, die schematisch beispielhafte Speicherabschnitte gemäß manchen Ausführungsformen veranschaulichen.
• 3 stellt ein Flussdiagramm dar, das ein beispielhaftes Verfahren gemäß manchen Ausführungsformen veranschaulicht.

The claimed subject matter is described below with reference to the drawings. Throughout the description, like terms as used herein refer to like elements. The detailed description refers to the accompanying figures. The same numbers may be used throughout the drawings to refer to like features and components. It should be noted that views of embodiments are merely illustrative of selected features of the embodiment.

• 1 FIG. 12 illustrates a block diagram illustrating an apparatus according to some embodiments. FIG.
• 2A . 2 B and 2C FIG. 12 illustrates tables that schematically illustrate example storage sections according to some embodiments.
• 3 FIG. 3 illustrates a flowchart illustrating an example method according to some embodiments. FIG.

DETAILED DESCRIPTION

For the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it may be obvious that the claimed subject matter may be practiced without these specific details.

The following detailed description refers to the accompanying drawings which show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as certain embodiments may be combined with one or more other embodiments to form new embodiments. Various Embodiments are described in conjunction with methods and various embodiments are described in connection with devices. It should be understood, however, that embodiments described in connection with methods apply equally to devices and vice versa.

1 FIG. 12 is a block diagram illustrating a measurement system including an apparatus according to some embodiments. FIG. The measuring system includes a control system 100 For example, configured to control a motor (not shown). In one implementation, merely as an example of an operational task performed by the control system 100 is performed, the control system is configured to execute a computer-implemented instruction code to control a fuel injection pump (not shown). The tax system 100 comprises a first processor, in the present case as a central processor 110 , which is configured to derive data from a measurement signal, and a second processor, in this case as a trace processor 120 , which is configured to provide interface functionality to the control system 100 to provide for communicating with other components of the measurement system, as will be explained in more detail below.

Furthermore, the control system includes 100 a memory, present as an operation memory 130 designated. The central processor 110 and the trace processor 120 can through an inter-processor bus 112 be communicatively coupled. Furthermore, the central processor 110 and the memory through a system bus 140 be communicatively coupled. In some embodiments, the central processor 110 and the operations memory 130 as separate components of the control system 100 provided, for example, on separate circuit boards through the system bus 140 communicatively coupled. The inter-processor bus 112 and / or the system bus 140 For example, coaxial transmission media, wired transmission media, optical fiber transmission media, wireless transmission media, and other transmission media may be implemented. In some embodiments, the control system is 100 as a control unit or a control module as separate chips provided on a circuit board. In some embodiments, the control system is 100 provided as a system-on-chip, wherein the central processor 110 and the trace processor 120 together in an integrated circuit. As used herein, the phrase "removed" includes colocation in a single integrated circuit, although in different areas of an integrated circuit chip. Nevertheless, the trace processor may be 120 away from the central processor 110 are located. The tax system 100 includes an input port 108 which is configured to receive values of a measurement signal MS, a control port 107 which is configured to output control signals to, for example, a motor (not shown) and a trace port 109 for example, configured to transmit trace data TD to a data recorder.

An embodiment of the measuring system comprises a sensor unit 180 configured to detect values associated with a physical property, such as pressure, temperature or acceleration. Over time, the detected values may vary continuously to form an analog measurement signal MS. In an alternative embodiment (not shown), the sensor unit comprises 180 an analog-to-digital converter configured to form a digital measurement signal. The sensor unit 180 may be configured to read the values of the measurement signal MS via a coupling to the input port 108 of the tax system 100 transferred to.

In some embodiments, the measurement system includes a trace tool. The trace tool may be configured to record and / or analyze behavior of the control system. In particular, in some embodiments, the trace tool includes a trace memory 190 , The trace memory 190 is configured to be coupled to the trace port 109 of the tax system 100 Receive trace data TD and store the trace data TD. At least one effect may be that of the trace memory 190 as a recording device for the trace data TD can be used. In some embodiments, the control system 100 be configured to cooperate with the trace tool on the condition that the trace tool is validated for cooperation. For example, the trace tool may include a certificate, and the control system is configured to receive the certificate from the trace tool and to verify validity of the certificate. If it is determined that the certificate is valid, then the control system cooperates 100 with the trace memory 190 , as described below.

With reference to the tax system 100 includes the central processor 110 an analog-to-digital converter ADC 111 configured to receive values of the analog measurement signal MS at the input port 108 is received to translate digital representations of the values. A sequence of digital representations which are generated over time on the basis of the values of the analog measurement signal MS thus forms digital measurement signal data (MD), ie a digital representation of the analog measurement signal MS.

The central processor 110 is configured to use the system bus 140 , the digital measurement signal data in the operations memory 130 to write. A SAVE statement, for example, can be defined, for example, if it is on the central processor 110 is executed, causes the central processor 110 the digital measurement signal data into the operations memory 130 writes.

2A FIG. 12 illustrates a table that schematically illustrates an exemplary portion of the operations memory 130 illustrated. For the sake of illustration, the addresses and also the values written at the addresses are indicated as binary numbers. It is understood that values can also be written as hexadecimal numbers, for example. The illustrated section of the operations memory 130 includes an address space having 6-bit operation memory addresses from 011110 to 111011. In some embodiments, the operations memory includes 130 a block of memory cells at a base address. In the example, four leftmost bits, ie the four most significant bits, represent the addresses in the address space, ie the values respectively 0111 ... 1110, a respective base address. The two most right bits, ie the two least significant bits, of the base address are padded with 0, for example. In some embodiments, one or more of the least significant bits of the base address, instead of being padded, are used for signaling. For example, a 2-bit code may be written in the two least significant bits of the base address. To access the operations memory 130 at the base address, the 2-bit code is ignored and / or replaced with the fill. To determine a signaled content for use in data processing and / or tracing, the 2-bit code can be interpreted.

In one example, the operation memory address is offset from the base address by an offset address. At the in 2A illustrated example, the operation memory addresses of the example address space as a sum of the base address 011100 ... 111000 plus the offset address can be represented in a range of 00 to 11. For example, to allow the central processor 110 the operations memory 130 addressed, is the central processor 110 in some embodiments, configured to store the operations memory address from the base address 0111 ... 1110 and the offset address 00 ... 11 to put together. In some embodiments, the offset address may be determined based on a previously used offset address, for example, by incrementing the previously used offset address or decrementing the previously used offset address, using a constant step size that is predetermined , It should be understood that although in the example the offset address is a 2-bit value, this is for illustrative purposes only. In some implementations, the offset address includes a nibble, byte, or any other number of digits that corresponds to a size of an address range based on the base address. In some embodiments, a size of a block or portion of data that should be subjected to the predetermined operation determines the length of the offset address. In some implementations (not shown), the offset address may be positive or negative. A representation of the offset address may include a bit for indicating a sign of the offset address. For example, the most significant bit (MSB) of the offset address may be interpreted as the sign of the offset address.

Again with reference to the tax system 100 includes the central processor 110 a processor address memory 115 which is configured to store a stored operations memory base address. A processor address register of the processor address memory 115 may be associated with a predetermined operation.

2 B FIG. 12 illustrates a table that schematically illustrates an exemplary portion of processor address memory 115 of the central processor 110 illustrated. In the in 2 B illustrated example includes the processor address memory 115 four registers at register addresses 00 . 01 . 10 and 11 , In the example, the base addresses 011100 . 001000 . 100100 and 011000 in the processor memory 115 at the register addresses 00 . 01 . 10 respectively. 11 written.

In some embodiments, at least one processor address register, ie, the hardware itself, and / or at least one address of the processor address memory 115 ie a reference to one of the registers in the processor memory 115 , associated with a predetermined operation. At the in 2 B Illustrated example is one of the processor address registers, the processor address registers 10 , associated with an example operation TRACE, while three other processor address registers, the registers 00 . 01 and 11 are associated with any surgery. Thus, while the base addresses 011100 . 001000 and 011000 in the illustrated example, are associated with no operation, the base address is 100100 associated with the TRACE operation. In some embodiments, the TRACE operation causes the control system 100 selected data to the trace port 109 writes. In some embodiments, the predetermined operation provides the selected data to the trace tool 190 that with the tax system 100 is coupled, ready.

Although in the illustrated example, the association of the processor address register with the predetermined operation is static, the association may be configurable in some embodiments, for example, by adjustments made prior to the execution of software and / or by reconfiguring the settings during software execution. At least one effect may be that the software can control the conditions of the predetermined operation to be performed.

In general, in some embodiments, a content of the referenced processor address register may be interpreted as to whether the predetermined operation should be performed or not. The predetermined operation is performed only if a result of interpreting the content indicates that the predetermined operation should be performed. In some embodiments (not shown), interpreting the contents of the referenced processor address register includes comparing at least a portion of the content with a predetermined representation associated with the predetermined operation. The result of the interpretation is determined to indicate that the predetermined operation should be performed if the portion of the content is equal to the predetermined representation. For example, not shown, one or more selected base addresses may be selectively predetermined for tracing. The predetermined operation, such as tracing, is performed only if the base address register contains a predetermined selected base address.

In general, in some embodiments, a control code in the instruction called by the first processor may be included with the reference to the referenced processor address register. The control code indicates whether or not the predetermined operation should be performed. In some implementations, performing the predetermined operation only occurs if the control code indicates that the predetermined operation should be performed. For example, in some implementations, the processor uses 110 the least significant bit of the base address to control that the instruction should be traced. In this example, where the processor address register 10 is associated with the example operation TRACE, the operation TRACE is called depending on the least significant bit of the base address or not. In one implementation, all base address registers of the first processor are associated with the predetermined operation. In this case, the predetermined operation is called only in dependence on how the processor sets the control bit.

In general, any one bit in an argument of the instruction may be used to indicate whether or not the predetermined operation should be performed. In some implementations (not shown), the sign of the address offset is used to indicate whether or not the predetermined operation should be performed. Thus, the predetermined operation is performed only if the sign of the address offset indicates that the predetermined operation should be performed. For example, in some implementations, the processor is configured to interpret a most significant bit of a representation of the address offset as a sign of the address offset. The first processor is further configured to use the sign of the address offset to control that the instruction should be traced. In this example, where the processor address register is associated with the example operation TRACE, the operation TRACE becomes dependent on the sign of the address offset 1 or 0 is, called or not. In one implementation, all base address registers of the first processor are associated with the predetermined operation. In this case, in the absence of any other control bit to indicate whether or not to perform the predetermined operation, the predetermined operation is called only in dependence on how the processor sets the sign bit.

Although the association of the processor address register with the predetermined operation is unconditioned in the illustrated example, in some embodiments the association may depend on, for example, an instruction called to access the operation memory address. In one example, the control system 100 configured such that an association of a processor address register with a predetermined operation is defined or valid if the instruction causing access at a certain processor address register associated with the predetermined operation is a first instruction, for example a SAVE instruction. However, the association of the processor address register with the predetermined operation is undefined or invalid if the instruction causing access to the processor address register associated with the predetermined operation is a second instruction, for example a READ instruction.

In some embodiments, the central processor is 110 configured to send the information to the trace processor via a selected processor address register associated with a predetermined operation, also referred to herein as filter data (FD) 120 for use in processing the digital measurement signal data (TM). In the above with reference to 1 and 2 B discussed example, the central processor 110 using the inter-processor bus 112 the information about the base address 100100 that is associated with the TRACE operation to the trace processor 120 provide.

Again referring to 1 is now the trace processor 120 described in more detail. As can be seen, the trace processor can 120 to be configured based on the filter data (FD) provided by the central processor 110 to determine whether access to the operations memory address should be retrieved.

Furthermore, the trace processor includes 120 in some embodiments, a filter module 128 configured to receive the digital measurement signal data (MD) based on the filter data (FD) provided by the central processor 110 are received to filter for receiving selected data, also referred to herein as trace data (TD). In some embodiments, the filter data (FD) is merely a flag indicating the predetermined operation to be performed. In some embodiments, the trace processor is 120 configured to interpret the flag such that the digital value that is about to arrive in the operations memory 130 should also be used as an operand in the execution of the associated operation.

In some embodiments, the control system is 100 configured to the filter module 128 to overwrite. At least one effect may be that the predetermined operation is not performed although the filter module 128 has found out that the predetermined operation should be performed. Overriding can be used, for example, with an interrupt handler (ISR) operation. The interrupt services may not be related to a flow of processes according to software instructions issued by the central processor 110 be executed. Accordingly, it may not be desirable to allow an interrupt service access to the processor address register 10 Trace associated with the predetermined operation. For example, at least one effect of overwriting may be to avoid undesired tracing of interrupt service accesses to the processor address register despite the association of the processor address register with the tracing as the predetermined operation.

In some embodiments, the first processor includes a counter configured to be incremented with a transmission of a process datum to the second processor. The counter is configured to be periodically decremented. The first processor is configured to stop if the counter is above a configurable load threshold. In some alternative embodiments, the counter is configured to be periodically incremented. The first processor is configured to stop if the counter is below a configurable load threshold. As will be described in more detail below, at least one effect may be to reschedule the transfer of process data to the second processor.

Further with reference to 1 now become more aspects of the central processor 110 according to a general aspect set forth above in more detail.

In some embodiments, the central processor includes 110 a modeling unit 117 , which is configured to operate the trace processor 120 based on the data selected by the central processor 110 to the trace processor 120 be transferred to model. In some embodiments, the modeling unit becomes 117 implemented as a state machine. In some embodiments, the modeling unit is 117 configured to have an expected load status, such as a load status of the trace processor 120 to determine. In some embodiments, the modeling unit is 117 configured to do the operation of the trace processor 120 modeled using a prior provision of selected data to the trace processor. For an example, the modeling unit 117 provided as a counter configured to control the operation of the trace processor 120 to model by transmitting data from the central processor 110 to the trace processor 120 counts. In some embodiments, the modeling unit is 117 configured to do the operation of the trace processor 120 models the selected data by the trace processor to the trace port 109 be provided to use.

For another example, the modeling unit 117 provided as a counter configured to control the operation of the trace processor 120 to model it by transferring data from the trace processor 120 to the trace port 109 counts.

In an embodiment where the buffer 124 Thus, as a FIFO buffer is configured, a buffer fill level can be modeled. Modeling an operation of the trace processor 120 may be modeling or simulating the filling of the data buffer 124 with the selected data and / or the removal of the selected data from the data buffer 124 include.

For example, the modeling unit 117 provided as a counter configured to control the operation of the trace processor 120 to model by communicating with each transfer of data from the central processor 110 to the trace processor 120 is incremented and decremented in proportion to a clock count. In one embodiment, the modeling unit checks 117 continuously, whether a clock value since a recent decrement of a transfer count value has a duration that the trace processor 120 on average, for processing the contents of a register of the buffer 124 needed, exceeds. If so, the modeling unit decrements 117 the transfer counter value and reset the clock value to zero.

In some embodiments, the central processor includes 110 a scheduler 119 , The scheduler 119 is configured to transmit or otherwise provide the selected data from the central processor 110 to the trace processor 120 reschedule if the expected load status is a predetermined overload status. The scheduler 119 For example, it may delay transmission by a predetermined number of clock cycles. In some embodiments, the scheduler may predetermine the number of clock cycles for the delay to correspond to an expected or otherwise determined congestion level. In some embodiments, the scheduler is 119 configured to invoke a NOP operation instruction that stops the processor. At least one effect may be providing the data to the trace processor 120 to reschedule. At least one more effect may be that of the buffer 124 of the trace processor 120 is prevented from suffering from overflow.

In some embodiments, the trace processor 120 be provided as a state machine. In yet another embodiment, the trace processor is 120 with the central processor 110 integrated. Thus, the central processor delivers 110 the functionality of the trace processor 120 ,

2C represents a table that schematically illustrates an exemplary section of a memory of a trace tool 190 of the tax system 100 illustrated. Im in 2C illustrated example includes the memory of the trace tool 190 six memory cells at the addresses 0000 ... 0110 and holds a block 192 of trace data. As will be explained below, this block of data is a copy or 'trace' of a block 132 of digital measurement signal data stored in the operations memory 130 get saved.

In general, a method includes incrementing a counter with a transmission of a process datum from a first processor to a second processor, and periodically decrementing the counter if the counter is greater than a predetermined lower bounds threshold. In some embodiments, the method includes stopping the first processor if the counter is over a configurable load threshold. In a complementary aspect, a method includes decrementing a counter with a transmission of a process data from a first processor to a second processor and periodically incrementing the counter if the counter is less than a predetermined upper limit threshold. In some embodiments, the method includes stopping the first processor if the counter is below a configurable load threshold. At least one effect of stopping may be that the transfer of process data from the first processor to the second processor is rescheduled. In some embodiments, the method further comprises using the first processor to implement the counter.

In some embodiments, a period is a predetermined time interval, for example, a predetermined number of clocks. In some embodiments, the predetermined time interval is equal to or greater than an average time required by the second processor to process the process data. In some embodiments, the predetermined time interval is greater than a maximum time required by the second processor to process the process data.

In some embodiments, processing the process data by the second processor includes writing selected data to a trace port. In some embodiments, processing the process data by the second processor includes filtering the process data based on a referenced processor address register to obtain the selected data. In some embodiments, the method further comprises deriving the process data from a measurement signal.

The following is an example operation of the control system 100 according to a general aspect set forth above briefly with reference to 3 10, which illustrates a flowchart illustrating an example method according to some embodiments. It will also relate to the 1 . 2A . 2 B and 2C taken.

At S310, a processor address register is associated with a predetermined operation. At the in 2 B illustrated example, the predetermined operation is a TRACE operation. The TRACE operation is performed using the processor address register 10 associated.

At S320, a stored operations memory base address is stored in the processor address register. At the in 2 B Illustrated example is the stored operations memory base address 100100 ,

At S330, an instruction is invoked that points to the operations memory 130 accesses. The instruction may, for example, be a SAVE statement which, when executed, causes the central processor 110 writes a value of the digital measurement signal into the operations memory. At the in 2A illustrated example, the digital measurement signal value passing through the bits 011101 is represented at the operation memory address 100111 (in 2A at reference number 131 shown). However, instead of directly the operations memory address 100111 To address, the SAVE statement uses the processor address register 10 and an address offset. For example, the SAVE statement assigns the argument (Processor Address Register 10 , Address offset 11 , Value 011101 ) on.

At S340, the SAVE statement causes the processor to set the operations memory base address 100100 from the processor address register 10 read.

At S350, the SAVE statement causes the processor to set the operations memory base address 100100 with the address offset 11 combined to the operations memory address 100111 to obtain. Furthermore, the execution of the SAVE statement may proceed by using the system bus 140 the value 011101 into the memory cell of the operations memory 130 containing the operations memory address 100111 has to write, as in 2A illustrated.

At S360, the processor determines whether the processor address register 10 associated with a predetermined operation. If no association is determined, then the flow goes to another processing step S399 at S361. Im in 2 B Illustrated example is the processor address register 10 however, associated with the operation TRACE and therefore the exemplary operation continues to perform the predetermined operation.

At S370, the modeling unit checks 117 whether the trace processor 120 ready to process more data. The modeling unit 117 checks whether the transmission counter value exceeds a predetermined limit. If an overflow is determined, then the scheduler delays 119 at S380 further processing. If no overflow is determined, then flow transfers to another processing step S399 at S371. A copy of the value 011101 is done using the inter-processor bus 112 to the buffer 124 of the trace processor 120 transfer and the modeling unit 117 increments the transmission counter value according to the transmission.

At S390, the associated predetermined operation is performed. In the illustrated example, the TRACE operation is performed. In the example illustrated, the filter module chooses 128 according to filter data FD the binary representation 011101 which is to be provided as trace data (TD). The trace data TD, ie the bits 011101 , be on trace port 109 output. As in 2C illustrates the binary representation 011101 The trace data TD is then used in some embodiments where the trace tool 190 to the trace port 109 is coupled to the memory of the trace tool 190 at the address 0100 (in 2C at reference number 191 shown). Im in the 2A and 2C thus exemplifying the tracing of a block 132 from four digital measurement signal data stored in the operations memory at the base address 100100 are saved, thus terminated. Accordingly, thus becomes a block 191 trace data in the memory of the trace tool 190 saved a copy or a trace of the block 132 of data are in the operations memory 130 are stored.

At S399, the operation of the control system continues 100 continues with another processing.

In another embodiment, a control system includes an operations memory and a first processor coupled to the operations memory. The first processor is configured to derive digital measurement signal data from a measurement signal. The first processor is further configured to write the digital measurement signal data to the operations memory at an operation memory address. The control system further includes a second processor coupled to the first processor and configured to process, for example, filter and compress the digital measurement signal data based on the operation memory address to obtain selected data.

In an example aspect, a method of use in providing data from a first processor to a second processor includes using the first processor to determine an expected load status of the second processor and, if the expected load status is a predetermined overload status, one Rescheduling data from the first processor to the second processor.

In another embodiment, a first processor is configured to be coupled to a second processor, the first processor having a scheduler configured to schedule transmission of data to the second processor, and a modeling unit configured to to model an operation of the second processor on data transmitted from the first processor to the second processor to determine an expected load status. The scheduler is configured to reschedule transmission of data to the second processor if the expected load status is a predetermined overload status.

In yet another embodiment aspect, a control system includes a first processor configured to derive data from a measurement signal and a second processor coupled to the first processor and remote from the first processor. The first processor includes a modeling unit configured to model an operation of the second processor for data transmitted from the first processor to the second processor to determine an expected load status.

In some embodiments (not shown), the control system includes a plurality of first processors or central processors. The plurality of first processors may be coupled to a common bus and, via the common bus, to a common operation memory. The concepts and principles set forth below with respect to a central processor can thus be implemented with more than one central processor.

In the above description of exemplary implementations, for purposes of explanation, specific numbers, material configurations and other details are set forth in order to better explain the invention as claimed. However, one of ordinary skill in the art appreciates that the claimed invention may be practiced using other details than the examples described herein.

Although some aspects have been described in the context of a device, it is to be understood that these aspects also represent a description of the corresponding method, wherein a block or device corresponds to a method step or feature of a method step. By analogy, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus.

The disclosed arrangements may be partially or fully implemented in hardware using logic circuits or a VLSI design.

The present implementations are described with respect to embodiments. However, it should be understood that individual aspects of the implementations may be claimed separately and one or more of the features of the various embodiments may be combined. In some cases, well-known features are omitted or simplified to clarify the description of the example implementations.

As used herein, the word "exemplary" means serving as an example, a case or an illustration. Any aspect or design described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects or configurations. Rather, the use of the word exemplifies concepts and techniques in a concrete way.

As used herein, the term "or" is intended to mean an inclusive "or" as an exclusive "or". That is, "X implies A or B" should mean any natural permutation included, unless otherwise specified or clear from the context. That is, if X uses A; X B inserts; or X inserts both A and B, "X sets A or B" then satisfied under any of the preceding cases.

As used herein, the words "a" and "an" should generally be construed to mean "one or more," unless otherwise specified or clearly directed to a singular form by context.

As used herein, the terms "coupled" and "connected" may have been used to describe how various elements are linked. Unless expressly stated or otherwise suggested, such linking of various elements described herein may be either direct or indirect.

As used herein, the terms "having," "containing," "including," "having," or variants thereof, and similar terms are open-ended terms that are intended to be inclusive in nature. These terms indicate the presence of said elements or features, but exclude any additional elements or features.

As used herein, the word "continuous" should be understood according to an implemented underlying mode of operation. For example, if it is understood that one system is operating in a clocked mode, the phrase "continuous operation" may mean a clocked mode operation while the formulation does not address operation in another mode.

As used herein, the term "module" may refer to any known or later developed hardware, software, firmware or combination thereof that is capable of performing the functionality associated with that item.

As used herein, the terms "determine," "compute," and "calculate," and variations thereof, are used interchangeably and encompass any type of methodology, process, mathematical operation, or technique.

As used herein, terms such as "first," "second," and the like are also used to describe various elements, regions, portions, and so forth, and are not intended to be limiting in the present.

Claims (26)

A method comprising: Associating an associated processor address register with a predetermined operation; Calling a statement including a reference to a referenced processor address register; and, if the referenced processor address register is the associated processor address register, performing the predetermined operation. Method according to Claim 1 wherein the predetermined operation comprises signaling that the referenced processor address register is the associated processor address register. Method according to Claim 1 or 2 wherein the instruction comprises working on process data, and wherein the predetermined operation comprises writing selected data to a trace port, wherein the selected data is based on the process data. Method according to Claim 3 wherein the instruction comprises accessing an operation memory. Method according to Claim 4 wherein the instruction is one of a group including a write instruction for writing the process data to the operation memory and a read instruction for reading the process data from the operation memory. Method according to Claim 4 or 5 wherein the instruction includes an address offset, the method further comprising: - at the referenced processor address register, storing a representation of a stored operation memory base address; based on the representation of the stored operations memory base address and the address offset, forming an operation memory access address. Method according to Claim 6 wherein forming the operations memory access address comprises: adding the address offset to the stored operations memory base address; or concatenating the representation of the stored operations memory base address and the address offset. Method according to one of Claims 4 to 7 wherein the predetermined operation comprises generating a trace message to be written to the trace port. Method according to one of Claims 3 to 8th further comprising - based on the referenced processor address register, filtering the process data to obtain selected data to be written to the trace port. Method according to one of Claims 1 to 9 wherein the method further comprises: interpreting a content of the referenced processor address register, whether or not the predetermined operation is to be performed; and performing the predetermined operation only if a result of interpreting the content indicates that the predetermined operation should be performed. Method according to Claim 10 wherein the interpreting the content of the referenced processor address register comprises comparing at least a portion of the content with a predetermined representation associated with the predetermined operation and determining the result of the interpreting to indicate that the predetermined operation should be performed if the portion of the content is equal to the predetermined representation. Method according to one of Claims 1 to 11 wherein the method further comprises: including a control code with the reference to the referenced processor address register in the instruction, the control code indicating whether or not the predetermined operation should be performed; and - performing the predetermined operation only if the control code indicates that the predetermined operation should be performed. Method according to one of Claims 6 to 12 wherein the method further comprises: using a sign of the address offset to indicate whether or not the predetermined operation should be performed; and performing the predetermined operation only if the sign of the address offset indicates that the predetermined operation should be performed. A control system comprising: an associated processor address register associated with a predetermined operation; and a first processor configured to invoke an instruction that includes a reference to a referenced processor address register; wherein the control system is configured, if the referenced processor address register is the associated processor address register, to perform the predetermined operation. Control system after Claim 14 wherein the predetermined operation comprises signaling that the referenced processor address register is the associated processor address register. Control system after Claim 12 or 15 wherein the instruction comprises working on process data, wherein the predetermined operation comprises writing selected data to a trace port, and wherein the selected data is based on the process data. Control system after Claim 16 comprising: a memory coupled to the first processor, wherein the first processor is configured to write the process data to the operations memory at an operation memory address or to transfer the process data from the operations memory to the operation memory; Memory address to read. Control system after Claim 17 wherein the instruction includes an address offset and wherein the control system is further configured to store a representation of a stored operations memory base address at the referenced processor address register and, based on the representation of the stored operations memory base address and the address offset, the operations Form memory address. Control system after Claim 17 or 18 wherein the operations memory includes a block of memory cells at the stored operations memory base address; wherein the operations memory access address is offset from the stored operations memory base address by the address offset. Control system after Claim 18 or 19 wherein the control system is configured to form the operations memory address by adding the address offset to the stored operations memory base address or associating the representation of the stored operations memory base address and the address offset. Control system according to one of Claims 15 to 20 wherein the first processor comprises the referenced processor address register. Control system according to one of Claims 14 to 21 wherein the predetermined operation comprises generating a trace message to be written to the trace port. Control system according to one of Claims 16 to 22 method comprising: a second processor coupled to the first processor, the second processor configured to filter the process data based on the referenced processor address register to obtain selected data to be written to the trace port. Control system after Claim 23 wherein the first processor comprises a counter configured to be incremented with transfers of process data from the first processor to the second processor and decremented in proportion to clock cycles. Control system after Claim 23 or 26 , wherein the first processor and the second processor are together in an integrated circuit. Control system according to one of Claims 14 to 25 wherein the control system is configured to control a motor.

Images