DE102017107431B4 - Methods and devices for error correction coding based on high rate generalized concatenated codes - Google Patents

Abstract

Method for error correction coding of data to be stored in a storage device (3), the method being carried out by a coding device (2) and error correction coding being applied to the data to generate coded data which is based on generalized concatenated codes, GCC, where:the GCC is constructed from L inner interleaved binary extended BCH codes and L outer codes, preferably RS codes, where L ≥ 2 is a positive integer;the extended BCH code at the lowest nest level of the inner interleaved BCH codes is an SPC code;the extended BCH code of at least one higher nest level of the inner nested BCH codes has an error correction capability and is a subcode of the BCH code of the lowest nest level; and "BCH code" denotes a Bose-Chaudhuri-Hocquenghem code, "RS code" denotes a Reed-Solomon code, and "SPC code" denotes a single parity check code.

Description

FIELD OF THE INVENTION

The present invention relates to error correction coding, particularly for non-volatile flash memory applications. More precisely, the invention relates to a method for error-correction coding of data to be stored in a storage device, a corresponding method for decoding a codeword matrix resulting from the coding method, a coding device set up to carry out one or more of these methods , and a corresponding computer program for executing these methods on the coding device.

BACKGROUND

Error correction coding (ECC) based on generalized concatenated codes (GC codes) has a high potential for various applications in the field of data communication and data storage systems, for example for digital magnetic storage systems, as in [ 1] (see list of literature sources given below [...]), for non-volatile flash memory (cf. [2]), and for two-dimensional barcodes (cf. [3]). In particular, GC codes can be used for error correction in flash memories, as suggested in [2] and [4].

In particular, such GCC codes can be constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes, such as generally described in [5], [6], and [7]. , and they are well suited for fast hardware-based decoder architectures (cf. [4]). In the theory of coding, the BCH codes form a class of linear cyclic error correction codes constructed using finite fields (Galois fields, GF), while the Reed-Solomon codes belong to the class of non-binary cyclic error correction codes belong and are based on univariant polynomials over finite fields (GF).

U.S. 7,296,212 B1 describes multi-dimensional irregular array codes and methods for forward error correction, and apparatus and systems using such codes and methods. Specifically disclosed are methods, apparatus and systems for encoding information symbols comprising loading information symbols into a data array having n ⁽¹⁾ rows and n ⁽²⁾ columns, each column having k ⁽¹⁾ information symbols and where k ⁽¹⁾ one field that has at least two different values, coding each column with a code C ⁽¹⁾ from a family of nested codes C ⁽¹⁾ , where C ⁽¹⁾ contains two different nested codes, and coding each row with a code C ⁽²⁾ .

Flash memory, especially NAND flash memory, is an important component of embedded systems and consumer electronics. Flash memory requires ECC to ensure data integrity and reliability for the user data (see [8]). In many flash technologies, a binary symmetric channel (BSC) can be assumed as the statistical error model. Therefore, BCH codes are typically used for error correction, as described for example in [9], [10], [11], [12] and [13]. GC codes have lower decoding complexity than long BCH codes. Flash memory typically reserves an extra memory area that is used to store the redundancies needed for the ECC. This extra memory area determines the code rate for the error correction code.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide methods and devices for further improving error correction coding, in particular for improving code rates. In particular, it is desirable that such methods and apparatus are capable of enhanced ECC encoding/decoding of data associated with storing/reading that data to/from a memory such as non-volatile memory.

A solution to this problem is achieved through the teaching of the independent claims. Various preferred embodiments of the present invention are subject of the dependent claims.

A first aspect of the invention relates to a method for error correction coding of data to be stored in a storage device, the method being carried out by a coding device and error correction coding being applied to the data to generate coded data based on Generalized Concatenated Codes (GCC), based. Here (i) the GCC is constructed from L inner interleaved binary extended Bose-Chaudhuri-Hocquenghem codes (BCH codes) and L outer codes, preferably Reed-Solomon codes (RS codes), where L ≥ 2 a positive integer number is, (ii) the extended BCH code at the lowest nesting level of the inner nested BCH codes is a single parity check (SPC) code, and (iii) the extended BCH code of at least one higher nest level of the inner nested BCH codes has an error correction capability (in contrast to the SPC code, which can only detect certain errors) and is a subcode of the BCH code of the lowest nest level.

The term "extended BCH code" as used herein refers to a code whose codewords generally include both a BCH codeword and an additional simple parity check (SPC) symbol (i.e., a parity bit if the SPC symbol is only a single bit). However, a mere SPC code (without further BCH parity symbols) is already an extended BCH code and represents even its simplest form. While a BCH code (which is not just an SPC code) requires the correction of a certain number of Allowing for errors in a codeword during decoding, an SPC code only allows certain errors to be detected, especially when there is an odd number of errors in the codeword.

The term "subcode" of a particular (parent) BCH code, as used herein, refers to a code that consists of a true subset of the codewords of the (parent) BCH code. So a BCH code B ⁽ⁿ⁾ is a subset of another BCH code B ^(m) if the set of code words of B ⁽ⁿ⁾ is a proper subset of the set of code words of B ^(m) . Specifically, the subcode may be the BCH code of a certain nesting level of the nested structure of the inner nested BCH codes, which subcode is a subset of a BCH code of a lower level of the nested structure. Accordingly, in the nested structure B ^(L-1) ⊆ B ^(L-2) ⊆ .... ⊆ B ^(0), the BCH code B ^(Lq) with L > q > 0 and the integer q is an a subcode at least the BCH code B ⁽⁰⁾ of the lowest nesting level 0 and, if q < L-1, also any higher nested BCH code defined between B ⁽⁰⁾ and B ^(Lq) in the nested structure. An interleaving of the BCH codes with different levels is described in particular in [2] and [4].

Preferably the outer codes are block codes and most preferably RS codes.

While the code constructions described in references [2] and [4] are limited to codes having an overall code rate less than or equal to 0.9, which is indicated by flash memory that only has a small extra storage area for storing the redundancy needed for the ECC is not applicable, the coding method according to the first aspect of the present invention enables high-rate GC codes with code rates above 0.9. Accordingly, such high-rate GC codes can be used to encode data to be stored in memories, such as flash memories, which provide only a small amount of extra storage space. Although in the lowest nesting level only SPC is used instead of higher BCH codes, comparable ECC error correction levels can be achieved and thus the efficiency (code rate) of the code can be increased. In other words, the efficiency of such memories in terms of their storage capacity for user data can be improved due to the increased code rate.

Preferred embodiments of the coding method according to the first aspect are described below, which can be combined with one another or with the other aspects of the invention as desired, unless such a combination is expressly excluded or technically impossible.

• (i) Anordnen der zu codierenden Daten in einer zweidimensionalen Datenmatrix mit einer ersten Dimension n_a, die der Länge der äußeren RS-Codes entspricht, und einer zweiten Dimension n_b, die der Länge der inneren erweiterten BCH-Codes entspricht, wobei eine Linie der ersten Dimension einer Matrix eine Zeile der Matrix und eine Linie ihrer zweiten Dimension eine Spalte der Matrix ist, oder andersherum, und die äußeren RS-Codes über ein Galois-Feld GF(2^m1) definiert sind, sodass m₁ Elemente jeder Linie der zweiten Dimension ein Symbol des Galois-Feld GF(2^m1) darstellen;
• (ii) Anwenden der L äußeren RS-Codes auf die entsprechenden L * m₁ Linien der ersten Dimension der Datenmatrix, sodass jeder der L äußeren RS-Codes ein Codewort aus den entsprechenden m₁ Linien der zweiten Dimension liefert und insgesamt L * m₁ Linien der sich ergebenden Zwischenmatrix durch die äußeren RS-Codes geschützt sind, wobei m₁ eine positive Ganzzahl ist, mit vorzugsweise m₁ > 1; und
• (iii) nachfolgend Anwenden der inneren verschachtelten erweiterten BCH-Codes auf die Linien der zweiten Dimension der Zwischenmatrix, um eine Codewortmatrix zu erhalten, welche die codierten Daten enthält, sodass n_b - L * m₁ Linien der ersten Dimension der Codewortmatrix für die Codierungsredundanz der inneren verschachtelten erweiterten BCH-Codes verwendet werden, und jede Linie der zweiten Dimension der Codewortmatrix gleich der Summe der L Codeworte der einzelnen verschachtelten erweiterten BCH-Codes für diese Linie ist.

According to a first preferred embodiment, applying error correction coding comprises:

• (i) Arranging the data to be encoded in a two-dimensional data matrix with a first dimension _{na corresponding to the length of the outer RS codes and a second dimension n b corresponding} to the length of the inner extended BCH codes, where a line the first dimension of a matrix is a row of the matrix and a line of its second dimension is a column of the matrix, or vice versa, and the outer RS codes are defined over a Galois field GF(2 ^m1 ) such that m ₁ elements of each line of the second dimension represent a symbol of the Galois field GF(2 ^m1 );
• (ii) Applying the L outer RS codes to the corresponding L * m ₁ lines of the first dimension of the data matrix, such that each of the L outer RS codes yields a codeword from the corresponding m ₁ lines of the second dimension, and a total of L * m ₁ Lines of the resulting intermediate matrix are protected by the outer RS codes, where m ₁ is a positive integer, with preferably m ₁ >1; and
• (iii) subsequently applying the inner interleaved extended BCH codes to the lines of the second dimension of the intermediate matrix to obtain a codeword matrix containing the encoded data such that n _b - L * m ₁ lines of the first dimension of the codeword matrix for the coding redundancy of the inner nested extended BCH codes are used, and each line of the second dimension of the codeword matrix is equal to the sum of the L codewords of the individual nested extended BCH codes for that line.

This embodiment enables a particularly efficient and clearly structured implementation of the method according to the first aspect of the present invention.

wobei die Codeworte $b_j^{\left(i\right)}$

gebildet werden, indem die Symbole a_j,i mit den erweiterten BCH-Codes B⁽ⁱ⁾ der i-ten Verschachtelungsebene codiert werden, wobei a_j,i das j-te Symbol aus m₁ Bits des i-ten äußeren RS-Codes A⁽ⁱ⁾ entlang der ersten Richtung der Zwischenmatrix ist und für diese Codierung (L - i -1)*m₁ Nullbits vor oder nach dem Symbol a_j,i an dieses angehängt werden. Diese Ausführungsform ermöglicht insbesondere eine einfache, effiziente und klar strukturierte Implementierung des Verfahrens, weil aufgrund der Hinzufügung der Nullbits eine konstante Länge der Codeworte sowohl der äußeren RS-Codes als auch der darauf aufbauenden erweiterten BCH-Codes erreicht wird.According to a related further preferred embodiment, the code word b _j of the jth line of the second dimension of the code word matrix is determined by the following formula: $$b_j={\displaystyle \sum _{i=0}^{L-1}{b}_j^{\left(i\right)}}$$

where the code words $b_j^{\left(i\right)}$

are formed by encoding the symbols a _j,i with the extended BCH codes B ⁽ⁱ⁾ of the i-th nesting level, where a _j,i is the j-th symbol from m ₁ bits of the i-th outer RS code A ⁽ⁱ⁾ along the first direction of the intermediate matrix and for this coding (L - i -1)*m ₁ zero bits are appended to the symbol a _j,i before or after it. In particular, this embodiment enables a simple, efficient and clearly structured implementation of the method because the addition of the zero bits means that the code words of both the outer RS codes and the extended BCH codes based thereon have a constant length.

According to a further preferred embodiment, the code rate of the first RS code word defined along the direction of the second dimension of the intermediate matrix (which corresponds to i=0 in the above sum) is lower than the code rate of the Lth RS code word defined along this direction (which corresponds to i = L -1 in the above sum). Accordingly, this can be used to further increase the overall code rate of the code without sacrificing its security level. Such a reduction of the code rates of the RS code words along the direction of the second dimension of the matrix is possible because on the decoding side the structure of the overall GCC code as it results from the decoding allows reuse of the decoding results of a given level i to Next level i+1 decoding allowed.

According to another preferred embodiment, the inner extended BCH codes are defined over a Galois field GF (2 ^m2 ) and m ₁ is different from m ₂ , where m ₂ is a positive integer. In a first preferred variant thereof, m ₁ = 8 and m ₂ = 6. In a second preferred variant, m ₁ = 9 and m ₂ = 7. The number of nesting levels for the inner extended BCH codes is special in this second variant preferably 13, so that n _a = 152 and n _b = 118. Furthermore, for each of said nesting levels j, the corresponding code dimension of the inner extended BCH code k _b,j and its minimum Hamming distance db _,j as well as the corresponding code dimension k _{a ,j} of the outer RS code and its minimum Hamming distance d _a,j must be those from the following table: j k _b,j d _b,j k _a,j d _a,j 0 117 2 84 69 1 108 4 130 23 2 99 6 136 17 3 90 8th 142 11 4-12 81 12 148 5

The GC code according to this embodiment is particularly suitable for error correction in data storage in flash memory. Specifically, this GC code is adapted for 2KB information blocks, i. H. for a code that can be used to store 2 KB of data and an additional 4 bytes of meta information. This applies in particular to the second variant mentioned, including when it is implemented according to the table mentioned above.

According to a further preferred embodiment, in the step of applying the inner nested extended BCH codes to the lines of the second dimension of the intermediate matrix, at least in one of the nesting levels, preferably in the lowest nesting level, the single parity bit of the corresponding extended BCH code of this nesting level is off a predefined real subset of the bits of the corresponding line of the second dimension. In particular, this can lead to increased performance of the coding because fewer bits have to be involved in the calculation of the parity symbols or parity bits of the SPC belonging to the corresponding extended BCH code(s).

According to a further preferred embodiment, the method further comprises transferring the obtained encoded data to one or more storage devices for storing the data therein. Especially when--as described in the preferred embodiments explained above--the data to be encoded are arranged in a two-dimensional data matrix and the resulting encoded data are thus arranged in a corresponding two-dimensional array Len code word matrix are arranged, the received encoded data to be stored contain this code word matrix, at least in part.

A second aspect of the present invention relates to a method for iterative error correction decoding of a codeword matrix based on generalized concatenated codes (GCC), where: the GCC consists of L inner interleaved binary extended Bose-Chaudhuri-Hocquenghem codes (BCH codes) and L outer codes, preferably constructed from Reed-Solomon codes (RS codes), where L ≥ 2 is a positive integer; the extended BCH code at the lowest nest level of the inner nested BCH codes is only a single parity check (SPC) code; and the extended BCH code of at least one higher nest level of the inner nested BCH codes has an error correction capability and is a subcode of the BCH code of the lowest nest level.

• (i) eine erste Iteration, die zu der niedrigsten Verschachtelungsebene der inneren erweiterten BCH-Codes der Codewortmatrix korrespondiert und die folgenden Schritte aufweist:
  • - Anwenden einer SPC-Decodierung auf die Linien der zweiten Dimension der Codewortmatrix bezüglich der niedrigsten Verschachtelungsebene der inneren verschachtelten erweiterten BCH-Codes, in denen die Linien einer zweiten Dimension der Codewortmatrix codiert sind, um eine vorläufige Decodierdatenmatrix der ersten Iteration zu erhalten und Löschinformationen festzustellen, welche die Linien der zweiten Dimension der Codewortmatrix charakterisieren, in denen beruhend auf der SPC-Decodierung eine Löschung detektiert wurde;
  • - Entnehmen der Informationsbits, die in den Linien der zweiten Dimension der vorläufigen Decodierdatenmatrix der ersten Iteration enthalten sind, um Codesymbole der äußeren RS-Codes wiederzugewinnen, in denen die Linien einer ersten Dimension der Codewortmatrix codiert sind;
  • - Anwenden einer RS-Decodierung, die zu den entsprechenden RS-Codes korrespondiert, welche zur Erzeugung der ursprünglichen Codewortmatrix während des Codierens verwendet wurden, auf die wiedergewonnenen RS-Symbole in den Linien der ersten Dimension der vorläufigen Decodierdatenmatrix der ersten Iteration, um eine Teildecodierungsergebnismatrix der ersten Iteration zu erhalten, wobei die Löschinformationen während der RS-Decodierung verwendet werden, um fehlerhafte RS-Symbole in der vorläufigen Decodierdatenmatrix der ersten Iteration zu identifizieren;
  • - Zurückcodieren der Teildecodierungsergebnismatrix der ersten Iteration durch Anwendung einer SPC-Codierung auf die zweite Dimension dieser Matrix, um eine zurückcodierte Matrix der ersten Iteration zu erhalten; und
  • - Subtrahieren der zurückcodierten Matrix der ersten Iteration von der Codewortmatrix, um eine Startmatrix für eine nachfolgende weitere Iteration zu erhalten; und
• (ii) für jede der weiteren Verschachtelungsebenen der inneren erweiterten BCH-Codes der Codewortmatrix, eine entsprechende weitere Iteration mit den folgenden Schritten:
  • - Anwenden der erweiterten BCH-Decodierung auf die Linien der zweiten Dimension der Start Matrix der aktuellen Iteration bezüglich der aktuellen Verschachtelungsebene der inneren verschachtelten erweiterten BCH-Codes, in denen die Linien einer zweiten Dimension der Startmatrix der aktuellen Iteration codiert sind, um eine vorläufige Decodierdatenmatrix der aktuellen Iteration zu erhalten;
  • - Entnehmen der Informationsbits, die in den Linien der zweiten Dimension der vorläufigen Decodierdatenmatrix der aktuellen Iteration enthalten sind, um Codesymbole der äußeren RS-Codes wiederzugewinnen, in denen die Linien einer ersten Dimension der Codewortmatrix codiert sind;
  • - Anwenden einer RS-Decodierung, die zu den entsprechenden RS-Codes korrespondiert, welche zur Erzeugung der ursprünglichen Codewortmatrix während des Codierens verwendet wurden, auf die wiedergewonnenen Code Symbole in den Linien der ersten Dimension der vorläufigen Decodierdatenmatrix der aktuellen Iteration, um eine Teildecodierungsergebnismatrix der aktuellen Iteration zu erhalten;
  • - falls die aktuelle Iteration zu der höchsten Verschachtelungsebene der inneren verschachtelten erweiterten BCH-Codes in der Codewortmatrix korrespondiert, ausgeben der Teildecodierungsergebnismatrix der aktuellen Iteration als eine sich aus der Decodierung ergebende Datenmatrix, und
  • - andernfalls, Zurückcodieren der Teildecodierungsergebnismatrix der aktuellen Iteration durch Anwendung einer erweiterten BCH Codierung, die zu der aktuellen Verschachtelungsebene korrespondiert, auf die zweite Dimension dieser Matrix, um eine zurückcodierte Matrix der aktuellen Iteration zu erhalten; und Subtrahieren der zurückcodierten Matrix der aktuellen Iteration von der Startmatrix der aktuellen Iteration, um eine Startmatrix für eine nachfolgende weitere Iteration zu erhalten.

The decoding process features:

• (i) a first iteration, corresponding to the lowest nesting level of the inner extended BCH codes of the codeword matrix, comprising the following steps:
  • - Applying an SPC decoding to the lines of the second dimension of the codeword matrix with respect to the lowest nesting level of the inner nested extended BCH codes in which the lines of a second dimension of the codeword matrix are encoded to obtain a preliminary decoding data matrix of the first iteration and detect erasure information , which characterize the lines of the second dimension of the codeword matrix in which an erasure was detected based on the SPC decoding;
  • - extracting the information bits contained in the lines of the second dimension of the preliminary decoding data matrix of the first iteration in order to recover code symbols of the outer RS codes in which the lines of a first dimension of the codeword matrix are encoded;
  • - applying an RS decoding corresponding to the respective RS codes used to generate the original codeword matrix during encoding to the recovered RS symbols in the first dimension lines of the first iteration preliminary decoding data matrix to obtain a partial decoding result matrix the first iteration, wherein the erasure information is used during RS decoding to identify erroneous RS symbols in the preliminary first iteration decoding data matrix;
  • - recoding the partial decoding result matrix of the first iteration by applying an SPC coding to the second dimension of this matrix to obtain a recoded matrix of the first iteration; and
  • - subtracting the recoded matrix of the first iteration from the codeword matrix to obtain a starting matrix for a subsequent further iteration; and
• (ii) for each of the further nesting levels of the inner extended BCH codes of the codeword matrix, a corresponding further iteration with the following steps:
  • - Applying extended BCH decoding to the lines of the second dimension of the current iteration's start matrix with respect to the current nesting level of the inner nested extended BCH codes in which the lines of a second dimension of the start matrix of the current iteration are encoded, by a preliminary decoding data matrix get the current iteration;
  • - extracting the information bits contained in the lines of the second dimension of the preliminary decoding data matrix of the current iteration in order to recover code symbols of the outer RS codes in which the lines of a first dimension of the codeword matrix are encoded;
  • - applying an RS decoding corresponding to the respective RS codes used to generate the original codeword matrix during encoding to the recovered code symbols in the first dimension lines of the current iteration's preliminary decoding data matrix to obtain a partial decoding result matrix of the get current iteration;
  • - if the current iteration corresponds to the highest nesting level of the inner nested extended BCH codes in the codeword matrix, outputting the partial decoding result matrix of the current iteration as a decoding-resultant data matrix, and
  • - otherwise, recoding the partial decoding result matrix of the current iteration by applying an extended BCH coding corresponding to the current nesting level to the second dimension of this matrix to obtain a recoded matrix of the current iteration; and subtracting the recoded matrix of the current iteration from the starting matrix of the current iteration to get a starting matrix for a subsequent further iteration.

In this way, this method enables the decoding of ECC encoded data arranged in a codeword matrix, which is obtainable by applying the matrix-based preferred embodiments of the coding methods described herein. This method enables increased code rates, in particular even code rates above 0.9. This becomes achievable because due to the interaction of the SPC decoding and the BCH coding in the first iteration, the erasure information during the RS decoding is used to identify erroneous RS symbols in the preliminary decoding data matrix of the first iteration, the reduction of the parity symbols, which now only refer to an SPC coding instead of a BCH coding for the lowest interleaving level, creates additional space for data within the code without increasing the overall length of the GCC code or its security level, in particular its error correction ability, to affect. In addition, performance improvements are even made possible because the processing of the SPC-based first iteration is less complex than the other BCH-based iterations.

According to a preferred embodiment of this decoding method, for at least one of the further iterations: (i) the step of applying the extended BCH decoding further comprises detecting erasure information characterizing lines of the second dimension of the starting matrix of the current iteration in which based an erasure was detected on SPC decoding of an SPC parity bit contained in the extended BCH code of the current iteration; and (ii) in the step of applying RS decoding, said current iteration erasure information is used during RS decoding to identify erroneous RS symbols in the preliminary decoding data matrix of the current interaction. In this way, the concept of the interaction between the SPC decoding and the BCH decoding can be further expanded. In particular, this can lead to further improvements in performance and/or code rate by using extended BCH codes of a higher code dimension k, i. H. with less redundancy overhead.

A third aspect of the present invention relates to a coding device, in particular a semiconductor device having a memory controller. The coding device is set up to carry out the coding method according to the first aspect and/or the decoding method according to the second aspect, each preferably according to one or more of the preferred embodiments described herein.

According to a preferred embodiment thereof, the coding device has one or more processors, a memory and one or more programs stored in the memory which, when executed on the one or more processors, cause the coding device, said coding method and/or said perform the decoding process.

A fourth aspect of the present invention relates to a computer program which contains instructions which cause a coding device, preferably the coding device according to the third aspect, to carry out the coding method according to the first aspect and/or the decoding method according to the second aspect, the coding device and each of the said methods are preferably formed in accordance with one or more of their associated preferred embodiments described herein.

The computer program can be implemented in particular in the form of a data carrier on which one or more programs for executing the method or methods are stored. This is preferably a data carrier in the form of a CD, a DVD or a flash memory module. This may be advantageous when the program is intended to be traded as a distinct product independent of the processor platform on which the one or more programs are to be executed. In another implementation, the computer program is provided as a file on a data processing unit, preferably on a server, and can be downloaded via a data connection, for example via the Internet or a dedicated data connection, for example via a proprietary or local area network.

Accordingly, the properties and advantages described here of the methods according to the first and/or the second aspect of the invention also apply mutatis mutandis to the coding device according to the third aspect and the computer program according to the fourth aspect.

In particular, the present invention enables high-rate codes. In addition, the use of extended BCH codes makes it possible to detect decoding errors in the inner codes. These errors can be using exploit the fact that the algebraic decoding methods for the relevant outer codes, especially for RS codes, can correct both errors and erasures. If outer RS decoding is configured to correct up to t errors, it can correct up to 2t erasures. Furthermore, these GC codes are basically able to correct burst errors. The proposed GC codes are well suited for error correction in flash memory for high reliability data storage because very low residual error probabilities can be achieved. The GC codes have a performance similar to that of pure BCH codes, but they can be decoded faster and with a lower decoder complexity (cf. [4]). Furthermore, the GC codes can use reliability information regarding the channel [17].

character list

• 1 gemäß einer bevorzugten Ausführungsform der vorliegenden Erfindung schematisch eine Codierungsvorrichtung in Form eines Speichercontrollers innerhalb eines Speichersystems illustriert;
• 2 gemäß einer bevorzugten Ausführungsform der vorliegenden Erfindung schematisch ein Codierungsschema für die Transformation einer Datenmatrix, welche zu codierende Informationen enthält, in eine korrespondierende Codewortmatrix illustriert;
• 3 gemäß einer bevorzugten Ausführungsform der Erfindung schematisch eine vereinfachte Version des Codierungsschemas aus 2 in größeren Detail illustriert;
• 4 gemäß einer bevorzugten Ausführungsform der vorliegenden Erfindung schematisch ein Decodierungsschema für eine Codewortmatrix illustriert, die gemäß dem Codierungsschema aus 2 erhältlich ist; und
• 5 ein Diagramm zeigt, welches gemäß einer bevorzugten Ausführungsform der vorliegenden Erfindung die Coderate gegenüber dem Signal-zu-Rauschverhältnis für beispielhafte GC-Codes im Vergleich zu langen BCH-Codes bei algebraischer Decodierung zeigt.

Further advantages, features and possible applications of the present invention result from the following detailed description in connection with the attached figures, in which:

• 1 Figure 12 schematically illustrates an encoding device in the form of a memory controller within a memory system, according to a preferred embodiment of the present invention;
• 2 according to a preferred embodiment of the present invention, schematically illustrates a coding scheme for the transformation of a data matrix, which contains information to be coded, into a corresponding codeword matrix;
• 3 according to a preferred embodiment of the invention, schematically shows a simplified version of the coding scheme 2 illustrated in greater detail;
• 4 according to a preferred embodiment of the present invention schematically illustrates a decoding scheme for a codeword matrix coded according to the coding scheme from 2 is available; and
• 5 Figure 12 is a graph showing code rate versus signal-to-noise ratio for exemplary GC codes versus long BCH codes when algebraically decoded, in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

1 FIG. 1 shows an exemplary memory system 1, which has a memory controller 2 and a memory device 3, which in particular can be a flash memory device, for example of the NAND type. The storage system 1 is connected to a host 4, such as a computer owning the storage system 1, via a set of address lines A1, a set of data lines D1 and a set of control lines C1. The memory controller 2 comprises a processing unit 2a and an internal memory 2b, typically of the embedded type, and is connected to the memory 3 via an address bus A2, a data bus D2 and a control bus C2. Accordingly, the host 4 has indirect read and/or write access to the memory 3 via its connections A1, D1 and C1 to the memory controller 2, which in turn can access the memory 3 directly via the buses A2, D2 and C2. Each of the sets of lines or buses A1, B1, C1, A2, B2 and C2 can be implemented using one or more individual communication lines.

The memory controller 2 is also configured as a coding device and is therefore arranged to carry out the coding and decoding methods of the present invention, in particular as described below with reference to FIG 2 until 4 described. For this purpose, the memory controller 2 can have a computer program stored in its internal memory 2B, which is configured to carry out one or more of these coding methods when it is executed on the processor unit 2a of the memory controller 2. As an alternative to this, the program can, for example, be stored in whole or in part in the memory 3 or in an additional program memory (not shown), or even be implemented by means of a hard-wired circuit.

The in the 2 until 4 The coding methods illustrated are based on the use of GC codes for error correction in memories, such as flash memories, which require high-rate codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. Extended BCH codes are used for the inner codes, where simple parity check codes are used on the first level of the GC code (cf. 2 and 3 ). This construction enables high rate GC codes. A corresponding decoding method for the GC codes is in 4 illustrated. A detailed basic discussion of GC codes can be found in [5].

Below is on 2 1, which illustrates the encoding process of a GC code in accordance with a preferred embodiment of the present invention. The GC code word is arranged in an n _b × n _a matrix, where _{na and n b are} the lengths of the outer and inner codes, respectively. Coding starts with the outer codes. The rows are protected by L Reed-Solomon codes of length na _, ie L denotes the number of levels. m elements of each column represent a symbol of the Galois field GF(2 ^m ). Accordingly, m adjacent rows form a codeword of an outer code A ⁽ⁱ⁾ , i=0,...,L-1. Note that the code rate of the outer codes increases from level to level. The outer codes protect Lm rows of the matrix. The remaining n _b - Lm rows are used for redundancy of the inner codes.

The shaded area in 2 illustrates the redundancies of the code components that are filled by the outer and inner coding. After the outer coding, the columns of the codeword matrix are coded with binary inner codes of length _nb . Each column of the codeword matrix is the sum of L codewords from interleaved linear BCH codes. $$B^{\left(L-1\right)}\subseteq B^{\left(L-2\right)}\subseteq ...\subseteq B^{\left(0\right)}$$

Thus, a higher level code is a subcode of its predecessor, with the higher levels having higher error correction capabilities, ie t _b , _L-1 ≥ t _b,L-2 ≥ ... ≥, t _b,0 , where t _b,i is the level i error correction capability. The code dimensions are k ⁽⁰⁾ =Lm, k ⁽¹⁾ =(L-1)m,..., k ^(L-1) =m.

The codeword b _j of the j-th column is the sum of the L codewords. $$b_j={\displaystyle \sum _{i=0}^{L-1}{b}_j^{\left(i\right)}}$$

werden durch Codierung der Symbole a_j,i mit dem korrespondierenden Subcode B⁽ⁱ⁾ gebildet, wobei a_j,i das j-te Symbol (m Bits) des äußeren Code A⁽ⁱ⁾ ist. Für diese Codierung werden dem Symbol a_j,i (L - i - 1)m Null-Bits vorangestellt. Es ist zu vermerken, dass die j-te Spalte b_j wegen der Linearität der verschachtelten Codes ein Codewort von B⁽⁰⁾ ist.Those code words $b_j^{\left(i\right)}$

are formed by encoding the symbols a _j,i with the corresponding subcode B ⁽ⁱ⁾ , where a _j,i is the jth symbol (m bits) of the outer code A ⁽ⁱ⁾ . For this encoding, the symbol a _j,i is prefixed with (L - i - 1)m zero bits. Note that the _jth column bj is a codeword of B ⁽⁰⁾ because of the linearity of the interleaved codes.

3 Figure 1 illustrates this coding scheme in more detail based on a simple exemplary case (Example 1) where L=2, m=3 and _na = _nb =7 is chosen. So in this example there are only L = 2 levels and with m ₁ = m = 3 bits per symbol the outer RS codes are constructed over the Galois field GF(2 ³ ), while for the sake of simplicity the inner extended BCH- Codes are defined via GF(2 ¹ ), ie m ₂ =1. In a first step S1, a data structure, which represents an n _b × n _a matrix (here 7 × 7 matrix) D, is filled with data to be encoded, which consist of 24 information bits i ₀ to i ₂₃ . The filling scheme corresponds to that of the data matrix D in 2 . Accordingly, in the first level (i=0) the number of information bits is lower than in the second level (i=1) and the remaining prefixed bits of both levels are reserved for the redundancy that is added in a subsequent step S2 by means of the outer coding becomes. Each symbol has three adjacent bits of the same column, so for example in the fifth column of D, bits i ₀ , i ₃ and i ₆ form a first symbol of the column and bits i ₁₁ , i ₁₆ i ₂₁ form another symbol. In addition, the last row of the matrix D is reserved for redundancy, which is added by means of the inner coding in a further step S3.

In step S2 for outer coding, the information is encoded in each of the two levels i=0 and i=1 using a corresponding RS code, the code dimension of the outer RS code for level 0 being only k _a ⁽⁰⁾ = 3, while the level 1 code dimension is increased to k _a ⁽¹⁾ =5. The outer coding in step S2 results in an intermediate matrix A having the code symbols a _i,j , each of these symbols a _i,j having m ₁ = 3 bits and the rows of the matrix A being code words of the outer code.

In the inner coding step S3, each of the symbols a _i,j of the intermediate matrix A is individually coded by means of a corresponding inner code in the form of an extended BCH code B ⁽ⁱ⁾ . In the first level i=0, the corresponding extended BCH code B ⁽⁰⁾ is just a single parity check (SPC) code. Accordingly, as in 3 for the symbol a _4,0 exemplifies each symbol a _{0, j} of level 0 (j = 0, ..., 6) by prefixing (L - i-1)* m ₁ , ie (2 - 0 - 1) *3 = 3 zero bits (i.e. "0" symbol) encoded before the symbol and applying an SPC code to the two symbols, which is added in the last row of the column, giving a resulting codeword b _j ⁽⁰⁾ for column j and level 0.

In the second level i=1, the corresponding extended BCH code B ⁽¹⁾ which, unlike the SPC code, has an error correction capability of 1 bit, is applied in each column of the matrix A to the corresponding symbol a _j,1 . Since this is already the last level in this simple example, there is no need to prepend "0" symbols. Again an SPC code is applied to the resulting BCH codeword and added to the last row of the corresponding column j.

In order to obtain the final GC codeword matrix C, column by column all of the individual codewords b _j ⁽ⁱ⁾ of all levels are the of column j according to formula (2) above to obtain the corresponding codeword b _j , which then represents column j of the resulting GC codeword matrix C, as again exemplified in 3 illustrated for column j = 4.

In another example (Example 2) that goes to 2 Correspondingly, we consider a GC code suitable for error correction in flash memory. The GC code is designed for 2KB information blocks, ie it is a code that can be used to store 2KB of data and an additional 4 bytes of meta information. For this GC code we use L = 13 levels with inner nested BCH codes over GF(2 ⁷ ), ie m ₂ = 7, and outer RS codes over GF(2 ⁹ ) (ie m ₁ = 9). In the first level i = 0 we apply simple parity check codes SPC. Thus all inner codes are extended BCH codes of length n _b = 13. 9 + 1 = 118.

und die Länge n = n_a · n_b = 17936. TABELLE I j k _b,j d _{b, j} K _a,j d _a,j 0 117 2 84 69 1 108 4 130 23 2 99 6 136 17 3 90 8 142 11 4-12 81 12 148 5
Parameter des Beispielscodes. k_b,j und d_b,_j sind die Codedimension und die minimale Hammingdistanz des binären inneren Codes der Ebene j. k_a,j und d_a,j sind die Codedimension und die minimale Hammingdistanz der äußeren RS-Codes.The outer RS codes are constructed over the Galois field GF(2 ⁹ ). Thus the code dimension of the inner codes is reduced by m ₁ = 9 bits from level to level. The GC code is constructed from L=13 outer RS codes of length _na =152. The parameters of the codes are summarized in Table I, where we use the same RS codes in each of levels 4 to 12. The code as a whole has the code dimension $k=m{\displaystyle \sum {}_{j=0}^{L-1}{k}_{a,j}=16416}$

and the length n = n _a n _b = 17936. TABLE I j k _b,j db _{, j} K _a,j d _a,j 0 117 2 84 69 1 108 4 130 23 2 99 6 136 17 3 90 8th 142 11 4-12 81 12 148 5
Parameters of the example code. k _b,j and _db , _j are the code dimension and minimum Hamming distance of the binary inner code of level j. k _a,j and d _a,j are the code dimension and minimum Hamming distance of the outer RS codes.

This code has a code rate R = 0.915. It is also able to correct burst errors. The minimum distance of all outer RS codes is greater than or equal to 5. Consequently, each of the outer codes can correct at least two erroneous symbols, and thus two columns of the codeword matrix can be corrupted by any number of errors.

4 FIG. 12 illustrates, according to a preferred embodiment of the present invention, a corresponding decoding scheme for a codeword matrix r, which in principle is produced by means of the coding scheme 2 is available. In fact, the codeword matrix r to be decoded may differ from the original codeword matrix C, as derived from the application of the coding scheme 2 may be different if the data to be encoded has previously been encoded (e.g. before being stored in a memory) by means of one or more erroneous symbols caused by an unintentional modification of the original codeword matrix C. Such a modification could be caused, for example, by one or more faulty memory cells within the memory device, by memory degradation, by write/read disturbs, or other influences on the data.

The decoder, eg the coding device in the memory controller 2 1 , processes the received data matrix r level by level, starting with i = 0 up to the last level i = n, with n = L-1, where i is the index of the current level. 4 Figure 12 depicts the decoding steps Si-1 to Si-5. First, the columns of the data matrix r are decoded (Si-1) with respect to B ⁽ⁱ⁾ and information bits have to be extracted (de-mapping, Si -2) to form the code symbols a _{i ,j} from A ⁽ⁱ⁾ , where j is the column index. When all symbols of code A ⁽ⁱ⁾ have been extracted, the RS code can be decoded (Si-3). At this point a partial decoding result â _i is available. Finally, this result must be recoded (Si-4) using B ⁽ⁱ ). The inner code B ⁽ⁱ⁾ estimated codewords are subtracted (Si-5) from the codeword matrix before the next level can be decoded.

A similar coding and decoding process is also described in detail in [14]. However, in deviation from this, according to the present invention, in the first level i=0 only error detection can be applied for the simple parity check codes (S0-1). The simple parity check code can detect any odd weight error. If an error is detected in column j, the corresponding symbol a _0,j is considered an erasure. After evaluating the error in the simple parity check code, erasure decoding can be applied to the RS code (cf. [15]). Starting with the second level, the structure of the interleaved BCH codes can be exploited, ie a BCH code can be decoded that can correct a single bit error per codeword due to the expansion of the BCH code any error of weight 2 can be detected . In this In this case, an inner code decoding error is declared, considering the inner code decoding errors as deleted symbols of the RS code. Accordingly, error and erasure decoding are used at all levels of the RS code.

5 1 illustrates the error correction performance of an exemplary GC code according to the present invention. More specifically, it shows a plot of code rate versus noise-to-signal ratio SNR (“E _b /N ₀ ”) for the example GC code versus long BCH codes when algebraically decoded. The code rate required to guarantee a total block error rate of less than 10 ^-16 for a given error probability in the channel is used as a performance measure. The comparison clearly shows that the achievable code rate of the GC codes is higher than the code rate of the long BCH codes across almost all values of SNR.

All of the individual codes of this example GC code are constructed similar to the code presented in Example 2 above. In particular, the inner codes are chosen according to Table / above, while the error correction capability of the outer codes is adjusted to obtain the highest possible code rate for an error probability in the channel. It should be noted that in this example, due to the choice of the inner codes, the overall code rate of the GC code is at most R=0.99. In contrast, the codes described in [2], [4] only have a code rate of 0.9 or below.

REFERENCES

• [1] A. Fahrner, H. Griesser, R. Klarer, and V. Zyablov, "Low-complexity GEL codes for digital magnetic storage systems," IEEE Transactions on Magnetics, Vol. 40, No. 4, pp. 3093- 3095, July 2004.
• [2] J. Freudenberger, U. Kaiser, and J. Spinner, "Concatenated code constructions for error correction in non-volatile memories," in Int. Symposium on Signals, Systems, and Electronics (ISSSE), Potsdam, October 2012, pp. 1-6.
• [3] J. Freudenberger, J. Spinner, and S. Shavgulidze, "Generalized concatenated codes for correcting two-dimensional clusters of errors and independent errors," in Int. Conference on Communication and Signal Processing (CSP), Castelldefels-Barcelona, Feb. 2014, pp. 1-5.
• [4] J. Spinner and J. Freudenberger, "Decoder architecture for generalized concatenated codes," IET Circuits, Devices & Systems, Vol. 9, No. 5, pp. 328-335, 2015.
• [5] I. Dumer, Concatenated codes and their multilevel generalizations, in Handbook of Coding Theory, Vol. II, Elsevier, Amsterdam, 1998.
• [6] M. Bossert, Channel coding for telecommunications, Wiley, 1999.
• [7] V Zyablov, S Shavgulidze, and M Bossert, "An introduction to generalized concatenated codes," European Transactions on Telecommunications, vol. 10, no. 6, pp. 609-622, 1999.
• [8] R Micheloni, A Marelli, and R Ravasio, Error Correction Codes for Non-Volatile Memories, Springer, 2008.
• [9] Zhang X and Parhi KK, "High-speed architectures for parallel long BCH encoders," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 7, pp. 872-877, 2005.
• [10] F Sun, S Devarajan, K Rose, and T Zhang, "Design of on-chip error correction systems for multilevel NOR and NAND flash memories," IET Circuits, Devices Systems, Vol. 1, No. 3, pp. 241-249, June 2007.
• [11] E Yaakobi, J Ma, L Grupp, P Siegel, S Swanson, and J Wolf, "Error characterization and coding schemes for flash memories," in IEEE GLOBECOM Workshops, Dec 2010, p. 1856-1860.
• [12] E Yaakobi, L Grupp, P Siegel, S Swanson, and J Wolf, "Characterization and error-correcting codes for TLC flash memories," in Computing, Networking and Communications (ICNC), 2012 International Conference on, Jan 2012, pp. 486-491.
• [13] J. Freudenberger and J. Spinner, "A configurable Bose-Chaudhuri-Hocquenghem codec architecture for flash controller applications," Journal of Circuits, Systems, and Computers, Vol. 23, No. 2, pp. 1-15, Feb 2014.
• [14] J. Spinner and J. Freudenberger, "Design and implementation of a pipelined decoder for generalized concatenated codes," in Proceedings of 27th Symposium on Integrated Circuits and Systems Design (SBCCI), Aracaju, Brazil, Sept. 2014, p. 1-16
• [15] L. Weiburn and J. Cavers, "Improved performance of Reed-Solomon decoding with the use of pilot signals for erasure generation," in Vehicular Technology Conference, 1998. VTC 98. 48th IEEE, Vol. 3, May 1998, pp. 1930-1934 Vol.3.
• [16] U. Wachsmann, R. Fischer, and J. Huber, "Multilevel codes: theoretical concepts and practical design rules," IEEE Transactions on Information Theory, Vol. 45, No. 5, pp. 1361-1391, July 1999 .
• [17] J. Spinner and J. Freudenberger, "Soft input decoding of generalized concatenated codes using a stack decoding algorithm," in Proceedings of 2nd BW-CAR Symposium on Information and Communication Systems (SlnCom), Dec. 2015, p. 1 -5.

Reference List

1

storage system

2

Memory controller including encoding device

2a

processor unit

2 B

embedded memory of the memory controller

3

non-volatile memory, in particular flash memory

4

host

A1

address line(s)

D1

data line(s)

C1

control line(s)

A2

address bus

D2

data bus

C2

control bus

Claims (14)

Method for error correction coding of data to be stored in a storage device (3), the method being carried out by a coding device (2) and error correction coding being applied to the data to generate coded data which is based on generalized concatenated codes, GCC, whereby: the GCC is constructed from L inner interleaved binary extended BCH codes and L outer codes, preferably RS codes, where L ≥ 2 is a positive integer; the extended BCH code at the lowest nest level of the inner nested BCH codes is an SPC code; the extended BCH code of at least one higher nest level of the inner nested BCH codes has an error correction capability and is a subcode of the BCH code of the lowest nest level; and "BCH code" denotes a Bose-Chaudhuri-Hocquenghem code, "RS code" denotes a Reed-Solomon code, and "SPC code" denotes a single parity check code. procedure according to claim 1 , wherein applying error correction coding comprises: arranging the data to be encoded in a two-dimensional data matrix (D) with a first dimension _{na corresponding to the length of the outer RS codes and a second dimension n b corresponding} to the length of the inner extended ones Correspond to BCH codes where a line of the first dimension of a matrix (D) is a row of the matrix (D) and a line of its second dimension is a column of the matrix (D), or vice versa, and the outer RS codes over a Galois -field GF(2 ^m1 ) are defined such that m ₁ elements of each line of the second dimension represent a symbol of the Galois field GF(2 ^m1 ); Applying the L outer RS codes to the corresponding L * m ₁ lines of the first dimension of the data matrix (D) such that each of the L outer RS codes yields a codeword from the corresponding m ₁ lines of the second dimension, and a total of L* m ₁ lines of the resulting intermediate matrix (A) are protected by the outer RS codes, where m ₁ is a positive integer; and subsequently applying the inner interleaved extended BCH codes to the second dimension lines of the intermediate matrix (A) to obtain a codeword matrix (C) containing the encoded data such that n _b - L * m ₁ first dimension lines of the codeword matrix (C) are used for the coding redundancy of the inner interleaved extended BCH codes, and each line of the second dimension of the codeword matrix is equal to the sum of the L codewords of the individual interleaved extended BCH codes for that line. procedure according to claim 2 , where the codeword b _j of the j-th line of the second dimension of the codeword matrix is determined by the following formula: $$b_j={\displaystyle \sum _{i=0}^{L-1}{b}_j^{\left(i\right)}}$$

where the codewords b _j ⁽ⁱ⁾ are formed by encoding the symbols a _j,i with the extended BCH codes B ⁽ⁱ⁾ of the i-th nesting level, where a _j,i is the j-th symbol of m ₁ bits of the i-th outer RS code A ⁽ⁱ⁾ along the first direction of the intermediate matrix and for this coding (L - i -1)*m ₁ zero bits are appended to the symbol a _j,i before or after it. procedure according to claim 2 or 3 , wherein the code rate of the first RS codeword defined along the direction of the second dimension of the intermediate matrix (A) is lower than the code rate of the Lth RS codeword defined along this direction. Method according to one of claims 2 until 4 , where the inner extended BCH codes are defined over a Galois field GF(2 ^m2 ) and m ₁ of m ₂ is different, where m ₂ is a positive integer. procedure according to claim 5 , whereby $$m_1=\mathrm{8th}\mathrm{and}n\mathrm{i.e}{m}_2=\mathrm{6,}$$

or $$m_1=9\mathrm{and}n\mathrm{i.e}{m}_2=7.$$

procedure according to claim 6 , where m ₁ = 9 and m ₂ = 7 and the number of nesting levels for the inner extended BCH codes is 13, so n _a = 152 and n _b = 118; and for each of said nesting levels j the corresponding code dimension of the inner extended BCH code k _b,j and its minimum Hamming distance db _,j and the corresponding code dimension k _a,j of the outer RS code and its minimum Hamming distance d _a,j those from the following table are: j k _b,j d _b,j k _a,j d _a,j 0 117 2 84 69 1 108 4 130 23 2 99 6 136 17 3 90 8th 142 11 4-12 81 12 148 5 Method according to one of claims 2 until 7 , wherein in the step of applying the inner interleaved extended BCH codes to the lines of the second dimension of the intermediate matrix (A), at least in one of the nesting levels, the single parity bit of the corresponding extended BCH code of that nesting level is selected from a predefined true subset of the bits of the corresponding line of the second dimension is calculated. A method according to any one of the preceding claims, further comprising transferring the obtained encoded data to one or more storage devices for storing the data therein. Method for iterative error correction decoding of a codeword matrix (r) based on generalized concatenated codes, GCC, where: The GCC is constructed from L inner interleaved binary extended BCH codes and L outer codes, preferably RS codes, where L ≥ 2 a is a positive integer; the extended BCH code at the lowest nest level of the inner nested BCH codes is only an SPC code; and the extended BCH code of at least one higher nest level of the inner nested BCH codes has an error correction capability and is a subcode of the BCH code of the lowest nest level; where “BCH code” denotes a Bose-Chaudhuri-Hocquenghem code, “RS code” denotes a Reed-Solomon code, and “SPC code” denotes a single parity check code; and wherein the decoding method comprises: a first iteration corresponding to the lowest nesting level of the inner extended BCH codes of the codeword matrix (r) and comprising the following steps: - applying an SPC decoding to the lines of the second dimension of the codeword matrix (r) regarding the lowest nesting level of the inner nested extended BCH codes in which the lines of a second dimension of the codeword matrix (r) are encoded, to obtain a preliminary decoding data matrix of the first iteration and to determine erasure information characterizing the lines of the second dimension of the codeword matrix, in which an erasure was detected based on SPC decoding; - extracting the information bits contained in the lines of the second dimension of the preliminary decoding data matrix of the first iteration in order to recover code symbols (aij) of the outer RS codes in which the lines of a first dimension of the codeword matrix (r) are encoded; - applying an RS decoding corresponding to the respective RS codes used to generate the original codeword matrix (C) during encoding to the recovered RS symbols in the first dimension lines of the preliminary decoding data matrix of the first iteration, to obtain a first iteration partial decoding result matrix, wherein the erasure information is used during RS decoding to identify erroneous RS symbols in the preliminary first iteration decoding data matrix; - recoding the partial decoding result matrix of the first iteration by applying an SPC coding to the second dimension of this matrix to obtain a recoded matrix of the first iteration; and - subtracting the recoded matrix of the first iteration from the codeword matrix (r) to obtain a starting matrix for a subsequent further iteration; and for each of the further nesting levels of the inner extended BCH codes of the codeword matrix (r), a corresponding further iteration with the following steps: - applying the extended BCH decoding to the lines of the second dimension of the start matrix of the current iteration with respect to the current nesting level the inner nested extended BCH codes in which the lines of a second dimension of the starting matrix of the current iteration are encoded to obtain a preliminary decoding data matrix of the current iteration; - extracting the information bits contained in the lines of the second dimension of the preliminary decoding data matrix of the current iteration in order to recover code symbols of the outer RS codes in which the lines of a first dimension of the codeword matrix are encoded; - applying an RS decoding, corresponding to the corresponding RS codes used to generate the original codeword matrix (C) during encoding, to the recovered code symbols in the first dimension lines of the current iteration's preliminary decoding data matrix, in order to obtain a partial decoding result matrix of the current iteration; - if the current iteration corresponds to the highest nesting level of the inner nested extended BCH codes in the codeword matrix (r), output the current iteration's partial decoding result matrix as a decoding-resultant data matrix, and - otherwise, re-encode the current iteration's partial decoding result matrix applying an extended BCH coding corresponding to the current nesting level to the second dimension of this matrix to obtain a back-coded matrix of the current iteration; and subtracting the recoded matrix of the current iteration from the starting matrix of the current iteration to obtain a starting matrix for a subsequent further iteration. procedure according to claim 10 , wherein for at least one of the further iterations: the step of applying the extended BCH decoding further comprises detecting erasure information characterizing lines of the second dimension of the starting matrix of the current iteration in which based on the SPC decoding one in the extended BCH code of the current iteration contained SPC parity bits an erasure was detected; and in the step of applying RS decoding, said current iteration erasure information is used during RS decoding to identify erroneous RS symbols in the preliminary decoding data matrix of the current interaction. Coding device (2), in particular a semiconductor device with a memory controller, wherein the coding device is set up, the coding method according to one of Claims 1 until 9 ; and/or the decoding method according to claim 10 or 11 to execute. Coding device (2) according to claim 12 , comprising: one or more processors (2a); a memory (2b); and one or more programs stored in the memory (2b, 3) which, when executed on the one or more processors (2a), cause the coding device to use the coding method according to one of Claims 1 until 9 and/or the decoding method according to claim 10 or 11 to execute. Computer program containing instructions that a coding device (2), in particular the coding device (2) according to claim 12 or 13 , cause the coding method according to one of Claims 1 until 9 and/or the decoding method according to claim 10 or 11 to execute.

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